60 lines
1.6 KiB
Fortran
60 lines
1.6 KiB
Fortran
../../rtl/define/chip_define.v
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../../rtl/io/iopad.v
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../../rtl/systemregfile/systemregfile.v
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../../rtl/dacif/dacif.v
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../../rtl/fifo/syn_fwft_fifo.v
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../../rtl/dac_regfile/dac_regfile.v
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../../rtl/lvds/ulink_rx.sv
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../../rtl/rstgen/rst_gen_unit.v
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../../rtl/rstgen/rst_sync.v
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../../rtl/comm/sirv_gnrl_xchecker.v
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../../rtl/comm/pulse_generator.sv
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../../rtl/comm/sirv_gnrl_dffs.v
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../../rtl/comm/syncer.v
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../../rtl/comm/ramp_gen.v
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../../rtl/comm/dout_mux.v
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../../rtl/memory/tsmc_dpram.v
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../../rtl/memory/sram_if.sv
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../../rtl/memory/sram_dmux.sv
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../../rtl/memory/dpram.v
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../../rtl/memory/bhv_spram.v
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../../rtl/memory/spram.v
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../../rtl/nco/coef_c.v
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../../rtl/nco/coef_s.v
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../../rtl/nco/cos_op.v
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../../rtl/nco/nco.v
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../../rtl/nco/p_nco.v
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../../rtl/nco/ph2amp.v
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../../rtl/nco/pipe_acc_48bit.v
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../../rtl/nco/pipe_add_48bit.v
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../../rtl/nco/sin_op.v
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../../rtl/clk/clk_regfile.v
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../../rtl/awg/awg_top.sv
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../../rtl/awg/awg_ctrl.v
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../../rtl/dem/DEM_PhaseSync_4008.sv
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../../rtl/dem/DA4008_DEM_Parallel_PRBS_1CH.v
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../../rtl/dem/DA4008_DEM_Parallel_PRBS_64CH.v
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../../rtl/top/da4008_chip_top.sv
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../../rtl/top/digital_top.sv
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../../rtl/spi/spi_bus_decoder.sv
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../../rtl/spi/spi_slave.v
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../../rtl/spi/spi_pll.v
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../../rtl/spi/spi_sys.v
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../../model/clock_tb.v
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../../model/spi_if.sv
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../../model/clk_gen.v
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../../model/DEM_Reverse_64CH.v
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../../model/DEM_Reverse.v
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../../model/reset_tb.v
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../../model/DW_stream_sync.v
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../../model/DW_reset_sync.v
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../../model/DW_sync.v
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../../model/DW_pulse_sync.v
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../../model/DW02_mult.v
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../../model/DW_mult_pipe.v
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../../lib/tphn28hpcpgv18.v
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../../lib/tsdn28hpcpuhdb4096x128m4mw_170a_ffg0p99v0c.v
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../../sim/chip_top/TB.sv
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../../rtl/define/chip_undefine.v
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