496 lines
19 KiB
Verilog
496 lines
19 KiB
Verilog
////////////////////////////////////////////////////////////////////////////////
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//
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// This confidential and proprietary software may be used only
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// as authorized by a licensing agreement from Synopsys Inc.
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// In the event of publication, the following notice is applicable:
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//
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// (C) COPYRIGHT 2005 - 2018 SYNOPSYS INC.
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// ALL RIGHTS RESERVED
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//
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// The entire notice above must be reproduced on all authorized
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// copies.
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//
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// AUTHOR: Doug Lee 12/20/05
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//
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// VERSION: Simulation Architecture
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//
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// DesignWare_version: 2105953f
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// DesignWare_release: O-2018.06-DWBB_201806.1
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// ABSTRACT: Data Stream Synchronizer Simulation Model
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//
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// This synchronizes an incoming data stream from a source domain
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// to a destination domain with a minimum amount of latency.
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//
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// Parameters: Valid Values Description
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// ========== ============ ===========
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// width 1 to 1024 default: 8
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// Width of data_s and data_d ports
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//
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// depth 2 to 256 default: 4
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// Depth of FIFO
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//
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// prefill_lvl 0 to depth-1 default: 0
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// number of FIFO locations filled before
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// transferring to destination domain ]
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//
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// f_sync_type 0 to 4 default: 2
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// Forward Synchronization Type (Source to Destination Domains)
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// 0 => no synchronization, single clock system
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// 1 => 2-stage synchronization w/ 1st stage neg-edge & 2nd stage pos-edge capturing
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// 2 => 2-stage synchronization w/ both stages pos-edge capturing
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// 3 => 3-stage synchronization w/ all stages pos-edge capturing
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// 4 => 4-stage synchronization w/ all stages pos-edge capturing
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//
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// reg_stat 0 or 1 default: 1
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// Register internally calculated status
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// 0 => don't register internally calculated status
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// 1 => register internally calculated status
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//
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// tst_mode 0 or 2 default: 0
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// Insert neg-edge hold latch at front-end of synchronizers during "test"
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// 0 => no hold latch inserted,
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// 1 => insert hold 'latch' using a neg-edge triggered register
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// 2 => insert hold latch using an active low latch
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//
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// verif_en 0 to 4 default: 1
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// Enable missampling of synchronized signals during simulation
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// 0 => no sampling errors inserted,
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// 1 => sampling errors are randomly inserted with 0 or up to 1 destination clock cycle delays
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// 2 => sampling errors are randomly inserted with 0, 0.5, 1, or 1.5 destination clock cycle delays
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// 3 => sampling errors are randomly inserted with 0, 1, 2, or 3 destination clock cycle delays
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// 4 => sampling errors are randomly inserted with 0 or up to 0.5 destination clock cycle delays
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//
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// r_sync_type 0 to 4 default: 2
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// Reverse Synchronization Type (Destination to Source Domains)
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// 0 => no synchronization, single clock system
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// 1 => 2-stage synchronization w/ 1st stage neg-edge & 2nd stage pos-edge capturing
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// 2 => 2-stage synchronization w/ both stages pos-edge capturing
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// 3 => 3-stage synchronization w/ all stages pos-edge capturing
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// 4 => 4-stage synchronization w/ all stages pos-edge capturing
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//
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// clk_d_faster 0 to 15 default: 1
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// clk_d faster than clk_s by difference ratio
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// 0 => Either clr_s or clr_d active with the other tied low at input
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// 1 to 15 => ratio of clk_d to clk_s frequencies plus 1
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//
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// reg_in_prog 0 or 1 default: 1
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// Register the 'clr_in_prog_s' and 'clr_in_prog_d' Outputs
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// 0 => unregistered
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// 1 => registered
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//
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// Input Ports: Size Description
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// =========== ==== ===========
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// clk_s 1 bit Source Domain Input Clock
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// rst_s_n 1 bit Source Domain Active Low Async. Reset
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// init_s_n 1 bit Source Domain Active Low Sync. Reset
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// clr_s 1 bit Source Domain Internal Logic Clear (reset)
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// send_s 1 bit Source Domain Active High Send Request
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// data_s N bits Source Domain Data
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//
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// clk_d 1 bit Destination Domain Input Clock
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// rst_d_n 1 bit Destination Domain Active Low Async. Reset
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// init_d_n 1 bit Destination Domain Active Low Sync. Reset
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// clr_d 1 bit Destination Domain Internal Logic Clear (reset)
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// prefill_d 1 bit Destination Domain Prefill Control
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//
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// test 1 bit Test input
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//
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// Output Ports Size Description
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// ============ ==== ===========
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// clr_sync_d 1 bit Source Domain Clear
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// clr_in_prog_s 1 bit Source Domain Clear in Progress
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// clr_cmplt_s 1 bit Soruce Domain Clear Complete (pulse)
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//
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// clr_in_prog_d 1 bit Destination Domain Clear in Progress
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// clr_sync_d 1 bit Destination Domain Clear (pulse)
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// clr_cmplt_d 1 bit Destination Domain Clear Complete (pulse)
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// data_avail_d 1 bit Destination Domain Data Available
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// data_d N bits Destination Domain Data
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// prefilling_d 1 bit Destination Domain Prefillng Status
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//
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// Note: (1) The value of N is equal to the 'width' parameter value
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//
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//
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// MODIFIED:
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// 05/06/16 RJK Removed some X propagation coding that interferes with VCS
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// NLP flow and is redundant since VCS added X propagation options
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//
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// 07/25/11 DLL Removed or-ing of 'clr_in_prog_d' with 'init_d_n' that
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// wires to DW_sync 'init_d_n' input port.
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// Added checking and comments for tst_mode = 2.
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//
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// 10/20/06 DLL Updated with new version of DW_reset_sync
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//
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// 11/15/06 DLL Added 4-stage synchronization capability
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//
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// 7/13/09 DLL Changed all `define declarations to have the
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// "DW_" prefix and then `undef them at the approprite time.
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//
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//
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//
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module DW_stream_sync (
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clk_s,
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rst_s_n,
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init_s_n,
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clr_s,
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send_s,
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data_s,
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clr_sync_s,
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clr_in_prog_s,
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clr_cmplt_s,
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clk_d,
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rst_d_n,
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init_d_n,
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clr_d,
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prefill_d,
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clr_in_prog_d,
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clr_sync_d,
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clr_cmplt_d,
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data_avail_d,
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data_d,
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prefilling_d,
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test
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);
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parameter integer width = 8; // RANGE 1 to 1024
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parameter integer depth = 4; // RANGE 2 to 256
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parameter integer prefill_lvl = 0; // RANGE 0 to 255
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parameter integer f_sync_type = 2; // RANGE 0 to 4
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parameter integer reg_stat = 1; // RANGE 0 to 1
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parameter integer tst_mode = 0; // RANGE 0 to 2
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parameter integer verif_en = 1; // RANGE 0 to 4
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parameter integer r_sync_type = 2; // RANGE 0 to 4
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parameter integer clk_d_faster = 1; // RANGE 0 to 15
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parameter integer reg_in_prog = 1; // RANGE 0 to 1
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localparam cnt_depth = ((depth>16)?((depth>64)?((depth>128)?8:7):((depth>32)?6:5)):((depth>4)?((depth>8)?4:3):((depth>2)?2:1)));
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localparam sync_verif_en = (verif_en == 2) ? 4 : (verif_en == 3) ? 1 : verif_en;
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input clk_s; // clock input from source domain
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input rst_s_n; // active low asynchronous reset from source domain
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input init_s_n; // active low synchronous reset from source domain
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input clr_s; // active high clear from source domain
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input send_s; // active high send request from source domain
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input [width-1:0] data_s; // data to be synchronized from source domain
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output clr_sync_s; // clear to source domain sequential devices
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output clr_in_prog_s; // clear in progress status to source domain
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output clr_cmplt_s; // clear sequence complete (pulse)
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input clk_d; // clock input from destination domain
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input rst_d_n; // active low asynchronous reset from destination domain
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input init_d_n; // active low synchronous reset from destination domain
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input clr_d; // active high clear from destination domain
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input prefill_d; // active high prefill control from destination domain
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output clr_in_prog_d; // clear in progress status to source domain
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output clr_sync_d; // clear to destination domain sequential devices (pulse)
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output clr_cmplt_d; // clear sequence complete (pulse)
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output data_avail_d; // data available to destination domain
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output [width-1:0] data_d; // data synchronized to destination domain
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output prefilling_d; // prefilling status to destination domain
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input test; // test input
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// synopsys translate_off
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//-------------------------------------------------------------------------
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// Parameter legality check
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//-------------------------------------------------------------------------
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initial begin : parameter_check
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integer param_err_flg;
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param_err_flg = 0;
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if ( (depth < 2) || (depth > 256) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter depth (legal range: 2 to 256)",
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depth );
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end
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if ( (prefill_lvl < 0) || (prefill_lvl > depth-1) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter prefill_lvl (legal range: 0 to depth-1)",
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prefill_lvl );
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end
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if ( ((f_sync_type & 7) < 0) || ((f_sync_type & 7) > 4) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter (f_sync_type & 7) (legal range: 0 to 4)",
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(f_sync_type & 7) );
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end
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if ( (reg_stat < 0) || (reg_stat > 1) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter reg_stat (legal range: 0 to 1)",
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reg_stat );
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end
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if ( (tst_mode < 0) || (tst_mode > 2) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter tst_mode (legal range: 0 to 2)",
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tst_mode );
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end
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if ( (verif_en < 0) || (verif_en > 4) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter verif_en (legal range: 0 to 4)",
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verif_en );
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end
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if ( ((r_sync_type & 7) < 0) || ((r_sync_type & 7) > 4) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter (r_sync_type & 7) (legal range: 0 to 4)",
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(r_sync_type & 7) );
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end
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if ( (clk_d_faster < 0) || (clk_d_faster > 15) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter clk_d_faster (legal range: 0 to 15)",
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clk_d_faster );
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end
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if ( (reg_in_prog < 0) || (reg_in_prog > 1) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter reg_in_prog (legal range: 0 to 1)",
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reg_in_prog );
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end
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if ( param_err_flg == 1) begin
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$display(
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"%m :\n Simulation aborted due to invalid parameter value(s)");
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$finish;
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end
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end // parameter_check
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wire next_data_avail_d_int;
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reg data_avail_d_int;
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wire [width-1:0] next_data_d_int;
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reg [width-1:0] data_d_int;
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wire next_prefilling_d_int;
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reg prefilling_d_int;
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reg [width-1:0] data_mem [0:depth-1];
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wire [cnt_depth-1:0] next_wr_ptr_s;
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reg [cnt_depth-1:0] wr_ptr_s;
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wire [cnt_depth-1:0] next_rd_ptr_d;
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reg [cnt_depth-1:0] rd_ptr_d;
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reg [cnt_depth-1:0] next_valid_cnt;
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reg [cnt_depth-1:0] valid_cnt;
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wire [depth-1:0] next_event_vec_s;
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reg [depth-1:0] event_vec_s;
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reg [depth-1:0] event_vec_l;
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wire [depth-1:0] event_vec_selected;
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wire [depth-1:0] dw_sync_event_vec;
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wire next_detect_lvl;
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reg detect_lvl;
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wire [31:0] one;
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integer i, idx;
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assign one = 1;
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initial begin
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if ((f_sync_type > 0)&&(f_sync_type < 8))
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$display("Information: *** Instance %m is the DW_stream_sync Clock Domain Crossing Module ***");
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end
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DW_reset_sync #((f_sync_type + 8), (r_sync_type + 8), clk_d_faster, reg_in_prog, tst_mode, verif_en) U_RST_SYNC (
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.clk_s(clk_s),
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.rst_s_n(rst_s_n),
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.init_s_n(init_s_n),
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.clr_s(clr_s),
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.clk_d(clk_d),
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.rst_d_n(rst_d_n),
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.init_d_n(init_d_n),
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.clr_d(clr_d),
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.test(test),
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.clr_sync_s(clr_sync_s),
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.clr_in_prog_s(clr_in_prog_s),
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.clr_cmplt_s(clr_cmplt_s),
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.clr_in_prog_d(clr_in_prog_d),
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.clr_sync_d(clr_sync_d),
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.clr_cmplt_d(clr_cmplt_d)
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);
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always @(posedge clk_s or negedge rst_s_n) begin : a1001_PROC
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if (rst_s_n == 1'b0) begin
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for (idx = 0; idx < depth; idx = idx + 1) begin
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data_mem[idx] <= {width{1'b0}};
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end
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end else begin
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if (!init_s_n || clr_in_prog_s) begin
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for (idx = 0; idx < depth; idx = idx + 1) begin
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data_mem[idx] <= {width{1'b0}};
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end
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end else begin
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if (send_s == 1'b1) begin
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data_mem[wr_ptr_s] <= data_s;
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end
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end
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end
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end
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assign next_wr_ptr_s = (send_s == 1'b1) ? ((wr_ptr_s === depth-1) ? {cnt_depth{1'b0}} :
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wr_ptr_s + one[cnt_depth-1:0]) : wr_ptr_s;
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assign next_event_vec_s = (send_s == 1'b1) ? {event_vec_s[depth-2:0], ~event_vec_s[depth-1]} :
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event_vec_s;
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generate
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if (((f_sync_type&7)>1)&&(tst_mode==2)) begin : GEN_LATCH_hold_latch_PROC
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reg [depth-1:0] event_vec_l;
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always @ (clk_s or event_vec_s) begin : LATCH_hold_latch_PROC_PROC
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if (clk_s == 1'b0)
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event_vec_l = event_vec_s;
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end // LATCH_hold_latch_PROC_PROC
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assign event_vec_selected = (test==1'b1)? event_vec_l : event_vec_s;
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end else begin : GEN_DIRECT_hold_latch_PROC
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assign event_vec_selected = event_vec_s;
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end
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endgenerate
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DW_sync #(depth, f_sync_type+8, tst_mode, sync_verif_en) U_SYNC(
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.clk_d(clk_d),
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.rst_d_n(rst_d_n),
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.init_d_n(init_d_n),
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.data_s(event_vec_selected),
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.test(test),
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.data_d(dw_sync_event_vec) );
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always @(dw_sync_event_vec or next_valid_cnt or rd_ptr_d) begin : a1002_PROC
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next_valid_cnt = {cnt_depth{1'b0}};
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for (i = 0; i < depth; i = i + 1) begin
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if (rd_ptr_d > i) begin
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next_valid_cnt = next_valid_cnt + (dw_sync_event_vec[i] === ~detect_lvl);
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end else begin
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next_valid_cnt = next_valid_cnt + (dw_sync_event_vec[i] === detect_lvl);
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end
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if (dw_sync_event_vec[i] === 1'bX)
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next_valid_cnt = {cnt_depth{1'b0}};
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end
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end
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assign next_rd_ptr_d = next_data_avail_d_int ? ((rd_ptr_d === depth-1) ? {cnt_depth{1'b0}} : (rd_ptr_d + one[cnt_depth-1:0])) :
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rd_ptr_d;
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assign next_detect_lvl = (next_data_avail_d_int && (next_rd_ptr_d === {cnt_depth{1'b0}})) ?
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~detect_lvl : detect_lvl;
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assign next_prefilling_d_int = ((prefill_d === 1'bX) || (prefilling_d_int === 1'bX)) ? 1'bX :
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(prefill_lvl == 0) ? 1'b0 :
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((prefill_d === 1'b1) && (prefill_lvl > (reg_stat ? valid_cnt : next_valid_cnt))) ? 1'b1 :
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(prefill_lvl <= (reg_stat ? valid_cnt : next_valid_cnt)) ? 1'b0 : prefilling_d_int;
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assign next_data_avail_d_int = ((dw_sync_event_vec[rd_ptr_d] === 1'bX) || (next_prefilling_d_int === 1'bX)) ? 1'bX :
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(next_prefilling_d_int === 1'b0) && (detect_lvl === dw_sync_event_vec[rd_ptr_d]) ? 1'b1 : 1'b0;
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assign next_data_d_int = (next_data_avail_d_int === 1'bX) ? {width{1'bX}} :
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(next_data_avail_d_int === 1'b1) ? data_mem[rd_ptr_d] : data_d_int;
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always @(posedge clk_s or negedge rst_s_n) begin : a1003_PROC
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if (rst_s_n == 1'b0) begin
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wr_ptr_s <= {cnt_depth{1'b0}};
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event_vec_s <= {depth{1'b0}};
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end else begin
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if ((init_s_n == 1'b0) || (clr_in_prog_s == 1'b1)) begin
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wr_ptr_s <= {cnt_depth{1'b0}};
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event_vec_s <= {depth{1'b0}};
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end else begin
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wr_ptr_s <= next_wr_ptr_s;
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event_vec_s <= next_event_vec_s;
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end
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end
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end
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always @(posedge clk_d or negedge rst_d_n) begin : a1004_PROC
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if (rst_d_n == 1'b0) begin
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rd_ptr_d <= {cnt_depth{1'b0}};
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valid_cnt <= {cnt_depth{1'b0}};
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detect_lvl <= 1'b1;
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data_avail_d_int <= 1'b0;
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data_d_int <= {width{1'b0}};
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prefilling_d_int <= 1'b0;
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|
end else begin
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|
if ((init_d_n == 1'b0) || (clr_in_prog_d == 1'b1)) begin
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|
rd_ptr_d <= {cnt_depth{1'b0}};
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|
valid_cnt <= {cnt_depth{1'b0}};
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|
detect_lvl <= 1'b1;
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data_avail_d_int <= 1'b0;
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data_d_int <= {width{1'b0}};
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prefilling_d_int <= 1'b0;
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end else begin
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|
rd_ptr_d <= next_rd_ptr_d;
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|
valid_cnt <= next_valid_cnt;
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|
detect_lvl <= next_detect_lvl;
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|
data_avail_d_int <= next_data_avail_d_int;
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|
data_d_int <= next_data_d_int;
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|
prefilling_d_int <= next_prefilling_d_int;
|
|
end
|
|
end
|
|
end
|
|
|
|
assign data_avail_d = data_avail_d_int;
|
|
assign data_d = data_d_int;
|
|
assign prefilling_d = prefilling_d_int;
|
|
|
|
|
|
|
|
always @ (clk_s) begin : monitor_clk_s
|
|
if ( (clk_s !== 1'b0) && (clk_s !== 1'b1) && ($time > 0) )
|
|
$display( "WARNING: %m :\n at time = %t, detected unknown value, %b, on clk_s input.",
|
|
$time, clk_s );
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|
end // monitor_clk_s
|
|
|
|
always @ (clk_d) begin : monitor_clk_d
|
|
if ( (clk_d !== 1'b0) && (clk_d !== 1'b1) && ($time > 0) )
|
|
$display( "WARNING: %m :\n at time = %t, detected unknown value, %b, on clk_d input.",
|
|
$time, clk_d );
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|
end // monitor_clk_d
|
|
|
|
// synopsys translate_on
|
|
endmodule
|
|
/* vcs gen_ip dbg_ip off */
|
|
/* */ |