101 lines
4.9 KiB
Tcl
101 lines
4.9 KiB
Tcl
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#################################################################################################################
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#### Library Setup
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#################################################################################################################
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set svars(lib,path,std) ""
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set svars(lib,path,io) ""
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set svars(lib,path,pmk) ""
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set svars(lib,path,mem) ""
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set svars(lib,path,ip) ""
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#set svars(lib,db,std) "../lib/STD/9T/SCC40NLL_HS_RVT_V0p2b/liberty/1.1v/scc40nll_hs_rvt_ss_v0p99_-40c_ccs.db"
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set svars(lib,db,std) "/data/pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp7t35p140_180a/tcbn28hpcplusbwp7t35p140ssg0p72vm40c.db"
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set svars(lib,db,pmk) ""
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set svars(lib,db,io) " \
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/data/pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tphn28hpcpgv18_170a/tphn28hpcpgv18ssg0p81v1p62vm40c.db \
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"
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set svars(lib,db,mem) " \
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/data/pdk/TSMCHOME/sram/Cell/tsdn28hpcpuhdb64x32m4mw_170a/NLDM/tsdn28hpcpuhdb64x32m4mw_170a_ssg0p81vm40c.db \
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/data/pdk/TSMCHOME/sram/Cell/tsdn28hpcpuhdb128x128m4mw_170a/NLDM/tsdn28hpcpuhdb128x128m4mw_170a_ssg0p81vm40c.db \
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/data/pdk/TSMCHOME/sram/Cell/tsdn28hpcpuhdb1024x128m4mw_170a/NLDM/tsdn28hpcpuhdb1024x128m4mw_170a_ssg0p81vm40c.db \
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/data/pdk/TSMCHOME/sram/Cell/tsdn28hpcpuhdb4096x32m4mw_170a/NLDM/tsdn28hpcpuhdb4096x32m4mw_170a_ssg0p81vm40c.db \
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/data/pdk/TSMCHOME/sram/Cell/tsdn28hpcpuhdb4096x128m4mw_170a/NLDM/tsdn28hpcpuhdb4096x128m4mw_170a_ssg0p81vm40c.db \
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/data/pdk/TSMCHOME/sram/Cell/tsdn28hpcpuhdb2048x64m4mw_170a/NLDM/tsdn28hpcpuhdb2048x64m4mw_170a_ssg0p81vm40c.db \
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"
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set svars(lib,db,ip) " \
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/data/pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp7t35p140_180a/tcbn28hpcplusbwp7t35p140ssg0p72vm40c.db \
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"
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set svars(lib,db,synthetic) "standard.sldb dw_foundation.sldb"
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set search_path ". $svars(lib,path,std) \
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$svars(lib,path,pmk) \
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$svars(lib,path,io) \
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$svars(lib,path,mem) \
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$svars(lib,path,ip) \
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"
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set link_library "* $svars(lib,db,std) \
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$svars(lib,db,pmk) \
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$svars(lib,db,io) \
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$svars(lib,db,mem) \
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$svars(lib,db,ip) \
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$svars(lib,db,synthetic) \
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"
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set target_library " $svars(lib,db,std) \
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$svars(lib,db,pmk) \
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"
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#========================================================================================
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#20190916:follow dc_ref settings
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#========================================================================================
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set dont_use_list "
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/ANTENNA* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/BHD* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/BOUNDARY* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/BUFTD* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/CK* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/DCAP* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/DEL* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/FILL* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/GAN* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/GAOI* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/GBUFF* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/GDCAP* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/GDF* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/GFILL* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/GINV* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/GMUX* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/GND* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/GNR* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/GOA* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/GOR* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/GSDF* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/GTIEH* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/GTIEL* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/GXN* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/GXO* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/LH* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/LN* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/SDF* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/TAP* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/TIE* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/*D0* \
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tcbn28hpcplusbwp7t35p140ssg0p72vm40c/*D20* \
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"
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foreach cell $dont_use_list {
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set_dont_use [get_lib_cells $cell]
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}
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