81 lines
2.9 KiB
Tcl
81 lines
2.9 KiB
Tcl
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#################################################################################################################
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#### Enviroments Setup
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#################################################################################################################
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#set_host_options -max_cores 8
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set_host_options -max_cores 4
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#### user defined variable
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set enable_page_mode false
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set collection_result_display_limit -1
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set timing_enable_multiple_clocks_per_reg true
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set ungroup_keep_original_design true
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set power_preserve_rtl_hier_names TRUE
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set_app_var hdlin_vrlg_std 2005
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# VER-61 : Statement unreachable (Branch condition impossible to meet),
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# VER-61 : Statement unreachable (Prior branch conditions are always met).
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# VER-130 : Intraassignment delays for nonblocking assignments are ignored.
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# VER-318 : signed to unsigned assignment occurs.
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# VER-921 : The macro 'REG_VID' you are attempting to undefine with the '`undef' directive is not defined.
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# VER-936 : The undeclared symbol 'XXX' assumed to have the default net type, which is 'wire'.
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# ELAB-311: DEFAULT branch of CASE statement cannot be reached.
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# ELAB-985: Netlist for always block is empty.
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# UCN-1 : net 'XXX' is connecting multiple ports.
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#set_app_var suppress_errors {VER-61 VER-130 VER-318 ELAB-311 VER-936 ELAB-985 UCN-1}
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set_app_var suppress_errors {}
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set hdlin_enable_rtldrc_info true
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set hdlin_keep_signal_name all
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set hdlin_check_no_latch true
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set hdlin_shorten_long_module_name true
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set hdlin_module_name_limit 64
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set verilogout_show_unconnected_pins true
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set verilogout_no_tri true
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set verilogout_higher_designs_first true
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set verilogout_equation false
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# for area opt
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set compile_delete_unloaded_sequential_cells true
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set compile_seqmap_propagate_constants true
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set case_analysis_with_logic_constants false
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set enable_recovery_removal_arcs false
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set synlib_enable_dpgen true
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set uniquify_keep_original_design false
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set access_internal_pins true
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set synlib_dwgen_fmlink_active true
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set timing_use_enhanced_capacitance_modeling true
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set synlib_abort_wo_dw_license true
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set timing_check_defaults "clock_crossing \
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data_check_multiple_clock \
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data_check_no_clock \
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generic \
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loops \
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multiple_clock \
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no_input_delay \
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partial_input_delay \
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ideal_clocks \
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no_driving_cell \
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retain \
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unconstrained_endpoints \
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clock_no_period \
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pulse_clock_cell_type \
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"
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set compile_seqmap_identify_shift_registers false
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#### low power
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set power_driven_clock_gating true
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#set auto_insert_level_shifters true
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#set auto_insert_level_shifters_on_clocks "true"
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#set mv_insert_level_shifters_on_ideal_nets "true"
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