61 lines
2.4 KiB
Tcl
61 lines
2.4 KiB
Tcl
#dc common setting
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#set_host_options -max_cores 8
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set compile_enable_register_merging false
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set svf_file_records_change_names_changes true
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set enable_recovery_removal_arcs true
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set case_analysis_with_logic_constants true
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set timing_enable_multiple_clocks_per_reg "true"
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set compile_instance_name_prefix "U"
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set verilogout_no_tri true
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set verilogout_show_unconnected_pins true
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set bind_unused_hierarchical_pins false
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#CLOCK gating setting
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set compile_clock_gating_through_hierarchy false
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#set power_cg_gated_clock_net_naming_style "pckg_net_wc_suffix"
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#set power_cg_cell_naming_style "pckg_wc_midfix_wd_suffix"
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#set power_cg_module_naming_style "pckg_wp_wd_suffix"
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#->set power_cg_auto_identify true
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#->positive_edge_logic integrated
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#same setting already in opt_setup.tcl
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#set_clock_gating_style \
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# -sequential_cell latch \
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# -control_point before \
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# -control_signal scan_enable \
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# -observation_point false \
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# -positive_edge_logic integrated:${lib_icg_name}/${ICG_NAME} \
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# -max_fanout 16 \
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# -minimum_bitwidth 4
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#--append --------------------------------------------
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set pwr_hdlc_split_cg_cells true
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set timing_scgc_override_library_setup_hold true
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set power_keep_license_after_power_commands true
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set verilogout_equation false
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set compile_seqmap_propagate_constants false
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set compile_seqmap_propagate_high_effort false
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set set_ultra_optimization "true"
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set compile_seqmap_identify_shift_registers false
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set compile_seqmap_no_scan_cell true
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set compile_delete_unloaded_seqential_cells false
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set timing_report_unconstrained_paths true
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set hdlin_enable_vpp true
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set power_keep_license_after_power_command true
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set single_group_per_sheet true
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set auto_wire_load_selection false
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set timing_disable_recovery_removal_checks false
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#set enable_recovery_removal_arcs true
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#start to compile
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#same setting already in opt_setup.tcl
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#set_fix_multiple_port_nets -all -buffer_constants
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#set_max_area 0
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#set verilogout_equation false
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#set compile_seqmap_propagate_constants false
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#set compile_seqmap_propagate_high_effort false
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#set set_ultra_optimization "true"
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#set compile_seqmap_identify_shift_registers false
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