319 lines
15 KiB
Tcl
319 lines
15 KiB
Tcl
## ------------------------------------------------------------------------------------------
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##
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## Copyright (c) 2018 ChipMotion, Inc.
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## All rights reserved.
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##
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## ------------------------------------------------------------------------------------------
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## Filename : run_dc.tcl
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## Department :
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## Author :
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## Keywords :
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## Description :
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##
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## RELEASE HISTORY
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## VERSION DATE AUTHOR DESCRIPTION
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## v0_01 20200317 wenyi.Peng Initialized for QKD-SoC project
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##
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## ------------------------------------------------------------------------------------------
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set hostname [sh hostname]
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set starttime [clock seconds]
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echo "INFORM: Job excuted on $hostname"
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echo "INFORM: Start job at: " [clock format $starttime -gmt false]
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#################################################################################################
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##
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## Pre Setup
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##
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#################################################################################################
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#set_app_var hdlin_enable_hier_map "true"; #enable hier info in svf
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set svars(top_design) "da4008_chip_top"
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set svars(upf) "false"
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set svars(scan) "false"
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source $svars(dir,scripts)/setup.utility.tcl
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source -e -v $svars(dir,scripts)/setup.dir.tcl
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source -e -v $svars(dir,scripts)/setup.dc.tcl
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source -e -v $svars(dir,scripts)/setup.lib.tcl
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define_design_lib work -path $svars(rtl,path,work)
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#################################################################################################
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##
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## Create MW Library for DCT/DCG FLOW
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##
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#################################################################################################
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if {[shell_is_in_topographical_mode]} {
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source -e -v $svars(dir,scripts)/dct_config.tcl
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source -e -v $svars(dir,scripts)/setup.physical.tcl
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}
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################################################################################################
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##
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## Read and Elaborate Design
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##
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#################################################################################################
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source -e -v $svars(dir,scripts)/read_filelist.tcl
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echo $rtl_files
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#20190916: follow dc_ref settings
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set_app_var dc_allow_rtl_pg true
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analyze -lib work -format sverilog $rtl_files
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elaborate $svars(top_design)
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current_design $svars(top_design)
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#set svf
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#set_verification_top
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set_svf $svars(dir,outputs)/$svars(top_design).syn.svf
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if {$svars(upf) == "true"} {
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# Load UPF
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load_upf $svars(dir,inputs)/powerspec/design.upf > $svars(dir,logs)/load_upf.log
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source -e -v $svars(dir,scripts)/power_constraints.tcl
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}
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current_design $svars(top_design)
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link
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check_design > $svars(dir,reports)/pre_check_design.rpt
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check_mv_design -verbose > $svars(dir,reports)/pre_check_mv_design.rpt
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write -f ddc -hier -output $svars(dir,outputs)/$svars(top_design).elab.ddc
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write -f verilog -hier -output $svars(dir,outputs)/$svars(top_design).elab.v
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#################################################################################################
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##
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## Optimization Constraints
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##
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#################################################################################################
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source -e -v $svars(dir,inputs)/design.sdc > $svars(dir,logs)/read_syn_sdc.log
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#source -e -v $svars(dir,scripts)/mbist.tcl > $svars(dir,logs)/read_sdc_mbist.log
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source -e -v $svars(dir,scripts)/opt_setup.tcl > $svars(dir,logs)/read_opt_setup.log
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#source -e -v $svars(dir,scripts)/group_path.tcl > $svars(dir,logs)/read_group_path.log
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#20190916: follow dc_ref settings
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source -e -v $svars(dir,scripts)/setup.addition.tcl > $svars(dir,logs)/read_addition_setup.log
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if {[shell_is_in_topographical_mode]} {
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extract_physical_constraints -exact -no_incremental -verbose > $svars(dir,logs)/read_def.log
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} else {
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# set_wire_load_model -name Zero
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# set_wire_load_mode top
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# set auto_wire_load_selection false
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set auto_wire_load_selection true
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}
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# Uniquify the design
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#20190916: follow dc_ref settings
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set uniquify_naming_style $svars(top_design)_%s_%d
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#20190916: follow dc_ref settings
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uniquify -force
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propagate_constraints
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#define_name_rules verilog -target_bus_naming_style {%s_%d} \
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# -remove_port_bus
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#20190916: follow dc_ref settings
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#change_names -rules verilog -hierarchy -log_changes $svars(dir,logs)/change_names.log
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source $svars(dir,scripts)/change_name.tcl
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write -f ddc -hier -output $svars(dir,outputs)/$svars(top_design).change.ddc
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write -f verilog -hier -output $svars(dir,outputs)/$svars(top_design).change.v
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write_sdc $svars(dir,outputs)/$svars(top_design).change.sdc
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#################################################################################################
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##
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## Compile Design: 1st compile_ultra
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##
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#################################################################################################
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puts ""
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puts "--------------------------------------"
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puts " Initial Compile "
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puts "**************************************"
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puts ""
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if {[shell_is_in_topographical_mode]} {
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compile_ultra -scan -no_autoungroup -spg -no_seq_output_inversion -gate_clock
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} else {
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compile_ultra -no_autoungroup -no_seq_output_inversion -gate_clock
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# compile_ultra -scan -no_autoungroup -no_seq_output_inversion -gate_clock
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# compile_ultra -scan -no_autoungroup -no_seq_output_inversion
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puts " **********************"
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puts " Saving debug database."
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puts ""
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}
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write -f ddc -hier -output $svars(dir,outputs)/$svars(top_design).cmpl.ddc
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write -f verilog -hier -output $svars(dir,outputs)/$svars(top_design).cmpl.v
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write_sdc $svars(dir,outputs)/$svars(top_design).cmpl.sdc
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report_constraint -all_violators > $svars(dir,reports)/debug.all_vios.summary.rpt
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#report_constraint -all_violators -verbose > $svars(dir,reports)/debug.all_vios.rpt
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check_design > $svars(dir,reports)/debug.check_design.rpt
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check_mv_design -verbose > $svars(dir,reports)/debug.check_mv_design.rpt
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#
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# 20190510, when check_timing, dc_shell(syn_vL-2016.03-SP5-7) has encountered a fatal error
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#
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check_timing > $svars(dir,reports)/debug.check_timing.rpt
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check_timing -multiple_clock > $svars(dir,reports)/debug.check_timing.multiple_clock.rpt
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report_qor > $svars(dir,reports)/debug.qor.rpt
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report_clock > $svars(dir,reports)/debug.clock.rpt
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report_clock_gating > $svars(dir,reports)/debug.clock_gating.rpt
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report_clock_tree -interclock_timing -summary > $svars(dir,reports)/debug.clock_tree.rpt
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report_timing -nets -capacitance -transition_time -max_path 10 > $svars(dir,reports)/debug.timing.rpt
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report_timing_requirements > $svars(dir,reports)/debug.check_timing_requirements.rpt
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if {$svars(upf) == "true"} {
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report_power_domain [get_power_domains * -hierarchical ] > $svars(dir,reports)/debug.power.rpt
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report_isolation_cell -domain [get_power_domains * -hierarchical ] >> $svars(dir,reports)/debug.power.rpt
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report_pst >> $svars(dir,reports)/debug.power.rpt
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}
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#################################################################################################
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##
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## Optimization Design: 2nd compile_ultra
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##
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#################################################################################################
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puts ""
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puts "--------------------------------------------------"
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puts " Initial Incremental Compile "
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puts "**************************************************"
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puts ""
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if {[shell_is_in_topographical_mode]} {
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compile_ultra -scan -no_autoungroup -spg -incr -no_seq_output_inversion -gate_clock
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set_icc_dp_options -work_dir $work_dir -icc_executable $icc_execute_dir
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} else {
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# compile_ultra -scan -no_autoungroup -incr -no_seq_output_inversion -gate_clock
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compile_ultra -no_autoungroup -incr -no_seq_output_inversion -gate_clock
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# compile_ultra -scan -no_autoungroup -incr -no_seq_output_inversion
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}
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report_constraint -all_violators > $svars(dir,reports)/debugIncr.all_vios.summary.rpt
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#report_constraint -all_violators -verbose > $svars(dir,reports)/debugIncr.all_vios.rpt
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check_design > $svars(dir,reports)/debugIncr.check_design.rpt
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check_mv_design -verbose > $svars(dir,reports)/debugIncr.check_mv_design.rpt
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check_timing > $svars(dir,reports)/debugIncr.check_timing.rpt
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check_timing -multiple_clock > $svars(dir,reports)/debugIncr.check_timing.multiple_clock.rpt
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report_qor > $svars(dir,reports)/debugIncr.qor.rpt
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report_clock > $svars(dir,reports)/debugIncr.clock.rpt
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report_clock_gating > $svars(dir,reports)/debugIncr.clock_gating.rpt
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report_clock_tree -interclock_timing -summary > $svars(dir,reports)/debugIncr.clock_tree.rpt
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report_timing -nets -capacitance -transition_time -max_path 10 > $svars(dir,reports)/debugIncr.timing.rpt
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report_timing_requirements > $svars(dir,reports)/debugIncr.check_timing_requirements.rpt
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if {$svars(upf) == "true"} {
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report_power_domain [get_power_domains * -hierarchical ] > $svars(dir,reports)/debugIncr.power.rpt
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report_isolation_cell -domain [get_power_domains * -hierarchical ] >> $svars(dir,reports)/debugIncr.power.rpt
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report_pst >> $svars(dir,reports)/debugIncr.power.rpt
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}
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write -f ddc -hier -output $svars(dir,outputs)/$svars(top_design).cmplIncr.ddc
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write -f verilog -hier -output $svars(dir,outputs)/$svars(top_design).cmplIncr.v
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write_sdc $svars(dir,outputs)/$svars(top_design).cmplIncr.sdc
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save_upf $svars(dir,outputs)/$svars(top_design).cmplIncr.upf
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#################################################################################################
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##
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## DFT
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##
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#################################################################################################
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#if {$svars(scan) == "true"} {
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# source -e -v $svars(dir,scripts)/setup.dft.tcl
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# source -e -v $svars(dir,scripts)/insert_dft.tcl
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#} else {
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# set uniquify_naming_style $svars(top_design)_%s_%d
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# uniquify -force
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# change_names -rules verilog -hierarchy -log_changes $svars(dir,logs)/change_names_syn.log
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#
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#}
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#################################################################################################
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##
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## Export Design Data, Generate Final Reports
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##
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#################################################################################################
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report_constraint -all_violators > $svars(dir,reports)/syn_final.all_vios.summary.rpt
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#report_constraint -all_violators -verbose > $svars(dir,reports)/syn_final.all_vios.rpt
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check_design > $svars(dir,reports)/syn_final.check_design.rpt
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check_mv_design -verbose > $svars(dir,reports)/syn_final.check_mv_design.rpt
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check_timing > $svars(dir,reports)/syn_final.check_timing.rpt
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check_timing -multiple_clock > $svars(dir,reports)/syn_final.check_timing.multiple_clock.rpt
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report_qor > $svars(dir,reports)/syn_final.qor.rpt
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report_clock > $svars(dir,reports)/syn_final.clock.rpt
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report_clock_gating > $svars(dir,reports)/syn_final.clock_gating.rpt
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report_clock_tree -interclock_timing -summary > $svars(dir,reports)/syn_final.clock_tree.rpt
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report_timing -nets -capacitance -transition_time -max_path 10 > $svars(dir,reports)/syn_final.timing.rpt
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report_timing_requirements > $svars(dir,reports)/syn_final.check_timing_requirements.rpt
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report_size_only -nosplit > $svars(dir,reports)/syn_final.syn_size_only.rpt
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report_power > $svars(dir,reports)/syn_final.power.rpt
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if {$svars(upf) == "true"} {
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report_power_domain [get_power_domains * -hierarchical ] > $svars(dir,reports)/syn_final.power.rpt
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report_isolation_cell -domain [get_power_domains * -hierarchical ] >> $svars(dir,reports)/syn_final.power.rpt
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report_pst >> $svars(dir,reports)/syn_final.power.rpt
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}
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source $svars(dir,scripts)/change_name.tcl
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write -f ddc -hier -output $svars(dir,outputs)/$svars(top_design).syn.ddc
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write -f verilog -hier -output $svars(dir,outputs)/$svars(top_design).syn.v
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write_sdc $svars(dir,outputs)/$svars(top_design).syn.sdc
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save_upf $svars(dir,outputs)/$svars(top_design).syn.upf
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set_svf -off
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#################################################################################################
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##
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## Summary
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##
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#################################################################################################
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set endtime [clock seconds]
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echo "INFORM: End job at: " [clock format $endtime -gmt false]
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set hostname [sh hostname]
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set pwd [pwd]
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set runtime "[format %02d [expr ($endtime - $starttime)/3600]]:[format %02d [expr (($endtime - $starttime)%3600)/60]]:[format %02d [expr ((($endtime - $starttime))%3600)%60]]"
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echo [format "%-15s %-2s %-70s" "" "" ""]
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echo " ------------------------------------------------------------------------------------------"
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echo [format "%-15s %-2s %-70s" " | Host" "|" "$hostname"]
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echo [format "%-15s %-2s %-70s" " | Working Dir" "|" "$pwd"]
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echo [format "%-15s %-2s %-70s" " | runtime" "|" "$runtime"]
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alias rf report_timing -from
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alias rt report_timing -to
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#exit
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