78 lines
2.7 KiB
Tcl
78 lines
2.7 KiB
Tcl
#### clock gating setup
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#### 2014-10-03
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#### Original: PREICG_X9B_A9TL40
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#### NEW: PREICG_X9B_A9TR40
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set_clock_gating_style -sequential_cell latch \
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-positive_edge_logic integrated:CKLNQD20BWP7T35P140 \
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-control_point before \
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-control_signal scan_enable \
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-max_fanout 16 \
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-minimum_bitwidth 4 \
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-num_stages 4
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# 12 track : PREICG_X0P5B_A12TR50
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# 9 track : PREICG_X0P5B_A9TR50
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set power_cg_module_naming_style "CG_%e_%t"
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set power_cg_auto_identify true
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set power_cg_print_enable_conditions true
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set timing_separate_clock_gating_group true
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set clks [all_clocks]
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foreach_in_collection clk $clks {
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set clk_name [get_object_name $clk]
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set regs [all_registers -edge_triggered -fall_clock $clk_name]
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foreach_in_collection reg $regs {
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set reg_name [get_object_name $reg]
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set ref_name [get_attribute $reg_name ref_name]
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set_clock_gating_registers -exclude_instances $reg_name
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echo "disable clock-gating of negedge register : ${reg_name}"
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echo $reg_name >> $svars(dir,logs)/disable_clk_gate_negedge_reg.list
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}
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}
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set_fix_multiple_port_nets -all -buffer_constants
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set_critical_range 0.1 [get_designs $svars(top_design)]
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set_register_merging $svars(top_design) true
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set_cost_priority -delay
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######################################################
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### drc rule
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set_max_transition 0.6 [get_designs $svars(top_design)]
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set_max_capacitance 0.1 [get_designs $svars(top_design)]
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set_max_fanout 32 [get_designs $svars(top_design)]
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######################################################
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### area optimazition
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set_max_area 0
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######################################################
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### remove wand
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#foreach_in_collection this_design [ all_designs ] \
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# {
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# current_design $this_design
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# remove_wand_attr
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# }
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#
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#set enable_recovery_removal_arcs false
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######################################################
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### Define operating_conditions
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#set_operating_conditions ss_typical_max_0p99v_m40c -lib sc9mc_cln40lp_base_rvt_c40_ss_typical_max_0p99v_m40c
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######################################################
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### Physical options
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if {[shell_is_in_topographical_mode]} {
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set_utilization 0.6
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set placer_max_cell_density_threshold 0.80
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set_ignored_layers
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set_delay_estimation_options
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set_ahfs_options -enable_port_punching false
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set psynopt_tns_high_effort true
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set glo_more_opto true
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set placer_disable_auto_bound_for_gated_clock false
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set phyopt_pccts_dont_touch_support true
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set placer_use_path_group_weight true
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set phyopt_enable_via_res_support true
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set placer_enable_advance_resistance_model true
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}
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