585 lines
34 KiB
Systemverilog
585 lines
34 KiB
Systemverilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : digital_top.v
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// Department :
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// Author : pwy
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 1.2 2024-04-16 pwy XYZ control the top-level module
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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`include "../define/chip_define.v"
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module digital_top (
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//system port
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input clk // System Main Clock
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,input rst_n // Spi Reset active low
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,input sync_in
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,output sync_out
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//spi port
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,input [4 :0] cfgid
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,input sclk // Spi Clock
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,input csn // Spi Chip Select active low
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,input mosi // Spi Mosi
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,output miso // Spi Miso
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,output oen
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//irq
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,output irq
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//wave port
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,output [7 :0] wave_data_out [63:0]
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,output wave_data_valid
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//lvds rx
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,input [3 :0] lvds_data
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,input [0 :0] lvds_valid
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,input [0 :0] lvds_clk
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,output [2 :0] phase_tap
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//DAC Cfg Port
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,output [3 :0] Rterm
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,output PrbsEn
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,output [14 :0] Set [63:0]
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,output [2 :0] CasAddr
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,output [2 :0] CasDw
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,output [9 :0] IMainCtrl
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,output [3 :0] IBleedCtrl
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,output [3 :0] ICkCml
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,output [31 :0] CurRsv0
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,output [31 :0] CurRsv1
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//CLK Cfg Port
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,output [0 :0] CcalRstn
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,output [3 :0] EnAllP
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,output [0 :0] DccEn
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,output [0 :0] CasGateCkCtrl
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,output [0 :0] SpiEnPi
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,output [0 :0] SpiEnQec
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,output [0 :0] SpiEnDcc
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,output [4 :0] SpiQecCtrlIp
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,output [4 :0] SpiQecCtrlIn
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,output [4 :0] SpiQecCtrlQp
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,output [4 :0] SpiQecCtrlQn
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,output [5 :0] SpiDccCtrlIup
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,output [5 :0] SpiDccCtrlIdn
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,output [5 :0] SpiDccCtrlQup
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,output [5 :0] SpiDccCtrlQdn
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,output [7 :0] SpiSiqNOut
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,output [7 :0] SpiSiqPOut
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,output [3 :0] SpiSiPOut
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,output [3 :0] SpiSqPOut
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,output [2 :0] CrtlCrossOverN
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,output [2 :0] CrtlCrossOverP
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,output [31 :0] CcalRsv0
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,output [31 :0] CcalRsv1
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,output [3 :0] SelCk10GDig
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,output [3 :0] SelCk2p5GDig
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,output [8 :0] SelCk625MDig
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,output [15 :0] P2sDataEn
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,output [15 :0] P2sEnAllP
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,output [15 :0] EnPiP
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,output [15 :0] CkDivRstn
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,output [31 :0] p2srsv0
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,output [31 :0] p2srsv1
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,output [15 :0] CkRxSw
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,output [15 :0] RstnCk
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,output [15 :0] CtrlZin
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);
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//------------------------------spi_slave instantiation start----------------------------------
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// spi_slave
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//---------------------------------------------------------------------------------------------
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sram_if#(25,32) mst(clk);
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sram_if#(20,32) slv[3:0](clk);
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//connect pll
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wire [31 :0] clk_wrdata ;
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wire clk_wren ;
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wire [7 :0] clk_rwaddr ;
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wire clk_rden ;
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wire [31 :0] clk_rddata ;
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//connect system
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wire [31 :0] sys_wrdata ;
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wire sys_wren ;
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wire [24 :0] sys_rwaddr ;
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wire sys_rden ;
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wire [31 :0] sys_rddata ;
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wire pll_rstn_o;
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assign mst.wben = 4'hf;
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spi_slave U_spi_slave (
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.clk ( clk )
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,.rst_n ( pll_rstn_o )
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,.cfgid ( cfgid )
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,.sclk ( sclk )
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,.csn ( csn )
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,.mosi ( mosi )
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,.miso ( miso )
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,.oen ( oen )
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,.pll_wrdata ( clk_wrdata )
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,.pll_wren ( clk_wren )
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,.pll_rwaddr ( clk_rwaddr )
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,.pll_rden ( clk_rden )
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,.pll_rddata ( clk_rddata )
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,.sys_wrdata ( mst.din )
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,.sys_wren ( mst.wren )
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,.sys_rwaddr ( mst.addr )
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,.sys_rden ( mst.rden )
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,.sys_rddata ( mst.dout )
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);
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//---------------------------------------------------------------------------------------------
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// spi_slave
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//------------------------------spi_slave instantiation end------------------------------------
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spi_bus_decoder #(
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.SLVNUM ( `SLVNUM )
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,.SPIBUS_CMD_REG ( `SPIBUS_CMD_REG )
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,.SPIBUS_OUT_REG ( `SPIBUS_OUT_REG )
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) U_spi_bus_decoder (
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.clk ( clk )
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,.rst_n ( pll_rstn_o )
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,.mst ( mst )
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,.slv ( slv )
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);
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//---------------------------------------------------------------------------------------------
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// spi_bus_decoder
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//------------------------------spi_bus_decoder instantiation end------------------------------
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//-----------------------------system_regfile instantiation start------------------------------
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// system_regfile as slave device 0
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//---------------------------------------------------------------------------------------------
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wire [2 :0] awg_status ;
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wire awg_busy ;
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wire sys_soft_rstn ;
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wire [2 :0] dout_sel ;
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wire [15 :0] sync_delay ;
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wire int_sync ;
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wire int_sync_en ;
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wire sync_oen ;
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wire ramp_en ;
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wire [31 :0] ramp_ifs ;
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wire [7 :0] ramp_step ;
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wire ramp_fixed ;
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wire [7 :0] ramp_fixed_value ;
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//LVDS
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wire force_train ;
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wire tap_force ;
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wire [2 :0] tap_step ;
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wire [2 :0] tap_adj_mask ;
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wire [19 :0] train_threshold ;
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wire descram_en ;
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wire always_on ;
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;
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wire link_down ;
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wire train_ready ;
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wire crc_error ;
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wire phase_adj_req ;
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wire [31 :0] frame_success_cnt;
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wire [31 :0] crc_err_cnt ;
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wire prefilling ;
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wire [31 :0] train_status ;
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wire [31 :0] frame_status ;
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//NCO
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wire [47 :0] nco_fcw ;
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wire [15 :0] nco_pha ;
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wire nco_clr ;
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wire nco_en ;
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wire p2a_en ;
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systemregfile U_systemregfile (
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.clk ( clk )
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,.rst_n ( pll_rstn_o )
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,.wrdata ( slv[0].din )
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,.wren ( slv[0].wren )
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,.rwaddr ( slv[0].addr[15:0] )
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,.rden ( slv[0].rden )
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,.rddata ( slv[0].dout )
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,.irq ( irq )
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,.cmd_fifo_full ( cmd_fifo_full )
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,.cmd_fifo_empty ( cmd_fifo_empty )
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,.awg_status ( awg_status )
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,.awg_busy ( awg_busy )
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,.sys_soft_rstn ( sys_soft_rstn )
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,.dout_sel ( dout_sel )
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,.sync_delay ( sync_delay )
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,.int_sync ( int_sync )
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,.int_sync_en ( int_sync_en )
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,.sync_oen ( sync_oen )
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,.ramp_en ( ramp_en )
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,.ramp_ifs ( ramp_ifs )
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,.ramp_step ( ramp_step )
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,.ramp_fixed ( ramp_fixed )
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,.ramp_fixed_value ( ramp_fixed_value )
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,.force_train ( force_train )
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,.tap_force ( tap_force )
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,.tap_step ( tap_step )
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,.tap_adj_mask ( tap_adj_mask )
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,.train_threshold ( train_threshold )
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,.descram_en ( descram_en )
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,.always_on ( always_on )
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,.link_down ( link_down )
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,.train_ready ( train_ready )
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,.crc_error ( crc_error )
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,.phase_adj_req ( phase_adj_req )
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,.phase_tap ( phase_tap )
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,.frame_success_cnt ( frame_success_cnt )
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,.crc_err_cnt ( crc_err_cnt )
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,.prefilling ( prefilling )
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,.train_status ( train_status )
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,.frame_status ( frame_status )
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,.nco_fcw ( nco_fcw )
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,.nco_pha ( nco_pha )
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,.nco_clr ( nco_clr )
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,.nco_en ( nco_en )
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,.p2a_en ( p2a_en )
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);
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//---------------------------------------------------------------------------------------------
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// system_regfile
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//------------------------------system_regfile instantiation end-------------------------------
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//---------------------------------------------------------------------------------------------
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// rst_gen_unit instantiation start
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//---------------------------------------------------------------------------------------------
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wire ch0_rstn_o;
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rst_gen_unit U_rst_gen_unit (
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.async_rstn_i ( rst_n )
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,.por_rstn_i ( 1'b1 )
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,.sys_soft_resetn_i ( sys_soft_rstn )
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,.ch0_soft_rstn_i ( 1'b1 )
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,.ch1_soft_rstn_i ( 1'b1 )
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,.ch2_soft_rstn_i ( 1'b1 )
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,.ch3_soft_rstn_i ( 1'b1 )
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,.clk ( clk )
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,.ch0_rstn_o ( ch0_rstn_o )
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,.ch1_rstn_o ( )
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,.ch2_rstn_o ( )
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,.ch3_rstn_o ( )
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,.pll_rstn_o ( pll_rstn_o )
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);
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//---------------------------------------------------------------------------------------------
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// DW_stream_sync instantiation start
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//---------------------------------------------------------------------------------------------
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wire dst_valid ;
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wire [3 :0] dst_data ;
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wire prefill_d ;
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DW_stream_sync #(
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.width ( 4 )
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,.depth ( 32 )
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,.prefill_lvl ( 16 )
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,.tst_mode ( 0 )
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,.verif_en ( 0 )
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) u_dw_stream_sync (
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.clk_s ( lvds_clk )
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,.rst_s_n ( pll_rstn_o )
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,.init_s_n ( 1'b1 )
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,.clr_s ( 1'b0 )
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,.send_s ( 1'b1 )
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,.data_s ( lvds_data )
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,.clr_sync_s ( )
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,.clr_in_prog_s ( )
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,.clr_cmplt_s ( )
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,.clk_d ( clk )
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,.rst_d_n ( pll_rstn_o )
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,.init_d_n ( 1'b1 )
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,.clr_d ( 1'b0 )
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,.prefill_d ( prefill_d )
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,.clr_in_prog_d ( )
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,.clr_sync_d ( )
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,.clr_cmplt_d ( )
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,.data_avail_d ( dst_valid )
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,.data_d ( dst_data )
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,.prefilling_d ( prefilling )
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,.test ( 1'b0 )
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);
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//---------------------------------------------------------------------------------------------
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// lvds_rx_4ch instantiation start
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//---------------------------------------------------------------------------------------------
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parameter FIFO_DEPTH = 64;
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parameter SCRAMBLER_SEED = 32'hFFFFFFFF;
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wire [511:0] wave_awrdata ;
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wire [0 :0] wave_awren ;
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wire [12 :0] wave_arwaddr ;
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wire [63 :0] wave_awrmask ;
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ulink_rx #(
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.FIFO_DEPTH ( FIFO_DEPTH )
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,.SCRAMBLER_SEED ( SCRAMBLER_SEED )
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) U_ulink_rx (
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.clk ( clk )
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,.rst_n ( pll_rstn_o )
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,.serial_in ( dst_data )
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,.patn_count ( train_threshold )
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,.tap_step ( tap_step )
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,.descram_en ( descram_en )
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,.link_down ( link_down )
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,.delay_tap ( phase_tap )
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,.wr_addr ( wave_arwaddr )
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,.wr_data ( wave_awrdata )
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,.wr_en ( wave_awren )
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,.byte_mask ( wave_awrmask )
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,.crc_error ( crc_error )
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,.tap_adj_mask ( tap_adj_mask )
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,.tap_force ( tap_force )
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,.tap_adj_req ( tap_adj_req )
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,.frame_done ( frame_done )
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,.train_status ( train_status )
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,.frame_status ( frame_status )
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,.always_on ( always_on )
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,.prefilling ( prefilling )
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,.prefill_start ( prefill_d )
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,.train_ready ( train_ready )
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,.force_train ( force_train )
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);
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//---------------------------------------------------------------------------------------------
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// sync_int
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//------------------------------sync_int instantiation start-----------------------------------
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wire sync_int;
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wire sync_pulse;
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syncer #(1, 2) sync_in_syncer (clk, pll_rstn_o, sync_in, sync_int);
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sirv_gnrl_dffr #(1) sync_out_dffr (sync_pulse & sync_oen, sync_out, clk, pll_rstn_o);
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//---------------------------------------------------------------------------------------------
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// Synchronization Signal Delay Adjustment Module instantiation start
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//---------------------------------------------------------------------------------------------
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wire sync_src = (int_sync | sync_int) & int_sync_en;
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pulse_generator pulse_inst_sync (
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.clk ( clk )
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,.rst_n ( pll_rstn_o )
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,.pulse_en ( sync_src )
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,.delay ( sync_delay )
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,.width ( 16'd1 )
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,.inv_en ( 1'b0 )
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,.pulse ( sync_pulse )
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);
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//---------------------------------------------------------------------------------------------
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// sync_int
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//------------------------------sync_int instantiation end-------------------------------------
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//---------------------------------------------------------------------------------------------
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// awg_top instantiation start
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//---------------------------------------------------------------------------------------------
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wire [511:0] wave_data_out_bank ;
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wire [7 :0] awg_data_out [63:0] ;
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wire awg_data_valid ;
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awg_top U_awg_top (
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.clk ( clk )
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,.rst_n ( ch0_rstn_o )
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,.start ( sync_pulse )
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,.wave_awrdata ( wave_awrdata )
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,.wave_awren ( wave_awren )
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,.wave_arwaddr ( wave_arwaddr )
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,.wave_awrmask ( wave_awrmask )
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,.wave_bwrdata ( slv[2].din )
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,.wave_bwren ( slv[2].wren )
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,.wave_brwaddr ( slv[2].addr[18:0] )
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,.wave_brden ( slv[2].rden )
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,.wave_brddata ( slv[2].dout )
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,.cmd_fifo_bwrdata ( slv[1].din )
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,.cmd_fifo_bwren ( slv[1].wren )
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,.cmd_fifo_brwaddr ( slv[1].addr[7 :0] )
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,.cmd_fifo_brden ( slv[1].rden )
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,.cmd_fifo_brddata ( slv[1].dout )
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,.wave_data_out ( wave_data_out_bank )
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,.wave_valid_out ( awg_data_valid )
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,.cmd_fifo_empty ( cmd_fifo_empty )
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,.cmd_fifo_full ( cmd_fifo_full )
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,.status ( awg_status )
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,.wave_busy ( awg_busy )
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);
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genvar i;
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generate
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for(i = 0; i < 64; i++) begin
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assign awg_data_out[i] = wave_data_out_bank[8*i +: 8];
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end
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endgenerate
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//---------------------------------------------------------------------------------------------
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// ramp_gen instantiation start
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//---------------------------------------------------------------------------------------------
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wire [7 :0] ramp_data [63:0];
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wire ramp_vld;
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ramp_gen U_ramp_gen (
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//system port
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.clk ( clk )
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,.rst_n ( ch0_rstn_o )
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,.dac_mode_sel ( 2'b10 )
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,.cen ( ramp_en )
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,.step ( ramp_step )
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,.ifs ( ramp_ifs )
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,.fixed ( ramp_fixed )
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,.fixed_value ( ramp_fixed_value )
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,.ramp ( ramp_data )
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,.ramp_vld ( ramp_vld )
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);
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//------------------------------------------------------------------------------------------
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// 64ch NCO
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//------------------------------------------------------------------------------------------
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wire [7:0] cos [63:0] ;
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wire [7:0] sin [63:0] ;
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NCO #(
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.WIDTH ( 8 )
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,.PARALLEL ( 64 )
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) U_NCO (
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.clk ( clk )
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,.rstn ( ch0_rstn_o )
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,.phase_manual_clr ( nco_clr )
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,.phase_auto_clr ( nco_clr )
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,.fcw ( nco_fcw )
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,.pha ( nco_pha )
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,.nco_en ( nco_en )
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,.p2a_en ( p2a_en )
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,.cos ( cos )
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,.sin ( sin )
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);
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//------------------------------------------------------------------------------------------
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// dout_mux
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//------------------------------------------------------------------------------------------
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wire [7 :0] wave_data_out_i [63:0];
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wire wave_data_valid_i;
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dout_mux #(
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.PARALLEL ( 64 )
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) U_modout_mux (
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. clk ( clk )
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,. rst_n ( ch0_rstn_o )
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,. sel ( dout_sel )
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,.data0 ( awg_data_out )
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,.data0_vld ( awg_data_valid )
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,.data1 ( ramp_data )
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,.data1_vld ( ramp_vld )
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,.data2 ( sin )
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,.data2_vld ( nco_en & p2a_en )
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,.mux_data ( wave_data_out_i )
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,.mux_data_vld ( wave_data_valid_i )
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);
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//---------------------------------------------------------------------------------------------
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// dacif instantiation start
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//---------------------------------------------------------------------------------------------
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dacif dacif_inst (
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.clk ( clk )
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,.rstn ( rst_n )
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,.din_vld ( wave_data_valid_i )
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,.din ( wave_data_out_i )
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,.dout_vld ( wave_data_valid )
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,.dout ( wave_data_out )
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);
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//---------------------------------------------------------------------------------------------
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// dac_regfile instantiation start
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//---------------------------------------------------------------------------------------------
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dac_regfile U_dac_regfile (
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.clk ( clk )
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,.rstn ( ch0_rstn_o )
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,.wrdata ( slv[3].din )
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,.wren ( slv[3].wren )
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,.rwaddr ( slv[3].addr[15:0] )
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,.rden ( slv[3].rden )
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,.rddata ( slv[3].dout )
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,.Rterm ( Rterm )
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,.PrbsEn ( PrbsEn )
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,.Set ( Set )
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,.CasAddr ( CasAddr )
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,.CasDw ( CasDw )
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,.IMainCtrl ( IMainCtrl )
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,.IBleedCtrl ( IBleedCtrl )
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,.ICkCml ( ICkCml )
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,.CurRsv0 ( CurRsv0 )
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,.CurRsv1 ( CurRsv1 )
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);
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//---------------------------------------------------------------------------------------------
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// clk_regfile instantiation start
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//---------------------------------------------------------------------------------------------
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clk_regfile U_clk_regfile (
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.clk ( sclk )
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,.rstn ( pll_rstn_o )
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,.wrdata ( clk_wrdata )
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,.wren ( clk_wren )
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,.rwaddr ( clk_rwaddr )
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,.rden ( clk_rden )
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,.rddata ( clk_rddata )
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,.CcalRstn ( CcalRstn )
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,.EnAllP ( EnAllP )
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,.DccEn ( DccEn )
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,.CasGateCkCtrl ( CasGateCkCtrl )
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,.SpiEnPi ( SpiEnPi )
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,.SpiEnQec ( SpiEnQec )
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,.SpiEnDcc ( SpiEnDcc )
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,.SpiQecCtrlIp ( SpiQecCtrlIp )
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,.SpiQecCtrlIn ( SpiQecCtrlIn )
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,.SpiQecCtrlQp ( SpiQecCtrlQp )
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,.SpiQecCtrlQn ( SpiQecCtrlQn )
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,.SpiDccCtrlIup ( SpiDccCtrlIup )
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,.SpiDccCtrlIdn ( SpiDccCtrlIdn )
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,.SpiDccCtrlQup ( SpiDccCtrlQup )
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,.SpiDccCtrlQdn ( SpiDccCtrlQdn )
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,.SpiSiqNOut ( SpiSiqNOut )
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,.SpiSiqPOut ( SpiSiqPOut )
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,.SpiSiPOut ( SpiSiPOut )
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,.SpiSqPOut ( SpiSqPOut )
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,.CrtlCrossOverN ( CrtlCrossOverN )
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,.CrtlCrossOverP ( CrtlCrossOverP )
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,.CcalRsv0 ( CcalRsv0 )
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,.CcalRsv1 ( CcalRsv1 )
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,.SelCk10GDig ( SelCk10GDig )
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,.SelCk2p5GDig ( SelCk2p5GDig )
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,.SelCk625MDig ( SelCk625MDig )
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,.P2sDataEn ( P2sDataEn )
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,.P2sEnAllP ( P2sEnAllP )
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,.EnPiP ( EnPiP )
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,.CkDivRstn ( CkDivRstn )
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,.p2srsv0 ( p2srsv0 )
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,.p2srsv1 ( p2srsv1 )
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,.CkRxSw ( CkRxSw )
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,.RstnCk ( RstnCk )
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,.CtrlZin ( CtrlZin )
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);
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endmodule
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`include "../define/chip_undefine.v"
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