yangshenbo
/
lin-win-share
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
lin-win-share/DA4008_V1.3/rtl/top/da4008_chip_top.sv

602 lines
26 KiB
Systemverilog
Raw Permalink Blame History

`include "../define/chip_define.v"
module da4008_chip_top (
//spi port
input PI_sclk // Spi Clock
,input PI_csn // Spi Chip Select active low
,input PI_mosi // Spi Mosi
,output PO_miso // Spi Miso
//irq
,output PO_irq
//system port
,input PI_async_rstn
,input PI_sync_in
,output PO_sync_out
,input clk
//lvds rx
,input [3 :0] lvds_data
,input [0 :0] lvds_valid
,input [0 :0] lvds_clk
,output [2 :0] phase_tap
//DAC Data
,output [6 :0] MSB_POS_OUT0
,output [6 :0] MSB_POS_OUT1
,output [6 :0] MSB_POS_OUT2
,output [6 :0] MSB_POS_OUT3
,output [6 :0] MSB_POS_OUT4
,output [6 :0] MSB_POS_OUT5
,output [6 :0] MSB_POS_OUT6
,output [6 :0] MSB_POS_OUT7
,output [6 :0] MSB_POS_OUT8
,output [6 :0] MSB_POS_OUT9
,output [6 :0] MSB_POS_OUT10
,output [6 :0] MSB_POS_OUT11
,output [6 :0] MSB_POS_OUT12
,output [6 :0] MSB_POS_OUT13
,output [6 :0] MSB_POS_OUT14
,output [6 :0] MSB_POS_OUT15
,output [6 :0] MSB_POS_OUT16
,output [6 :0] MSB_POS_OUT17
,output [6 :0] MSB_POS_OUT18
,output [6 :0] MSB_POS_OUT19
,output [6 :0] MSB_POS_OUT20
,output [6 :0] MSB_POS_OUT21
,output [6 :0] MSB_POS_OUT22
,output [6 :0] MSB_POS_OUT23
,output [6 :0] MSB_POS_OUT24
,output [6 :0] MSB_POS_OUT25
,output [6 :0] MSB_POS_OUT26
,output [6 :0] MSB_POS_OUT27
,output [6 :0] MSB_POS_OUT28
,output [6 :0] MSB_POS_OUT29
,output [6 :0] MSB_POS_OUT30
,output [6 :0] MSB_POS_OUT31
,output [4 :0] LSB_POS_OUT0
,output [4 :0] LSB_POS_OUT1
,output [4 :0] LSB_POS_OUT2
,output [4 :0] LSB_POS_OUT3
,output [4 :0] LSB_POS_OUT4
,output [4 :0] LSB_POS_OUT5
,output [4 :0] LSB_POS_OUT6
,output [4 :0] LSB_POS_OUT7
,output [4 :0] LSB_POS_OUT8
,output [4 :0] LSB_POS_OUT9
,output [4 :0] LSB_POS_OUT10
,output [4 :0] LSB_POS_OUT11
,output [4 :0] LSB_POS_OUT12
,output [4 :0] LSB_POS_OUT13
,output [4 :0] LSB_POS_OUT14
,output [4 :0] LSB_POS_OUT15
,output [4 :0] LSB_POS_OUT16
,output [4 :0] LSB_POS_OUT17
,output [4 :0] LSB_POS_OUT18
,output [4 :0] LSB_POS_OUT19
,output [4 :0] LSB_POS_OUT20
,output [4 :0] LSB_POS_OUT21
,output [4 :0] LSB_POS_OUT22
,output [4 :0] LSB_POS_OUT23
,output [4 :0] LSB_POS_OUT24
,output [4 :0] LSB_POS_OUT25
,output [4 :0] LSB_POS_OUT26
,output [4 :0] LSB_POS_OUT27
,output [4 :0] LSB_POS_OUT28
,output [4 :0] LSB_POS_OUT29
,output [4 :0] LSB_POS_OUT30
,output [4 :0] LSB_POS_OUT31
,output [0 :0] MSB_POS_DUM0
,output [0 :0] MSB_POS_DUM1
,output [0 :0] MSB_POS_DUM2
,output [0 :0] MSB_POS_DUM3
,output [0 :0] MSB_POS_DUM4
,output [0 :0] MSB_POS_DUM5
,output [0 :0] MSB_POS_DUM6
,output [0 :0] MSB_POS_DUM7
,output [0 :0] MSB_POS_DUM8
,output [0 :0] MSB_POS_DUM9
,output [0 :0] MSB_POS_DUM10
,output [0 :0] MSB_POS_DUM11
,output [0 :0] MSB_POS_DUM12
,output [0 :0] MSB_POS_DUM13
,output [0 :0] MSB_POS_DUM14
,output [0 :0] MSB_POS_DUM15
,output [0 :0] MSB_POS_DUM16
,output [0 :0] MSB_POS_DUM17
,output [0 :0] MSB_POS_DUM18
,output [0 :0] MSB_POS_DUM19
,output [0 :0] MSB_POS_DUM20
,output [0 :0] MSB_POS_DUM21
,output [0 :0] MSB_POS_DUM22
,output [0 :0] MSB_POS_DUM23
,output [0 :0] MSB_POS_DUM24
,output [0 :0] MSB_POS_DUM25
,output [0 :0] MSB_POS_DUM26
,output [0 :0] MSB_POS_DUM27
,output [0 :0] MSB_POS_DUM28
,output [0 :0] MSB_POS_DUM29
,output [0 :0] MSB_POS_DUM30
,output [0 :0] MSB_POS_DUM31
,output [6 :0] MSB_NEG_OUT0
,output [6 :0] MSB_NEG_OUT1
,output [6 :0] MSB_NEG_OUT2
,output [6 :0] MSB_NEG_OUT3
,output [6 :0] MSB_NEG_OUT4
,output [6 :0] MSB_NEG_OUT5
,output [6 :0] MSB_NEG_OUT6
,output [6 :0] MSB_NEG_OUT7
,output [6 :0] MSB_NEG_OUT8
,output [6 :0] MSB_NEG_OUT9
,output [6 :0] MSB_NEG_OUT10
,output [6 :0] MSB_NEG_OUT11
,output [6 :0] MSB_NEG_OUT12
,output [6 :0] MSB_NEG_OUT13
,output [6 :0] MSB_NEG_OUT14
,output [6 :0] MSB_NEG_OUT15
,output [6 :0] MSB_NEG_OUT16
,output [6 :0] MSB_NEG_OUT17
,output [6 :0] MSB_NEG_OUT18
,output [6 :0] MSB_NEG_OUT19
,output [6 :0] MSB_NEG_OUT20
,output [6 :0] MSB_NEG_OUT21
,output [6 :0] MSB_NEG_OUT22
,output [6 :0] MSB_NEG_OUT23
,output [6 :0] MSB_NEG_OUT24
,output [6 :0] MSB_NEG_OUT25
,output [6 :0] MSB_NEG_OUT26
,output [6 :0] MSB_NEG_OUT27
,output [6 :0] MSB_NEG_OUT28
,output [6 :0] MSB_NEG_OUT29
,output [6 :0] MSB_NEG_OUT30
,output [6 :0] MSB_NEG_OUT31
,output [4 :0] LSB_NEG_OUT0
,output [4 :0] LSB_NEG_OUT1
,output [4 :0] LSB_NEG_OUT2
,output [4 :0] LSB_NEG_OUT3
,output [4 :0] LSB_NEG_OUT4
,output [4 :0] LSB_NEG_OUT5
,output [4 :0] LSB_NEG_OUT6
,output [4 :0] LSB_NEG_OUT7
,output [4 :0] LSB_NEG_OUT8
,output [4 :0] LSB_NEG_OUT9
,output [4 :0] LSB_NEG_OUT10
,output [4 :0] LSB_NEG_OUT11
,output [4 :0] LSB_NEG_OUT12
,output [4 :0] LSB_NEG_OUT13
,output [4 :0] LSB_NEG_OUT14
,output [4 :0] LSB_NEG_OUT15
,output [4 :0] LSB_NEG_OUT16
,output [4 :0] LSB_NEG_OUT17
,output [4 :0] LSB_NEG_OUT18
,output [4 :0] LSB_NEG_OUT19
,output [4 :0] LSB_NEG_OUT20
,output [4 :0] LSB_NEG_OUT21
,output [4 :0] LSB_NEG_OUT22
,output [4 :0] LSB_NEG_OUT23
,output [4 :0] LSB_NEG_OUT24
,output [4 :0] LSB_NEG_OUT25
,output [4 :0] LSB_NEG_OUT26
,output [4 :0] LSB_NEG_OUT27
,output [4 :0] LSB_NEG_OUT28
,output [4 :0] LSB_NEG_OUT29
,output [4 :0] LSB_NEG_OUT30
,output [4 :0] LSB_NEG_OUT31
,output [0 :0] MSB_NEG_DUM0
,output [0 :0] MSB_NEG_DUM1
,output [0 :0] MSB_NEG_DUM2
,output [0 :0] MSB_NEG_DUM3
,output [0 :0] MSB_NEG_DUM4
,output [0 :0] MSB_NEG_DUM5
,output [0 :0] MSB_NEG_DUM6
,output [0 :0] MSB_NEG_DUM7
,output [0 :0] MSB_NEG_DUM8
,output [0 :0] MSB_NEG_DUM9
,output [0 :0] MSB_NEG_DUM10
,output [0 :0] MSB_NEG_DUM11
,output [0 :0] MSB_NEG_DUM12
,output [0 :0] MSB_NEG_DUM13
,output [0 :0] MSB_NEG_DUM14
,output [0 :0] MSB_NEG_DUM15
,output [0 :0] MSB_NEG_DUM16
,output [0 :0] MSB_NEG_DUM17
,output [0 :0] MSB_NEG_DUM18
,output [0 :0] MSB_NEG_DUM19
,output [0 :0] MSB_NEG_DUM20
,output [0 :0] MSB_NEG_DUM21
,output [0 :0] MSB_NEG_DUM22
,output [0 :0] MSB_NEG_DUM23
,output [0 :0] MSB_NEG_DUM24
,output [0 :0] MSB_NEG_DUM25
,output [0 :0] MSB_NEG_DUM26
,output [0 :0] MSB_NEG_DUM27
,output [0 :0] MSB_NEG_DUM28
,output [0 :0] MSB_NEG_DUM29
,output [0 :0] MSB_NEG_DUM30
,output [0 :0] MSB_NEG_DUM31
,output DEM_VLD
//DAC Cfg Port
,output [3 :0] Rterm
,output [2 :0] CasAddr
,output [2 :0] CasDw
,output [9 :0] IMainCtrl
,output [3 :0] IBleedCtrl
,output [3 :0] ICkCml
,output [31 :0] CurRsv0
,output [31 :0] CurRsv1
//CLK Cfg Port
,output [0 :0] CcalRstn
,output [3 :0] EnAllP
,output [0 :0] DccEn
,output [0 :0] CasGateCkCtrl
,output [0 :0] SpiEnPi
,output [0 :0] SpiEnQec
,output [0 :0] SpiEnDcc
,output [4 :0] SpiQecCtrlIp
,output [4 :0] SpiQecCtrlIn
,output [4 :0] SpiQecCtrlQp
,output [4 :0] SpiQecCtrlQn
,output [5 :0] SpiDccCtrlIup
,output [5 :0] SpiDccCtrlIdn
,output [5 :0] SpiDccCtrlQup
,output [5 :0] SpiDccCtrlQdn
,output [7 :0] SpiSiqNOut
,output [7 :0] SpiSiqPOut
,output [3 :0] SpiSiPOut
,output [3 :0] SpiSqPOut
,output [2 :0] CrtlCrossOverN
,output [2 :0] CrtlCrossOverP
,output [31 :0] CcalRsv0
,output [31 :0] CcalRsv1
,output [3 :0] SelCk10GDig
,output [3 :0] SelCk2p5GDig
,output [8 :0] SelCk625MDig
,output [15 :0] P2sDataEn
,output [15 :0] P2sEnAllP
,output [15 :0] EnPiP
,output [15 :0] CkDivRstn
,output [31 :0] p2srsv0
,output [31 :0] p2srsv1
,output [15 :0] CkRxSw
,output [15 :0] RstnCk
,output [15 :0] CtrlZin
);
//------------------------------iopad instantiation start--------------------------------------
// iopad
//---------------------------------------------------------------------------------------------
wire async_rstn ;
wire sync_in ;
wire sync_out ;
wire sclk ;
wire csn ;
wire mosi ;
wire miso ;
wire oen ;
wire irq ;
iopad U_iopad (
//+++++++++++++++++++++++++++++++++++++++++++++//
// PAD Strat //
//+++++++++++++++++++++++++++++++++++++++++++++//
.PI_async_rstn ( PI_async_rstn )
,.PI_sync_in ( PI_sync_in )
,.PO_sync_out ( PO_sync_out )
,.PI_sclk ( PI_sclk )
,.PI_csn ( PI_csn )
,.PI_mosi ( PI_mosi )
,.PO_miso ( PO_miso )
,.PO_irq ( PO_irq )
//+++++++++++++++++++++++++++++++++++++++++++++//
// PAD End //
//+++++++++++++++++++++++++++++++++++++++++++++//
//+++++++++++++++++++++++++++++++++++++++++++++//
// Internal signal Start //
//+++++++++++++++++++++++++++++++++++++++++++++//
,.async_rstn ( async_rstn )
,.sync_in ( sync_in )
,.sync_out ( sync_out )
,.sclk ( sclk )
,.csn ( csn )
,.mosi ( mosi )
,.miso ( miso )
,.oen ( oen )
,.irq_n ( ~irq )
);
//------------------------------spi_slave instantiation start----------------------------------
// spi_slave
//---------------------------------------------------------------------------------------------
wire [7 :0] wave_data_out [63:0] ;
wire wave_data_valid ;
wire [14 :0] Set [63:0] ;
wire PrbsEn ;
digital_top U_digital_top (
.clk ( clk )
,.rst_n ( async_rstn )
,.sync_in ( sync_in )
,.sync_out ( sync_out )
,.cfgid ( 5'b00000 )
,.sclk ( sclk )
,.csn ( csn )
,.mosi ( mosi )
,.miso ( miso )
,.oen ( oen )
,.irq ( irq )
,.wave_data_out ( wave_data_out )
,.wave_data_valid ( wave_data_valid )
,.lvds_data ( lvds_data )
,.lvds_valid ( lvds_valid )
,.lvds_clk ( lvds_clk )
,.phase_tap ( phase_tap )
,.Rterm ( Rterm )
,.PrbsEn ( PrbsEn )
,.Set ( Set )
,.CasAddr ( CasAddr )
,.CasDw ( CasDw )
,.IMainCtrl ( IMainCtrl )
,.IBleedCtrl ( IBleedCtrl )
,.ICkCml ( ICkCml )
,.CurRsv0 ( CurRsv0 )
,.CurRsv1 ( CurRsv1 )
,.CcalRstn ( CcalRstn )
,.EnAllP ( EnAllP )
,.DccEn ( DccEn )
,.CasGateCkCtrl ( CasGateCkCtrl )
,.SpiEnPi ( SpiEnPi )
,.SpiEnQec ( SpiEnQec )
,.SpiEnDcc ( SpiEnDcc )
,.SpiQecCtrlIp ( SpiQecCtrlIp )
,.SpiQecCtrlIn ( SpiQecCtrlIn )
,.SpiQecCtrlQp ( SpiQecCtrlQp )
,.SpiQecCtrlQn ( SpiQecCtrlQn )
,.SpiDccCtrlIup ( SpiDccCtrlIup )
,.SpiDccCtrlIdn ( SpiDccCtrlIdn )
,.SpiDccCtrlQup ( SpiDccCtrlQup )
,.SpiDccCtrlQdn ( SpiDccCtrlQdn )
,.SpiSiqNOut ( SpiSiqNOut )
,.SpiSiqPOut ( SpiSiqPOut )
,.SpiSiPOut ( SpiSiPOut )
,.SpiSqPOut ( SpiSqPOut )
,.CrtlCrossOverN ( CrtlCrossOverN )
,.CrtlCrossOverP ( CrtlCrossOverP )
,.CcalRsv0 ( CcalRsv0 )
,.CcalRsv1 ( CcalRsv1 )
,.SelCk10GDig ( SelCk10GDig )
,.SelCk2p5GDig ( SelCk2p5GDig )
,.SelCk625MDig ( SelCk625MDig )
,.P2sDataEn ( P2sDataEn )
,.P2sEnAllP ( P2sEnAllP )
,.EnPiP ( EnPiP )
,.CkDivRstn ( CkDivRstn )
,.p2srsv0 ( p2srsv0 )
,.p2srsv1 ( p2srsv1 )
,.CkRxSw ( CkRxSw )
,.RstnCk ( RstnCk )
,.CtrlZin ( CtrlZin )
);
//------------------------------spi_slave instantiation start----------------------------------
// DEM
//---------------------------------------------------------------------------------------------
sirv_gnrl_dffr #(1) DEM_VLD_dffr (wave_data_valid, DEM_VLD, clk, async_rstn);
wire [6 :0] MSB_POS_OUT_W [31:0] ;
wire [4 :0] LSB_POS_OUT_W [31:0] ;
wire MSB_POS_DUM_W [31:0] ;
wire [6 :0] MSB_NEG_OUT_W [31:0] ;
wire [4 :0] LSB_NEG_OUT_W [31:0] ;
wire MSB_NEG_DUM_W [31:0] ;
DEM_PhaseSync_4008 U_DEM_PhaseSync_4008 (
.clk ( clk )
,.prbs_en ( PrbsEn )
,.RST_N ( async_rstn )
,.dem_set ( Set )
,.data_in ( wave_data_out )
,.MSB_POS_OUT ( MSB_POS_OUT_W )
,.LSB_POS_OUT ( LSB_POS_OUT_W )
,.MSB_POS_DUM ( MSB_POS_DUM_W )
,.MSB_NEG_OUT ( MSB_NEG_OUT_W )
,.LSB_NEG_OUT ( LSB_NEG_OUT_W )
,.MSB_NEG_DUM ( MSB_NEG_DUM_W )
);
//DAC Data
assign MSB_POS_OUT0 = MSB_POS_OUT_W[0 ];
assign MSB_POS_OUT1 = MSB_POS_OUT_W[1 ];
assign MSB_POS_OUT2 = MSB_POS_OUT_W[2 ];
assign MSB_POS_OUT3 = MSB_POS_OUT_W[3 ];
assign MSB_POS_OUT4 = MSB_POS_OUT_W[4 ];
assign MSB_POS_OUT5 = MSB_POS_OUT_W[5 ];
assign MSB_POS_OUT6 = MSB_POS_OUT_W[6 ];
assign MSB_POS_OUT7 = MSB_POS_OUT_W[7 ];
assign MSB_POS_OUT8 = MSB_POS_OUT_W[8 ];
assign MSB_POS_OUT9 = MSB_POS_OUT_W[9 ];
assign MSB_POS_OUT10 = MSB_POS_OUT_W[10];
assign MSB_POS_OUT11 = MSB_POS_OUT_W[11];
assign MSB_POS_OUT12 = MSB_POS_OUT_W[12];
assign MSB_POS_OUT13 = MSB_POS_OUT_W[13];
assign MSB_POS_OUT14 = MSB_POS_OUT_W[14];
assign MSB_POS_OUT15 = MSB_POS_OUT_W[15];
assign MSB_POS_OUT16 = MSB_POS_OUT_W[16];
assign MSB_POS_OUT17 = MSB_POS_OUT_W[17];
assign MSB_POS_OUT18 = MSB_POS_OUT_W[18];
assign MSB_POS_OUT19 = MSB_POS_OUT_W[19];
assign MSB_POS_OUT20 = MSB_POS_OUT_W[20];
assign MSB_POS_OUT21 = MSB_POS_OUT_W[21];
assign MSB_POS_OUT22 = MSB_POS_OUT_W[22];
assign MSB_POS_OUT23 = MSB_POS_OUT_W[23];
assign MSB_POS_OUT24 = MSB_POS_OUT_W[24];
assign MSB_POS_OUT25 = MSB_POS_OUT_W[25];
assign MSB_POS_OUT26 = MSB_POS_OUT_W[26];
assign MSB_POS_OUT27 = MSB_POS_OUT_W[27];
assign MSB_POS_OUT28 = MSB_POS_OUT_W[28];
assign MSB_POS_OUT29 = MSB_POS_OUT_W[29];
assign MSB_POS_OUT30 = MSB_POS_OUT_W[30];
assign MSB_POS_OUT31 = MSB_POS_OUT_W[31];
assign LSB_POS_OUT0 = LSB_POS_OUT_W[0 ];
assign LSB_POS_OUT1 = LSB_POS_OUT_W[1 ];
assign LSB_POS_OUT2 = LSB_POS_OUT_W[2 ];
assign LSB_POS_OUT3 = LSB_POS_OUT_W[3 ];
assign LSB_POS_OUT4 = LSB_POS_OUT_W[4 ];
assign LSB_POS_OUT5 = LSB_POS_OUT_W[5 ];
assign LSB_POS_OUT6 = LSB_POS_OUT_W[6 ];
assign LSB_POS_OUT7 = LSB_POS_OUT_W[7 ];
assign LSB_POS_OUT8 = LSB_POS_OUT_W[8 ];
assign LSB_POS_OUT9 = LSB_POS_OUT_W[9 ];
assign LSB_POS_OUT10 = LSB_POS_OUT_W[10];
assign LSB_POS_OUT11 = LSB_POS_OUT_W[11];
assign LSB_POS_OUT12 = LSB_POS_OUT_W[12];
assign LSB_POS_OUT13 = LSB_POS_OUT_W[13];
assign LSB_POS_OUT14 = LSB_POS_OUT_W[14];
assign LSB_POS_OUT15 = LSB_POS_OUT_W[15];
assign LSB_POS_OUT16 = LSB_POS_OUT_W[16];
assign LSB_POS_OUT17 = LSB_POS_OUT_W[17];
assign LSB_POS_OUT18 = LSB_POS_OUT_W[18];
assign LSB_POS_OUT19 = LSB_POS_OUT_W[19];
assign LSB_POS_OUT20 = LSB_POS_OUT_W[20];
assign LSB_POS_OUT21 = LSB_POS_OUT_W[21];
assign LSB_POS_OUT22 = LSB_POS_OUT_W[22];
assign LSB_POS_OUT23 = LSB_POS_OUT_W[23];
assign LSB_POS_OUT24 = LSB_POS_OUT_W[24];
assign LSB_POS_OUT25 = LSB_POS_OUT_W[25];
assign LSB_POS_OUT26 = LSB_POS_OUT_W[26];
assign LSB_POS_OUT27 = LSB_POS_OUT_W[27];
assign LSB_POS_OUT28 = LSB_POS_OUT_W[28];
assign LSB_POS_OUT29 = LSB_POS_OUT_W[29];
assign LSB_POS_OUT30 = LSB_POS_OUT_W[30];
assign LSB_POS_OUT31 = LSB_POS_OUT_W[31];
assign MSB_POS_DUM0 = MSB_POS_DUM_W[0 ];
assign MSB_POS_DUM1 = MSB_POS_DUM_W[1 ];
assign MSB_POS_DUM2 = MSB_POS_DUM_W[2 ];
assign MSB_POS_DUM3 = MSB_POS_DUM_W[3 ];
assign MSB_POS_DUM4 = MSB_POS_DUM_W[4 ];
assign MSB_POS_DUM5 = MSB_POS_DUM_W[5 ];
assign MSB_POS_DUM6 = MSB_POS_DUM_W[6 ];
assign MSB_POS_DUM7 = MSB_POS_DUM_W[7 ];
assign MSB_POS_DUM8 = MSB_POS_DUM_W[8 ];
assign MSB_POS_DUM9 = MSB_POS_DUM_W[9 ];
assign MSB_POS_DUM10 = MSB_POS_DUM_W[10];
assign MSB_POS_DUM11 = MSB_POS_DUM_W[11];
assign MSB_POS_DUM12 = MSB_POS_DUM_W[12];
assign MSB_POS_DUM13 = MSB_POS_DUM_W[13];
assign MSB_POS_DUM14 = MSB_POS_DUM_W[14];
assign MSB_POS_DUM15 = MSB_POS_DUM_W[15];
assign MSB_POS_DUM16 = MSB_POS_DUM_W[16];
assign MSB_POS_DUM17 = MSB_POS_DUM_W[17];
assign MSB_POS_DUM18 = MSB_POS_DUM_W[18];
assign MSB_POS_DUM19 = MSB_POS_DUM_W[19];
assign MSB_POS_DUM20 = MSB_POS_DUM_W[20];
assign MSB_POS_DUM21 = MSB_POS_DUM_W[21];
assign MSB_POS_DUM22 = MSB_POS_DUM_W[22];
assign MSB_POS_DUM23 = MSB_POS_DUM_W[23];
assign MSB_POS_DUM24 = MSB_POS_DUM_W[24];
assign MSB_POS_DUM25 = MSB_POS_DUM_W[25];
assign MSB_POS_DUM26 = MSB_POS_DUM_W[26];
assign MSB_POS_DUM27 = MSB_POS_DUM_W[27];
assign MSB_POS_DUM28 = MSB_POS_DUM_W[28];
assign MSB_POS_DUM29 = MSB_POS_DUM_W[29];
assign MSB_POS_DUM30 = MSB_POS_DUM_W[30];
assign MSB_POS_DUM31 = MSB_POS_DUM_W[31];
assign MSB_NEG_OUT0 = MSB_NEG_OUT_W[0 ];
assign MSB_NEG_OUT1 = MSB_NEG_OUT_W[1 ];
assign MSB_NEG_OUT2 = MSB_NEG_OUT_W[2 ];
assign MSB_NEG_OUT3 = MSB_NEG_OUT_W[3 ];
assign MSB_NEG_OUT4 = MSB_NEG_OUT_W[4 ];
assign MSB_NEG_OUT5 = MSB_NEG_OUT_W[5 ];
assign MSB_NEG_OUT6 = MSB_NEG_OUT_W[6 ];
assign MSB_NEG_OUT7 = MSB_NEG_OUT_W[7 ];
assign MSB_NEG_OUT8 = MSB_NEG_OUT_W[8 ];
assign MSB_NEG_OUT9 = MSB_NEG_OUT_W[9 ];
assign MSB_NEG_OUT10 = MSB_NEG_OUT_W[10];
assign MSB_NEG_OUT11 = MSB_NEG_OUT_W[11];
assign MSB_NEG_OUT12 = MSB_NEG_OUT_W[12];
assign MSB_NEG_OUT13 = MSB_NEG_OUT_W[13];
assign MSB_NEG_OUT14 = MSB_NEG_OUT_W[14];
assign MSB_NEG_OUT15 = MSB_NEG_OUT_W[15];
assign MSB_NEG_OUT16 = MSB_NEG_OUT_W[16];
assign MSB_NEG_OUT17 = MSB_NEG_OUT_W[17];
assign MSB_NEG_OUT18 = MSB_NEG_OUT_W[18];
assign MSB_NEG_OUT19 = MSB_NEG_OUT_W[19];
assign MSB_NEG_OUT20 = MSB_NEG_OUT_W[20];
assign MSB_NEG_OUT21 = MSB_NEG_OUT_W[21];
assign MSB_NEG_OUT22 = MSB_NEG_OUT_W[22];
assign MSB_NEG_OUT23 = MSB_NEG_OUT_W[23];
assign MSB_NEG_OUT24 = MSB_NEG_OUT_W[24];
assign MSB_NEG_OUT25 = MSB_NEG_OUT_W[25];
assign MSB_NEG_OUT26 = MSB_NEG_OUT_W[26];
assign MSB_NEG_OUT27 = MSB_NEG_OUT_W[27];
assign MSB_NEG_OUT28 = MSB_NEG_OUT_W[28];
assign MSB_NEG_OUT29 = MSB_NEG_OUT_W[29];
assign MSB_NEG_OUT30 = MSB_NEG_OUT_W[30];
assign MSB_NEG_OUT31 = MSB_NEG_OUT_W[31];
assign LSB_NEG_OUT0 = LSB_NEG_OUT_W[0 ];
assign LSB_NEG_OUT1 = LSB_NEG_OUT_W[1 ];
assign LSB_NEG_OUT2 = LSB_NEG_OUT_W[2 ];
assign LSB_NEG_OUT3 = LSB_NEG_OUT_W[3 ];
assign LSB_NEG_OUT4 = LSB_NEG_OUT_W[4 ];
assign LSB_NEG_OUT5 = LSB_NEG_OUT_W[5 ];
assign LSB_NEG_OUT6 = LSB_NEG_OUT_W[6 ];
assign LSB_NEG_OUT7 = LSB_NEG_OUT_W[7 ];
assign LSB_NEG_OUT8 = LSB_NEG_OUT_W[8 ];
assign LSB_NEG_OUT9 = LSB_NEG_OUT_W[9 ];
assign LSB_NEG_OUT10 = LSB_NEG_OUT_W[10];
assign LSB_NEG_OUT11 = LSB_NEG_OUT_W[11];
assign LSB_NEG_OUT12 = LSB_NEG_OUT_W[12];
assign LSB_NEG_OUT13 = LSB_NEG_OUT_W[13];
assign LSB_NEG_OUT14 = LSB_NEG_OUT_W[14];
assign LSB_NEG_OUT15 = LSB_NEG_OUT_W[15];
assign LSB_NEG_OUT16 = LSB_NEG_OUT_W[16];
assign LSB_NEG_OUT17 = LSB_NEG_OUT_W[17];
assign LSB_NEG_OUT18 = LSB_NEG_OUT_W[18];
assign LSB_NEG_OUT19 = LSB_NEG_OUT_W[19];
assign LSB_NEG_OUT20 = LSB_NEG_OUT_W[20];
assign LSB_NEG_OUT21 = LSB_NEG_OUT_W[21];
assign LSB_NEG_OUT22 = LSB_NEG_OUT_W[22];
assign LSB_NEG_OUT23 = LSB_NEG_OUT_W[23];
assign LSB_NEG_OUT24 = LSB_NEG_OUT_W[24];
assign LSB_NEG_OUT25 = LSB_NEG_OUT_W[25];
assign LSB_NEG_OUT26 = LSB_NEG_OUT_W[26];
assign LSB_NEG_OUT27 = LSB_NEG_OUT_W[27];
assign LSB_NEG_OUT28 = LSB_NEG_OUT_W[28];
assign LSB_NEG_OUT29 = LSB_NEG_OUT_W[29];
assign LSB_NEG_OUT30 = LSB_NEG_OUT_W[30];
assign LSB_NEG_OUT31 = LSB_NEG_OUT_W[31];
assign MSB_NEG_DUM0 = MSB_NEG_DUM_W[0 ];
assign MSB_NEG_DUM1 = MSB_NEG_DUM_W[1 ];
assign MSB_NEG_DUM2 = MSB_NEG_DUM_W[2 ];
assign MSB_NEG_DUM3 = MSB_NEG_DUM_W[3 ];
assign MSB_NEG_DUM4 = MSB_NEG_DUM_W[4 ];
assign MSB_NEG_DUM5 = MSB_NEG_DUM_W[5 ];
assign MSB_NEG_DUM6 = MSB_NEG_DUM_W[6 ];
assign MSB_NEG_DUM7 = MSB_NEG_DUM_W[7 ];
assign MSB_NEG_DUM8 = MSB_NEG_DUM_W[8 ];
assign MSB_NEG_DUM9 = MSB_NEG_DUM_W[9 ];
assign MSB_NEG_DUM10 = MSB_NEG_DUM_W[10];
assign MSB_NEG_DUM11 = MSB_NEG_DUM_W[11];
assign MSB_NEG_DUM12 = MSB_NEG_DUM_W[12];
assign MSB_NEG_DUM13 = MSB_NEG_DUM_W[13];
assign MSB_NEG_DUM14 = MSB_NEG_DUM_W[14];
assign MSB_NEG_DUM15 = MSB_NEG_DUM_W[15];
assign MSB_NEG_DUM16 = MSB_NEG_DUM_W[16];
assign MSB_NEG_DUM17 = MSB_NEG_DUM_W[17];
assign MSB_NEG_DUM18 = MSB_NEG_DUM_W[18];
assign MSB_NEG_DUM19 = MSB_NEG_DUM_W[19];
assign MSB_NEG_DUM20 = MSB_NEG_DUM_W[20];
assign MSB_NEG_DUM21 = MSB_NEG_DUM_W[21];
assign MSB_NEG_DUM22 = MSB_NEG_DUM_W[22];
assign MSB_NEG_DUM23 = MSB_NEG_DUM_W[23];
assign MSB_NEG_DUM24 = MSB_NEG_DUM_W[24];
assign MSB_NEG_DUM25 = MSB_NEG_DUM_W[25];
assign MSB_NEG_DUM26 = MSB_NEG_DUM_W[26];
assign MSB_NEG_DUM27 = MSB_NEG_DUM_W[27];
assign MSB_NEG_DUM28 = MSB_NEG_DUM_W[28];
assign MSB_NEG_DUM29 = MSB_NEG_DUM_W[29];
assign MSB_NEG_DUM30 = MSB_NEG_DUM_W[30];
assign MSB_NEG_DUM31 = MSB_NEG_DUM_W[31];
endmodule
`include "../define/chip_undefine.v"
Reference in New Issue View Git Blame Copy Permalink