818 lines
30 KiB
Verilog
818 lines
30 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : ssytem_regfile.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 1.0 2026-03-01 PWY
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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// -----------------------------------------------------------
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// -- Register address offset macros
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// -----------------------------------------------------------
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//Identity Register
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`define IDR 16'h00
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//Vendor Code Register
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`define VIDR 16'h04
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//RTL Freeze Date Register
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`define DATER 16'h08
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//Version Register
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`define VERR 16'h0C
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//Wirte And Read Test Register
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`define TESTR 16'h10
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//Status Register
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`define ISR 16'h14
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//Soft Reset Time Register
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`define SFRTR 16'h18
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//Soft Reset Register
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`define SFRR 16'h1C
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//Sync Cntrl Register
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`define SYNCR 16'h20
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//Ramp Ctrl Register
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`define RAMPCTR 16'h24
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//Ramp IFS Register
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`define RAMPIFSR 16'h28
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//Data Out Select Register
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`define DOSELR 16'h2C
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//Lvds Force Train Register
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`define LVDSFTR 16'h30
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//Lvds Tap Force Register
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`define LVDSTFR 16'h34
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//Lvds Tap Step Register
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`define LVDSTSR 16'h38
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//Lvds Train Threshold Register
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`define LVDSTHR 16'h3C
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//Lvds Tap Adj Mask Register
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`define LVDSTAMR 16'h40
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//Lvds Descram Enable Register
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`define LVDSDSER 16'h44
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//Lvds Train Always On Register
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`define LVDSTAOR 16'h48
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//Lvds Status Register
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`define LVDSSR 16'h4C
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//Lvds Frame Success Count Register
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`define LVDSFSCR 16'h50
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//Lvds CRC Error Count Register
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`define LVDSCECR 16'h54
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//Lvds Frame Status Register
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`define LVDSFSTR 16'h58
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//Lvds Train Status Register
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`define LVDSTSTR 16'h5C
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//Interrupt Mask Register
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//[31 :6] --> Reserved
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//[5 ] --> crc_error Interrupt Mask
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//[4 ] --> phase_adj_req Interrupt Mask
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//[3 ] --> train_ready Interrupt Mask
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//[2 ] --> link_down Interrupt Mask
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//[1 ] --> cmd_fifo_empty Interrupt Mask
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//[0 ] --> cmd_fifo_full Interrupt Mask
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`define IMR 16'h60
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//Interrupt Mask Register
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//[31 :6] --> Reserved
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//[5 ] --> crc_error Masked Interrupt Status
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//[4 ] --> phase_adj_req Masked Interrupt Status
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//[3 ] --> train_ready Masked Interrupt Status
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//[2 ] --> link_down Masked Interrupt Status
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//[1 ] --> cmd_fifo_empty Masked Interrupt Status
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//[0 ] --> cmd_fifo_full Masked Interrupt Status
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`define MISR 16'h64
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//NCO Frequency Control Word High Register
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`define NCOFCWHR 16'h68
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//NCO Frequency Control Word Low Register
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`define NCOFCWLR 16'h6C
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//NCO Phase Control Word Register
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`define NCOPCWR 16'h70
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//NCO Control Register
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`define NCOCTLR 16'h74
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module systemregfile # (
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parameter CHIPCODE = 32'hDA400801 // 32'hDA400801:DA4008-01
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,parameter MFDATE = 32'h20260510 // The production date is May 10, 2026
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)(
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//system port
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input clk // System Main Clock
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,input rst_n // Spi Reset active low
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//rw op port
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,input [31 :0] wrdata // write data
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,input wren // write enable
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,input [15 :0] rwaddr // read & write address
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,input rden // read enable
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,output [31 :0] rddata // read data
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//irq
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,output irq
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//Status input
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,input cmd_fifo_full
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,input cmd_fifo_empty
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,input [2 :0] awg_status
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,input awg_busy
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//Soft Reset out
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,output sys_soft_rstn
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//Data Out Select port
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,output [2 :0] dout_sel //1'b0: Sram Data; 1'b1: Ramp Data;
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//SYNC Ctrl
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,output [15 :0] sync_delay
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,output int_sync
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,output int_sync_en
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,output sync_oen
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//Ramp Cntrl Signals
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,output ramp_en //ramp_en = dout_sel[0];
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,output [31 :0] ramp_ifs
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,output [7 :0] ramp_step
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,output ramp_fixed
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,output [7 :0] ramp_fixed_value
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//LVDS
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,output force_train
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,output tap_force
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,output [2 :0] tap_step
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,output [2 :0] tap_adj_mask
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,output [19 :0] train_threshold
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,output descram_en
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,output always_on
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,input link_down
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,input train_ready
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,input crc_error
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,input phase_adj_req
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,input [2 :0] phase_tap
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,input [31 :0] frame_success_cnt
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,input [31 :0] crc_err_cnt
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,input prefilling
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,input [31 :0] train_status
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,input [31 :0] frame_status
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//NCO
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,output [47:0] nco_fcw
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,output [15:0] nco_pha
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,output nco_clr
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,output nco_en
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,output p2a_en
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);
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localparam L = 1'b0,
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H = 1'b1;
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localparam IDRD = CHIPCODE;
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localparam VIDRD = 32'h58445500;
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localparam DATERD = MFDATE;
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localparam VERSION = 32'h00000001;
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localparam TESTRD = 32'h01234567;
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// ------------------------------------------------------
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// -- Register enable (select) wires
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// ------------------------------------------------------
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wire idren ; // IDR select
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wire vidren ; // VIDR select
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wire dateren ; // DATER select
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wire verren ; // VERR select
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wire testren ; // TESTR select
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wire isren ; // ISR select
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wire sfrtren ; // MISR select
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wire sfrren ; // SFRTR select
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wire syncren ; // SFRR select
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wire rampctren ; // RAMPCTR select
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wire rampifsren ; // RAMPIFSR select
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wire doselren ; // DOSELR select
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wire lvdsftren ; // LVDSFTR select
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wire lvdstfren ; // LVDSTFR select
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wire lvdstsren ; // LVDSTSR select
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wire lvdsthren ; // LVDSTHR select
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wire lvdssren ; // LVDSSR select
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wire lvdsfcsren ; // LVDSFSCR select
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wire lvdscecren ; // LVDSCECR select
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wire lvdstamren ; // LVDSTAMR select
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wire lvdsdseren ; // LVDSDSER select
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wire lvdstaoren ; // LVDSTAOR select
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wire lvdsfstren ; // LVDSFSTR select
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wire lvdststren ; // LVDSTSTR select
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wire imren ; // IMR select
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wire misren ; // MISR select
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wire ncofcwhren ; // NCOFCWHR select
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wire ncofcwlren ; // NCOFCWLR select
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wire ncopcwren ; // NCOPCWR select
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wire ncoctrlren ; // NCOCTLR select
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// ------------------------------------------------------
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// -- Register write enable wires
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// ------------------------------------------------------
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wire testrwe ; // testr write enable
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wire sfrtrwe ; // sfrtr write enable
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wire sfrrwe ; // sfrr write enable
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wire syncrwe ; // syncr write enable
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wire rampctrwe ; // RAMPCTR write enable
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wire rampifsrwe ; // RAMPIFSR write enable
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wire doselrwe ; // DOSELR write enable
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wire lvdsftrwe ; // LVDSFTR write enable
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wire lvdsatrwe ; // LVDSATR write enable
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wire lvdstsrwe ; // LVDSTSR write enable
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wire lvdsthrwe ; // LVDSTHR write enable
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wire lvdsdserwe ; // LVDSDSER write enable
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wire lvdstaorwe ; // LVDSTAOR write enable
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wire imrwe ; // IMR write enable
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wire ncofcwhrwe ; // NCOFCWHR write enable
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wire ncofcwlrwe ; // NCOFCWLR write enable
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wire ncopcwrwe ; // NCOPCWR write enable
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wire ncoctrlrwe ; // NCOCTLR write enable
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// ------------------------------------------------------
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// -- Misc wires
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// ------------------------------------------------------
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wire [5 :0] irisr ; // original status wire
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// ------------------------------------------------------
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// -- Misc Registers
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// ------------------------------------------------------
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wire [31 :0] testr ;
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wire [5 :0] isr ;
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wire [31 :0] sfrtr ;
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wire [0 :0] sfrr ;
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wire [18 :0] syncr ;
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wire [23 :0] rampctr ;
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wire [31 :0] rampifsr ;
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wire [2 :0] doselr ;
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wire [0 :0] lvdsftr ;
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wire [0 :0] lvdsatr ;
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wire [2 :0] lvdstsr ;
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wire [19 :0] lvdsthr ;
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wire [7 :0] lvdssr ;
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wire [31 :0] lvdsfcsr ;
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wire [31 :0] lvdscecr ;
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wire [2 :0] lvdstamr ;
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wire [0 :0] lvdsdser ;
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wire [0 :0] lvdstaor ;
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wire [31 :0] lvdsfstr ;
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wire [31 :0] lvdststr ;
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wire [5 :0] imr ;
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wire [5 :0] misr ;
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wire [31 :0] ncofcwhr ;
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wire [15 :0] ncofcwlr ;
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wire [15 :0] ncopcwr ;
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wire [2 :0] ncoctrlr ;
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reg [31 :0] rddata_reg ;
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// ------------------------------------------------------
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// -- Address decoder
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//
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// Decodes the register address offset input(reg_addr)
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// to produce enable (select) signals for each of the
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// SW-registers in the macrocell. The reg_addr input
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// is bits [8:0] of the paddr bus.
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// ------------------------------------------------------
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assign idren = (rwaddr[15:2] == `IDR >> 2) ? 1'b1 : 1'b0;
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assign vidren = (rwaddr[15:2] == `VIDR >> 2) ? 1'b1 : 1'b0;
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assign dateren = (rwaddr[15:2] == `DATER >> 2) ? 1'b1 : 1'b0;
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assign verren = (rwaddr[15:2] == `VERR >> 2) ? 1'b1 : 1'b0;
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assign testren = (rwaddr[15:2] == `TESTR >> 2) ? 1'b1 : 1'b0;
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assign isren = (rwaddr[15:2] == `ISR >> 2) ? 1'b1 : 1'b0;
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assign sfrtren = (rwaddr[15:2] == `SFRTR >> 2) ? 1'b1 : 1'b0;
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assign sfrren = (rwaddr[15:2] == `SFRR >> 2) ? 1'b1 : 1'b0;
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assign syncren = (rwaddr[15:2] == `SYNCR >> 2) ? 1'b1 : 1'b0;
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assign rampctren = (rwaddr[15:2] == `RAMPCTR >> 2) ? 1'b1 : 1'b0;
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assign rampifsren = (rwaddr[15:2] == `RAMPIFSR >> 2) ? 1'b1 : 1'b0;
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assign doselren = (rwaddr[15:2] == `DOSELR >> 2) ? 1'b1 : 1'b0;
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assign lvdsftren = (rwaddr[15:2] == `LVDSFTR >> 2) ? 1'b1 : 1'b0;
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assign lvdstfren = (rwaddr[15:2] == `LVDSTFR >> 2) ? 1'b1 : 1'b0;
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assign lvdstsren = (rwaddr[15:2] == `LVDSTSR >> 2) ? 1'b1 : 1'b0;
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assign lvdsthren = (rwaddr[15:2] == `LVDSTHR >> 2) ? 1'b1 : 1'b0;
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assign lvdssren = (rwaddr[15:2] == `LVDSSR >> 2) ? 1'b1 : 1'b0;
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assign lvdsfcsren = (rwaddr[15:2] == `LVDSFSCR >> 2) ? 1'b1 : 1'b0;
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assign lvdscecren = (rwaddr[15:2] == `LVDSCECR >> 2) ? 1'b1 : 1'b0;
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assign lvdstamren = (rwaddr[15:2] == `LVDSTAMR >> 2) ? 1'b1 : 1'b0;
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assign lvdsdseren = (rwaddr[15:2] == `LVDSDSER >> 2) ? 1'b1 : 1'b0;
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assign lvdstaoren = (rwaddr[15:2] == `LVDSTAOR >> 2) ? 1'b1 : 1'b0;
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assign lvdsfstren = (rwaddr[15:2] == `LVDSFSTR >> 2) ? 1'b1 : 1'b0;
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assign lvdststren = (rwaddr[15:2] == `LVDSTSTR >> 2) ? 1'b1 : 1'b0;
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assign imren = (rwaddr[15:2] == `IMR >> 2) ? 1'b1 : 1'b0;
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assign misren = (rwaddr[15:2] == `MISR >> 2) ? 1'b1 : 1'b0;
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assign ncofcwhren = (rwaddr[15:2] == `NCOFCWHR >> 2) ? 1'b1 : 1'b0;
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assign ncofcwlren = (rwaddr[15:2] == `NCOFCWLR >> 2) ? 1'b1 : 1'b0;
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assign ncopcwren = (rwaddr[15:2] == `NCOPCWR >> 2) ? 1'b1 : 1'b0;
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assign ncoctrlren = (rwaddr[15:2] == `NCOCTLR >> 2) ? 1'b1 : 1'b0;
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// ------------------------------------------------------
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// -- Write enable signals
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//
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// Write enable signals for writable SW-registers.
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// The write enable for each register is the ANDed
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// result of the register enable and the input reg_wren
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// ------------------------------------------------------
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assign testrwe = testren & wren;
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assign sfrtrwe = sfrtren & wren;
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assign sfrrwe = sfrren & wren;
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assign syncrwe = syncren & wren;
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assign rampctrwe = rampctren & wren;
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assign rampifsrwe = rampifsren & wren;
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assign doselrwe = doselren & wren;
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assign lvdsftrwe = lvdsftren & wren;
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assign lvdstfrwe = lvdstfren & wren;
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assign vdstsrwe = lvdstsren & wren;
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assign lvdsthrwe = lvdsthren & wren;
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assign lvdstamrwe = lvdstamren & wren;
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assign lvdsdserwe = lvdsdseren & wren;
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assign ncofcwhrwe = ncofcwhren & wren;
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assign ncofcwlrwe = ncofcwlren & wren;
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assign ncopcwrwe = ncopcwren & wren;
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assign ncoctrlrwe = ncoctrlren & wren;
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assign imrwe = imren & wren;
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// ------------------------------------------------------
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// -- testr Register
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//
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// Write testr for 'TESTR' : 32-bit register
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// Register is split into the following bit fields
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//
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// [31:0] --> testr
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(32) testr_dfflrd (TESTRD, testrwe, wrdata[31:0], testr, clk, rst_n);
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// ------------------------------------------------------
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// -- Soft Reset Count Register
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//
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// Write Soft Reset Count for 'sfrtcr' : 6-bit register
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// Register is split into the following bit fields
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//
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// [31:0] --> sfrtcr,default value 32'd300
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(32) sfrtr_dfflrd (32'd1, sfrtrwe, wrdata[31:0], sfrtr, clk, rst_n);/////////////////////////////sfrtcr-->sfrtr
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// ------------------------------------------------------
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// -- SYNC Contrl Register
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//
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//
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// [17 ] --> sync_oen ,default value 1'b0
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// [17 ] --> int_sync_en,default value 1'b0
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// [16 ] --> int_sync ,default value 1'b0
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// [15:0] --> sync_delay ,default value 16'd0
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// ------------------------------------------------------
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//sirv_gnrl_dfflr #(18) syncr_dfflr (syncrwe, wrdata[17:0], syncr, clk, rst_n);
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// sirv_gnrl_dfflr #(17) syncr_dfflr (syncrwe, {syncrwe,wrdata[15:0]}, syncr, clk, rst_n); //pwy-20250808
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sirv_gnrl_dfflrd #(16) syncr_dfflrd (16'd1, syncrwe, wrdata[15:0], syncr[15:0], clk, rst_n); //pwy-20250808
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sirv_gnrl_dffr #(1) syncr16_dffr (syncrwe & wrdata[16], syncr[16], clk, rst_n); //pwy-20250808
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sirv_gnrl_dfflrd #(1) syncr16_dfflrd (1'b1, syncrwe, wrdata[17], syncr[17], clk, rst_n); //pwy-20250808
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sirv_gnrl_dfflrd #(1) sync_oen_dfflrd (1'b0, syncrwe, wrdata[18], syncr[18], clk, rst_n); //pwy-20260303
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// ------------------------------------------------------
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// -- rampctr register
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//
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// Write rampctr for 'RAMPCTR' : 24-bit register
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// Register is split into the following bit fields
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//
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// [23:0] --> rampctr
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// ------------------------------------------------------
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sirv_gnrl_dfflr #(24) rampctr_dfflrs (rampctrwe, wrdata[23:0], rampctr, clk, rst_n);
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// ------------------------------------------------------
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// -- rampifsr register
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//
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// Write rampifsr for 'rampifsr' : 32-bit register
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// Register is split into the following bit fields
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//
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// [31:0] --> ramp_ifs
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// ------------------------------------------------------
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sirv_gnrl_dfflr #(32) ramp_ifs_dfflrs (rampifsrwe, wrdata[31:0], rampifsr, clk, rst_n);
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// ------------------------------------------------------
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// -- doselr register
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//
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// Write doselr for 'DOSELR' : 3-bit register
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// Register is split into the following bit fields
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//
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// [2:0] --> doselr
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(3) doselr_dfflrd (3'b001, doselrwe, wrdata[2:0], doselr, clk, rst_n);
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// ------------------------------------------------------
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// -- lvdsftr Register
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//
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// Write lvdsftr for 'LVDSFTR' : 1-bit register
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// Register is split into the following bit fields
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//
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// [0:0] --> lvdsftr
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// ------------------------------------------------------
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sirv_gnrl_dffr #(1) lvdsftr_dffr (lvdsftrwe & wrdata[0], lvdsftr, clk, rst_n);
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// ------------------------------------------------------
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// -- lvdstfr register
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//
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// Write lvdstfr for 'LVDSTFR' : 1-bit register
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// Register is split into the following bit fields
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//
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// [0:0] --> lvdstfr
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// ------------------------------------------------------
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sirv_gnrl_dfflr #(1) lvdstfr_dfflrs (lvdstfrwe, wrdata[0], lvdstfr, clk, rst_n);
|
|
|
|
// ------------------------------------------------------
|
|
// -- lvdstsr register
|
|
//
|
|
// Write lvdstsr for 'LVDSTSR' : 1-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [2:0] --> lvdstsr
|
|
// ------------------------------------------------------
|
|
sirv_gnrl_dfflrd #(3) lvdstsr_dfflrd (3'd1, lvdstsrwe, wrdata[2:0], lvdstsr, clk, rst_n);
|
|
|
|
// ------------------------------------------------------
|
|
// -- lvdsthr register
|
|
//
|
|
// Write lvdsthr for 'LVDSTHR' : 20-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [19:0] --> lvdsthr
|
|
// ------------------------------------------------------
|
|
sirv_gnrl_dfflrd #(20) lvdsthr_dfflrd (20'd100, lvdsthrwe, wrdata[19:0], lvdsthr, clk, rst_n);
|
|
|
|
// ------------------------------------------------------
|
|
// -- lvdstamr register
|
|
//
|
|
// Write lvdsfcsr for 'LVDSTAMR' : 3-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [2:0] --> lvdstamr
|
|
// ------------------------------------------------------
|
|
sirv_gnrl_dfflrd #(3) lvdstamr_dfflrd (3'b111, lvdstamrwe, wrdata[2:0], lvdstamr, clk, rst_n);
|
|
|
|
// ------------------------------------------------------
|
|
// -- lvdsdser register
|
|
//
|
|
// Write lvdsfcsr for 'LVDSDSER' : 1-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [0:0] --> lvdsdser
|
|
// ------------------------------------------------------
|
|
sirv_gnrl_dfflrd #(1) lvdsdser_dfflrd (1'b1, lvdsdserwe, wrdata[0], lvdsdser, clk, rst_n);
|
|
|
|
|
|
// ------------------------------------------------------
|
|
// -- lvdstaor register
|
|
//
|
|
// Write lvdstaor for 'LVDSTAOR' : 1-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [0:0] --> lvdstaor
|
|
// ------------------------------------------------------
|
|
sirv_gnrl_dfflrd #(1) lvdstaor_dfflrd (1'b1, lvdstaorwe, wrdata[0], lvdstaor, clk, rst_n);
|
|
|
|
// ------------------------------------------------------
|
|
// -- lvdssr register
|
|
//
|
|
// Write lvdssr for 'LVDSSR' : 8-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [7:0] --> lvdssr
|
|
// ------------------------------------------------------
|
|
sirv_gnrl_dffr #(8) llvdssr_dffr ({ link_down ,train_ready ,crc_error ,
|
|
phase_adj_req ,phase_tap[2:0] ,
|
|
prefilling }, lvdssr, clk, rst_n);
|
|
|
|
// ------------------------------------------------------
|
|
// -- lvdsfcsr register
|
|
//
|
|
// Write lvdsfcsr for 'LVDSFSCR' : 32-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [31:0] --> lvdsfcsr
|
|
// ------------------------------------------------------
|
|
sirv_gnrl_dffr #(32) lvdsfcsr_dffr (frame_success_cnt, lvdsfcsr, clk, rst_n);
|
|
|
|
|
|
// ------------------------------------------------------
|
|
// -- lvdscecr register
|
|
//
|
|
// Write lvdscecr for 'LVDSCECR' : 32-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [31:0] --> lvdscecr
|
|
// ------------------------------------------------------
|
|
sirv_gnrl_dffr #(32) lvdscecr_dffr (crc_err_cnt, lvdscecr, clk, rst_n);
|
|
|
|
// ------------------------------------------------------
|
|
// -- lvdsfstr register
|
|
//
|
|
// Write lvdsfstr for 'LVDSFSR' : 32-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [31:0] --> lvdsfstr
|
|
// ------------------------------------------------------
|
|
sirv_gnrl_dffr #(32) lvdsfstr_dffr (frame_status, lvdsfstr, clk, rst_n);
|
|
|
|
// ------------------------------------------------------
|
|
// -- lvdststr register
|
|
//
|
|
// Write lvdststr for 'LVDTFSR' : 32-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [31:0] --> lvdststr
|
|
// ------------------------------------------------------
|
|
sirv_gnrl_dffr #(32) lvdststr_dffr (train_status, lvdststr, clk, rst_n);
|
|
|
|
|
|
// ------------------------------------------------------
|
|
// -- ncofcwhr register
|
|
//
|
|
// Write ncofcwhr for 'NCOFCWHR' : 32-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [31:0] --> ncofcwhr
|
|
// ------------------------------------------------------
|
|
sirv_gnrl_dfflrd #(32) ncofcwhr_dfflrd (32'b0, ncofcwhrwe, wrdata[31:0], ncofcwhr, clk, rst_n);
|
|
|
|
|
|
// ------------------------------------------------------
|
|
// -- ncofcwlr register
|
|
//
|
|
// Write ncofcwlr for 'NCOFCWLR' : 32-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [15:0] --> ncofcwlr
|
|
// ------------------------------------------------------
|
|
sirv_gnrl_dfflrd #(16) ncofcwlr_dfflrd (16'b0, ncofcwlrwe, wrdata[15:0], ncofcwlr, clk, rst_n);
|
|
|
|
// ------------------------------------------------------
|
|
// -- ncopcwr register
|
|
//
|
|
// Write ncopcwr for 'NCOPCWR' : 32-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [15:0] --> ncopcwr
|
|
// ------------------------------------------------------
|
|
sirv_gnrl_dfflrd #(16) ncopcwr_dfflrd (16'b0, ncopcwrwe, wrdata[15:0], ncopcwr, clk, rst_n);
|
|
|
|
// ------------------------------------------------------
|
|
// -- NCO Contrl Register
|
|
//
|
|
//
|
|
// [2 ] --> nco_clr ,default value 1'b0
|
|
// [1 ] --> nco_en ,default value 1'b0
|
|
// [0 ] --> p2a_en ,default value 1'b0
|
|
// ------------------------------------------------------
|
|
|
|
sirv_gnrl_dffr #(1) ncoctrlr2_dffr (ncoctrlrwe & wrdata[2], ncoctrlr[2], clk, rst_n);
|
|
sirv_gnrl_dfflrd #(2) ncoctrlr12_dfflrd (2'b0, ncoctrlrwe, wrdata[1:0], ncoctrlr[1:0], clk, rst_n);
|
|
|
|
|
|
// ---------------------------------------------------------------------------------------------------
|
|
// -- interrupt Mask Register
|
|
//
|
|
// Write interrupt Mask for 'imr' : 6-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
//Interrupt Mask Register
|
|
//[31 :6] --> Reserved
|
|
//[5 ] --> crc_error Interrupt Mask
|
|
//[4 ] --> phase_adj_req Interrupt Mask
|
|
//[3 ] --> train_ready Interrupt Mask
|
|
//[2 ] --> link_down Interrupt Mask
|
|
//[1 ] --> cmd_fifo_empty Interrupt Mask
|
|
//[0 ] --> cmd_fifo_full Interrupt Mask
|
|
// ---------------------------------------------------------------------------------------------------
|
|
sirv_gnrl_dfflr #(6) imr_dfflr (imrwe, wrdata[5:0], imr, clk, rst_n);
|
|
|
|
// ------------------------------------------------------
|
|
// -- soft reset count
|
|
// ------------------------------------------------------
|
|
|
|
wire [31:0] cnt_c;
|
|
wire sys_soft_rstn_r;
|
|
wire add_cnt = (sys_soft_rstn_r == L) ;
|
|
|
|
wire end_cnt = add_cnt & (cnt_c == sfrtr-1);
|
|
|
|
wire [31:0] cnt_n = end_cnt ? 32'h0 :
|
|
add_cnt ? cnt_c + 1'b1 :
|
|
cnt_c ;
|
|
|
|
|
|
sirv_gnrl_dffr #(32) cnt_c_dffr (cnt_n, cnt_c, clk, rst_n);
|
|
|
|
// ------------------------------------------------------
|
|
// -- Soft Reset Register
|
|
//
|
|
// Write Soft Reset for 'sfrtr' : 1-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [16'h001C] --> System Soft Reset ,low active
|
|
// ------------------------------------------------------
|
|
|
|
//sys_soft_rstn_r
|
|
wire sys_soft_rstn_en = end_cnt | sfrrwe;
|
|
wire sys_soft_rstn_w = end_cnt ? 1'b1 :
|
|
sfrrwe ? 1'b0 :
|
|
1'b1 ;
|
|
sirv_gnrl_dfflrs #(1) sys_soft_rstn_r_dffls (sys_soft_rstn_en, sys_soft_rstn_w, sys_soft_rstn_r, clk, rst_n);
|
|
|
|
assign sys_soft_rstn = sys_soft_rstn_r;
|
|
|
|
|
|
// ------------------------------------------------------
|
|
// -- Read data mux
|
|
//
|
|
// -- The data from the selected register is
|
|
// -- placed on a zero-padded 32-bit read data bus.
|
|
// ------------------------------------------------------
|
|
always @(*) begin : RDDATA_PROC
|
|
rddata_reg = {32{1'b0}};
|
|
if(idren == H) rddata_reg[31:0] = IDRD ;
|
|
if(vidren == H) rddata_reg[31:0] = VIDRD ;
|
|
if(dateren == H) rddata_reg[31:0] = DATERD ;
|
|
if(verren == H) rddata_reg[31:0] = VERSION ;
|
|
if(testren == H) rddata_reg[31:0] = testr ;
|
|
if(isren == H) rddata_reg[31:0] = isr ;
|
|
if(sfrtren == H) rddata_reg[31:0] = sfrtr ;
|
|
if(syncren == H) rddata_reg[18:0] = syncr ;
|
|
if(rampctren == H) rddata_reg[23:0] = rampctr ;
|
|
if(rampifsren == H) rddata_reg[31:0] = rampifsr ;
|
|
if(doselren == H) rddata_reg[2 :0] = doselr ;
|
|
if(lvdsftren == H) rddata_reg[0 :0] = lvdsftr ;
|
|
if(lvdstfren == H) rddata_reg[0 :0] = lvdstfr ;
|
|
if(lvdstsren == H) rddata_reg[2 :0] = lvdstsr ;
|
|
if(lvdsthren == H) rddata_reg[19:0] = lvdsthr ;
|
|
if(lvdssren == H) rddata_reg[7 :0] = lvdssr ;
|
|
if(lvdstamren == H) rddata_reg[2 :0] = lvdstamr ;
|
|
if(lvdsfcsren == H) rddata_reg[31:0] = lvdsfcsr ;
|
|
if(lvdscecren == H) rddata_reg[31:0] = lvdscecr ;
|
|
if(lvdsdseren == H) rddata_reg[0 :0] = lvdsdser ;
|
|
if(lvdstaoren == H) rddata_reg[0 :0] = lvdstaor ;
|
|
if(lvdsfstren == H) rddata_reg[31:0] = lvdsfstr ;
|
|
if(lvdststren == H) rddata_reg[31:0] = lvdststr ;
|
|
if(imren == H) rddata_reg[5 :0] = imr ;
|
|
if(misren == H) rddata_reg[5 :0] = misr ;
|
|
if(ncofcwhren == H) rddata_reg[31:0] = ncofcwhr ;
|
|
if(ncofcwlren == H) rddata_reg[15:0] = ncofcwlr ;
|
|
if(ncopcwren == H) rddata_reg[15:0] = ncopcwr ;
|
|
if(ncoctrlren == H) rddata_reg[2 :0] = ncoctrlr ;
|
|
end
|
|
|
|
|
|
|
|
//rddata
|
|
sirv_gnrl_dfflr #(32) rddata_dfflr (rden, rddata_reg, rddata, clk, rst_n);
|
|
|
|
// ------------------------------------------------------
|
|
// -- status
|
|
// ------------------------------------------------------
|
|
//read misr clear interrupts
|
|
wire icr = (misren) && rden;
|
|
|
|
//train_ready
|
|
wire train_ready_r;
|
|
wire train_ready_en = icr | train_ready;
|
|
wire train_ready_w = ~icr | train_ready;
|
|
sirv_gnrl_dfflr #(1) train_ready_r_dfflr (train_ready_en, train_ready_w, train_ready_r, clk, rst_n);
|
|
|
|
//crc_error
|
|
wire crc_error_r;
|
|
wire crc_error_en = icr | crc_error;
|
|
wire crc_error_w = ~icr | crc_error;
|
|
sirv_gnrl_dfflr #(1) crc_error_r_dfflr (crc_error_en, crc_error_w, crc_error_r, clk, rst_n);
|
|
|
|
//phase_adj_req
|
|
wire phase_adj_req_r;
|
|
wire phase_adj_req_en = icr | phase_adj_req;
|
|
wire phase_adj_req_w = ~icr | phase_adj_req;
|
|
sirv_gnrl_dfflr #(1) cphase_adj_req_r_dfflr (phase_adj_req_en, phase_adj_req_w, phase_adj_req_r, clk, rst_n);
|
|
|
|
//link_down
|
|
wire link_down_r;
|
|
wire link_down_en = icr | link_down;
|
|
wire link_down_w = ~icr | link_down;
|
|
sirv_gnrl_dfflr #(1) link_down_r_dfflr (link_down_en, link_down_w, link_down_r, clk, rst_n);
|
|
|
|
//cmd_fifo_full
|
|
wire cmd_fifo_full_r;
|
|
wire cmd_fifo_full_en = icr | cmd_fifo_full;
|
|
wire cmd_fifo_full_w = ~icr | cmd_fifo_full;
|
|
sirv_gnrl_dfflr #(1) cmd_fifo_full_r_dfflr (cmd_fifo_full_en, cmd_fifo_full_w, cmd_fifo_full_r, clk, rst_n);
|
|
|
|
//cmd_fifo_empty
|
|
wire cmd_fifo_empty_r;
|
|
wire cmd_fifo_empty_en = icr | cmd_fifo_empty;
|
|
wire cmd_fifo_empty_w = ~icr | cmd_fifo_empty;
|
|
sirv_gnrl_dfflr #(1) cmd_fifo_empty_r_dfflr (cmd_fifo_empty_en, cmd_fifo_empty_w, cmd_fifo_empty_r, clk, rst_n);
|
|
|
|
//irisr
|
|
//Interrupt Status Register
|
|
//[31 :6] --> Reserved
|
|
//[5 ] --> crc_error Interrupt Status
|
|
//[4 ] --> phase_adj_req Interrupt Status
|
|
//[3 ] --> train_ready Interrupt Status
|
|
//[2 ] --> link_down Interrupt Status
|
|
//[1 ] --> cmd_fifo_empty Interrupt Status
|
|
//[0 ] --> cmd_fifo_full Interrupt Status
|
|
|
|
assign irisr[5 ] = crc_error_r ;
|
|
assign irisr[4 ] = phase_adj_req_r ;
|
|
assign irisr[3 ] = train_ready_r ;
|
|
assign irisr[2 ] = link_down_r ;
|
|
assign irisr[1 ] = cmd_fifo_full_r ;
|
|
assign irisr[0 ] = cmd_fifo_empty_r ;
|
|
|
|
// ------------------------------------------------------
|
|
// -- Interrupt Status Register - Read Only
|
|
//
|
|
// This register contains the status of all
|
|
// DA4008 Chip interrupts after masking.
|
|
// ------------------------------------------------------
|
|
sirv_gnrl_dffr #(6) isr_dffr (irisr, isr, clk, rst_n);
|
|
|
|
//misr
|
|
wire[5:0] misr_w = imr & irisr;
|
|
sirv_gnrl_dffr #(6) misr_dffr (misr_w, misr, clk, rst_n);
|
|
|
|
//irq
|
|
wire irq_w = |misr;
|
|
sirv_gnrl_dffr #(1) irq_dffr (irq_w, irq, clk, rst_n);
|
|
|
|
|
|
//sync ctrl
|
|
assign sync_oen = syncr[18 ] ;
|
|
assign int_sync_en = syncr[17 ] ;
|
|
assign int_sync = syncr[16 ] ;
|
|
assign sync_delay = syncr[15:0] ;
|
|
|
|
//Ramp & Data Select
|
|
//Data Select
|
|
assign dout_sel = doselr ;
|
|
//RAMP cfg
|
|
assign ramp_en = doselr[0] ;
|
|
assign ramp_step = rampctr[23:16] ;
|
|
assign ramp_fixed_value = rampctr[15:8] ;
|
|
assign ramp_fixed = rampctr[0] ;
|
|
assign ramp_ifs = rampifsr ;
|
|
|
|
//LVDS
|
|
assign force_train = lvdsftr ;
|
|
assign tap_force = lvdstfr ;
|
|
assign tap_step = lvdstsr ;
|
|
assign tap_adj_mask = lvdstamr;
|
|
assign train_threshold = lvdsthr ;
|
|
assign descram_en = lvdsdser;
|
|
assign always_on = lvdstaor;
|
|
|
|
//NCO
|
|
assign nco_fcw = {ncofcwhr,ncofcwlr};
|
|
assign nco_pha = ncopcwr ;
|
|
assign nco_clr = ncoctrlr[2] ;
|
|
assign nco_en = ncoctrlr[1] & doselr[2] ;
|
|
assign p2a_en = ncoctrlr[0] & doselr[2] ;
|
|
|
|
endmodule
|
|
|
|
`undef IDR
|
|
`undef VIDR
|
|
`undef DATER
|
|
`undef VERR
|
|
`undef TESTR
|
|
`undef ISR
|
|
`undef MISR
|
|
`undef SFRTR
|
|
`undef SFRR
|
|
`undef RAMPCTR
|
|
`undef RAMPIFSR
|
|
`undef DOSELR
|
|
`undef LVDSFTR
|
|
`undef LVDSTFR
|
|
`undef LVDSTSR
|
|
`undef LVDSTHR
|
|
`undef LVDSSR
|
|
`undef LVDSFSCR
|
|
`undef LVDSCECR
|
|
`undef LVDSTAMR
|
|
`undef LVDSDSER
|
|
`undef LVDSTAOR
|
|
`undef LVDSFSTR
|
|
`undef LVDSTSTR
|
|
`undef IMR
|
|
`undef MISR
|
|
`undef NCOFCWHR
|
|
`undef NCOFCWLR
|
|
`undef NCOPCWR
|
|
`undef NCOCTLR
|