104 lines
2.6 KiB
Verilog
104 lines
2.6 KiB
Verilog
module P_NCO # (
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parameter WIDTH = 16
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, parameter PARALLEL = 16
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)(
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input clk
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,input rstn
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,input clr
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,input clr_acc
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,input [15 :0] ptw
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,input p2a_en
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,input [15 :0] s1
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,input [15 :0] s2
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,input [15 :0] s3
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,output [15 :0] s1_o
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,output [15 :0] s2_o
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,output [15 :0] s3_o
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,input [47 :0] fcw [PARALLEL-1:0]//fcw[0]=16*fcw; fcw[i]=i*fcw, i=1,2,...,15
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,output [WIDTH-1:0] cos [PARALLEL-1:0]
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,output [WIDTH-1:0] sin [PARALLEL-1:0]
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);
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wire [15:0] cos_16bit [PARALLEL-1:0];
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wire [15:0] sin_16bit [PARALLEL-1:0];
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reg [15:0] ptw_r;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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ptw_r <= 16'd0;
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else
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ptw_r <= ptw;
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wire [18:0] pha [PARALLEL-1:0];
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PIPE3_ACC_48BIT inst_pipe_0(
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.clk (clk )
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,.rstn (rstn )
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,.in (fcw[0] )
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,.clr (clr_acc )
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,.en (1'b1 )
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,.ptw (ptw )
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,.s_o_1 (s1_o )
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,.s_o_2 (s2_o )
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,.s_o_3 (s3_o )
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,.s_i_1 (s1 )
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,.s_i_2 (s2 )
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,.s_i_3 (s3 )
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,.out (pha[0] ));
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reg [18:0] pha_0_r;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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pha_0_r <= 16'd0;
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else if (p2a_en == 1'b0)
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pha_0_r <= 16'd0;
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else
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pha_0_r <= pha[0];
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PH2AMP inst_ph2amp_0(
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.clk (clk ),
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.rstn (rstn ),
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.pha_map (pha_0_r ),
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.sin_o (sin_16bit[0]),
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.cos_o (cos_16bit[0])
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);
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assign cos[0] = cos_16bit[0][15:16-WIDTH];
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assign sin[0] = sin_16bit[0][15:16-WIDTH];
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genvar i;
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generate
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for(i = 1; i < PARALLEL; i++) begin
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PIPE3_ADD_48BIT inst_pipe_i(
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.clk (clk )
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,.rstn (rstn )
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,.in (fcw[i] )
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,.clr (clr )
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,.en (p2a_en )
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,.ptw (ptw_r )
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,.s1 (s1 )
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,.s2 (s2 )
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,.s3 (s3 )
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,.out (pha[i] ));
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PH2AMP inst_ph2amp_i(
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.clk (clk )
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,.rstn (rstn )
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,.pha_map (pha[i] )
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,.sin_o (sin_16bit[i])
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,.cos_o (cos_16bit[i]));
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assign cos[i] = cos_16bit[i][15:16-WIDTH];
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assign sin[i] = sin_16bit[i][15:16-WIDTH];
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end
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endgenerate
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endmodule
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