173 lines
12 KiB
Verilog
173 lines
12 KiB
Verilog
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module tsmc_dpram #(
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parameter DATAWIDTH = 32
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,parameter ADDRWIDTH = 14
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)(
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input PortClk
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,input [ADDRWIDTH-1 :0] PortAAddr
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,input [DATAWIDTH-1 :0] PortADataIn
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,input PortAWriteEnable //active low
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,input PortAChipEnable //active low
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,input [(DATAWIDTH/8)-1 :0] PortAByteWriteEnable //active low
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,output [DATAWIDTH-1 :0] PortADataOut
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,input [ADDRWIDTH-1 :0] PortBAddr
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,input [DATAWIDTH-1 :0] PortBDataIn
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,input PortBWriteEnable //active low
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,input PortBChipEnable //active low
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,input [(DATAWIDTH/8)-1 :0] PortBByteWriteEnable //active low
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,output [DATAWIDTH-1 :0] PortBDataOut
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);
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////////////////////////////////////////////////////////////////////////////////
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//Function
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////////////////////////////////////////////////////////////////////////////////
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function integer clog2(input integer bit_depth);
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begin
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for(clog2=0;bit_depth>0;clog2=clog2+1)
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bit_depth =bit_depth>>1;
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end
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endfunction
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localparam LSB = clog2(DATAWIDTH/8 -1);
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generate
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if((DATAWIDTH == 512) && (ADDRWIDTH == 19)) begin:spram_512X8192_generation
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genvar i;
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wire [DATAWIDTH-1:0] BWEBA ;
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wire [DATAWIDTH-1:0] BWEBB ;
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for(i = 0; i < DATAWIDTH/8; i = i + 1) begin
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assign BWEBA[8*i +: 8] = {8{PortAByteWriteEnable[i]}};
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assign BWEBB[8*i +: 8] = {8{PortBByteWriteEnable[i]}};
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end
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genvar k;
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wire [1 :0] U_CEBA;
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wire [1 :0] U_CEBB;
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wire [DATAWIDTH-1:0] U_QA[1 :0];
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wire [DATAWIDTH-1:0] U_QB[1 :0];
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reg [1 :0] AA_1D_MSB;
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reg [1 :0] AB_1D_MSB;
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for(k = 0; k < 2; k = k + 1) begin
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assign U_CEBA[k] = ~(PortAAddr[ADDRWIDTH-1] == k) | PortAChipEnable;
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assign U_CEBB[k] = ~(PortBAddr[ADDRWIDTH-1] == k) | PortBChipEnable;
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tsdn28hpcpuhdb4096x128m4mw_170a U0_tsdn28hpcpuhdb4096x128m4mw_170a (
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.CLK ( PortClk )
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,.CEBA ( U_CEBA[k] )
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,.WEBA ( PortAWriteEnable )
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,.BWEBA ( BWEBA[127:0] )
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,.AA ( PortAAddr[ADDRWIDTH-2:LSB] )
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,.DA ( PortADataIn[127:0] )
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,.QA ( U_QA[k][127:0] )
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,.CEBB ( U_CEBB[k] )
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,.WEBB ( PortBWriteEnable )
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,.BWEBB ( BWEBB[127:0] )
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,.AB ( PortBAddr[ADDRWIDTH-2:LSB] )
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,.DB ( PortBDataIn[127:0] )
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,.QB ( U_QB[k][127:0] )
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,.RTSEL ( 2'b00 )
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,.WTSEL ( 2'b00 )
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,.PTSEL ( 2'b00 )
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);
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tsdn28hpcpuhdb4096x128m4mw_170a U1_tsdn28hpcpuhdb4096x128m4mw_170a (
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.CLK ( PortClk )
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,.CEBA ( U_CEBA[k] )
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,.WEBA ( PortAWriteEnable )
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,.BWEBA ( BWEBA[255:128] )
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,.AA ( PortAAddr[ADDRWIDTH-2:LSB] )
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,.DA ( PortADataIn[255:128] )
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,.QA ( U_QA[k][255:128] )
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,.CEBB ( U_CEBB[k] )
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,.WEBB ( PortBWriteEnable )
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,.BWEBB ( BWEBB[255:128] )
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,.AB ( PortBAddr[ADDRWIDTH-2:LSB] )
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,.DB ( PortBDataIn[255:128] )
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,.QB ( U_QB[k][255:128] )
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,.RTSEL ( 2'b00 )
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,.WTSEL ( 2'b00 )
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,.PTSEL ( 2'b00 )
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);
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tsdn28hpcpuhdb4096x128m4mw_170a U2_tsdn28hpcpuhdb4096x128m4mw_170a (
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.CLK ( PortClk )
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,.CEBA ( U_CEBA[k] )
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,.WEBA ( PortAWriteEnable )
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,.BWEBA ( BWEBA[383:256] )
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,.AA ( PortAAddr[ADDRWIDTH-2:LSB] )
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,.DA ( PortADataIn[383:256] )
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,.QA ( U_QA[k][383:256] )
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,.CEBB ( U_CEBB[k] )
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,.WEBB ( PortBWriteEnable )
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,.BWEBB ( BWEBB[383:256] )
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,.AB ( PortBAddr[ADDRWIDTH-2:LSB] )
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,.DB ( PortBDataIn[383:256] )
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,.QB ( U_QB[k][383:256] )
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,.RTSEL ( 2'b00 )
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,.WTSEL ( 2'b00 )
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,.PTSEL ( 2'b00 )
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);
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tsdn28hpcpuhdb4096x128m4mw_170a U3_tsdn28hpcpuhdb4096x128m4mw_170a (
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.CLK ( PortClk )
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,.CEBA ( U_CEBA[k] )
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,.WEBA ( PortAWriteEnable )
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,.BWEBA ( BWEBA[511:384] )
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,.AA ( PortAAddr[ADDRWIDTH-2:LSB] )
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,.DA ( PortADataIn[511:384] )
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,.QA ( U_QA[k][511:384] )
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,.CEBB ( U_CEBB[k] )
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,.WEBB ( PortBWriteEnable )
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,.BWEBB ( BWEBB[511:384] )
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,.AB ( PortBAddr[ADDRWIDTH-2:LSB] )
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,.DB ( PortBDataIn[511:384] )
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,.QB ( U_QB[k][511:384] )
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,.RTSEL ( 2'b00 )
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,.WTSEL ( 2'b00 )
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,.PTSEL ( 2'b00 )
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);
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end
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always @(posedge PortClk) begin
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if(PortAWriteEnable == 1'b1) begin
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AA_1D_MSB <= PortAAddr[ADDRWIDTH-1];
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end
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else begin
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AA_1D_MSB <= AA_1D_MSB;
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end
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end
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always @(posedge PortClk) begin
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if(PortBWriteEnable == 1'b1) begin
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AB_1D_MSB <= PortBAddr[ADDRWIDTH-1];
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end
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else begin
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AB_1D_MSB <= AB_1D_MSB;
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end
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end
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assign PortADataOut = {DATAWIDTH{AA_1D_MSB == 1'h0}} & U_QA[0]
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| {DATAWIDTH{AA_1D_MSB == 1'h1}} & U_QA[1]
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;
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assign PortBDataOut = {DATAWIDTH{AB_1D_MSB == 1'h0}} & U_QB[0]
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| {DATAWIDTH{AB_1D_MSB == 1'h1}} & U_QB[1]
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;
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end
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else begin:dpram_model_generation
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dpram_model #(
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.DATAWIDTH ( DATAWIDTH )
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,.ADDRWIDTH ( ADDRWIDTH-LSB )
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) U_dpram_model (
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.PortClk ( PortClk )
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,.PortAWriteEnable ( PortAWriteEnable )
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,.PortAChipEnable ( PortAChipEnable )
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,.PortAByteWriteEnable ( PortAByteWriteEnable )
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,.PortAAddr ( PortAAddr[ADDRWIDTH-1:LSB] )
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,.PortADataIn ( PortADataIn )
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,.PortADataOut ( PortADataOut )
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,.PortBWriteEnable ( PortBWriteEnable )
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,.PortBChipEnable ( PortBChipEnable )
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,.PortBByteWriteEnable ( PortBByteWriteEnable )
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,.PortBAddr ( PortBAddr[ADDRWIDTH-1:LSB] )
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,.PortBDataIn ( PortBDataIn )
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,.PortBDataOut ( PortBDataOut )
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);
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end
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endgenerate
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endmodule
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