188 lines
8.6 KiB
Verilog
188 lines
8.6 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : iopad.v
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// Department :
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// Author : pwy
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 1.2 2024-06-12 pwy Integrate a digital module and two SPI modules with PLL
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// 1.3 2024-11-12 pwy Adding an Attenuator Configuration Interface
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// 1.4 2025-08-14 pwy Modify IRQ output logic
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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`include "../define/chip_define.v"
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module iopad (
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//+++++++++++++++++++++++++++++++++++++++++++++//
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// PAD Strat //
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//+++++++++++++++++++++++++++++++++++++++++++++//
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input PI_async_rstn // hardware Reset, active low
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//sync
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,input PI_sync_in // Chip synchronization signal input, high pulse valid
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,output PO_sync_out // Chip synchronization signal output, high pulse valid
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//spi port
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,input PI_sclk // Spi Clock
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,input PI_csn // Spi Chip Select active low
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,input PI_mosi // Spi Mosi
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,output PO_miso // Spi Miso
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//irq
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,output PO_irq // Interrupt signal in the chip, high level active
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//+++++++++++++++++++++++++++++++++++++++++++++//
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// PAD End //
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//+++++++++++++++++++++++++++++++++++++++++++++//
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//+++++++++++++++++++++++++++++++++++++++++++++//
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// Internal signal Start //
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//+++++++++++++++++++++++++++++++++++++++++++++//
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,output async_rstn // hardware Reset, active low
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//sync
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,output sync_in // Chip synchronization signal to analog, high pulse valid
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,input sync_out // Chip synchronization signal output, high pulse valid
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//spi port
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,output sclk // Spi Clock
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,output csn // Spi Chip Select active low
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,output mosi // Spi Mosi
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,input miso // Spi Miso
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,input oen // Spi Miso output enable
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//irq
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,input irq_n // Interrupt signal in the chip, high level active
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);
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`ifdef TSMC_IC
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//++++++++++++++++++++++++++++++++++++++++++++++++++//
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// ASIC PAD --> TSMC //
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//++++++++++++++++++++++++++++++++++++++++++++++++++//
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//PI_async_rstn,pull-up
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PDUW04SDGZ_V_G PDUW08SDGZ_V_G_async_rstn (
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.I ( 1'b0 )
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,.OEN ( 1'b1 )
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,.REN ( 1'b0 )
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,.PAD ( PI_async_rstn )
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,.C ( async_rstn )
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);
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//sync_in,pull-down
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PDDW04SDGZ_V_G PDDW04SDGZ_V_G_sync_in (
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.I ( 1'b0 )
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,.OEN ( 1'b1 )
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,.REN ( 1'b0 )
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,.PAD ( PI_sync_in )
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,.C ( sync_in )
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);
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//sync_out,pull-down
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PDDW04SDGZ_V_G PDDW08SDGZ_V_G_sync_out (
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.I ( sync_out )
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,.OEN ( 1'b0 )
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,.REN ( 1'b0 )
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,.PAD ( PO_sync_out )
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,.C ( )
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);
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//sclk,pull-up
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PDUW04SDGZ_V_G PDUW04SDGZ_V_G_sclk (
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.I ( 1'b0 )
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,.OEN ( 1'b1 )
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,.REN ( 1'b0 )
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,.PAD ( PI_sclk )
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,.C ( sclk )
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);
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//csn,pull-up
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PDUW04SDGZ_V_G PDUW04SDGZ_V_G_csn (
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.I ( 1'b0 )
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,.OEN ( 1'b1 )
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,.REN ( 1'b0 )
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,.PAD ( PI_csn )
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,.C ( csn )
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);
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//mosi,pull-up
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PDUW08SDGZ_V_G PDUW08SDGZ_V_G_mosi (
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.I ( 1'b0 )
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,.OEN ( 1'b1 )
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,.REN ( 1'b0 )
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,.PAD ( PI_mosi )
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,.C ( mosi )
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);
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//miso,pull-up
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PDUW08SDGZ_V_G PDUW08SDGZ_V_G_miso (
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.I ( miso )
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,.OEN ( oen )
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,.REN ( 1'b0 )
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,.PAD ( PO_miso )
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,.C ( )
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);
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//irq,pull-up
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PDUW08SDGZ_V_G PDUW08SDGZ_V_G_irq (
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.I ( 1'b0 )
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,.OEN ( irq_n )
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,.REN ( 1'b0 )
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,.PAD ( PO_irq )
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,.C ( )
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);
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`elsif XILINX_FPGA
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//++++++++++++++++++++++++++++++++++++++++++++++++++//
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// FPGA PAD --> Xlinx //
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//++++++++++++++++++++++++++++++++++++++++++++++++++//
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//async_rstn
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assign async_rstn = PI_async_rstn ;
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//sync_in
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assign sync_to_analog = PI_sync_in ;
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//sync_out
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assign PO_sync_out = sync_out ;
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//Feedback signal
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assign ch0_feedback = PI_ch0_feedback ;
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`ifdef CHANNEL_IS_FOUR
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assign ch1_feedback = PI_ch1_feedback ;
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assign ch2_feedback = PI_ch2_feedback ;
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assign ch3_feedback = PI_ch3_feedback ;
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`endif
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//config chip id
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assign cfgid = PI_cfgid ;
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//spi port
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assign sclk = PI_sclk ;
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assign csn = PI_csn ;
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assign mosi = PI_mosi ;
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assign PO_miso = oen ? 1'bz : miso ;
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//irq
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assign PO_irq = irq_n ;
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`ifdef CHANNEL_IS_FOUR
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assign PO_ch0_att = ch0_att ;
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assign PO_ch1_att = ch1_att ;
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assign PO_ch2_att = ch2_att ;
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assign PO_ch3_att = ch3_att ;
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`endif
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`endif
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endmodule
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`include "../define/chip_undefine.v"
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