80 lines
3.1 KiB
Verilog
80 lines
3.1 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : modout_mux.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-05-13 PWY debug top-level
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module dout_mux #(
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parameter PARALLEL = 64
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)(
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//system port
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input clk // System Main Clock
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,input rst_n // Spi Reset active low
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//---------------from ctrl regfile------------------------------------
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,input [2 :0] sel //3'h0: mix; 3'h1:enve_i; 3'h2:drag_q
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// 3'h3: cos ; 3'h4: sin
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//data0
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,input [7:0] data0 [PARALLEL-1 : 0]
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,input data0_vld
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//data1
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,input [7:0] data1 [PARALLEL-1 : 0]
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,input data1_vld
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//data2
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,input [7:0] data2 [PARALLEL-1 : 0]
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,input data2_vld
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//mux out data
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,output [7:0] mux_data [PARALLEL-1 : 0]
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,output mux_data_vld
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);
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wire mux_data_vld_w = (sel == 3'd1) ? data0_vld:
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(sel == 3'd2) ? data1_vld:
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(sel == 3'd4) ? data2_vld:
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1'b0 ;
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sirv_gnrl_dffr #(1) mux_data_vld_dffr (mux_data_vld_w, mux_data_vld, clk, rst_n);
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wire [7 :0] mux_data_w [PARALLEL-1 : 0];
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genvar k;
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generate
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for(k = 0; k < PARALLEL; k = k + 1) begin
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assign mux_data_w[k] = (sel == 3'd1) ? data0[k]:
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(sel == 3'd2) ? data1[k]:
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(sel == 3'd4) ? data2[k]:
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32'd0 ;
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sirv_gnrl_dffr #(8) mux_data_dffr (mux_data_w[k], mux_data[k], clk, rst_n);
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end
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endgenerate
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endmodule
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