386 lines
13 KiB
Verilog
386 lines
13 KiB
Verilog
////////////////////////////////////////////////////////////////////////////////
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//
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// This confidential and proprietary software may be used only
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// as authorized by a licensing agreement from Synopsys Inc.
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// In the event of publication, the following notice is applicable:
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//
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// (C) COPYRIGHT 2005 - 2018 SYNOPSYS INC.
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// ALL RIGHTS RESERVED
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//
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// The entire notice above must be reproduced on all authorized
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// copies.
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//
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// AUTHOR: Doug Lee 3/3/05
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//
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// VERSION: Simulation Architecture
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//
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// DesignWare_version: c5e9837c
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// DesignWare_release: O-2018.06-DWBB_201806.1
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// ABSTRACT: Fundamental Synchronizer Simulation Model
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//
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// This synchronizes incoming data into the destination domain
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// with a configurable number of sampling stages.
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//
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// Parameters: Valid Values
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// ========== ============
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// width [ 1 to 1024 ]
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// f_sync_type [ 0 = single clock design, no synchronizing stages implemented,
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// 1 = 2-stage synchronization w/ 1st stage neg-edge & 2nd stage pos-edge capturing,
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// 2 = 2-stage synchronization w/ both stages pos-edge capturing,
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// 3 = 3-stage synchronization w/ all stages pos-edge capturing,
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// 4 = 4-stage synchronization w/ all stages pos-edge capturing ]
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// tst_mode [ 0 = no hold latch inserted,
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// 1 = insert hold 'latch' using a neg-edge triggered register
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// 2 = reserved (functions same as tst_mode=0 ]
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// verif_en [ 0 = no sampling errors inserted,
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// 1 = sampling errors are randomly inserted with 0 or 1 destination clock cycle delays
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// 2 = sampling errors are randomly inserted with 0, 0.5, 1, or 1.5 destination clock cycle delays
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// 3 = sampling errors are randomly inserted with 0, 1, 2, or 3 destination clock cycle delays
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// 4 = sampling errors are randomly inserted with 0 or up to 0.5 destination clock cycle delays ]
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//
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// Input Ports: Size Description
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// =========== ==== ===========
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// clk_d 1 bit Destination Domain Input Clock
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// rst_d_n 1 bit Destination Domain Active Low Async. Reset
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// init_d_n 1 bit Destination Domain Active Low Sync. Reset
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// data_s N bits Source Domain Data Input
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// test 1 bit Test input
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//
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// Output Ports Size Description
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// ============ ==== ===========
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// data_d N bits Destination Domain Data Output
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//
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// Note: the value of N is equal to the 'width' parameter value
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//
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//
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// MODIFIED:
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// RJK 09-17-13 updated to eliminate race (STAR 9000661688)
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// RJK 01-15-13 updated to eliminate `define
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// RJK 10-11-12 corrected test mode behavior when tst_mode=2
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// DLL 8-8-11 Added tst_mode=2 (not a functional change)
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// DLL 6-12-06 Removed unnecessary To_X01 processing of 'data_s_int'
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//
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// DLL 11-7-06 Modified functionality to support f_sync_type = 4
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//
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// DLL 11-14-06 Revised approach to routing missampling of data_s
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//
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//
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// DLL 8-18-10 Fixed typo that results in correct resolution of 'data_s_delta_t'
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// in the missampling code. Addresses STAR#9000412693.
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module DW_sync (
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clk_d,
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rst_d_n,
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init_d_n,
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data_s,
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test,
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data_d
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);
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parameter integer width = 8;
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parameter integer f_sync_type = 2;
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parameter integer tst_mode = 0;
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parameter integer verif_en = 1;
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input clk_d;
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input rst_d_n;
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input init_d_n;
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input [width-1:0] data_s;
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input test;
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output [width-1:0] data_d;
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// synopsys translate_off
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localparam F_SYNC_TYPE_INT = f_sync_type % 8;
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//-------------------------------------------------------------------------
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// Parameter legality check
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//-------------------------------------------------------------------------
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initial begin : parameter_check
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integer param_err_flg;
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param_err_flg = 0;
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if (width < 1 ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter width (lower bound: 1 )",
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width );
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end
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if ( (F_SYNC_TYPE_INT < 0) || (F_SYNC_TYPE_INT > 4) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter F_SYNC_TYPE_INT (legal range: 0 to 4)",
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F_SYNC_TYPE_INT );
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end
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if ( (verif_en < 0) || (verif_en > 4) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter verif_en (legal range: 0 to 4)",
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verif_en );
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end
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if ( param_err_flg == 1) begin
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$display(
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"%m :\n Simulation aborted due to invalid parameter value(s)");
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$finish;
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end
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end // parameter_check
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wire [width-1:0] data_s_int;
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reg [width-1:0] ndata1_int;
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reg [width-1:0] data1_int;
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reg [width-1:0] data_d2_int;
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reg [width-1:0] data_d3_int;
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reg [width-1:0] data_d4_int;
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reg [width-1:0] test_nout1_int;
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wire [width-1:0] next_data1_int;
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wire [width-1:0] next_data_d2_int;
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wire [width-1:0] next_data_d3_int;
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wire [width-1:0] tst_mode_sel_data;
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wire [width-1:0] f_sync_type0_data;
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`ifdef DW_MODEL_MISSAMPLES
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initial begin
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$display("Information: %m: *** Running with DW_MODEL_MISSAMPLES defined, verif_en is: %0d ***",
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verif_en);
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end
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reg [width-1:0] test_hold_ms;
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wire hclk_odd;
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reg [width-1:0] last_data_dyn, data_s_delta_t;
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reg [width-1:0] last_data_s, last_data_s_q, last_data_s_qq;
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wire [width-1:0] data_s_sel_0, data_s_sel_1;
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reg [width-1:0] data_select; initial data_select = 0;
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reg [width-1:0] data_select_2; initial data_select_2 = 0;
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always @ (negedge clk_d or negedge rst_d_n) begin : PROC_test_hold_ms_registers
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if (rst_d_n == 1'b0) begin
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test_hold_ms <= {width{1'b0}};
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end else if (init_d_n == 1'b0) begin
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test_hold_ms <= {width{1'b0}};
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end else begin
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test_hold_ms <= data_s;
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end
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end
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reg init_dly_n;
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always @ (posedge hclk_odd or data_s or rst_d_n) begin : PROC_catch_last_data
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data_s_delta_t <= (data_s | (data_s ^ data_s)) & {width{rst_d_n}} & {width{init_dly_n}};
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last_data_dyn <= data_s_delta_t & {width{rst_d_n}} & {width{init_dly_n}};
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end // PROC_catch_last_data
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generate if ((verif_en % 2) == 1) begin : GEN_HO_VE_EVEN
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assign hclk_odd = clk_d;
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end else begin : GEN_HO_VE_ODD
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assign hclk_odd = ~clk_d;
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end
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endgenerate
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always @ (posedge clk_d or negedge rst_d_n) begin : PROC_missample_hist_even
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if (rst_d_n == 1'b0) begin
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last_data_s_q <= {width{1'b0}};
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init_dly_n <= 1'b1;
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end else if (init_d_n == 1'b0) begin
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last_data_s_q <= {width{1'b0}};
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init_dly_n <= 1'b0;
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end else begin
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last_data_s_q <= last_data_s;
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init_dly_n <= 1'b1;
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end
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end // PROC_missample_hist_even
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always @ (posedge hclk_odd or negedge rst_d_n) begin : PROC_missample_hist_odd
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if (rst_d_n == 1'b0) begin
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last_data_s <= {width{1'b0}};
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last_data_s_qq <= {width{1'b0}};
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end else if (init_d_n == 1'b0) begin
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last_data_s <= {width{1'b0}};
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last_data_s_qq <= {width{1'b0}};
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end else begin
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last_data_s <= (data_s | (data_s ^ data_s));
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last_data_s_qq <= last_data_s_q;
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end
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end // PROC_missample_hist_odd
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always @ (data_s or last_data_s) begin : PROC_mk_next_data_select
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if (data_s != last_data_s) begin
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data_select = wide_random(width);
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if ((verif_en == 2) || (verif_en == 3))
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data_select_2 = wide_random(width);
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else
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data_select_2 = {width{1'b0}};
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end
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end // PROC_mk_next_data_select
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assign data_s_sel_0 = (verif_en < 1)? data_s : ((data_s & ~data_select) | (last_data_dyn & data_select));
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assign data_s_sel_1 = (verif_en < 2)? {width{1'b0}} : ((last_data_s_q & ~data_select) | (last_data_s_qq & data_select));
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assign data_s_int = ((data_s_sel_0 & ~data_select_2) | (data_s_sel_1 & data_select_2));
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function [width-1:0] wide_random;
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input [31:0] in_width; // should match "width" parameter -- need one input to satisfy Verilog function requirement
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reg [width-1:0] temp_result;
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reg [31:0] rand_slice;
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integer i, j, base;
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begin
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temp_result = $random;
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if (((width / 32) + 1) > 1) begin
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for (i=1 ; i < ((width / 32) + 1) ; i=i+1) begin
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base = i << 5;
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rand_slice = $random;
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for (j=0 ; ((j < 32) && (base+j < in_width)) ; j=j+1) begin
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temp_result[base+j] = rand_slice[j];
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end
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end
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end
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wide_random = temp_result;
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end
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endfunction // wide_random
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initial begin : seed_random_PROC
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integer seed, init_rand;
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`ifdef DW_MISSAMPLE_SEED
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seed = `DW_MISSAMPLE_SEED;
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`else
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seed = 32'h0badbeef;
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`endif
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init_rand = $random(seed);
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end // seed_random_PROC
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`else
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assign data_s_int = (data_s | (data_s ^ data_s));
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`endif
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initial begin
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if ((f_sync_type > 0)&&(f_sync_type < 8))
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$display("Information: *** Instance %m is the DW_sync Clock Domain Crossing Module ***");
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end
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`ifdef DW_REPORT_SYNC_PARAMS
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initial begin
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if (F_SYNC_TYPE_INT > 0)
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$display("Information: *** Instance %m is configured as follows: width is: %0d, f_sync_type is: %0d, tst_mode is: %0d ***", width, F_SYNC_TYPE_INT, tst_mode);
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end
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`endif
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assign tst_mode_sel_data = (tst_mode == 1) ? test_nout1_int : data_s;
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assign f_sync_type0_data = (test == 1'b1) ? tst_mode_sel_data : data_s;
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assign next_data1_int = (test == 1'b0) ? data_s_int : tst_mode_sel_data;
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generate
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if ((f_sync_type & 7) == 1) begin : GEN_NXT_SMPL_SM1_FST_EQUAL1
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assign next_data_d2_int = ndata1_int;
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end
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if ((f_sync_type & 7) > 1) begin : GEN_NXT_SMPL_SM1_FST_GRTH1
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assign next_data_d2_int = data1_int;
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end
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endgenerate
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always @(negedge clk_d or negedge rst_d_n) begin : a1000_PROC
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if (rst_d_n === 1'b0) begin
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ndata1_int <= {width{1'b0}};
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test_nout1_int <= {width{1'b0}};
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end else if (rst_d_n === 1'b1) begin
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if (init_d_n === 1'b0) begin
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ndata1_int <= {width{1'b0}};
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test_nout1_int <= {width{1'b0}};
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end else if (init_d_n === 1'b1) begin
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ndata1_int <= data_s_int;
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test_nout1_int <= data_s;
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end else begin
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ndata1_int <= {width{1'bX}};
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test_nout1_int <= {width{1'bX}};
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end
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end else begin
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ndata1_int <= {width{1'bX}};
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test_nout1_int <= {width{1'bX}};
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end
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end
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always @(posedge clk_d or negedge rst_d_n) begin : a1001_PROC
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if (rst_d_n === 1'b0) begin
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data1_int <= {width{1'b0}};
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data_d2_int <= {width{1'b0}};
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data_d3_int <= {width{1'b0}};
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data_d4_int <= {width{1'b0}};
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end else if (rst_d_n === 1'b1) begin
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if (init_d_n === 1'b0) begin
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data1_int <= {width{1'b0}};
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data_d2_int <= {width{1'b0}};
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data_d3_int <= {width{1'b0}};
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data_d4_int <= {width{1'b0}};
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end else if (init_d_n === 1'b1) begin
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data1_int <= next_data1_int;
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data_d2_int <= next_data_d2_int;
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data_d3_int <= data_d2_int;
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data_d4_int <= data_d3_int;
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end else begin
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data1_int <= {width{1'bX}};
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data_d2_int <= {width{1'bX}};
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data_d3_int <= {width{1'bX}};
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data_d4_int <= {width{1'bX}};
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end
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end else begin
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data1_int <= {width{1'bX}};
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data_d2_int <= {width{1'bX}};
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data_d3_int <= {width{1'bX}};
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data_d4_int <= {width{1'bX}};
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end
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end
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assign data_d = (F_SYNC_TYPE_INT == 0) ? f_sync_type0_data :
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(F_SYNC_TYPE_INT == 3) ? data_d3_int :
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(F_SYNC_TYPE_INT == 4) ? data_d4_int :
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data_d2_int;
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always @ (clk_d) begin : monitor_clk_d
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if ( (clk_d !== 1'b0) && (clk_d !== 1'b1) && ($time > 0) )
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$display( "WARNING: %m :\n at time = %t, detected unknown value, %b, on clk_d input.",
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$time, clk_d );
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end // monitor_clk_d
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// synopsys translate_on
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endmodule
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/* vcs gen_ip dbg_ip off */
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/* */
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