WAVE ?= 0

SIM = RTL

folder = simv

ifeq ($(WAVE),1)
  WAVE_OPTS = -debug_access+all -debug_region+cell+encrypt -P $(NOVAS_HOME)/share/PLI/VCS/linux64/novas_new_dumper.tab $(NOVAS_HOME)/share/PLI/VCS/linux64/pli.a +define+DUMP_FSDB  
  WAVE_SIM_OPTS = -fsdbDumpfile=sim.fsdb
  else
  WAVE_OPTS = -debug_access+pp
endif

ifeq ($(SIM),PostPr)
VCS  = vcs  -full64  -sverilog -Mupdate +lint=TFIPC-L +v2k +warn=noSDFCOM_IWSBA,noNTCDNC -notice +mindelays +tchk+edge+warn +neg_tchk -negdelay +overlap +sdfverbose -sdfretain +optconfigfile+notimingcheck.cfg -override_timescale=1ns/1ps -debug_access+all $(WAVE_OPTS) -lca -q -l compile.log -cm line+cond+fsm+tgl+branch  -cm_dir ./coverage/simv.vdb |tee 
else
VCS  = vcs  -full64 -j8 -sverilog +lint=TFIPC-L +v2k $(WAVE_OPTS) -lca -q -timescale=1ns/1ps +nospecify -l compile.log -cm line+cond+fsm+tgl+branch -cm_dir ./coverage/simv.vdb
endif

ifeq ($(SIM),PostPr)
  post_dir = ./data_PostPr
else
  post_dir = ./data_PostSyn
endif


ifeq ($(SIM),PostSyn)
FileList = filelist_syn.f
else
  ifeq ($(SIM),PostPr)
    FileList = filelist_pr.f
  else
    FileList = filelist_vlg.f
  endif
endif

SIMV = ./simv sync:busywait -Xdprof=timeline $(WAVE_SIM_OPTS) -l |tee sim.log

all:comp run

comp:
	${VCS} -f $(FileList) +incdir+./../../rtl/define +incdir+./../../rtl/qubitmcu +incdir+./../../model

run:
	${SIMV}

dbg:
	verdi -sverilog -f $(FileList) -top TB -ssf *.fsdb -nologo &

clean:
	rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *fsdb* *.dat *.daidir *.vdb *~

compare:
	./compare_files.csh ${post_dir} ./data_RTL ./compare.txt

regress:
	./regress.csh $(SIM)

rmwork:
	rm -rf ./work*

rmdata:
	rm -rf ./data*
cov:
	verdi -cov -covdir coverage/merged.vdb &
cov_d:
	dve -full64 -covdir coverage/*.vdb &
merge:
	urg -full64 -dbname coverage/merged.vdb -flex_merge union -dir coverage/simv.vdb  -parallel -maxjobs 64&
merge_i:
	urg -full64 -flex_merge union -dir coverage/merged.vdb -dir coverage/$(folder) -dbname coverage/merged.vdb -parallel -maxjobs 64&