../../rtl/define/chip_define.v
../../lib/tphn28hpcpgv18.v
../../lib/tsdn28hpcpuhdb4096x128m4mw_170a_ffg0p99v0c.v
../../rtl/io/iopad.v
../../rtl/systemregfile/systemregfile.v
../../rtl/dacif/dacif.v
../../rtl/fifo/syn_fwft_fifo.v
../../rtl/dac_regfile/dac_regfile.v
../../rtl/lvds/ulink_rx.sv
../../rtl/rstgen/rst_gen_unit.v
../../rtl/rstgen/rst_sync.v
../../rtl/comm/sirv_gnrl_xchecker.v
../../rtl/comm/pulse_generator.sv
../../rtl/comm/sirv_gnrl_dffs.v
../../rtl/comm/syncer.v
../../rtl/comm/ramp_gen.v
../../rtl/memory/tsmc_dpram.v
../../rtl/memory/sram_if.sv
../../rtl/memory/sram_dmux.sv
../../rtl/memory/dpram.v
../../rtl/memory/bhv_spram.v
../../rtl/memory/spram.v
../../rtl/clk/clk_regfile.v
../../rtl/awg/awg_top.sv
../../rtl/awg/awg_ctrl.v
../../rtl/dem/DEM_PhaseSync_4008.sv
../../rtl/dem/DA4008_DEM_Parallel_PRBS_1CH.v
../../rtl/dem/DA4008_DEM_Parallel_PRBS_64CH.v
../../rtl/top/da4008_chip_top.sv
../../rtl/top/digital_top.sv
../../rtl/spi/spi_bus_decoder.sv
../../rtl/spi/spi_slave.v
../../rtl/spi/spi_pll.v
../../rtl/spi/spi_sys.v
../../model/clock_tb.v
../../model/spi_if.sv
../../model/clk_gen.v
../../model/DEM_Reverse_64CH.v
../../model/DEM_Reverse.v
../../model/reset_tb.v
../../model/DW_stream_sync.v
../../model/DW_reset_sync.v
../../model/DW_sync.v
../../model/DW_pulse_sync.v
../../sim/chip_top/TB.sv
../../rtl/define/chip_undefine.v