../../rtl/define/chip_define.v
../../sim/chip_top/TB.sv
../../model/spi_if.sv
../../model/DW01_addsub.v
../../model/DW02_mult.v
../../model/DW_mult_pipe.v
../../model/clk_gen.v
../../model/clock_tb.v
../../model/reset_tb.v
../../model/thermo2binary_top.v
../../model/thermo7_binary3.v
../../model/thermo15_binary4.v
../../model/glbl.v
../../rtl/memory/tsdn28hpcpuhdb128x128m4mw_170a_ffg0p99v0c.v
../../rtl/memory/tsdn28hpcpuhdb4096x32m4mw_170a_ffg0p99v0c.v
../../rtl/memory/tsdn28hpcpuhdb64x32m4mw_170a_ffg0p99v0c.v
../../rtl/memory/tsdn28hpcpuhdb512x128m4mwr_170a_ffg0p99v0c.v
../../rtl/memory/tsdn28hpcpuhdb4096x128m4mw_170a_ffg0p99v0c.v
../../rtl/dem/DEM_31MSB_decoder_1ch.v
../../rtl/dem/DEM_31MSB_decoder_16ch_XY.v
/data/pdk/TSMCHOME/digital/Front_End/verilog/tphn28hpcpgv18_110a/tphn28hpcpgv18.v
../../lib/tcbn28hpcplusbwp7t35p140.v
../../syn/current/outputs/xyz_chip_top.syn.v