`include "../define/chip_define.v" module da4008_chip_top ( //spi port input PI_sclk // Spi Clock ,input PI_csn // Spi Chip Select active low ,input PI_mosi // Spi Mosi ,output PO_miso // Spi Miso //irq ,output PO_irq //system port ,input PI_async_rstn ,input PI_sync_in ,output PO_sync_out ,input clk //lvds rx ,input [3 :0] lvds_data ,input [0 :0] lvds_valid ,input [0 :0] lvds_clk ,output [2 :0] phase_tap //DAC Data ,output [6 :0] MSB_OUT [63:0] ,output [4 :0] LSB_OUT [63:0] ,output MSB_DUM [63:0] ,output DEM_VLD //DAC Cfg Port ,output [3 :0] Rterm ,output [2 :0] CasAddr ,output [2 :0] CasDw ,output [9 :0] IMainCtrl ,output [3 :0] IBleedCtrl ,output [3 :0] ICkCml ,output [31 :0] CurRsv0 ,output [31 :0] CurRsv1 //CLK Cfg Port ,output [0 :0] CcalRstn ,output [3 :0] EnAllP ,output [0 :0] DccEn ,output [0 :0] CasGateCkCtrl ,output [0 :0] SpiEnPi ,output [0 :0] SpiEnQec ,output [0 :0] SpiEnDcc ,output [4 :0] SpiQecCtrlIp ,output [4 :0] SpiQecCtrlIn ,output [4 :0] SpiQecCtrlQp ,output [4 :0] SpiQecCtrlQn ,output [5 :0] SpiDccCtrlIup ,output [5 :0] SpiDccCtrlIdn ,output [5 :0] SpiDccCtrlQup ,output [5 :0] SpiDccCtrlQdn ,output [7 :0] SpiSiqNOut ,output [7 :0] SpiSiqPOut ,output [3 :0] SpiSiPOut ,output [3 :0] SpiSqPOut ,output [2 :0] CrtlCrossOverN ,output [2 :0] CrtlCrossOverP ,output [31 :0] CcalRsv0 ,output [31 :0] CcalRsv1 ,output [3 :0] SelCk10GDig ,output [3 :0] SelCk2p5GDig ,output [8 :0] SelCk625MDig ,output [15 :0] P2sDataEn ,output [15 :0] P2sEnAllP ,output [15 :0] EnPiP ,output [15 :0] CkDivRstn ,output [31 :0] p2srsv0 ,output [31 :0] p2srsv1 ,output [15 :0] CkRxSw ,output [15 :0] RstnCk ,output [15 :0] CtrlZin ); //------------------------------iopad instantiation start-------------------------------------- // iopad //--------------------------------------------------------------------------------------------- wire async_rstn ; wire sync_in ; wire sync_out ; wire sclk ; wire csn ; wire mosi ; wire miso ; wire oen ; wire irq ; iopad U_iopad ( //+++++++++++++++++++++++++++++++++++++++++++++// // PAD Strat // //+++++++++++++++++++++++++++++++++++++++++++++// .PI_async_rstn ( PI_async_rstn ) ,.PI_sync_in ( PI_sync_in ) ,.PO_sync_out ( PO_sync_out ) ,.PI_sclk ( PI_sclk ) ,.PI_csn ( PI_csn ) ,.PI_mosi ( PI_mosi ) ,.PO_miso ( PO_miso ) ,.PO_irq ( PO_irq ) //+++++++++++++++++++++++++++++++++++++++++++++// // PAD End // //+++++++++++++++++++++++++++++++++++++++++++++// //+++++++++++++++++++++++++++++++++++++++++++++// // Internal signal Start // //+++++++++++++++++++++++++++++++++++++++++++++// ,.async_rstn ( async_rstn ) ,.sync_in ( sync_in ) ,.sync_out ( sync_out ) ,.sclk ( sclk ) ,.csn ( csn ) ,.mosi ( mosi ) ,.miso ( miso ) ,.oen ( oen ) ,.irq_n ( ~irq ) ); //------------------------------spi_slave instantiation start---------------------------------- // spi_slave //--------------------------------------------------------------------------------------------- wire [7 :0] wave_data_out [63:0] ; wire wave_data_valid ; wire [14 :0] Set [63:0] ; wire PrbsEn ; digital_top digital_top ( .clk ( clk ) ,.rst_n ( async_rstn ) ,.sync_in ( sync_in ) ,.sync_out ( sync_out ) ,.cfgid ( 5'b00000 ) ,.sclk ( sclk ) ,.csn ( csn ) ,.mosi ( mosi ) ,.miso ( miso ) ,.oen ( oen ) ,.irq ( irq ) ,.wave_data_out ( wave_data_out ) ,.wave_data_valid ( wave_data_valid ) ,.lvds_data ( lvds_data ) ,.lvds_valid ( lvds_valid ) ,.lvds_clk ( lvds_clk ) ,.phase_tap ( phase_tap ) ,.Rterm ( Rterm ) ,.PrbsEn ( PrbsEn ) ,.Set ( Set ) ,.CasAddr ( CasAddr ) ,.CasDw ( CasDw ) ,.IMainCtrl ( IMainCtrl ) ,.IBleedCtrl ( IBleedCtrl ) ,.ICkCml ( ICkCml ) ,.CurRsv0 ( CurRsv0 ) ,.CurRsv1 ( CurRsv1 ) ,.CcalRstn ( CcalRstn ) ,.EnAllP ( EnAllP ) ,.DccEn ( DccEn ) ,.CasGateCkCtrl ( CasGateCkCtrl ) ,.SpiEnPi ( SpiEnPi ) ,.SpiEnQec ( SpiEnQec ) ,.SpiEnDcc ( SpiEnDcc ) ,.SpiQecCtrlIp ( SpiQecCtrlIp ) ,.SpiQecCtrlIn ( SpiQecCtrlIn ) ,.SpiQecCtrlQp ( SpiQecCtrlQp ) ,.SpiQecCtrlQn ( SpiQecCtrlQn ) ,.SpiDccCtrlIup ( SpiDccCtrlIup ) ,.SpiDccCtrlIdn ( SpiDccCtrlIdn ) ,.SpiDccCtrlQup ( SpiDccCtrlQup ) ,.SpiDccCtrlQdn ( SpiDccCtrlQdn ) ,.SpiSiqNOut ( SpiSiqNOut ) ,.SpiSiqPOut ( SpiSiqPOut ) ,.SpiSiPOut ( SpiSiPOut ) ,.SpiSqPOut ( SpiSqPOut ) ,.CrtlCrossOverN ( CrtlCrossOverN ) ,.CrtlCrossOverP ( CrtlCrossOverP ) ,.CcalRsv0 ( CcalRsv0 ) ,.CcalRsv1 ( CcalRsv1 ) ,.SelCk10GDig ( SelCk10GDig ) ,.SelCk2p5GDig ( SelCk2p5GDig ) ,.SelCk625MDig ( SelCk625MDig ) ,.P2sDataEn ( P2sDataEn ) ,.P2sEnAllP ( P2sEnAllP ) ,.EnPiP ( EnPiP ) ,.CkDivRstn ( CkDivRstn ) ,.p2srsv0 ( p2srsv0 ) ,.p2srsv1 ( p2srsv1 ) ,.CkRxSw ( CkRxSw ) ,.RstnCk ( RstnCk ) ,.CtrlZin ( CtrlZin ) ); //------------------------------spi_slave instantiation start---------------------------------- // DEM //--------------------------------------------------------------------------------------------- sirv_gnrl_dffr #(1) DEM_VLD_dffr (wave_data_valid, DEM_VLD, clk, async_rstn); DEM_PhaseSync_4008 U_DEM_PhaseSync_4008 ( .clk ( clk ) ,.prbs_en ( PrbsEn ) ,.RST_N ( async_rstn ) ,.dem_set ( Set ) ,.data_in ( wave_data_out ) ,.MSB_OUT ( MSB_OUT ) ,.LSB_OUT ( LSB_OUT ) ,.MSB_DUM ( MSB_DUM ) ); endmodule `include "../define/chip_undefine.v"