//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    iopad.v
//  Department            :    
//  Author                :    pwy
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  1.2         2024-06-12       pwy           Integrate a digital module and two SPI modules with PLL
//  1.3         2024-11-12       pwy           Adding an Attenuator Configuration Interface
//  1.4         2025-08-14       pwy           Modify IRQ output logic
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//          
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------
`include "../define/chip_define.v"
module iopad (
  //+++++++++++++++++++++++++++++++++++++++++++++//
  //                 PAD Strat                   //
  //+++++++++++++++++++++++++++++++++++++++++++++//
   input          PI_async_rstn        // hardware Reset, active low           
  //sync
  ,input          PI_sync_in           // Chip synchronization signal input, high pulse valid
  ,output         PO_sync_out          // Chip synchronization signal output, high pulse valid
  //spi port                        
  ,input          PI_sclk              // Spi Clock
  ,input          PI_csn               // Spi Chip Select active low
  ,input          PI_mosi              // Spi Mosi
  ,output         PO_miso              // Spi Miso
  //irq
  ,output         PO_irq               // Interrupt signal in the chip, high level active
  //+++++++++++++++++++++++++++++++++++++++++++++//
  //                  PAD End                    //                    
  //+++++++++++++++++++++++++++++++++++++++++++++//

  //+++++++++++++++++++++++++++++++++++++++++++++//
  //           Internal signal Start             //
  //+++++++++++++++++++++++++++++++++++++++++++++// 
  ,output         async_rstn        // hardware Reset, active low           
  //sync
  ,output         sync_in           // Chip synchronization signal to analog, high pulse valid
  ,input          sync_out          // Chip synchronization signal output, high pulse valid
  //spi port                        
  ,output         sclk              // Spi Clock
  ,output         csn               // Spi Chip Select active low
  ,output         mosi              // Spi Mosi
  ,input          miso              // Spi Miso
  ,input          oen               // Spi Miso output enable
  //irq
  ,input          irq_n             // Interrupt signal in the chip, high level active    
);

`ifdef TSMC_IC
//++++++++++++++++++++++++++++++++++++++++++++++++++//
//                ASIC PAD --> TSMC                 //                    
//++++++++++++++++++++++++++++++++++++++++++++++++++//
//PI_async_rstn,pull-up
PDUW04SDGZ_V_G PDUW08SDGZ_V_G_async_rstn    (
  .I                                        ( 1'b0          )
 ,.OEN                                      ( 1'b1          )
 ,.REN                                      ( 1'b0          )
 ,.PAD                                      ( PI_async_rstn )
 ,.C                                        ( async_rstn    )
);                                          
                                            
//sync_in,pull-down                                  
PDDW04SDGZ_V_G PDDW04SDGZ_V_G_sync_in       (
  .I                                        ( 1'b0          )
 ,.OEN                                      ( 1'b1          )
 ,.REN                                      ( 1'b0          )
 ,.PAD                                      ( PI_sync_in    )
 ,.C                                        ( sync_in       )
);                                          
                                            
//sync_out,pull-down                                   
PDDW04SDGZ_V_G PDDW08SDGZ_V_G_sync_out      (
  .I                                        ( sync_out      )
 ,.OEN                                      ( 1'b0          )
 ,.REN                                      ( 1'b0          )
 ,.PAD                                      ( PO_sync_out   )
 ,.C                                        (               )
);

//sclk,pull-up
PDUW04SDGZ_V_G PDUW04SDGZ_V_G_sclk          (
  .I                                        ( 1'b0          )
 ,.OEN                                      ( 1'b1          )
 ,.REN                                      ( 1'b0          )
 ,.PAD                                      ( PI_sclk       )
 ,.C                                        ( sclk          )
); 

//csn,pull-up
PDUW04SDGZ_V_G PDUW04SDGZ_V_G_csn           (
  .I                                        ( 1'b0          )
 ,.OEN                                      ( 1'b1          )
 ,.REN                                      ( 1'b0          )
 ,.PAD                                      ( PI_csn        )
 ,.C                                        ( csn           )
);

//mosi,pull-up
PDUW08SDGZ_V_G PDUW08SDGZ_V_G_mosi          (
  .I                                        ( 1'b0          )
 ,.OEN                                      ( 1'b1          )
 ,.REN                                      ( 1'b0          )
 ,.PAD                                      ( PI_mosi       )
 ,.C                                        ( mosi          )
);

//miso,pull-up                                  
PDUW08SDGZ_V_G PDUW08SDGZ_V_G_miso          (
  .I                                        ( miso          )
 ,.OEN                                      ( oen           )
 ,.REN                                      ( 1'b0          )
 ,.PAD                                      ( PO_miso       )
 ,.C                                        (               )
);

//irq,pull-up                                  
PDUW08SDGZ_V_G PDUW08SDGZ_V_G_irq           (
  .I                                        ( 1'b0          )
 ,.OEN                                      ( irq_n         )
 ,.REN                                      ( 1'b0          )
 ,.PAD                                      ( PO_irq        )
 ,.C                                        (               )
);
  


`elsif XILINX_FPGA
//++++++++++++++++++++++++++++++++++++++++++++++++++//
//                FPGA PAD --> Xlinx                //                    
//++++++++++++++++++++++++++++++++++++++++++++++++++//
//async_rstn
assign async_rstn   = PI_async_rstn     ;  
//sync_in                               
assign sync_to_analog = PI_sync_in        ; 
//sync_out                              
assign PO_sync_out  =  sync_out         ; 
//Feedback signal                       
assign ch0_feedback = PI_ch0_feedback   ;  
`ifdef CHANNEL_IS_FOUR                  
assign ch1_feedback = PI_ch1_feedback   ;  
assign ch2_feedback = PI_ch2_feedback   ; 
assign ch3_feedback = PI_ch3_feedback   ; 
`endif                                  
//config chip id                        
assign cfgid        = PI_cfgid          ;                                           
//spi port                                    
assign sclk         = PI_sclk           ;      
assign csn          = PI_csn            ;   
assign mosi         = PI_mosi           ;   
assign PO_miso      = oen ? 1'bz : miso ;
//irq                                 
assign PO_irq       = irq_n             ; 
                               
`ifdef CHANNEL_IS_FOUR       
assign PO_ch0_att   = ch0_att           ;               
assign PO_ch1_att   = ch1_att           ;                                
assign PO_ch2_att   = ch2_att           ;                             
assign PO_ch3_att   = ch3_att           ;                             
`endif
         
`endif

endmodule
`include "../define/chip_undefine.v"