module DA4008_DEM_Parallel_PRBS_1CH ( clk,
		data_in,
		prbs_en,
		set,
                MSB_DUM_IN,
		DEM_LSB_OUT,
		DEM_MSB_OUT,
                DEM_MSB_DUM

);



input clk, prbs_en;
input [7:0] data_in;
input [14:0] set;
input MSB_DUM_IN;
output [4:0] DEM_LSB_OUT;
output [6:0] DEM_MSB_OUT;
output DEM_MSB_DUM;

 
reg [14:0]r_shift_data;
 
always @(posedge clk or negedge prbs_en)
begin
        if(!prbs_en)

           r_shift_data <=set;

        else

        begin

           r_shift_data[0] <=r_shift_data[3];

           r_shift_data[1] <= r_shift_data[4];

           r_shift_data[2] <= r_shift_data[5];

           r_shift_data[3] <= r_shift_data[6];

           r_shift_data[4] <= r_shift_data[7];

           r_shift_data[5] <= r_shift_data[8];

           r_shift_data[6] <= r_shift_data[9];

           r_shift_data[7] <= r_shift_data[10];
                                             
           r_shift_data[8] <= r_shift_data[11];
                                             
           r_shift_data[9] <= r_shift_data[12];

           r_shift_data[10] <= r_shift_data[13];

           r_shift_data[11] <= r_shift_data[14];

           r_shift_data[12] <= r_shift_data[0]^r_shift_data[1];
		   
           r_shift_data[13] <= r_shift_data[2]^r_shift_data[1];

           r_shift_data[14] <= r_shift_data[3]^r_shift_data[2];
        end
end

wire [2:0]dd;

assign dd = {r_shift_data[0],r_shift_data[1], r_shift_data[2]};

reg     [6:0]   r_MSB_BUF0;

always @(posedge clk)

begin

        case(dd[2:0])

                3'd0: r_MSB_BUF0 <= {data_in[7],data_in[7],data_in[7],data_in[7],data_in[6],data_in[6],data_in[5]};
				
                3'd1: r_MSB_BUF0 <= {data_in[7],data_in[7],data_in[7],data_in[6],data_in[6],data_in[5],data_in[7]};
				
                3'd2: r_MSB_BUF0 <= {data_in[7],data_in[7],data_in[6],data_in[6],data_in[5],data_in[7],data_in[7]};
				
                3'd3: r_MSB_BUF0 <= {data_in[7],data_in[6],data_in[6],data_in[5],data_in[7],data_in[7],data_in[7]};
				
                3'd4: r_MSB_BUF0 <= {data_in[6],data_in[6],data_in[5],data_in[7],data_in[7],data_in[7],data_in[7]};
				
                3'd5: r_MSB_BUF0 <= {data_in[6],data_in[5],data_in[7],data_in[7],data_in[7],data_in[7],data_in[6]};
				
                3'd6: r_MSB_BUF0 <= {data_in[5],data_in[7],data_in[7],data_in[7],data_in[7],data_in[6],data_in[6]};
				
                3'd7: r_MSB_BUF0 <= {data_in[7],data_in[7],data_in[7],data_in[7],data_in[6],data_in[6],data_in[5]};

        endcase

end

reg     [4:0]   r_LSB_BUF0;
reg		r_DUM_BUF;

always @(posedge clk)

begin

        r_LSB_BUF0 <= {data_in[4],data_in[3],data_in[2],data_in[1],data_in[0]};
        r_DUM_BUF <= MSB_DUM_IN;

end

assign  DEM_LSB_OUT = r_LSB_BUF0;
assign  DEM_MSB_DUM = r_DUM_BUF;
assign  DEM_MSB_OUT = r_MSB_BUF0;


endmodule