//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    dacif.v
//  Department            :    
//  Author                :    PWY
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.4         2024-03-12      PWY
//  0.9         2024-06-19      PWY             Add 2x, 4x, and 8x interpolation modes to EZQ2.0S.
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------
 
module dacif (
   input         clk
  ,input         rstn
  ,input         din_vld
  ,output        dout_vld
  //mixer data input 
  ,input  [7:0]  din [63:0]
  //data output
  ,output [7:0]  dout[63:0]
);

wire[1 :0] dacif_vld_dly;
sirv_gnrl_dffr #(2) dacif_vld_dffr ({dacif_vld_dly[0], din_vld}, dacif_vld_dly, clk, rstn);

////////////////////////////////////////////////////
// regs
////////////////////////////////////////////////////

wire[7:0] mux_p   [63:0];

wire[7:0] dout_w  [63:0];

genvar k;
generate

  for(k = 0; k < 64; k = k + 1) begin

    sirv_gnrl_dfflr #(8) mux_dfflr (1'b1, {~din[k][7], din[k][6:0]}, mux_p[k], clk, rstn);

  end
endgenerate


genvar m;
generate
  ////////////////////////////////////////////////////
  // mode select
  ////////////////////////////////////////////////////
  for(m = 0; m < 64; m = m + 1) begin
    
    assign dout_w[m] =  mux_p   [m] ;
    sirv_gnrl_dfflrd #(8) dout_dfflrd (8'h80, 1'b1, dout_w[m], dout[m], clk, rstn); 

  end
endgenerate

assign dout_vld = dacif_vld_dly[1];

endmodule