`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 2026/02/28 19:57:30 // Design Name: // Module Name: dac_regfile // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // Revision Date: 2026/02/28 19:57:30 // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// // ----------------------------------------------------------- // -- Register address offset macros // ----------------------------------------------------------- //Prbs_en Ctrl Register `define RTERMR 16'h0000 `define PRBSENR 16'h0004 `define SET0R 16'h0008 `define SET1R 16'h000C `define SET2R 16'h0010 `define SET3R 16'h0014 `define SET4R 16'h0018 `define SET5R 16'h001C `define SET6R 16'h0020 `define SET7R 16'h0024 `define SET8R 16'h0028 `define SET9R 16'h002C `define SET10R 16'h0030 `define SET11R 16'h0034 `define SET12R 16'h0038 `define SET13R 16'h003C `define SET14R 16'h0040 `define SET15R 16'h0044 `define SET16R 16'h0048 `define SET17R 16'h004C `define SET18R 16'h0050 `define SET19R 16'h0054 `define SET20R 16'h0058 `define SET21R 16'h005C `define SET22R 16'h0060 `define SET23R 16'h0064 `define SET24R 16'h0068 `define SET25R 16'h006C `define SET26R 16'h0070 `define SET27R 16'h0074 `define SET28R 16'h0078 `define SET29R 16'h007C `define SET30R 16'h0080 `define SET31R 16'h0084 `define CASADDRR 16'h0088 `define CASDWR 16'h008C `define IMCTR 16'h0090 `define IBLEEDCTR 16'h0094 `define ICLKCMLR 16'h0098 `define CURRSVR0 16'h009C `define CURRSVR1 16'h00A0 `define VERSIONR 16'h00A4 module dac_regfile #( parameter DACVERSION = 32'h2026_0510 ) ( //system port input clk // System Main Clock ,input rstn // Spi Reset active low //rw op port ,input [31 :0] wrdata // write data ,input wren // write enable ,input [15 :0] rwaddr // read & write address ,input rden // read enable ,output [31 :0] rddata // read data ,output [3 :0] Rterm // R_Terminate ,output PrbsEn // Prbs_en ,output [14 :0] Set [63:0] ,output [2 :0] CasAddr ,output [2 :0] CasDw ,output [9 :0] IMainCtrl ,output [3 :0] IBleedCtrl ,output [3 :0] ICkCml ,output [31 :0] CurRsv0 ,output [31 :0] CurRsv1 ); localparam L = 1'b0, H = 1'b1; // ------------------------------------------------------ // -- Register Default Vaule // ------------------------------------------------------ wire [3 :0] rtermrdft = 4'b0001 ; // RTERMR 16'h0000 wire [0 :0] prbsrdft = 1'b0 ; // PRBSENR 16'h0004 wire [31:0] set0rdft = {16'h05,16'h3B} ; // SET0R 16'h0008 wire [31:0] set1rdft = {16'h49,16'h19} ; // SET1R 16'h000C wire [31:0] set2rdft = {16'h4D,16'h9D} ; // SET2R 16'h0010 wire [31:0] set3rdft = {16'h89,16'h41} ; // SET3R 16'h0014 wire [31:0] set4rdft = {16'h40,16'hA6} ; // SET4R 16'h0018 wire [31:0] set5rdft = {16'h55,16'h14} ; // SET5R 16'h001C wire [31:0] set6rdft = {16'h03,16'h97} ; // SET6R 16'h0020 wire [31:0] set7rdft = {16'h2A,16'hD1} ; // SET7R 16'h0024 wire [31:0] set8rdft = {16'h42,16'h78} ; // SET8R 16'h0028 wire [31:0] set9rdft = {16'h12,16'h33} ; // SET9R 16'h002C wire [31:0] set10rdft = {16'h33,16'h01} ; // SET10R 16'h0030 wire [31:0] set11rdft = {16'hD0,16'h15} ; // SET11R 16'h0034 wire [31:0] set12rdft = {16'hB9,16'h15} ; // SET12R 16'h0038 wire [31:0] set13rdft = {16'hDF,16'h38} ; // SET13R 16'h003C wire [31:0] set14rdft = {16'h35,16'h7C} ; // SET14R 16'h0040 wire [31:0] set15rdft = {16'hAA,16'hDF} ; // SET15R 16'h0044 wire [31:0] set16rdft = {16'h66,16'h83} ; // SET16R 16'h0048 wire [31:0] set17rdft = {16'hC2,16'h8F} ; // SET17R 16'h004C wire [31:0] set18rdft = {16'hC4,16'hD0} ; // SET18R 16'h0050 wire [31:0] set19rdft = {16'hA3,16'hAE} ; // SET19R 16'h0054 wire [31:0] set20rdft = {16'h3F,16'hA0} ; // SET20R 16'h0058 wire [31:0] set21rdft = {16'hCD,16'h39} ; // SET21R 16'h005C wire [31:0] set22rdft = {16'h30,16'hF4} ; // SET22R 16'h0060 wire [31:0] set23rdft = {16'h24,16'hD6} ; // SET23R 16'h0064 wire [31:0] set24rdft = {16'h89,16'h26} ; // SET24R 16'h0068 wire [31:0] set25rdft = {16'h7F,16'h05} ; // SET25R 16'h006C wire [31:0] set26rdft = {16'h28,16'hF9} ; // SET26R 16'h0070 wire [31:0] set27rdft = {16'hC9,16'hCC} ; // SET27R 16'h0074 wire [31:0] set28rdft = {16'h8E,16'hEF} ; // SET28R 16'h0078 wire [31:0] set29rdft = {16'hC0,16'h5B} ; // SET29R 16'h007C wire [31:0] set30rdft = {16'hD6,16'h08} ; // SET30R 16'h0080 wire [31:0] set31rdft = {16'h20,16'hB0} ; // SET31R 16'h0084 wire [2 :0] casaddrrdft = 3'b111 ; // CASADDRR 16'h0088 wire [2 :0] casdwrdft = 3'b111 ; // CASDWR 16'h008C wire [9 :0] imctrdft = 10'b11_0000_0000 ; // IMCTR 16'h0090 wire [3 :0] ibleedctrdft = 4'b0111 ; // IBLEEDCTR 16'h0094 wire [3 :0] iclkcmlrdft = 4'b0111 ; // ICLKCMLR 16'h0098 wire [31:0] currsvr0dft = 32'h0 ; // CURRSVR0 16'h009C wire [31:0] currsvr1dft = 32'h0 ; // CURRSVR1 16'h00A0 // ------------------------------------------------------ // -- Register enable (select) wires // ------------------------------------------------------ wire rtermren ; // RTERMR Enable wire prbsren ; // PRBSENR Enable wire set0ren ; // SET0R Enable wire set1ren ; // SET1R Enable wire set2ren ; // SET2R Enable wire set3ren ; // SET3R Enable wire set4ren ; // SET4R Enable wire set5ren ; // SET5R Enable wire set6ren ; // SET6R Enable wire set7ren ; // SET7R Enable wire set8ren ; // SET8R Enable wire set9ren ; // SET9R Enable wire set10ren ; // SET10R Enable wire set11ren ; // SET11R Enable wire set12ren ; // SET12R Enable wire set13ren ; // SET13R Enable wire set14ren ; // SET14R Enable wire set15ren ; // SET15R Enable wire set16ren ; // SET16R Enable wire set17ren ; // SET17R Enable wire set18ren ; // SET18R Enable wire set19ren ; // SET19R Enable wire set20ren ; // SET20R Enable wire set21ren ; // SET21R Enable wire set22ren ; // SET22R Enable wire set23ren ; // SET23R Enable wire set24ren ; // SET24R Enable wire set25ren ; // SET25R Enable wire set26ren ; // SET26R Enable wire set27ren ; // SET27R Enable wire set28ren ; // SET28R Enable wire set29ren ; // SET29R Enable wire set30ren ; // SET30R Enable wire set31ren ; // SET31R Enable wire casaddrren ; // CASADDRR Enable wire casdwren ; // CASDWR Enable wire imctren ; // IMCTR Enable wire ibleedctren ; // IBLEEDCTR Enable wire iclkcmlren ; // ICLKCMLR Enable wire currsvr0en ; // CURRSVR0 Enable wire currsvr1en ; // CURRSVR1 Enable wire verren ; // VERSIONR Enable // ------------------------------------------------------ // -- Register write enable wires // ------------------------------------------------------ wire rtermrwe ; // RTERMR Write Enable wire prbsrwe ; // PRBSENR Write Enable wire set0rwe ; // SET0R Write Enable wire set1rwe ; // SET1R Write Enable wire set2rwe ; // SET2R Write Enable wire set3rwe ; // SET3R Write Enable wire set4rwe ; // SET4R Write Enable wire set5rwe ; // SET5R Write Enable wire set6rwe ; // SET6R Write Enable wire set7rwe ; // SET7R Write Enable wire set8rwe ; // SET8R Write Enable wire set9rwe ; // SET9R Write Enable wire set10rwe ; // SET10R Write Enable wire set11rwe ; // SET11R Write Enable wire set12rwe ; // SET12R Write Enable wire set13rwe ; // SET13R Write Enable wire set14rwe ; // SET14R Write Enable wire set15rwe ; // SET15R Write Enable wire set16rwe ; // SET16R Write Enable wire set17rwe ; // SET17R Write Enable wire set18rwe ; // SET18R Write Enable wire set19rwe ; // SET19R Write Enable wire set20rwe ; // SET20R Write Enable wire set21rwe ; // SET21R Write Enable wire set22rwe ; // SET22R Write Enable wire set23rwe ; // SET23R Write Enable wire set24rwe ; // SET24R Write Enable wire set25rwe ; // SET25R Write Enable wire set26rwe ; // SET26R Write Enable wire set27rwe ; // SET27R Write Enable wire set28rwe ; // SET28R Write Enable wire set29rwe ; // SET29R Write Enable wire set30rwe ; // SET30R Write Enable wire set31rwe ; // SET31R Write Enable wire casaddrrwe ; // CASADDRR Write Enable wire casdwrwe ; // CASDWR Write Enable wire imctrwe ; // IMCTR Write Enable wire ibleedctrwe ; // IBLEEDCTR Write Enable wire iclkcmlrwe ; // ICLKCMLR Write Enable wire currsvr0we ; // CURRSVR0 Write Enable wire currsvr1we ; // CURRSVR1 Write Enable // ------------------------------------------------------ // -- Misc Registers // ------------------------------------------------------ wire [3 :0] rtermr ; // RTERMR Register, Default vaule is 4'b0001 wire [0 :0] prbsr ; // PRBSENR Register, Default vaule is 1'b0 wire [31:0] set0r ; // SET0R Register, Default vaule is {16'h05,16'h3B} wire [31:0] set1r ; // SET1R Register, Default vaule is {16'h49,16'h19} wire [31:0] set2r ; // SET2R Register, Default vaule is {16'h4D,16'h9D} wire [31:0] set3r ; // SET3R Register, Default vaule is {16'h89,16'h41} wire [31:0] set4r ; // SET4R Register, Default vaule is {16'h40,16'hA6} wire [31:0] set5r ; // SET5R Register, Default vaule is {16'h55,16'h14} wire [31:0] set6r ; // SET6R Register, Default vaule is {16'h03,16'h97} wire [31:0] set7r ; // SET7R Register, Default vaule is {16'h2A,16'hD1} wire [31:0] set8r ; // SET8R Register, Default vaule is {16'h42,16'h78} wire [31:0] set9r ; // SET9R Register, Default vaule is {16'h12,16'h33} wire [31:0] set10r ; // SET10R Register, Default vaule is {16'h33,16'h01} wire [31:0] set11r ; // SET11R Register, Default vaule is {16'hD0,16'h15} wire [31:0] set12r ; // SET12R Register, Default vaule is {16'hB9,16'h15} wire [31:0] set13r ; // SET13R Register, Default vaule is {16'hDF,16'h38} wire [31:0] set14r ; // SET14R Register, Default vaule is {16'h35,16'h7C} wire [31:0] set15r ; // SET15R Register, Default vaule is {16'hAA,16'hDF} wire [31:0] set16r ; // SET16R Register, Default vaule is {16'h66,16'h83} wire [31:0] set17r ; // SET17R Register, Default vaule is {16'hC2,16'h8F} wire [31:0] set18r ; // SET18R Register, Default vaule is {16'hC4,16'hD0} wire [31:0] set19r ; // SET19R Register, Default vaule is {16'hA3,16'hAE} wire [31:0] set20r ; // SET20R Register, Default vaule is {16'h3F,16'hA0} wire [31:0] set21r ; // SET21R Register, Default vaule is {16'hCD,16'h39} wire [31:0] set22r ; // SET22R Register, Default vaule is {16'h30,16'hF4} wire [31:0] set23r ; // SET23R Register, Default vaule is {16'h24,16'hD6} wire [31:0] set24r ; // SET24R Register, Default vaule is {16'h89,16'h26} wire [31:0] set25r ; // SET25R Register, Default vaule is {16'h7F,16'h05} wire [31:0] set26r ; // SET26R Register, Default vaule is {16'h28,16'hF9} wire [31:0] set27r ; // SET27R Register, Default vaule is {16'hC9,16'hCC} wire [31:0] set28r ; // SET28R Register, Default vaule is {16'h8E,16'hEF} wire [31:0] set29r ; // SET29R Register, Default vaule is {16'hC0,16'h5B} wire [31:0] set30r ; // SET30R Register, Default vaule is {16'hD6,16'h08} wire [31:0] set31r ; // SET31R Register, Default vaule is {16'h20,16'hB0} wire [2 :0] casaddrr ; // CASADDRR Register, Default vaule is 3'b111 wire [2 :0] casdwr ; // CASDWR Register, Default vaule is 3'b111 wire [9 :0] imctr ; // IMCTR Register, Default vaule is 9'b11_0000_0000 wire [3 :0] ibleedctr ; // IBLEEDCTR Register, Default vaule is 4'b0111 wire [3 :0] iclkcmlr ; // ICLKCMLR Register, Default vaule is 4'b0111 wire [31:0] currsvr0 ; // CURRSVR0 Register, Default vaule is 32'h0 wire [31:0] currsvr1 ; // CURRSVR1 Register, Default vaule is 32'h0 reg [31 :0] rddata_reg ; // ------------------------------------------------------ // -- Address decoder // // Decodes the register address offset input(reg_addr) // to produce enable (select) signals for each of the // SW-registers in the macrocell. The reg_addr input // is bits [15:0] of the paddr bus. // -------------------------------------------------- ---- assign rtermren = (rwaddr[15:2] == `RTERMR >>2) ? 1'b1 : 1'b0; // RTERMR Enable assign prbsren = (rwaddr[15:2] == `PRBSENR >>2) ? 1'b1 : 1'b0; // PRBSENR Enable assign set0ren = (rwaddr[15:2] == `SET0R >>2) ? 1'b1 : 1'b0; // SET0R Enable assign set1ren = (rwaddr[15:2] == `SET1R >>2) ? 1'b1 : 1'b0; // SET1R Enable assign set2ren = (rwaddr[15:2] == `SET2R >>2) ? 1'b1 : 1'b0; // SET2R Enable assign set3ren = (rwaddr[15:2] == `SET3R >>2) ? 1'b1 : 1'b0; // SET3R Enable assign set4ren = (rwaddr[15:2] == `SET4R >>2) ? 1'b1 : 1'b0; // SET4R Enable assign set5ren = (rwaddr[15:2] == `SET5R >>2) ? 1'b1 : 1'b0; // SET5R Enable assign set6ren = (rwaddr[15:2] == `SET6R >>2) ? 1'b1 : 1'b0; // SET6R Enable assign set7ren = (rwaddr[15:2] == `SET7R >>2) ? 1'b1 : 1'b0; // SET7R Enable assign set8ren = (rwaddr[15:2] == `SET8R >>2) ? 1'b1 : 1'b0; // SET8R Enable assign set9ren = (rwaddr[15:2] == `SET9R >>2) ? 1'b1 : 1'b0; // SET9R Enable assign set10ren = (rwaddr[15:2] == `SET10R >>2) ? 1'b1 : 1'b0; // SET10R Enable assign set11ren = (rwaddr[15:2] == `SET11R >>2) ? 1'b1 : 1'b0; // SET11R Enable assign set12ren = (rwaddr[15:2] == `SET12R >>2) ? 1'b1 : 1'b0; // SET12R Enable assign set13ren = (rwaddr[15:2] == `SET13R >>2) ? 1'b1 : 1'b0; // SET13R Enable assign set14ren = (rwaddr[15:2] == `SET14R >>2) ? 1'b1 : 1'b0; // SET14R Enable assign set15ren = (rwaddr[15:2] == `SET15R >>2) ? 1'b1 : 1'b0; // SET15R Enable assign set16ren = (rwaddr[15:2] == `SET16R >>2) ? 1'b1 : 1'b0; // SET16R Enable assign set17ren = (rwaddr[15:2] == `SET17R >>2) ? 1'b1 : 1'b0; // SET17R Enable assign set18ren = (rwaddr[15:2] == `SET18R >>2) ? 1'b1 : 1'b0; // SET18R Enable assign set19ren = (rwaddr[15:2] == `SET19R >>2) ? 1'b1 : 1'b0; // SET19R Enable assign set20ren = (rwaddr[15:2] == `SET20R >>2) ? 1'b1 : 1'b0; // SET20R Enable assign set21ren = (rwaddr[15:2] == `SET21R >>2) ? 1'b1 : 1'b0; // SET21R Enable assign set22ren = (rwaddr[15:2] == `SET22R >>2) ? 1'b1 : 1'b0; // SET22R Enable assign set23ren = (rwaddr[15:2] == `SET23R >>2) ? 1'b1 : 1'b0; // SET23R Enable assign set24ren = (rwaddr[15:2] == `SET24R >>2) ? 1'b1 : 1'b0; // SET24R Enable assign set25ren = (rwaddr[15:2] == `SET25R >>2) ? 1'b1 : 1'b0; // SET25R Enable assign set26ren = (rwaddr[15:2] == `SET26R >>2) ? 1'b1 : 1'b0; // SET26R Enable assign set27ren = (rwaddr[15:2] == `SET27R >>2) ? 1'b1 : 1'b0; // SET27R Enable assign set28ren = (rwaddr[15:2] == `SET28R >>2) ? 1'b1 : 1'b0; // SET28R Enable assign set29ren = (rwaddr[15:2] == `SET29R >>2) ? 1'b1 : 1'b0; // SET29R Enable assign set30ren = (rwaddr[15:2] == `SET30R >>2) ? 1'b1 : 1'b0; // SET30R Enable assign set31ren = (rwaddr[15:2] == `SET31R >>2) ? 1'b1 : 1'b0; // SET31R Enable assign casaddrren = (rwaddr[15:2] == `CASADDRR >>2) ? 1'b1 : 1'b0; // CASADDRR Enable assign casdwren = (rwaddr[15:2] == `CASDWR >>2) ? 1'b1 : 1'b0; // CASDWR Enable assign imctren = (rwaddr[15:2] == `IMCTR >>2) ? 1'b1 : 1'b0; // IMCTR Enable assign ibleedctren = (rwaddr[15:2] == `IBLEEDCTR >>2) ? 1'b1 : 1'b0; // IBLEEDCTR Enable assign iclkcmlren = (rwaddr[15:2] == `ICLKCMLR >>2) ? 1'b1 : 1'b0; // ICLKCMLR Enable assign currsvr0en = (rwaddr[15:2] == `CURRSVR0 >>2) ? 1'b1 : 1'b0; // CURRSVR0 Enable assign currsvr1en = (rwaddr[15:2] == `CURRSVR1 >>2) ? 1'b1 : 1'b0; // CURRSVR1 Enable assign verren = (rwaddr[15:2] == `VERSIONR >>2) ? 1'b1 : 1'b0; // VERSIONR Enable // ------------------------------------------------------ // -- Write enable signals // // Write enable signals for writable SW-registers. // The write enable for each register is the ANDed // result of the register enable and the input reg_wren // ------------------------------------------------------ assign rtermrwe = rtermren & wren; // RTERMR Write Enable assign prbsrwe = prbsren & wren; // PRBSENR Write Enable assign set0rwe = set0ren & wren; // SET0R Write Enable assign set1rwe = set1ren & wren; // SET1R Write Enable assign set2rwe = set2ren & wren; // SET2R Write Enable assign set3rwe = set3ren & wren; // SET3R Write Enable assign set4rwe = set4ren & wren; // SET4R Write Enable assign set5rwe = set5ren & wren; // SET5R Write Enable assign set6rwe = set6ren & wren; // SET6R Write Enable assign set7rwe = set7ren & wren; // SET7R Write Enable assign set8rwe = set8ren & wren; // SET8R Write Enable assign set9rwe = set9ren & wren; // SET9R Write Enable assign set10rwe = set10ren & wren; // SET10R Write Enable assign set11rwe = set11ren & wren; // SET11R Write Enable assign set12rwe = set12ren & wren; // SET12R Write Enable assign set13rwe = set13ren & wren; // SET13R Write Enable assign set14rwe = set14ren & wren; // SET14R Write Enable assign set15rwe = set15ren & wren; // SET15R Write Enable assign set16rwe = set16ren & wren; // SET16R Write Enable assign set17rwe = set17ren & wren; // SET17R Write Enable assign set18rwe = set18ren & wren; // SET18R Write Enable assign set19rwe = set19ren & wren; // SET19R Write Enable assign set20rwe = set20ren & wren; // SET20R Write Enable assign set21rwe = set21ren & wren; // SET21R Write Enable assign set22rwe = set22ren & wren; // SET22R Write Enable assign set23rwe = set23ren & wren; // SET23R Write Enable assign set24rwe = set24ren & wren; // SET24R Write Enable assign set25rwe = set25ren & wren; // SET25R Write Enable assign set26rwe = set26ren & wren; // SET26R Write Enable assign set27rwe = set27ren & wren; // SET27R Write Enable assign set28rwe = set28ren & wren; // SET28R Write Enable assign set29rwe = set29ren & wren; // SET29R Write Enable assign set30rwe = set30ren & wren; // SET30R Write Enable assign set31rwe = set31ren & wren; // SET31R Write Enable assign casaddrrwe = casaddrren & wren; // CASADDRR Write Enable assign casdwrwe = casdwren & wren; // CASDWR Write Enable assign imctrwe = imctren & wren; // IMCTR Write Enable assign ibleedctrwe = ibleedctren & wren; // IBLEEDCTR Write Enable assign iclkcmlrwe = iclkcmlren & wren; // ICLKCMLR Write Enable assign currsvr0we = currsvr0en & wren; // CURRSVR0 Write Enable assign currsvr1we = currsvr1en & wren; // CURRSVR1 Write Enable // ------------------------------------------------------ // -- rtermr Register // // Write prbs_reg for 'RTERMR' : 4-bit register // Register is split into the following bit fields // // [3:0] --> rtermr // ------------------------------------------------------ sirv_gnrl_dfflrd #(4) rtermr_dfflrd (rtermrdft, rtermrwe, wrdata[3:0], rtermr, clk, rstn); // ------------------------------------------------------ // -- prbsr Register // // Write prbs_reg for 'PRBSENR' : 1-bit register // Register is split into the following bit fields // // [0:0] --> prbsr // ------------------------------------------------------ sirv_gnrl_dfflrd #(1) prbsr_dfflrd (prbsrdft, prbsrwe, wrdata[0], prbsr, clk, rstn); // ------------------------------------------------------ // -- set0r Register // // Write set0r for 'SET0R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set0r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set0r_dfflrd (set0rdft, set0rwe, wrdata[31:0], set0r, clk, rstn); // ------------------------------------------------------ // -- set1r Register // // Write set1r for 'SET1R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set1r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set1r_dfflrd (set1rdft, set1rwe, wrdata[31:0], set1r, clk, rstn); // ------------------------------------------------------ // -- set2r Register // // Write set2r for 'SET2R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set2r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set2r_dfflrd (set2rdft, set2rwe, wrdata[31:0], set2r, clk, rstn); // ------------------------------------------------------ // -- set3r Register // // Write set3r for 'SET3R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set3r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set3r_dfflrd (set3rdft, set3rwe, wrdata[31:0], set3r, clk, rstn); // ------------------------------------------------------ // -- set4r Register // // Write set4r for 'SET4R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set4r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set4r_dfflrd (set4rdft, set4rwe, wrdata[31:0], set4r, clk, rstn); // ------------------------------------------------------ // -- set5r Register // // Write set5r for 'SET5R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set5r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set5r_dfflrd (set5rdft, set5rwe, wrdata[31:0], set5r, clk, rstn); // ------------------------------------------------------ // -- set6r Register // // Write set6r for 'SET6R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set6r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set6r_dfflrd (set6rdft, set6rwe, wrdata[31:0], set6r, clk, rstn); // ------------------------------------------------------ // -- set7r Register // // Write set7r for 'SET7R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set7r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set7r_dfflrd (set7rdft, set7rwe, wrdata[31:0], set7r, clk, rstn); // ------------------------------------------------------ // -- set8r Register // // Write set8r for 'SET8R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set8r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set8r_dfflrd (set8rdft, set8rwe, wrdata[31:0], set8r, clk, rstn); // ------------------------------------------------------ // -- set9r Register // // Write set9r for 'SET9R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set9r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set9r_dfflrd (set9rdft, set9rwe, wrdata[31:0], set9r, clk, rstn); // ------------------------------------------------------ // -- set10r Register // // Write set10r for 'SET10R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set10r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set10r_dfflrd (set10rdft, set10rwe, wrdata[31:0], set10r, clk, rstn); // ------------------------------------------------------ // -- set11r Register // // Write set11r for 'SET11R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set11r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set11r_dfflrd (set11rdft, set11rwe, wrdata[31:0], set11r, clk, rstn); // ------------------------------------------------------ // -- set12r Register // // Write set12r for 'SET12R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set12r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set12r_dfflrd (set12rdft, set12rwe, wrdata[31:0], set12r, clk, rstn); // ------------------------------------------------------ // -- set13r Register // // Write set13r for 'SET13R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set13r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set13r_dfflrd (set13rdft, set13rwe, wrdata[31:0], set13r, clk, rstn); // ------------------------------------------------------ // -- set14r Register // // Write set14r for 'SET14R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set14r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set14r_dfflrd (set14rdft, set14rwe, wrdata[31:0], set14r, clk, rstn); // ------------------------------------------------------ // -- set15r Register // // Write set15r for 'SET15R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set15r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set15r_dfflrd (set15rdft, set15rwe, wrdata[31:0], set15r, clk, rstn); // ------------------------------------------------------ // -- set16r Register // // Write set16r for 'SET16R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set16r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set16r_dfflrd (set16rdft, set16rwe, wrdata[31:0], set16r, clk, rstn); // ------------------------------------------------------ // -- set17r Register // // Write set17r for 'SET17R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set17r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set17r_dfflrd (set17rdft, set17rwe, wrdata[31:0], set17r, clk, rstn); // ------------------------------------------------------ // -- set18r Register // // Write set18r for 'SET18R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set18r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set18r_dfflrd (set18rdft, set18rwe, wrdata[31:0], set18r, clk, rstn); // ------------------------------------------------------ // -- set19r Register // // Write set19r for 'SET19R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set19r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set19r_dfflrd (set19rdft, set19rwe, wrdata[31:0], set19r, clk, rstn); // ------------------------------------------------------ // -- set20r Register // // Write set20r for 'SET20R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set20r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set20r_dfflrd (set20rdft, set20rwe, wrdata[31:0], set20r, clk, rstn); // ------------------------------------------------------ // -- set21r Register // // Write set21r for 'SET21R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set21r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set21r_dfflrd (set21rdft, set21rwe, wrdata[31:0], set21r, clk, rstn); // ------------------------------------------------------ // -- set22r Register // // Write set22r for 'SET22R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set22r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set22r_dfflrd (set22rdft, set22rwe, wrdata[31:0], set22r, clk, rstn); // ------------------------------------------------------ // -- set23r Register // // Write set23r for 'SET23R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set23r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set23r_dfflrd (set23rdft, set23rwe, wrdata[31:0], set23r, clk, rstn); // ------------------------------------------------------ // -- set24r Register // // Write set24r for 'SET24R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set24r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set24r_dfflrd (set24rdft, set24rwe, wrdata[31:0], set24r, clk, rstn); // ------------------------------------------------------ // -- set25r Register // // Write set25r for 'SET25R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set25r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set25r_dfflrd (set25rdft, set25rwe, wrdata[31:0], set25r, clk, rstn); // ------------------------------------------------------ // -- set26r Register // // Write set26r for 'SET26R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set26r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set26r_dfflrd (set26rdft, set26rwe, wrdata[31:0], set26r, clk, rstn); // ------------------------------------------------------ // -- set27r Register // // Write set27r for 'SET0R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set27r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set27r_dfflrd (set27rdft, set27rwe, wrdata[31:0], set27r, clk, rstn); // ------------------------------------------------------ // -- set28r Register // // Write set28r for 'SET0R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set28r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set28r_dfflrd (set28rdft, set28rwe, wrdata[31:0], set28r, clk, rstn); // ------------------------------------------------------ // -- set29r Register // // Write set29r for 'SET29R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set29r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set29r_dfflrd (set29rdft, set29rwe, wrdata[31:0], set29r, clk, rstn); // ------------------------------------------------------ // -- set30r Register // // Write set30r for 'SET30R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set30r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set30r_dfflrd (set30rdft, set30rwe, wrdata[31:0], set30r, clk, rstn); // ------------------------------------------------------ // -- set31r Register // // Write set31r for 'SET31R' : 32-bit register // Register is split into the following bit fields // // [31:0] --> set31r // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) set31r_dfflrd (set31rdft, set31rwe, wrdata[31:0], set31r, clk, rstn); // ------------------------------------------------------ // -- casaddrr Register // // Write casaddrr for 'CASADDRR' : 3-bit register // Register is split into the following bit fields // // [2:0] --> casaddrr // ------------------------------------------------------ sirv_gnrl_dfflrd #(3) casaddrr_dfflrd (casaddrrdft, casaddrrwe, wrdata[2:0], casaddrr, clk, rstn); // ------------------------------------------------------ // -- casdwr Register // // Write casdwr for 'CASDWR' : 3-bit register // Register is split into the following bit fields // // [2:0] --> casdwr // ------------------------------------------------------ sirv_gnrl_dfflrd #(3) casdwr_dfflrd (casdwrdft, casdwrwe, wrdata[2:0], casdwr, clk, rstn); // ------------------------------------------------------ // -- imctr Register // // Write imctr for 'IMCTR' : 10-bit register // Register is split into the following bit fields // // [9:0] --> imctr // ------------------------------------------------------ sirv_gnrl_dfflrd #(10) imctr_dfflrd (imctrdft, imctrwe, wrdata[9:0], imctr, clk, rstn); // ------------------------------------------------------ // -- ibleedctr Register // // Write ibleedctr for 'IBLEEDCTR' : 4-bit register // Register is split into the following bit fields // // [3:0] --> ibleedctr // ------------------------------------------------------ sirv_gnrl_dfflrd #(4) ibleedctr_dfflrd (ibleedctrdft, ibleedctrwe, wrdata[3:0], ibleedctr, clk, rstn); // ------------------------------------------------------ // -- iclkcmlr Register // // Write iclkcmlr for 'ICLKCMLR' : 4-bit register // Register is split into the following bit fields // // [3:0] --> iclkcmlr // ------------------------------------------------------ sirv_gnrl_dfflrd #(4) iclkcmlr_dfflrd (iclkcmlrdft, iclkcmlrwe, wrdata[3:0], iclkcmlr, clk, rstn); // ------------------------------------------------------ // -- currsvr0 Register // // Write currsvr0 for 'CURRSVR0' : 32-bit register // Register is split into the following bit fields // // [31:0] --> currsvr0 // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) currsvr0_dfflrd (currsvr0dft, currsvr0we, wrdata[31:0], currsvr0, clk, rstn); // ------------------------------------------------------ // -- currsvr1 Register // // Write currsvr1 for 'CURRSVR1' : 32-bit register // Register is split into the following bit fields // // [31:0] --> currsvr1 // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) currsvr1_dfflrd (currsvr1dft, currsvr1we, wrdata[31:0], currsvr1, clk, rstn); // ------------------------------------------------------ // -- Read data mux // // -- The data from the selected register is // -- placed on a zero-padded 32-bit read data bus. // ------------------------------------------------------ always @(*) begin : RDDATA_PROC rddata_reg = {32{1'b0}}; if(rtermren == H ) rddata_reg[3 :0] = rtermr[3 :0] ; if(prbsren == H ) rddata_reg[0 :0] = prbsr[0 :0] ; if(set0ren == H ) rddata_reg[31:0] = set0r[31:0] ; if(set1ren == H ) rddata_reg[31:0] = set1r[31:0] ; if(set2ren == H ) rddata_reg[31:0] = set2r[31:0] ; if(set3ren == H ) rddata_reg[31:0] = set3r[31:0] ; if(set4ren == H ) rddata_reg[31:0] = set4r[31:0] ; if(set5ren == H ) rddata_reg[31:0] = set5r[31:0] ; if(set6ren == H ) rddata_reg[31:0] = set6r[31:0] ; if(set7ren == H ) rddata_reg[31:0] = set7r[31:0] ; if(set8ren == H ) rddata_reg[31:0] = set8r[31:0] ; if(set9ren == H ) rddata_reg[31:0] = set9r[31:0] ; if(set10ren == H ) rddata_reg[31:0] = set10r[31:0] ; if(set11ren == H ) rddata_reg[31:0] = set11r[31:0] ; if(set12ren == H ) rddata_reg[31:0] = set12r[31:0] ; if(set13ren == H ) rddata_reg[31:0] = set13r[31:0] ; if(set14ren == H ) rddata_reg[31:0] = set14r[31:0] ; if(set15ren == H ) rddata_reg[31:0] = set15r[31:0] ; if(set16ren == H ) rddata_reg[31:0] = set16r[31:0] ; if(set17ren == H ) rddata_reg[31:0] = set17r[31:0] ; if(set18ren == H ) rddata_reg[31:0] = set18r[31:0] ; if(set19ren == H ) rddata_reg[31:0] = set19r[31:0] ; if(set20ren == H ) rddata_reg[31:0] = set20r[31:0] ; if(set21ren == H ) rddata_reg[31:0] = set21r[31:0] ; if(set22ren == H ) rddata_reg[31:0] = set22r[31:0] ; if(set23ren == H ) rddata_reg[31:0] = set23r[31:0] ; if(set24ren == H ) rddata_reg[31:0] = set24r[31:0] ; if(set25ren == H ) rddata_reg[31:0] = set25r[31:0] ; if(set26ren == H ) rddata_reg[31:0] = set26r[31:0] ; if(set27ren == H ) rddata_reg[31:0] = set27r[31:0] ; if(set28ren == H ) rddata_reg[31:0] = set28r[31:0] ; if(set29ren == H ) rddata_reg[31:0] = set29r[31:0] ; if(set30ren == H ) rddata_reg[31:0] = set30r[31:0] ; if(set31ren == H ) rddata_reg[31:0] = set31r[31:0] ; if(casaddrren == H ) rddata_reg[2 :0] = casaddrr[2 :0] ; if(casdwren == H ) rddata_reg[2 :0] = casdwr[2 :0] ; if(imctren == H ) rddata_reg[9 :0] = imctr[9 :0] ; if(ibleedctren == H ) rddata_reg[3 :0] = ibleedctr[3 :0] ; if(iclkcmlren == H ) rddata_reg[3 :0] = iclkcmlr[3 :0] ; if(currsvr0en == H ) rddata_reg[31:0] = currsvr0[31:0] ; if(currsvr1en == H ) rddata_reg[31:0] = currsvr1[31:0] ; if(verren == H ) rddata_reg[31:0] = DACVERSION ; end //rddata sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rstn); // ------------------------------------------------------ // -- Output signals assignment // ------------------------------------------------------ assign Rterm = rtermr ; // R_Terminate assign PrbsEn = prbsr ; // Prbs_en assign Set[0] = set0r[14: 0] ; assign Set[1] = set0r[30:16] ; assign Set[2] = set1r[14: 0] ; assign Set[3] = set1r[30:16] ; assign Set[4] = set2r[14: 0] ; assign Set[5] = set2r[30:16] ; assign Set[6] = set3r[14: 0] ; assign Set[7] = set3r[30:16] ; assign Set[8] = set4r[14: 0] ; assign Set[9] = set4r[30:16] ; assign Set[10] = set5r[14: 0] ; assign Set[11] = set5r[30:16] ; assign Set[12] = set6r[14: 0] ; assign Set[13] = set6r[30:16] ; assign Set[14] = set7r[14: 0] ; assign Set[15] = set7r[30:16] ; assign Set[16] = set8r[14: 0] ; assign Set[17] = set8r[30:16] ; assign Set[18] = set9r[14: 0] ; assign Set[19] = set9r[30:16] ; assign Set[20] = set10r[14: 0] ; assign Set[21] = set10r[30:16] ; assign Set[22] = set11r[14: 0] ; assign Set[23] = set11r[30:16] ; assign Set[24] = set12r[14: 0] ; assign Set[25] = set12r[30:16] ; assign Set[26] = set13r[14: 0] ; assign Set[27] = set13r[30:16] ; assign Set[28] = set14r[14: 0] ; assign Set[29] = set14r[30:16] ; assign Set[30] = set15r[14: 0] ; assign Set[31] = set15r[30:16] ; assign Set[32] = set16r[14: 0] ; assign Set[33] = set16r[30:16] ; assign Set[34] = set17r[14: 0] ; assign Set[35] = set17r[30:16] ; assign Set[36] = set18r[14: 0] ; assign Set[37] = set18r[30:16] ; assign Set[38] = set19r[14: 0] ; assign Set[39] = set19r[30:16] ; assign Set[40] = set20r[14: 0] ; assign Set[41] = set20r[30:16] ; assign Set[42] = set21r[14: 0] ; assign Set[43] = set21r[30:16] ; assign Set[44] = set22r[14: 0] ; assign Set[45] = set22r[30:16] ; assign Set[46] = set23r[14: 0] ; assign Set[47] = set23r[30:16] ; assign Set[48] = set24r[14: 0] ; assign Set[49] = set24r[30:16] ; assign Set[50] = set25r[14: 0] ; assign Set[51] = set25r[30:16] ; assign Set[52] = set26r[14: 0] ; assign Set[53] = set26r[30:16] ; assign Set[54] = set27r[14: 0] ; assign Set[55] = set27r[30:16] ; assign Set[56] = set28r[14: 0] ; assign Set[57] = set28r[30:16] ; assign Set[58] = set29r[14: 0] ; assign Set[59] = set29r[30:16] ; assign Set[60] = set30r[14: 0] ; assign Set[61] = set30r[30:16] ; assign Set[62] = set31r[14: 0] ; assign Set[63] = set31r[30:16] ; assign CasAddr = casaddrr ; assign CasDw = casdwr ; assign IMainCtrl = imctr ; assign IBleedCtrl = ibleedctr ; assign ICkCml = iclkcmlr ; assign CurRsv0 = currsvr0 ; assign CurRsv1 = currsvr1 ; endmodule `undef RTERMR `undef PRBSENR `undef SET0R `undef SET1R `undef SET2R `undef SET3R `undef SET4R `undef SET5R `undef SET6R `undef SET7R `undef SET8R `undef SET9R `undef SET10R `undef SET11R `undef SET12R `undef SET13R `undef SET14R `undef SET15R `undef SET16R `undef SET17R `undef SET18R `undef SET19R `undef SET20R `undef SET21R `undef SET22R `undef SET23R `undef SET24R `undef SET25R `undef SET26R `undef SET27R `undef SET28R `undef SET29R `undef SET30R `undef SET31R `undef CASADDRR `undef CASDWR `undef IMCTR `undef IBLEEDCTR `undef ICLKCMLR `undef CURRSVR0 `undef CURRSVR1 `undef VERSIONR