/* HIDE <!----------------------------------------------------------------------------->
[comment]: <> (Verilog template v0.03)

## Project Information
|          >          |    Project Name    |          >          |      File Name      |
|         :-:         |        :-:         |         :-:         |         :-:         |
|          >          |        TODO        |          >          |        TODO         |
|    **Engineer**     |  **Institution**   |  **Target Devices** |  **Tool Versions**  |
|    Guo Cheng[^1]    |        USTC        |   XC6VLX240TFF1156  |   Xilinx ISE 13.3   |
|  **Dependencies**   |         >          |          >          |        TODO         |
|  **Descriptions**   |         >          |          >          |        TODO         |
[^1]: Author E-mail: <fortune@mail.ustc.edu.cn>

## Reversion Information
|          Revision          |            Time            |          Comments          |
|            :-:             |            :-:             |            :-:             |
|         ==v0.01==          |  2019-08-08T02:51:47.205Z  |        File Create         |

## Code Segments
<!----------------------------------------------------------------------------------> */

/* HIDE```verilog{.line-numbers}*/
`timescale 1ns / 1ps

module reset_tb #(
    parameter DELAY = 0,
    parameter POLAR = 0,
    parameter WIDTH = 4
    )(
    output reset_out
    );
    reg reset;

    initial begin
        reset = !POLAR;
        #DELAY reset = POLAR;
        #WIDTH reset = !POLAR;
    end
    assign reset_out = reset;
endmodule
/* HIDE```*/