## ------------------------------------------------------------------------------------------
##                                                                                           
## Copyright (c) 2018 ChipMotion, Inc.                                                       
## All rights reserved.                                                                      
##                                                                                           
## ------------------------------------------------------------------------------------------
## Filename           :  run_dc.tcl
## Department         :                                                                      
## Author             :                                                                      
## Keywords           :                                                                      
## Description        :                                                                      
##                                                                                           
## RELEASE HISTORY                                                                           
## VERSION    DATE        AUTHOR        DESCRIPTION
## v0_01      20200317    wenyi.Peng   Initialized for QKD-SoC project
##                                                                                           
## ------------------------------------------------------------------------------------------

set hostname [sh hostname]
set starttime [clock seconds]

echo "INFORM: Job excuted on $hostname"
echo "INFORM: Start job at: " [clock format $starttime -gmt false]


#################################################################################################
##
##  Pre Setup
##
#################################################################################################
#set_app_var hdlin_enable_hier_map "true"; #enable hier info in svf

set svars(top_design)   "xyz_chip_top"
set svars(upf)          "false"
set svars(scan)         "false"

source       $svars(dir,scripts)/setup.utility.tcl
source -e -v $svars(dir,scripts)/setup.dir.tcl
source -e -v $svars(dir,scripts)/setup.dc.tcl
source -e -v $svars(dir,scripts)/setup.lib.tcl



define_design_lib work -path $svars(rtl,path,work)

#################################################################################################
##
##  Create MW Library for DCT/DCG FLOW
##
#################################################################################################
if {[shell_is_in_topographical_mode]} {
   source -e -v $svars(dir,scripts)/dct_config.tcl
   source -e -v $svars(dir,scripts)/setup.physical.tcl
}

################################################################################################
##
##  Read and Elaborate Design
##
#################################################################################################

source -e -v $svars(dir,scripts)/read_filelist.tcl

echo $rtl_files

#20190916: follow dc_ref settings
set_app_var dc_allow_rtl_pg true


analyze -lib work -format sverilog $rtl_files

elaborate      $svars(top_design)


current_design $svars(top_design)

#set svf
#set_verification_top
set_svf $svars(dir,outputs)/$svars(top_design).syn.svf

if {$svars(upf) == "true"} {
    # Load UPF
    load_upf $svars(dir,inputs)/powerspec/design.upf  > $svars(dir,logs)/load_upf.log
    source -e -v $svars(dir,scripts)/power_constraints.tcl
}


current_design $svars(top_design)

link


check_design                 > $svars(dir,reports)/pre_check_design.rpt

check_mv_design -verbose     > $svars(dir,reports)/pre_check_mv_design.rpt

write -f ddc     -hier -output $svars(dir,outputs)/$svars(top_design).elab.ddc
write -f verilog -hier -output $svars(dir,outputs)/$svars(top_design).elab.v

#################################################################################################
##
##  Optimization Constraints
##
#################################################################################################

 source  -e -v $svars(dir,inputs)/design.sdc           > $svars(dir,logs)/read_syn_sdc.log
#source  -e -v $svars(dir,scripts)/mbist.tcl           > $svars(dir,logs)/read_sdc_mbist.log
 source  -e -v $svars(dir,scripts)/opt_setup.tcl       > $svars(dir,logs)/read_opt_setup.log
#source  -e -v $svars(dir,scripts)/group_path.tcl      > $svars(dir,logs)/read_group_path.log

#20190916: follow dc_ref settings
source -e -v $svars(dir,scripts)/setup.addition.tcl > $svars(dir,logs)/read_addition_setup.log

if {[shell_is_in_topographical_mode]} {
        extract_physical_constraints -exact -no_incremental -verbose > $svars(dir,logs)/read_def.log
} else {
      # set_wire_load_model -name Zero
      # set_wire_load_mode  top
      # set auto_wire_load_selection false
        set auto_wire_load_selection true
}

# Uniquify the design
#20190916: follow dc_ref settings
set uniquify_naming_style $svars(top_design)_%s_%d

#20190916: follow dc_ref settings
uniquify -force

propagate_constraints

#define_name_rules verilog -target_bus_naming_style {%s_%d} \
#                          -remove_port_bus

#20190916: follow dc_ref settings
#change_names -rules verilog -hierarchy -log_changes $svars(dir,logs)/change_names.log
source $svars(dir,scripts)/change_name.tcl
 
write     -f ddc     -hier -output $svars(dir,outputs)/$svars(top_design).change.ddc
write     -f verilog -hier -output $svars(dir,outputs)/$svars(top_design).change.v
write_sdc                          $svars(dir,outputs)/$svars(top_design).change.sdc
 
#################################################################################################
##
##  Compile Design: 1st compile_ultra 
##
#################################################################################################
puts ""
puts "--------------------------------------"
puts "            Initial Compile           "
puts "**************************************"
puts ""
if {[shell_is_in_topographical_mode]} {
        compile_ultra -scan -no_autoungroup -spg -no_seq_output_inversion -gate_clock
} else {
        compile_ultra -no_autoungroup      -no_seq_output_inversion -gate_clock
#       compile_ultra -scan -no_autoungroup      -no_seq_output_inversion -gate_clock
#       compile_ultra -scan -no_autoungroup      -no_seq_output_inversion
        puts " **********************"
        puts " Saving debug database."
        puts ""
}



write     -f ddc     -hier -output $svars(dir,outputs)/$svars(top_design).cmpl.ddc
write     -f verilog -hier -output $svars(dir,outputs)/$svars(top_design).cmpl.v
write_sdc                          $svars(dir,outputs)/$svars(top_design).cmpl.sdc



report_constraint -all_violators                               > $svars(dir,reports)/debug.all_vios.summary.rpt
#report_constraint -all_violators -verbose                      > $svars(dir,reports)/debug.all_vios.rpt
check_design                                                   > $svars(dir,reports)/debug.check_design.rpt
check_mv_design -verbose                                                > $svars(dir,reports)/debug.check_mv_design.rpt

#
# 20190510, when check_timing, dc_shell(syn_vL-2016.03-SP5-7) has encountered a fatal error 
#

check_timing                                                   > $svars(dir,reports)/debug.check_timing.rpt
check_timing -multiple_clock                                   > $svars(dir,reports)/debug.check_timing.multiple_clock.rpt
report_qor                                                     > $svars(dir,reports)/debug.qor.rpt
report_clock                                                   > $svars(dir,reports)/debug.clock.rpt
report_clock_gating                                            > $svars(dir,reports)/debug.clock_gating.rpt
report_clock_tree -interclock_timing -summary                  > $svars(dir,reports)/debug.clock_tree.rpt
report_timing -nets -capacitance -transition_time -max_path 10 > $svars(dir,reports)/debug.timing.rpt
report_timing_requirements                                     > $svars(dir,reports)/debug.check_timing_requirements.rpt


if {$svars(upf) == "true"} {
    report_power_domain [get_power_domains * -hierarchical ]             > $svars(dir,reports)/debug.power.rpt
    report_isolation_cell -domain  [get_power_domains * -hierarchical ] >> $svars(dir,reports)/debug.power.rpt
    report_pst                                                          >> $svars(dir,reports)/debug.power.rpt
}

#################################################################################################
##
##  Optimization Design: 2nd compile_ultra
##
#################################################################################################
puts ""
puts "--------------------------------------------------"
puts "            Initial Incremental Compile           "
puts "**************************************************"
puts ""
if {[shell_is_in_topographical_mode]} {
        compile_ultra -scan -no_autoungroup -spg -incr -no_seq_output_inversion -gate_clock
        set_icc_dp_options -work_dir $work_dir -icc_executable $icc_execute_dir
} else {
#       compile_ultra -scan -no_autoungroup -incr -no_seq_output_inversion -gate_clock
        compile_ultra -no_autoungroup -incr -no_seq_output_inversion -gate_clock
#       compile_ultra -scan -no_autoungroup -incr -no_seq_output_inversion
}


report_constraint -all_violators                               > $svars(dir,reports)/debugIncr.all_vios.summary.rpt
#report_constraint -all_violators -verbose                      > $svars(dir,reports)/debugIncr.all_vios.rpt
check_design                                                   > $svars(dir,reports)/debugIncr.check_design.rpt
check_mv_design -verbose                                                > $svars(dir,reports)/debugIncr.check_mv_design.rpt
check_timing                                                   > $svars(dir,reports)/debugIncr.check_timing.rpt
check_timing -multiple_clock                                   > $svars(dir,reports)/debugIncr.check_timing.multiple_clock.rpt
report_qor                                                     > $svars(dir,reports)/debugIncr.qor.rpt
report_clock                                                   > $svars(dir,reports)/debugIncr.clock.rpt
report_clock_gating                                            > $svars(dir,reports)/debugIncr.clock_gating.rpt
report_clock_tree -interclock_timing -summary                  > $svars(dir,reports)/debugIncr.clock_tree.rpt
report_timing -nets -capacitance -transition_time -max_path 10 > $svars(dir,reports)/debugIncr.timing.rpt
report_timing_requirements                                     > $svars(dir,reports)/debugIncr.check_timing_requirements.rpt

if {$svars(upf) == "true"} {
    report_power_domain [get_power_domains * -hierarchical ]             > $svars(dir,reports)/debugIncr.power.rpt
    report_isolation_cell -domain  [get_power_domains * -hierarchical ] >> $svars(dir,reports)/debugIncr.power.rpt
    report_pst                                                          >> $svars(dir,reports)/debugIncr.power.rpt
}

write     -f ddc     -hier -output $svars(dir,outputs)/$svars(top_design).cmplIncr.ddc
write     -f verilog -hier -output $svars(dir,outputs)/$svars(top_design).cmplIncr.v
write_sdc                          $svars(dir,outputs)/$svars(top_design).cmplIncr.sdc
save_upf                           $svars(dir,outputs)/$svars(top_design).cmplIncr.upf

#################################################################################################
##
##  Optimization Design: 3nd compile_ultra
##
#################################################################################################
puts ""
puts "--------------------------------------------------"
puts "            Initial 2th Incremental Compile           "
puts "**************************************************"
puts ""
if {[shell_is_in_topographical_mode]} {
        compile_ultra -scan -no_autoungroup -spg -incr -no_seq_output_inversion -gate_clock
        set_icc_dp_options -work_dir $work_dir -icc_executable $icc_execute_dir
} else {
#       compile_ultra -scan -no_autoungroup -incr -no_seq_output_inversion -gate_clock
        compile_ultra -no_autoungroup -incr -no_seq_output_inversion -gate_clock
#       compile_ultra -scan -no_autoungroup -incr -no_seq_output_inversion
}


report_constraint -all_violators                               > $svars(dir,reports)/debugIncr2.all_vios.summary.rpt
#report_constraint -all_violators -verbose                      > $svars(dir,reports)/debugIncr2.all_vios.rpt
check_design                                                   > $svars(dir,reports)/debugIncr2.check_design.rpt
check_mv_design -verbose                                                > $svars(dir,reports)/debugIncr2.check_mv_design.rpt
check_timing                                                   > $svars(dir,reports)/debugIncr2.check_timing.rpt
check_timing -multiple_clock                                   > $svars(dir,reports)/debugIncr2.check_timing.multiple_clock.rpt
report_qor                                                     > $svars(dir,reports)/debugIncr2.qor.rpt
report_clock                                                   > $svars(dir,reports)/debugIncr2.clock.rpt
report_clock_gating                                            > $svars(dir,reports)/debugIncr2.clock_gating.rpt
report_clock_tree -interclock_timing -summary                  > $svars(dir,reports)/debugIncr2.clock_tree.rpt
report_timing -nets -capacitance -transition_time -max_path 10 > $svars(dir,reports)/debugIncr2.timing.rpt
report_timing_requirements                                     > $svars(dir,reports)/debugIncr2.check_timing_requirements.rpt

if {$svars(upf) == "true"} {
    report_power_domain [get_power_domains * -hierarchical ]             > $svars(dir,reports)/debugIncr2.power.rpt
    report_isolation_cell -domain  [get_power_domains * -hierarchical ] >> $svars(dir,reports)/debugIncr2.power.rpt
    report_pst                                                          >> $svars(dir,reports)/debugIncr2.power.rpt
}

write     -f ddc     -hier -output $svars(dir,outputs)/$svars(top_design).cmplIncr2.ddc
write     -f verilog -hier -output $svars(dir,outputs)/$svars(top_design).cmplIncr2.v
write_sdc                          $svars(dir,outputs)/$svars(top_design).cmplIncr2.sdc
save_upf                           $svars(dir,outputs)/$svars(top_design).cmplIncr2.upf

#################################################################################################
##
##  DFT
##
#################################################################################################
#if {$svars(scan) == "true"} {
#       source -e -v $svars(dir,scripts)/setup.dft.tcl
#       source -e -v $svars(dir,scripts)/insert_dft.tcl
#} else {
#       set uniquify_naming_style $svars(top_design)_%s_%d
#       uniquify -force
#       change_names -rules verilog -hierarchy -log_changes $svars(dir,logs)/change_names_syn.log
#
#}



#################################################################################################
##
##  Export Design Data, Generate Final Reports
##
#################################################################################################

report_constraint -all_violators                               > $svars(dir,reports)/syn_final.all_vios.summary.rpt
#report_constraint -all_violators -verbose                      > $svars(dir,reports)/syn_final.all_vios.rpt
check_design                                                   > $svars(dir,reports)/syn_final.check_design.rpt
check_mv_design -verbose                                                > $svars(dir,reports)/syn_final.check_mv_design.rpt
check_timing                                                   > $svars(dir,reports)/syn_final.check_timing.rpt
check_timing -multiple_clock                                   > $svars(dir,reports)/syn_final.check_timing.multiple_clock.rpt
report_qor                                                     > $svars(dir,reports)/syn_final.qor.rpt
report_clock                                                   > $svars(dir,reports)/syn_final.clock.rpt
report_clock_gating                                            > $svars(dir,reports)/syn_final.clock_gating.rpt
report_clock_tree -interclock_timing -summary                  > $svars(dir,reports)/syn_final.clock_tree.rpt
report_timing -nets -capacitance -transition_time -max_path 10 > $svars(dir,reports)/syn_final.timing.rpt
report_timing_requirements                                     > $svars(dir,reports)/syn_final.check_timing_requirements.rpt
report_size_only  -nosplit                                     > $svars(dir,reports)/syn_final.syn_size_only.rpt
report_power                                                   > $svars(dir,reports)/syn_final.power.rpt

if {$svars(upf) == "true"} {
    report_power_domain [get_power_domains * -hierarchical ]             > $svars(dir,reports)/syn_final.power.rpt
    report_isolation_cell -domain  [get_power_domains * -hierarchical ] >> $svars(dir,reports)/syn_final.power.rpt
    report_pst                                                          >> $svars(dir,reports)/syn_final.power.rpt
}

source $svars(dir,scripts)/change_name.tcl

write     -f ddc     -hier -output $svars(dir,outputs)/$svars(top_design).syn.ddc
write     -f verilog -hier -output $svars(dir,outputs)/$svars(top_design).syn.v
write_sdc                          $svars(dir,outputs)/$svars(top_design).syn.sdc
save_upf                           $svars(dir,outputs)/$svars(top_design).syn.upf

 
set_svf -off



#################################################################################################
##
## Summary
##
#################################################################################################
set endtime   [clock seconds]
echo "INFORM: End job at: " [clock format $endtime -gmt false]

set hostname [sh hostname]
set pwd [pwd]
set runtime "[format %02d [expr ($endtime - $starttime)/3600]]:[format %02d [expr (($endtime - $starttime)%3600)/60]]:[format %02d [expr ((($endtime - $starttime))%3600)%60]]"

echo [format "%-15s %-2s %-70s" "" "" ""]
echo " ------------------------------------------------------------------------------------------"
echo [format "%-15s %-2s %-70s" " | Host" "|" "$hostname"]
echo [format "%-15s %-2s %-70s" " | Working Dir" "|" "$pwd"]
echo [format "%-15s %-2s %-70s" " | runtime" "|" "$runtime"]
alias rf report_timing -from
alias rt report_timing -to

#exit