#### clock gating setup
#### 2014-10-03
#### Original: PREICG_X9B_A9TL40
#### NEW:      PREICG_X9B_A9TR40

set_clock_gating_style -sequential_cell latch \
                       -positive_edge_logic integrated:CKLNQD20BWP7T35P140 \
                       -control_point before \
                       -control_signal scan_enable \
                       -max_fanout 16 \
                       -minimum_bitwidth 4 \
                       -num_stages 4

# 12 track : PREICG_X0P5B_A12TR50
# 9  track : PREICG_X0P5B_A9TR50

set power_cg_module_naming_style "CG_%e_%t"
set power_cg_auto_identify true
set power_cg_print_enable_conditions true
set timing_separate_clock_gating_group true

set clks [all_clocks]
foreach_in_collection clk $clks {
        set clk_name [get_object_name $clk]
        set regs [all_registers -edge_triggered -fall_clock $clk_name]
        foreach_in_collection reg $regs {
        set reg_name [get_object_name $reg]
        set ref_name [get_attribute $reg_name ref_name]
        set_clock_gating_registers -exclude_instances $reg_name
        echo "disable clock-gating of negedge register : ${reg_name}"
        echo $reg_name >> $svars(dir,logs)/disable_clk_gate_negedge_reg.list
        }
}

set_fix_multiple_port_nets -all -buffer_constants
set_critical_range 0.1 [get_designs $svars(top_design)]

set_register_merging $svars(top_design) true
set_cost_priority -delay

######################################################
### drc rule
set_max_transition  0.6   [get_designs $svars(top_design)]
set_max_capacitance 0.1   [get_designs $svars(top_design)]
set_max_fanout      32    [get_designs $svars(top_design)]
######################################################
### area optimazition
set_max_area 0
######################################################
### remove wand 
#foreach_in_collection this_design [ all_designs ] \
#   {
#    current_design $this_design
#    remove_wand_attr
#   }
#
#set enable_recovery_removal_arcs false
######################################################
### Define operating_conditions
#set_operating_conditions ss_typical_max_0p99v_m40c -lib	sc9mc_cln40lp_base_rvt_c40_ss_typical_max_0p99v_m40c
######################################################
### Physical options
if {[shell_is_in_topographical_mode]} {
   set_utilization 0.6
   set placer_max_cell_density_threshold 0.80
   set_ignored_layers
   set_delay_estimation_options
   set_ahfs_options -enable_port_punching false
   set psynopt_tns_high_effort true
   set glo_more_opto true
   set placer_disable_auto_bound_for_gated_clock false
   set phyopt_pccts_dont_touch_support true
   set placer_use_path_group_weight true
   set phyopt_enable_via_res_support true
   set placer_enable_advance_resistance_model true
}