set trep_persistence TRUE
set test_enable_dft_drc TRUE
set test_disable_enhanced_dft_drc_reporting false
set test_setup_additional_clock_pulse true

set hdlin_infer_mux all
##########################################################################################################################
set rm_num_scan_chains    
set rm_use_scan_comp   	  
set rm_max_length         
set rm_comp_enable        
set rm_clock_ports    	  [list ]
set rm_dft_const          [list ]
set rm_reset_ports    	  [list ] 
set rm_scan_enable        [list ]
set rm_scan_data_in       
set rm_scan_data_out      
##########################################################################################################################
set_scan_configuration -add_lockup true \
		       -power_domain_mixing true \
                       -reuse_mv_cells true \
                       -style multiplexed_flip_flop \
                       -clock_mixing mix_clocks \
                       -chain_count $rm_num_scan_chains \
		       -internal_clocks multi \
		       -test_mode all

set_dft_configuration -scan_compression enable \
 		      -connect_clock_gating enable

set_dft_drc_configuration -clock_gating_init_cycles 1 \
			  -static_x_analysis enable
 
set_dft_insertion_configuration -preserve_design_name true \
 				-synthesis_optimization none

set_scan_compression_configuration -min_power true \
                                   -static_x_chain_isolation true \
                                   -xtolerance high \
                                   -max_length $rm_max_length


source -e -v $svars(dir,scripts)/read_ctl.tcl
##########################################################################################################################
set_dft_signal -view existing_dft -type ScanClock -timing {45 55} -port $rm_clock_ports -test_mode all_dft

set_dft_signal -type ScanEnable -port $rm_scan_enable  -view spec -active_state 1 -test_mode all_dft
set_dft_signal -type ScanEnable -port $rm_scan_enable  -view existing_dft -active_state 1 -test_mode all_dft

set_dft_signal -view existing_dft -port [get_ports ${rm_reset_ports}] -type Reset -active_state 0 -test_mode all_dft

set_dft_signal -view existing_dft -type Constant -active_state 1 -port {te} -test_mode all_dft
set_dft_signal -view existing_dft -type Constant -active_state 0 -port {bist_en} -test_mode all_dft
set_dft_signal -view existing_dft -type Constant -active_state 0 -port {zsp_iso_en} -test_mode all_dft

if { ${rm_use_scan_comp} } {
  set_dft_signal -view spec -type TestMode -active_state 1 -port ${rm_comp_enable}
}

for { set i 0 } {$i < ${rm_num_scan_chains} } {incr i} {
    set_dft_signal -view spec -port ${rm_scan_data_in}[$i] -type ScanDataIn -test_mode all_dft
    set_dft_signal -view spec -port ${rm_scan_data_out}[$i] -type ScanDataOut -test_mode all_dft
}

set_scan_path  -view spec -scan_data_in  -scan_data_out 
# -----------------------------------------------------------------------------------
# Perform DFT DRC
# -----------------------------------------------------------------------------------
create_test_protocol -capture_procedure multi_clock 

dft_drc -verbose -pre_dft > $svars(dir,reports)/$svars(top_design)_prescan.dft
dft_drc -pre_dft > $svars(dir,reports)/$svars(top_design)_prescan.dft.summary

source -e -v /DDB04/Project/lc1812/User/lc1812_brite/Analyze/dft/tyrekes/scan/zsp/dft_vio.fix.tcl
# -----------------------------------------------------------------------------------
# Insert Scan structures
# -----------------------------------------------------------------------------------
create_test_protocol -capture_procedure multi_clock
dft_drc -pre_dft > $svars(dir,reports)/$svars(top_design)_prescan.dft.summary
preview_dft -show all > $svars(dir,reports)/$svars(top_design)_prescan_preview.dft

# -----------------------------------------------------------------------------------
# Do not run incremental compile as a part of insert_dft
# -----------------------------------------------------------------------------------
report_dft_insertion_configuration
insert_dft

check_mv_design > $svars(dir,reports)/$svars(top_design)_mv_check_dft.reports

change_names -rules verilog -hier

current_test_mode Internal_scan

dft_drc > $svars(dir,reports)/$svars(top_design)_InternalScan.dft

report_dft_drc_violations

report_scan_path -view existing_dft -chain all > $svars(dir,reports)/$svars(top_design).scanpath_chain.internal
report_scan_path -view existing_dft -cell all  > $svars(dir,reports)/$svars(top_design).scanpath_cell.internal

write_test_protocol -test_mode Internal_scan        -out $svars(dir,outputs)/$svars(top_design)-InternalScan.spf
write_test_protocol -test_mode ScanCompression_mode -out $svars(dir,outputs)/$svars(top_design)-ScanCompression.spf

current_test_mode ScanCompression_mode

report_scan_path -view existing_dft -chain all > $svars(dir,reports)/$svars(top_design).scanpath_chain.scancomp
report_scan_path -view existing_dft -cell all  > $svars(dir,reports)/$svars(top_design).scanpath_cell.scancomp

# Write out SCAN DEF file
write_scan_def -output $svars(dir,outputs)/$svars(top_design).scandef
check_scan_def -file   $svars(dir,outputs)/$svars(top_design).scandef

# Write out test model
write_test_model -format ctl -output $svars(dir,outputs)/$svars(top_design).ctl
write_test_model -format ddc -output $svars(dir,outputs)/$svars(top_design).ctlddc