module NCO # ( parameter WIDTH = 16 ,parameter PARALLEL = 16 )( input clk ,input rstn ,input phase_manual_clr ,input phase_auto_clr ,input [47 :0] fcw ,input [15 :0] pha ,input nco_en ,input p2a_en ,output [WIDTH-1:0] cos [PARALLEL-1:0] ,output [WIDTH-1:0] sin [PARALLEL-1:0] ); reg [47:0] fcw_r1 [PARALLEL-1:0]; wire [47:0] fcw2_w; wire [47:0] fcw4_w; wire [47:0] fcw8_w; wire [47:0] fcw16_w; wire [47:0] fcw32_w; wire [47:0] fcw64_w; reg [15:0] pha_r; assign fcw2_w =fcw<<3'd1; assign fcw4_w =fcw<<3'd2; assign fcw8_w =fcw<<3'd3; assign fcw16_w=fcw<<3'd4; assign fcw32_w=fcw<<3'd5; assign fcw64_w=fcw<<3'd6; always@(posedge clk or negedge rstn) if(!rstn) begin fcw_r1[ 1] <=48'd0; fcw_r1[ 2] <=48'd0; fcw_r1[ 3] <=48'd0; fcw_r1[ 4] <=48'd0; fcw_r1[ 5] <=48'd0; fcw_r1[ 6] <=48'd0; fcw_r1[ 7] <=48'd0; fcw_r1[ 8] <=48'd0; fcw_r1[ 9] <=48'd0; fcw_r1[10] <=48'd0; fcw_r1[11] <=48'd0; fcw_r1[12] <=48'd0; fcw_r1[13] <=48'd0; fcw_r1[14] <=48'd0; fcw_r1[15] <=48'd0; fcw_r1[16] <=48'd0; fcw_r1[17] <=48'd0; fcw_r1[18] <=48'd0; fcw_r1[19] <=48'd0; fcw_r1[20] <=48'd0; fcw_r1[21] <=48'd0; fcw_r1[22] <=48'd0; fcw_r1[23] <=48'd0; fcw_r1[24] <=48'd0; fcw_r1[25] <=48'd0; fcw_r1[26] <=48'd0; fcw_r1[27] <=48'd0; fcw_r1[28] <=48'd0; fcw_r1[29] <=48'd0; fcw_r1[30] <=48'd0; fcw_r1[31] <=48'd0; fcw_r1[32] <=48'd0; fcw_r1[33] <=48'd0; fcw_r1[34] <=48'd0; fcw_r1[35] <=48'd0; fcw_r1[36] <=48'd0; fcw_r1[37] <=48'd0; fcw_r1[38] <=48'd0; fcw_r1[39] <=48'd0; fcw_r1[40] <=48'd0; fcw_r1[41] <=48'd0; fcw_r1[42] <=48'd0; fcw_r1[43] <=48'd0; fcw_r1[44] <=48'd0; fcw_r1[45] <=48'd0; fcw_r1[46] <=48'd0; fcw_r1[47] <=48'd0; fcw_r1[48] <=48'd0; fcw_r1[49] <=48'd0; fcw_r1[50] <=48'd0; fcw_r1[51] <=48'd0; fcw_r1[52] <=48'd0; fcw_r1[53] <=48'd0; fcw_r1[54] <=48'd0; fcw_r1[55] <=48'd0; fcw_r1[56] <=48'd0; fcw_r1[57] <=48'd0; fcw_r1[58] <=48'd0; fcw_r1[59] <=48'd0; fcw_r1[60] <=48'd0; fcw_r1[61] <=48'd0; fcw_r1[62] <=48'd0; fcw_r1[63] <=48'd0; fcw_r1[0 ] <=48'd0; end else if(nco_en == 1'b0) begin fcw_r1[ 1] <=48'd0; fcw_r1[ 2] <=48'd0; fcw_r1[ 3] <=48'd0; fcw_r1[ 4] <=48'd0; fcw_r1[ 5] <=48'd0; fcw_r1[ 6] <=48'd0; fcw_r1[ 7] <=48'd0; fcw_r1[ 8] <=48'd0; fcw_r1[ 9] <=48'd0; fcw_r1[10] <=48'd0; fcw_r1[11] <=48'd0; fcw_r1[12] <=48'd0; fcw_r1[13] <=48'd0; fcw_r1[14] <=48'd0; fcw_r1[15] <=48'd0; fcw_r1[16] <=48'd0; fcw_r1[17] <=48'd0; fcw_r1[18] <=48'd0; fcw_r1[19] <=48'd0; fcw_r1[20] <=48'd0; fcw_r1[21] <=48'd0; fcw_r1[22] <=48'd0; fcw_r1[23] <=48'd0; fcw_r1[24] <=48'd0; fcw_r1[25] <=48'd0; fcw_r1[26] <=48'd0; fcw_r1[27] <=48'd0; fcw_r1[28] <=48'd0; fcw_r1[29] <=48'd0; fcw_r1[30] <=48'd0; fcw_r1[31] <=48'd0; fcw_r1[32] <=48'd0; fcw_r1[33] <=48'd0; fcw_r1[34] <=48'd0; fcw_r1[35] <=48'd0; fcw_r1[36] <=48'd0; fcw_r1[37] <=48'd0; fcw_r1[38] <=48'd0; fcw_r1[39] <=48'd0; fcw_r1[40] <=48'd0; fcw_r1[41] <=48'd0; fcw_r1[42] <=48'd0; fcw_r1[43] <=48'd0; fcw_r1[44] <=48'd0; fcw_r1[45] <=48'd0; fcw_r1[46] <=48'd0; fcw_r1[47] <=48'd0; fcw_r1[48] <=48'd0; fcw_r1[49] <=48'd0; fcw_r1[50] <=48'd0; fcw_r1[51] <=48'd0; fcw_r1[52] <=48'd0; fcw_r1[53] <=48'd0; fcw_r1[54] <=48'd0; fcw_r1[55] <=48'd0; fcw_r1[56] <=48'd0; fcw_r1[57] <=48'd0; fcw_r1[58] <=48'd0; fcw_r1[59] <=48'd0; fcw_r1[60] <=48'd0; fcw_r1[61] <=48'd0; fcw_r1[62] <=48'd0; fcw_r1[63] <=48'd0; fcw_r1[0 ] <=48'd0; end else begin fcw_r1[ 1] <=fcw; fcw_r1[ 2] <=fcw2_w; fcw_r1[ 3] <=fcw2_w + fcw; fcw_r1[ 4] <=fcw4_w; fcw_r1[ 5] <=fcw4_w + fcw; fcw_r1[ 6] <=fcw4_w + fcw2_w; fcw_r1[ 7] <=fcw8_w - fcw; fcw_r1[ 8] <=fcw8_w; fcw_r1[ 9] <=fcw8_w + fcw; fcw_r1[10] <=fcw8_w + fcw2_w; fcw_r1[11] <=fcw8_w + fcw2_w + fcw; fcw_r1[12] <=fcw8_w + fcw4_w; fcw_r1[13] <=fcw8_w + fcw4_w + fcw; fcw_r1[14] <=fcw16_w - fcw2_w; fcw_r1[15] <=fcw16_w - fcw; fcw_r1[16] <=fcw16_w; fcw_r1[17] <=fcw16_w + fcw; fcw_r1[18] <=fcw16_w + fcw2_w; fcw_r1[19] <=fcw16_w + fcw2_w + fcw; fcw_r1[20] <=fcw16_w + fcw4_w; fcw_r1[21] <=fcw16_w + fcw4_w + fcw; fcw_r1[22] <=fcw16_w + fcw4_w + fcw2_w; fcw_r1[23] <=fcw16_w + fcw8_w - fcw; fcw_r1[24] <=fcw16_w + fcw8_w; fcw_r1[25] <=fcw32_w - fcw8_w + fcw; fcw_r1[26] <=fcw32_w - fcw4_w - fcw2_w; fcw_r1[27] <=fcw32_w - fcw4_w - fcw; fcw_r1[28] <=fcw32_w - fcw4_w; fcw_r1[29] <=fcw32_w - fcw2_w - fcw; fcw_r1[30] <=fcw32_w - fcw2_w; fcw_r1[31] <=fcw32_w - fcw; fcw_r1[32] <=fcw32_w; fcw_r1[33] <=fcw32_w + fcw; fcw_r1[34] <=fcw32_w + fcw2_w; fcw_r1[35] <=fcw32_w + fcw2_w + fcw; fcw_r1[36] <=fcw32_w + fcw4_w; fcw_r1[37] <=fcw32_w + fcw4_w + fcw; fcw_r1[38] <=fcw32_w + fcw4_w + fcw2_w; fcw_r1[39] <=fcw32_w + fcw8_w - fcw; fcw_r1[40] <=fcw32_w + fcw8_w; fcw_r1[41] <=fcw32_w + fcw8_w + fcw; fcw_r1[42] <=fcw32_w + fcw8_w + fcw2_w; fcw_r1[43] <=fcw32_w + fcw8_w + fcw2_w + fcw; fcw_r1[44] <=fcw32_w + fcw8_w + fcw4_w; fcw_r1[45] <=fcw32_w + fcw8_w + fcw4_w + fcw; fcw_r1[46] <=fcw32_w + fcw8_w + fcw4_w + fcw2_w; fcw_r1[47] <=fcw32_w + fcw16_w - fcw; fcw_r1[48] <=fcw32_w + fcw16_w; fcw_r1[49] <=fcw32_w + fcw16_w + fcw; fcw_r1[50] <=fcw32_w + fcw16_w + fcw2_w; fcw_r1[51] <=fcw32_w + fcw16_w + fcw2_w + fcw; fcw_r1[52] <=fcw32_w + fcw16_w + fcw4_w; fcw_r1[53] <=fcw32_w + fcw16_w + fcw4_w + fcw; fcw_r1[54] <=fcw32_w + fcw16_w + fcw4_w + fcw2_w; fcw_r1[55] <=fcw32_w + fcw16_w + fcw8_w - fcw; fcw_r1[56] <=fcw32_w + fcw16_w + fcw8_w; fcw_r1[57] <=fcw32_w + fcw16_w + fcw8_w + fcw; fcw_r1[58] <=fcw64_w - fcw4_w - fcw2_w; fcw_r1[59] <=fcw64_w - fcw4_w - fcw; fcw_r1[60] <=fcw64_w - fcw4_w; fcw_r1[61] <=fcw64_w - fcw4_w + fcw; fcw_r1[62] <=fcw64_w - fcw2_w; fcw_r1[63] <=fcw64_w - fcw; fcw_r1[0 ] <=fcw64_w; end always @(posedge clk or negedge rstn) begin if(!rstn) begin pha_r <= 16'd0; end else if(nco_en == 1'b0) begin pha_r <= 16'd0; end else begin pha_r <= pha; end end wire clr_acc; wire clr_fix; assign clr_acc = phase_auto_clr | phase_manual_clr; assign clr_fix = phase_manual_clr; wire [15:0] s1_i_o; wire [15:0] s2_i_o; wire [15:0] s3_i_o; P_NCO #(.WIDTH(WIDTH), .PARALLEL(PARALLEL)) inst_p_nco( .clk (clk ), .rstn (rstn ), .clr (1'b0 ), //(clr_fix ), .clr_acc (clr_acc ), .ptw (pha_r ), .p2a_en (p2a_en ), .s1 (s1_i_o ), .s2 (s2_i_o ), .s3 (s3_i_o ), .s1_o (s1_i_o ), .s2_o (s2_i_o ), .s3_o (s3_i_o ), .fcw (fcw_r1 ), .cos (cos ), .sin (sin ) ); endmodule