//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    modout_mux.v
//  Department            :    
//  Author                :    PWY
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.1         2024-05-13      PWY             debug top-level
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------

module dout_mux #(
  parameter PARALLEL = 64
)(
//system port
   input         clk                             // System Main Clock
  ,input         rst_n                           // Spi Reset active low
  //---------------from ctrl regfile------------------------------------
  ,input  [2 :0] sel                             //3'h0: mix; 3'h1:enve_i; 3'h2:drag_q 
                                                 //           3'h3: cos  ; 3'h4: sin
  //data0
  ,input  [7:0] data0       [PARALLEL-1 : 0]
  ,input        data0_vld
  //data1
  ,input  [7:0] data1       [PARALLEL-1 : 0]
  ,input        data1_vld
  //data2
  ,input  [7:0] data2       [PARALLEL-1 : 0]
  ,input        data2_vld
  //mux out data
  ,output [7:0] mux_data  [PARALLEL-1 : 0]
  ,output       mux_data_vld
);
							   
wire mux_data_vld_w = (sel == 3'd1) ? data0_vld:
                      (sel == 3'd2) ? data1_vld:
                      (sel == 3'd4) ? data2_vld:
                                      1'b0     ;							   

sirv_gnrl_dffr #(1) mux_data_vld_dffr (mux_data_vld_w, mux_data_vld, clk, rst_n);

wire [7 :0] mux_data_w  [PARALLEL-1 : 0];

genvar k;
generate
  for(k = 0; k < PARALLEL; k = k + 1) begin
    assign mux_data_w[k]    = (sel == 3'd1) ? data0[k]:
                              (sel == 3'd2) ? data1[k]:
                              (sel == 3'd4) ? data2[k]:
                                              32'd0   ;
    sirv_gnrl_dffr #(8) mux_data_dffr (mux_data_w[k], mux_data[k], clk, rst_n);
  end
endgenerate


endmodule