#################################################################################################################
#### Enviroments Setup
#################################################################################################################
#set_host_options -max_cores 8
set_host_options  -max_cores 4

#### user defined variable
set enable_page_mode false
set collection_result_display_limit -1

set timing_enable_multiple_clocks_per_reg true
set ungroup_keep_original_design true
set power_preserve_rtl_hier_names TRUE

set_app_var hdlin_vrlg_std 2005



# VER-61  : Statement unreachable (Branch condition impossible to meet),
# VER-61  : Statement unreachable (Prior branch conditions are always met).
# VER-130 : Intraassignment delays for nonblocking assignments are ignored.
# VER-318 : signed to unsigned assignment occurs.
# VER-921 : The macro 'REG_VID' you are attempting to undefine with the '`undef' directive is not defined.
# VER-936 : The undeclared symbol 'XXX' assumed to have the default net type, which is 'wire'.
# ELAB-311: DEFAULT branch of CASE statement cannot be reached.
# ELAB-985: Netlist for always block is empty.
# UCN-1   : net 'XXX' is connecting multiple ports.

#set_app_var suppress_errors {VER-61 VER-130 VER-318 ELAB-311 VER-936 ELAB-985 UCN-1}
 set_app_var suppress_errors {}


set hdlin_enable_rtldrc_info true
set hdlin_keep_signal_name   all
set hdlin_check_no_latch     true
set hdlin_shorten_long_module_name true
set hdlin_module_name_limit        64 

set verilogout_show_unconnected_pins true
set verilogout_no_tri true
set verilogout_higher_designs_first true
set verilogout_equation false

# for area opt
set compile_delete_unloaded_sequential_cells true
set compile_seqmap_propagate_constants true
set case_analysis_with_logic_constants false

set enable_recovery_removal_arcs false
set synlib_enable_dpgen true
set uniquify_keep_original_design false
set access_internal_pins true
set synlib_dwgen_fmlink_active true
set timing_use_enhanced_capacitance_modeling true

set synlib_abort_wo_dw_license true

set timing_check_defaults "clock_crossing \
                           data_check_multiple_clock \
                           data_check_no_clock \
                           generic \
                           loops \
                           multiple_clock \
                           no_input_delay \
                           partial_input_delay \
                           ideal_clocks \
                           no_driving_cell \
                           retain \
                           unconstrained_endpoints \
                           clock_no_period \
                           pulse_clock_cell_type \
                          "

set compile_seqmap_identify_shift_registers false
#### low power
set power_driven_clock_gating true
#set auto_insert_level_shifters true
#set auto_insert_level_shifters_on_clocks "true"
#set mv_insert_level_shifters_on_ideal_nets "true"