# -----------------------------------------------------------------------------------
# Do not run incremental compile as a part of insert_dft
# -----------------------------------------------------------------------------------
report_dft_insertion_configuration
insert_dft

set uniquify_naming_style $svars(top_design)_%s_%d
uniquify -force
change_names -rules verilog -hierarchy -log_changes $svars(dir,logs)/change_names_syn.log

current_test_mode Internal_scan

dft_drc > $svars(dir,reports)/$svars(top_design)_InternalScan.dft

report_scan_path -view existing_dft -chain all > $svars(dir,reports)/$svars(top_design).scanpath_chain.internal
report_scan_path -view existing_dft -cell all  > $svars(dir,reports)/$svars(top_design).scanpath_cell.internal

# Write out SCAN SPF file
write_test_protocol -test_mode Internal_scan        -out $svars(dir,outputs)/$svars(top_design)-InternalScan.spf

# Write out SCAN DEF file
write_scan_def -output $svars(dir,outputs)/$svars(top_design).scandef
check_scan_def -file   $svars(dir,outputs)/$svars(top_design).scandef

# Write out test model
write_test_model -format ctl -output $svars(dir,outputs)/$svars(top_design).ctl
write_test_model -format ddc -output $svars(dir,outputs)/$svars(top_design).ctlddc

###############################################################################################
set rf2p [sizeof_collection [get_cells -hierarchical * -filter "ref_name =~ rf2p_*"]]
echo "total $rf2p rf2p memories needs [expr $rf2p * 4] scan chains"

set sfsp [sizeof_collection [get_cells -hierarchical * -filter "ref_name =~ sfsp_*"]]
echo "total $sfsp sfsp memories needs [expr $sfsp * 1] scan chains"

set rfsp [sizeof_collection [get_cells -hierarchical * -filter "ref_name =~ rfsp_*"]]
echo "total $rfsp rfsp memories needs [expr $rfsp * 2] scan chains"

echo "total needs [expr [expr $rf2p * 4] + [expr $rfsp * 2] + [expr $sfsp * 1]] scan chains "

for {set vars(num,chain) 475} {$vars(num,chain) <= 588} {incr vars(num,chain)} {
	create_port -direction "in"  scan_in$vars(num,chain)
	create_port -direction "out" scan_out$vars(num,chain)
}


set vars(num,mem) 0
set vars(num,0) [expr 475 + 0]
set vars(num,1) [expr 475 + 1]
set vars(num,2) [expr 475 + 2]
set vars(num,3) [expr 475 + 3]
foreach mem [get_object_name [get_cells -hierarchical * -filter "ref_name =~ rf2p_*"]] {
	puts "  $mem ------ | "
	puts "              v "
	
	disconnect_net [get_nets -of_objects [get_pins $mem/SIA[0]]] [get_pins $mem/SIA[0]]
	disconnect_net [get_nets -of_objects [get_pins $mem/SIA[1]]] [get_pins $mem/SIA[1]]
        disconnect_net [get_nets -of_objects [get_pins $mem/SOA[0]]] [get_pins $mem/SOA[0]]
	disconnect_net [get_nets -of_objects [get_pins $mem/SOA[1]]] [get_pins $mem/SOA[1]]
        disconnect_net [get_nets -of_objects [get_pins $mem/SEA]] [get_pins $mem/SEA]
	disconnect_net [get_nets -of_objects [get_pins $mem/SIB[0]]] [get_pins $mem/SIB[0]]
	disconnect_net [get_nets -of_objects [get_pins $mem/SIB[1]]] [get_pins $mem/SIB[1]]
        disconnect_net [get_nets -of_objects [get_pins $mem/SOB[0]]] [get_pins $mem/SOB[0]]
	disconnect_net [get_nets -of_objects [get_pins $mem/SOB[1]]] [get_pins $mem/SOB[1]]
        disconnect_net [get_nets -of_objects [get_pins $mem/SEB]] [get_pins $mem/SEB]

        connect_pin -from [get_pins $mem/SIA[0]] -to [get_ports scan_in$vars(num,0)] -port_name scan_in
	connect_pin -from [get_pins $mem/SIA[1]] -to [get_ports scan_in$vars(num,1)] -port_name scan_in
	connect_pin -from [get_pins $mem/SOA[0]] -to [get_ports scan_out$vars(num,0)] -port_name scan_out
        connect_pin -from [get_pins $mem/SOA[1]] -to [get_ports scan_out$vars(num,1)] -port_name scan_out
        connect_pin -from [get_pins $mem/SIB[0]] -to [get_ports scan_in$vars(num,2)] -port_name scan_in
	connect_pin -from [get_pins $mem/SIB[1]] -to [get_ports scan_in$vars(num,3)] -port_name scan_in
	connect_pin -from [get_pins $mem/SOB[0]] -to [get_ports scan_out$vars(num,2)] -port_name scan_out
        connect_pin -from [get_pins $mem/SOB[1]] -to [get_ports scan_out$vars(num,3)] -port_name scan_out
        connect_pin -from [get_pins $mem/SEA] -to [get_ports DFTSE] -port_name scan_en
	connect_pin -from [get_pins $mem/SEB] -to [get_ports DFTSE] -port_name scan_en

	set vars(num,0) [expr $vars(num,0)+4]
	set vars(num,1) [expr $vars(num,1)+4]
	set vars(num,2) [expr $vars(num,2)+4]
	set vars(num,3) [expr $vars(num,3)+4]
	set vars(num,mem) [expr $vars(num,mem)+1]

	puts "            memory connect successful"
}

echo "total $vars(num,mem) memories connect successful"

set vars(num,mem) 0
set vars(num,0) 555
set vars(num,1) 556
foreach mem [get_object_name [get_cells -hierarchical * -filter "ref_name =~ rfsp_*"]] {
	puts "  $mem ------ | "
	puts "              v "

	disconnect_net [get_nets -of_objects [get_pins $mem/SI[0]]] [get_pins $mem/SI[0]]
	disconnect_net [get_nets -of_objects [get_pins $mem/SI[1]]] [get_pins $mem/SI[1]]
        disconnect_net [get_nets -of_objects [get_pins $mem/SO[0]]] [get_pins $mem/SO[0]]
	disconnect_net [get_nets -of_objects [get_pins $mem/SO[1]]] [get_pins $mem/SO[1]]
        disconnect_net [get_nets -of_objects [get_pins $mem/SE]] [get_pins $mem/SE]
        
	connect_pin -from [get_pins $mem/SI[0]] -to [get_port scan_in$vars(num,0)] -port_name scan_in
	connect_pin -from [get_pins $mem/SI[1]] -to [get_port scan_in$vars(num,1)] -port_name scan_in
	connect_pin -from [get_pins $mem/SO[0]] -to [get_port scan_out$vars(num,0)] -port_name scan_out
        connect_pin -from [get_pins $mem/SO[1]] -to [get_port scan_out$vars(num,1)] -port_name scan_out
        connect_pin -from [get_pins $mem/SE] -to [get_port DFTSE] -port_name scan_en

	set vars(num,0) [expr $vars(num,0)+2]
	set vars(num,1) [expr $vars(num,1)+2]
	set vars(num,mem) [expr $vars(num,mem)+1]
	
	puts "            memory connect successful"
}

echo "total $vars(num,mem) memories connect successful"

###############################################################################################
create_cell ScanModeMUX_m400_pp_toplevel sc9mc_logic0040ll_base_lvt_c40_ss_typical_max_0p99v_125c/MXGL2_X2B_A9TL40
create_cell ScanModeOR_m400_pp_toplevel sc9mc_logic0040ll_base_lvt_c40_ss_typical_max_0p99v_125c/OR2_X4B_A9TL40

connect_pin -from [get_port DFTSE] -to [get_pins ScanModeOR_m400_pp_toplevel/A]
connect_pin -from [get_port dc_scan_mode] -to [get_pins ScanModeOR_m400_pp_toplevel/B]
connect_pin -from [get_pins ScanModeOR_m400_pp_toplevel/Y] -to [get_pins ScanModeMUX_m400_pp_toplevel/S0]
connect_pin -from [get_port ACLK] -to [get_pins ScanModeMUX_m400_pp_toplevel/B]
disconnect_net [get_nets LV_WRCK] [get_ports LV_WRCK]
connect_pin -from [get_port LV_WRCK] -to [get_pins ScanModeMUX_m400_pp_toplevel/A]
connect_net [get_nets LV_WRCK] [get_pins ScanModeMUX_m400_pp_toplevel/Y]

set_dont_touch [get_cells ScanModeMUX_m400_pp_toplevel]
set_dont_touch [get_cells ScanModeOR_m400_pp_toplevel]
###############################################################################################

set uniquify_naming_style $svars(top_design)_%s_%d
uniquify -force
change_names -rules verilog -hierarchy