set ports_clock_root [get_ports [all_fanout -flat -clock_tree -level 0]]
set input            [remove_from_collection [all_inputs] $ports_clock_root]
set design_signals   [remove_from_collection $input [get_ports test* -quiet]]

set mems [all_macro_cells]
set regs [remove_from_collection [all_registers] mems]

group_path -default
group_path -name R2R -from $regs -to $regs
group_path -name R2M -from $regs -to $mems
group_path -name M2R -from $mems -to $regs
group_path -name M2M -from $mems -to $mems
group_path -name I2R -from $design_signals -to $regs
group_path -name I2M -from $design_signals -to $mems
group_path -name R2O -from $regs -to [all_outputs]
group_path -name M2O -from $mems -to [all_outputs]
group_path -name INOUT -from $design_signals -to [all_outputs]
group_path -name GATING -from [all_registers] -to [get_pins -hier */E]