module P_NCO # ( parameter WIDTH = 16 , parameter PARALLEL = 16 )( input clk ,input rstn ,input clr ,input clr_acc ,input [15 :0] ptw ,input p2a_en ,input [15 :0] s1 ,input [15 :0] s2 ,input [15 :0] s3 ,output [15 :0] s1_o ,output [15 :0] s2_o ,output [15 :0] s3_o ,input [47 :0] fcw [PARALLEL-1:0]//fcw[0]=16*fcw; fcw[i]=i*fcw, i=1,2,...,15 ,output [WIDTH-1:0] cos [PARALLEL-1:0] ,output [WIDTH-1:0] sin [PARALLEL-1:0] ); wire [15:0] cos_16bit [PARALLEL-1:0]; wire [15:0] sin_16bit [PARALLEL-1:0]; reg [15:0] ptw_r; always@(posedge clk or negedge rstn) if(!rstn) ptw_r <= 16'd0; else ptw_r <= ptw; wire [18:0] pha [PARALLEL-1:0]; PIPE3_ACC_48BIT inst_pipe_0( .clk (clk ) ,.rstn (rstn ) ,.in (fcw[0] ) ,.clr (clr_acc ) ,.en (1'b1 ) ,.ptw (ptw ) ,.s_o_1 (s1_o ) ,.s_o_2 (s2_o ) ,.s_o_3 (s3_o ) ,.s_i_1 (s1 ) ,.s_i_2 (s2 ) ,.s_i_3 (s3 ) ,.out (pha[0] )); reg [18:0] pha_0_r; always@(posedge clk or negedge rstn) if(!rstn) pha_0_r <= 16'd0; else if (p2a_en == 1'b0) pha_0_r <= 16'd0; else pha_0_r <= pha[0]; PH2AMP inst_ph2amp_0( .clk (clk ), .rstn (rstn ), .pha_map (pha_0_r ), .sin_o (sin_16bit[0]), .cos_o (cos_16bit[0]) ); assign cos[0] = cos_16bit[0][15:16-WIDTH]; assign sin[0] = sin_16bit[0][15:16-WIDTH]; genvar i; generate for(i = 1; i < PARALLEL; i++) begin PIPE3_ADD_48BIT inst_pipe_i( .clk (clk ) ,.rstn (rstn ) ,.in (fcw[i] ) ,.clr (clr ) ,.en (p2a_en ) ,.ptw (ptw_r ) ,.s1 (s1 ) ,.s2 (s2 ) ,.s3 (s3 ) ,.out (pha[i] )); PH2AMP inst_ph2amp_i( .clk (clk ) ,.rstn (rstn ) ,.pha_map (pha[i] ) ,.sin_o (sin_16bit[i]) ,.cos_o (cos_16bit[i])); assign cos[i] = cos_16bit[i][15:16-WIDTH]; assign sin[i] = sin_16bit[i][15:16-WIDTH]; end endgenerate endmodule