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20260314 ready to test

This commit is contained in:
yangshenbo 2026-03-14 17:51:22 +08:00
parent 59487f9128
commit e908d3a088
359 changed files with 27833 additions and 12091 deletions
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20
DA4008_V1.2/sim/chip_top/TB.sv
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@ -99,10 +99,10 @@ initial begin
rst_n = 1'b1;
//lvds_drv.do_drive();
lvds_drv.train_count = 100; // ÉèÖÃѵÁ·´ÎÊý
lvds_drv.send_training(); // ·¢ËÍѵÁ·ÐòÁÐ
lvds_drv.train_count = 100; //
lvds_drv.send_training(); //
lvds_drv.scrambler_en = 1;
lvds_drv.send_frame_from_file(LVDS_FILE); // ·¢ËÍÊý¾ÝÖ¡
lvds_drv.send_frame_from_file(LVDS_FILE); //
file_path = $fopen(DATA_O_FILE, "w");
my_drv.do_drive(file_path);
@ -137,6 +137,12 @@ initial begin
start = 1'b0;
# 30000;
start = 1'b1;
# PERIOD;
# PERIOD;
start = 1'b0;
# 30000;
$finish(0);
end
@ -156,8 +162,8 @@ logic [0 :0] lvds_clk = '0;
//DAC Data
logic [6 :0] MSB_OUT [63:0] ;
logic [4 :0] LSB_OUT [63:0] ;
logic MSB_DUM [63:0] ;
logic DEM_VLD ;
logic MSB_DUM [63:0] ;
logic DEM_VLD ;
//DAC Cfg Port
logic [3 :0] Rterm ;
logic [2 :0] CasAddr ;
@ -271,7 +277,7 @@ da4008_chip_top U_da4008_chip_top (
//DEM_Reverse_64CH
////////////////////////////////////////////////////////////////////////////////////////
logic vld_out ;
logic vld_out ;
logic [7 :0] data_out [63:0] ;
DEM_Reverse_64CH U_DEM_Reverse_64CH (
@ -284,7 +290,7 @@ DEM_Reverse_64CH U_DEM_Reverse_64CH (
);
logic [7 :0] data_out_r [63:0] ;
logic vld_out_r ;
logic vld_out_r ;
always @(posedge clk_40g) begin
data_out_r <= data_out ;

396
DA4008_V1.2/sim/chip_top/TB.sv.bak Normal file
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@ -0,0 +1,396 @@
`include "../../rtl/define/chip_define.v"
`include "../../model/SPI_DRIVER.sv"
`include "../../model/LVDS_DRIVER.sv"
`timescale 1ns/1ps
module TB ();
//###################################
// Generate Clocks & Reset
//###################################
//Generate Clock
localparam PERIOD = 1.536;
logic clk ;
//clk
clock_tb #(
.PERIOD ( PERIOD )
,.PHASE ( 0 )
)clk_inst (
.clk_out ( clk )
);
//clk_40g
logic clk_40g;
clock_tb #(
.PERIOD ( 0.024)
,.PHASE ( 0 )
)clk_40g_inst (
.clk_out ( clk_40g )
);
//Generate Reset
logic rst_n;
int file_path;
string CONFIG_FILE = "";
string DATA_O_FILE = "";
parameter string CASE_TEMP = "../../case_temp.txt";
parameter string DATA_TEMP = "../../data_temp.txt";
parameter string LVDS_FILE = "../../../../case/lvds/0305/lvds.txt";
initial begin
file_path = $fopen(CASE_TEMP, "r");
if(file_path != 0) begin
$fscanf(file_path, "%s", CONFIG_FILE);
$display(CONFIG_FILE);
$fclose(file_path);
end
file_path = $fopen(DATA_TEMP, "r");
if(file_path != 0) begin
$fscanf(file_path, "%s", DATA_O_FILE);
$display(DATA_O_FILE);
$fclose(file_path);
end
$fsdbAutoSwitchDumpfile(500, "./verdplus.fsdb", 1000000);
$fsdbDumpvars();
$fsdbDumpMDA();
end
//###################################
// configure the dut
//###################################
virtual spi_if vif;
spi_if spi_bus(.clk(clk), .rstn(rst_n));
virtual lvds_if lvds_vif;
lvds_if lvds_bus(.clk(clk));
initial begin
spi_bus.sclk = 1'b1;
spi_bus.mosi = 1'b0;
spi_bus.csn = 1'b1;
vif = spi_bus;
lvds_vif = lvds_bus;
end
spi_driver my_drv;
lvds_driver lvds_drv;
logic start;
initial begin
rst_n = 1'b0;
start = 1'b0;
lvds_drv = new();
//lvds_drv.file_path = LVDS_FILE;
lvds_drv.drv_if = lvds_vif;
my_drv = new();
my_drv.file_path = CONFIG_FILE;
my_drv.itf = vif;
# 20;
rst_n = 1'b1;
//lvds_drv.do_drive();
lvds_drv.train_count = 100; //
lvds_drv.send_training(); //
lvds_drv.scrambler_en = 1;
lvds_drv.send_frame_from_file(LVDS_FILE); //
file_path = $fopen(DATA_O_FILE, "w");
my_drv.do_drive(file_path);
$fclose(file_path);
# 30;
start = 1'b1;
# PERIOD;
# PERIOD;
start = 1'b0;
# 30000;
file_path = $fopen(DATA_O_FILE, "w");
my_drv.do_drive(file_path);
$fclose(file_path);
start = 1'b1;
# PERIOD;
# PERIOD;
start = 1'b0;
# 30000;
file_path = $fopen(DATA_O_FILE, "w");
my_drv.do_drive(file_path);
$fclose(file_path);
start = 1'b1;
# PERIOD;
# PERIOD;
start = 1'b0;
# 30000;
start = 1'b1;
# PERIOD;
# PERIOD;
start = 1'b0;
# 30000;
$finish(0);
end
////////////////////////////////////////////////////////////////////////////////////////
//DUT
////////////////////////////////////////////////////////////////////////////////////////
//sync_out
logic sync_out ;
//irq
logic irq ;
//lvds rx
logic [3 :0] lvds_data = '0;
logic [0 :0] lvds_valid = '0;
logic [0 :0] lvds_clk = '0;
//DAC Data
logic [6 :0] MSB_OUT [63:0] ;
logic [4 :0] LSB_OUT [63:0] ;
logic MSB_DUM [63:0] ;
logic DEM_VLD ;
//DAC Cfg Port
logic [3 :0] Rterm ;
logic [2 :0] CasAddr ;
logic [2 :0] CasDw ;
logic [9 :0] IMainCtrl ;
logic [3 :0] IBleedCtrl ;
logic [3 :0] ICkCml ;
logic [31 :0] CurRsv0 ;
logic [31 :0] CurRsv1 ;
//CLK Cfg Port
logic [0 :0] CcalRstn ;
logic [3 :0] EnAllP ;
logic [0 :0] DccEn ;
logic [0 :0] CasGateCkCtrl ;
logic [0 :0] SpiEnPi ;
logic [0 :0] SpiEnQec ;
logic [0 :0] SpiEnDcc ;
logic [4 :0] SpiQecCtrlIp ;
logic [4 :0] SpiQecCtrlIn ;
logic [4 :0] SpiQecCtrlQp ;
logic [4 :0] SpiQecCtrlQn ;
logic [5 :0] SpiDccCtrlIup ;
logic [5 :0] SpiDccCtrlIdn ;
logic [5 :0] SpiDccCtrlQup ;
logic [5 :0] SpiDccCtrlQdn ;
logic [7 :0] SpiSiqNOut ;
logic [7 :0] SpiSiqPOut ;
logic [3 :0] SpiSiPOut ;
logic [3 :0] SpiSqPOut ;
logic [2 :0] CrtlCrossOverN ;
logic [2 :0] CrtlCrossOverP ;
logic [31 :0] CcalRsv0 ;
logic [31 :0] CcalRsv1 ;
logic [3 :0] SelCk10GDig ;
logic [3 :0] SelCk2p5GDig ;
logic [8 :0] SelCk625MDig ;
logic [15 :0] P2sDataEn ;
logic [15 :0] P2sEnAllP ;
logic [15 :0] EnPiP ;
logic [15 :0] CkDivRstn ;
logic [31 :0] p2srsv0 ;
logic [31 :0] p2srsv1 ;
logic [15 :0] CkRxSw ;
logic [15 :0] RstnCk ;
logic [15 :0] CtrlZin ;
da4008_chip_top U_da4008_chip_top (
.PI_sclk ( spi_bus.sclk )
,.PI_csn ( spi_bus.csn )
,.PI_mosi ( spi_bus.mosi )
,.PO_miso ( spi_bus.miso )
,.PO_irq ( irq )
,.PI_async_rstn ( rst_n )
,.PI_sync_in ( start )
,.PO_sync_out ( sync_out )
,.clk ( clk )
,.lvds_data ( lvds_bus.data )
,.lvds_valid ( lvds_bus.valid )
,.lvds_clk ( lvds_bus.clk )
,.MSB_OUT ( MSB_OUT )
,.LSB_OUT ( LSB_OUT )
,.MSB_DUM ( MSB_DUM )
,.DEM_VLD ( DEM_VLD )
,.Rterm ( Rterm )
,.CasAddr ( CasAddr )
,.CasDw ( CasDw )
,.IMainCtrl ( IMainCtrl )
,.IBleedCtrl ( IBleedCtrl )
,.ICkCml ( ICkCml )
,.CurRsv0 ( CurRsv0 )
,.CurRsv1 ( CurRsv1 )
,.CcalRstn ( CcalRstn )
,.EnAllP ( EnAllP )
,.DccEn ( DccEn )
,.CasGateCkCtrl ( CasGateCkCtrl )
,.SpiEnPi ( SpiEnPi )
,.SpiEnQec ( SpiEnQec )
,.SpiEnDcc ( SpiEnDcc )
,.SpiQecCtrlIp ( SpiQecCtrlIp )
,.SpiQecCtrlIn ( SpiQecCtrlIn )
,.SpiQecCtrlQp ( SpiQecCtrlQp )
,.SpiQecCtrlQn ( SpiQecCtrlQn )
,.SpiDccCtrlIup ( SpiDccCtrlIup )
,.SpiDccCtrlIdn ( SpiDccCtrlIdn )
,.SpiDccCtrlQup ( SpiDccCtrlQup )
,.SpiDccCtrlQdn ( SpiDccCtrlQdn )
,.SpiSiqNOut ( SpiSiqNOut )
,.SpiSiqPOut ( SpiSiqPOut )
,.SpiSiPOut ( SpiSiPOut )
,.SpiSqPOut ( SpiSqPOut )
,.CrtlCrossOverN ( CrtlCrossOverN )
,.CrtlCrossOverP ( CrtlCrossOverP )
,.CcalRsv0 ( CcalRsv0 )
,.CcalRsv1 ( CcalRsv1 )
,.SelCk10GDig ( SelCk10GDig )
,.SelCk2p5GDig ( SelCk2p5GDig )
,.SelCk625MDig ( SelCk625MDig )
,.P2sDataEn ( P2sDataEn )
,.P2sEnAllP ( P2sEnAllP )
,.EnPiP ( EnPiP )
,.CkDivRstn ( CkDivRstn )
,.p2srsv0 ( p2srsv0 )
,.p2srsv1 ( p2srsv1 )
,.CkRxSw ( CkRxSw )
,.RstnCk ( RstnCk )
,.CtrlZin ( CtrlZin )
);
////////////////////////////////////////////////////////////////////////////////////////
//DEM_Reverse_64CH
////////////////////////////////////////////////////////////////////////////////////////
logic vld_out ;
logic [7 :0] data_out [63:0] ;
DEM_Reverse_64CH U_DEM_Reverse_64CH (
.clk ( clk )
,.msb_in ( MSB_OUT )
,.lsb_in ( LSB_OUT )
,.vld_in ( DEM_VLD )
,.vld_out ( vld_out )
,.data_out ( data_out )
);
logic [7 :0] data_out_r [63:0] ;
logic vld_out_r ;
always @(posedge clk_40g) begin
data_out_r <= data_out ;
vld_out_r <= vld_out ;
end
///////////////////////////////////////////////////////////////////////
//DA4008 DEM output data save
///////////////////////////////////////////////////////////////////////
wire add_cnt = vld_out_r;
wire end_cnt = 1'b0;
logic [5 :0] cnt_c;
wire [5 :0] cnt_n = end_cnt ? 6'h0 :
add_cnt ? cnt_c + 1'b1 :
cnt_c ;
always @(posedge clk_40g or negedge rst_n) begin
if(rst_n==1'b0) begin
cnt_c <= 6'd0;
end
else begin
cnt_c <= cnt_n;
end
end
logic [7:0] cs_wave;
always @(posedge clk_40g or negedge rst_n) begin
if(rst_n==1'b0) begin
cs_wave <= 16'h0;
end
else begin
case(cnt_c)
6'd0 : cs_wave <= {~data_out_r[0 ][7],data_out_r[0 ][6:0]};
6'd1 : cs_wave <= {~data_out_r[1 ][7],data_out_r[1 ][6:0]};
6'd2 : cs_wave <= {~data_out_r[2 ][7],data_out_r[2 ][6:0]};
6'd3 : cs_wave <= {~data_out_r[3 ][7],data_out_r[3 ][6:0]};
6'd4 : cs_wave <= {~data_out_r[4 ][7],data_out_r[4 ][6:0]};
6'd5 : cs_wave <= {~data_out_r[5 ][7],data_out_r[5 ][6:0]};
6'd6 : cs_wave <= {~data_out_r[6 ][7],data_out_r[6 ][6:0]};
6'd7 : cs_wave <= {~data_out_r[7 ][7],data_out_r[7 ][6:0]};
6'd8 : cs_wave <= {~data_out_r[8 ][7],data_out_r[8 ][6:0]};
6'd9 : cs_wave <= {~data_out_r[9 ][7],data_out_r[9 ][6:0]};
6'd10 : cs_wave <= {~data_out_r[10][7],data_out_r[10][6:0]};
6'd11 : cs_wave <= {~data_out_r[11][7],data_out_r[11][6:0]};
6'd12 : cs_wave <= {~data_out_r[12][7],data_out_r[12][6:0]};
6'd13 : cs_wave <= {~data_out_r[13][7],data_out_r[13][6:0]};
6'd14 : cs_wave <= {~data_out_r[14][7],data_out_r[14][6:0]};
6'd15 : cs_wave <= {~data_out_r[15][7],data_out_r[15][6:0]};
6'd16 : cs_wave <= {~data_out_r[16][7],data_out_r[16][6:0]};
6'd17 : cs_wave <= {~data_out_r[17][7],data_out_r[17][6:0]};
6'd18 : cs_wave <= {~data_out_r[18][7],data_out_r[18][6:0]};
6'd19 : cs_wave <= {~data_out_r[19][7],data_out_r[19][6:0]};
6'd20 : cs_wave <= {~data_out_r[20][7],data_out_r[20][6:0]};
6'd21 : cs_wave <= {~data_out_r[21][7],data_out_r[21][6:0]};
6'd22 : cs_wave <= {~data_out_r[22][7],data_out_r[22][6:0]};
6'd23 : cs_wave <= {~data_out_r[23][7],data_out_r[23][6:0]};
6'd24 : cs_wave <= {~data_out_r[24][7],data_out_r[24][6:0]};
6'd25 : cs_wave <= {~data_out_r[25][7],data_out_r[25][6:0]};
6'd26 : cs_wave <= {~data_out_r[26][7],data_out_r[26][6:0]};
6'd27 : cs_wave <= {~data_out_r[27][7],data_out_r[27][6:0]};
6'd28 : cs_wave <= {~data_out_r[28][7],data_out_r[28][6:0]};
6'd29 : cs_wave <= {~data_out_r[29][7],data_out_r[29][6:0]};
6'd30 : cs_wave <= {~data_out_r[30][7],data_out_r[30][6:0]};
6'd31 : cs_wave <= {~data_out_r[31][7],data_out_r[31][6:0]};
6'd32 : cs_wave <= {~data_out_r[32][7],data_out_r[32][6:0]};
6'd33 : cs_wave <= {~data_out_r[33][7],data_out_r[33][6:0]};
6'd34 : cs_wave <= {~data_out_r[34][7],data_out_r[34][6:0]};
6'd35 : cs_wave <= {~data_out_r[35][7],data_out_r[35][6:0]};
6'd36 : cs_wave <= {~data_out_r[36][7],data_out_r[36][6:0]};
6'd37 : cs_wave <= {~data_out_r[37][7],data_out_r[37][6:0]};
6'd38 : cs_wave <= {~data_out_r[38][7],data_out_r[38][6:0]};
6'd39 : cs_wave <= {~data_out_r[39][7],data_out_r[39][6:0]};
6'd40 : cs_wave <= {~data_out_r[40][7],data_out_r[40][6:0]};
6'd41 : cs_wave <= {~data_out_r[41][7],data_out_r[41][6:0]};
6'd42 : cs_wave <= {~data_out_r[42][7],data_out_r[42][6:0]};
6'd43 : cs_wave <= {~data_out_r[43][7],data_out_r[43][6:0]};
6'd44 : cs_wave <= {~data_out_r[44][7],data_out_r[44][6:0]};
6'd45 : cs_wave <= {~data_out_r[45][7],data_out_r[45][6:0]};
6'd46 : cs_wave <= {~data_out_r[46][7],data_out_r[46][6:0]};
6'd47 : cs_wave <= {~data_out_r[47][7],data_out_r[47][6:0]};
6'd48 : cs_wave <= {~data_out_r[48][7],data_out_r[48][6:0]};
6'd49 : cs_wave <= {~data_out_r[49][7],data_out_r[49][6:0]};
6'd50 : cs_wave <= {~data_out_r[50][7],data_out_r[50][6:0]};
6'd51 : cs_wave <= {~data_out_r[51][7],data_out_r[51][6:0]};
6'd52 : cs_wave <= {~data_out_r[52][7],data_out_r[52][6:0]};
6'd53 : cs_wave <= {~data_out_r[53][7],data_out_r[53][6:0]};
6'd54 : cs_wave <= {~data_out_r[54][7],data_out_r[54][6:0]};
6'd55 : cs_wave <= {~data_out_r[55][7],data_out_r[55][6:0]};
6'd56 : cs_wave <= {~data_out_r[56][7],data_out_r[56][6:0]};
6'd57 : cs_wave <= {~data_out_r[57][7],data_out_r[57][6:0]};
6'd58 : cs_wave <= {~data_out_r[58][7],data_out_r[58][6:0]};
6'd59 : cs_wave <= {~data_out_r[59][7],data_out_r[59][6:0]};
6'd60 : cs_wave <= {~data_out_r[60][7],data_out_r[60][6:0]};
6'd61 : cs_wave <= {~data_out_r[61][7],data_out_r[61][6:0]};
6'd62 : cs_wave <= {~data_out_r[62][7],data_out_r[62][6:0]};
6'd63 : cs_wave <= {~data_out_r[63][7],data_out_r[63][6:0]};
endcase
end
end
endmodule

45
DA4008_V1.2/sim/chip_top/compile.log
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@ -10,7 +10,46 @@ Warning-[LCA_FEATURES_ENABLED] Usage warning
information regarding list of LCA features please refer to Chapter "LCA
features" in the VCS/VCS-MX Release Notes
The design hasn't changed and need not be recompiled.
If you really want to, delete file simv.daidir/.vcs.timestamp and
run VCS again.
Warning-[RVOSFD] Return value discarded
../../model/SPI_DRIVER.sv, 50
System function '$fscanf' is invoked as task, its return value is discarded.
"../../model/SPI_DRIVER.sv", 50
Source info: $fscanf(file_id,"%h\n",value);
Warning-[RVOSFD] Return value discarded
../../model/LVDS_DRIVER.sv, 41
System function '$fscanf' is invoked as task, its return value is discarded.
"../../model/LVDS_DRIVER.sv", 41
Source info: $fscanf(file_id, "%h\n", value);
Warning-[RVOSFD] Return value discarded
../../sim/chip_top/TB.sv, 46
System function '$fscanf' is invoked as task, its return value is discarded.
"../../sim/chip_top/TB.sv", 46
Source info: $fscanf(file_path, "%s", CONFIG_FILE);
Warning-[RVOSFD] Return value discarded
../../sim/chip_top/TB.sv, 52
System function '$fscanf' is invoked as task, its return value is discarded.
"../../sim/chip_top/TB.sv", 52
Source info: $fscanf(file_path, "%s", DATA_O_FILE);
Lint-[TFIPC-L] Too few instance port connections
../../sim/chip_top/TB.sv, 214
TB, "da4008_chip_top U_da4008_chip_top( .PI_sclk (spi_bus.sclk), .PI_csn (spi_bus.csn), .PI_mosi (spi_bus.mosi), .PO_miso (spi_bus.miso), .PO_irq (irq), .PI_async_rstn (rst_n), .PI_sync_in (start), .PO_sync_out (sync_out), .clk (clk), .lvds_data (lvds_bus.data), .lvds_valid (lvds_bus.valid), .lvds_clk (lvds_bus.clk), .MSB_OUT (MSB_OUT), .LSB_OUT (LSB_OUT), .MSB_DUM (MSB_DUM), .DEM_VLD (DEM_VLD), .Rterm (Rterm), .CasAddr (CasAddr), .CasDw (CasDw), .IMainCtrl (IMainCtrl), .IBleedCtrl (IBleedCtrl), .ICkCml (ICkCml), .CurRsv0 (CurRsv0), .CurRsv1 (CurRsv1), .CcalRstn (CcalRstn), .EnAllP (EnAllP), .DccEn (DccEn), .CasGateCkCtrl (CasGateCkCtrl), .SpiEnPi (SpiEnPi), .SpiEnQec (SpiEnQec), .SpiEnDcc (SpiEnDcc), .SpiQecCtrlIp (SpiQecCtrlI ... "
The above instance has fewer port connections than the module definition,
output port 'phase_tap' is not connected.
VCS Coverage Metrics Release O-2018.09-SP2_Full64 Copyright (c) 1991-2018 by Synopsys Inc.
Notice: Ports coerced to inout, use -notice for details
Note-[VCS_PARAL] Parallel code-gen enabled
VCS is running with parallel code generation(-j)...
147 modules and 0 UDP read.
../simv up to date

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@ -1,6 +1,6 @@
// Synopsys, Inc.
// User: shbyang
// Date: Fri Mar 13 14:54:44 2026
// Date: Sat Mar 14 17:19:26 2026
// ==================================================================================================
// This config file prototype is produced from the last run using the complete list of extracted fsms.

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"Compiled": "Yes",
"start_perf": [
1.9955570697784424,
0.124463,
0.021645000000000001,
321120,
321124,
1773479967.7919791,
70083385509464604
],
"nQuads": 148,
"child_modules": {},
"Compiled Times": 2,
"nRouts": 24,
"end_perf": [
1.9977540969848633,
0.12534400000000001,
0.022690999999999999,
321120,
321124,
70083385515729828,
137438953473,
0
],
"nMops": 349
},
"PDDW08SDGZ_H_G": {
"Compiled": "Yes",
"start_perf": [
1.9908609390258789,
0.121124,
0.020546999999999999,
321120,
321124,
1773479967.7872829,
70083385496140438
],
"nQuads": 148,
"child_modules": {},
"Compiled Times": 2,
"nRouts": 24,
"end_perf": [
1.9931700229644775,
0.122171,
0.021623,
321120,
321124,
70083385502730480,
68719476737,
0
],
"nMops": 349
},
"PRUW16SDGZ_H_G": {
"Compiled": "Yes",
"start_perf": [
2.0059709548950195,
0.13242100000000001,
0.023743,
321120,
321124,
1773479967.802393,
70083385538999072
],
"nQuads": 148,
"child_modules": {},
"Compiled Times": 2,
"nRouts": 24,
"end_perf": [
2.007688045501709,
0.134294,
0.023743,
321120,
321124,
70083385543897280,
300647710721,
0
],
"nMops": 349
},
"PVDD1AC_H_G": {
"Compiled": "Yes",
"start_perf": [
2.0096900463104248,
0.13531699999999999,
0.0247,
321120,
321124,
1773479967.8061121,
70083385549548408
],
"nQuads": 6,
"child_modules": {},
"Compiled Times": 2,
"nRouts": 8,
"end_perf": [
2.0103180408477783,
0.13589599999999999,
0.024806000000000002,
321120,
321124,
70083385551358514,
317827579905,
0
],
"nMops": 5
},
"DW_pulse_sync_0000": {
"Compiled": "Yes",
"start_perf": [
1.9828059673309326,
0.11507199999999999,
0.018454000000000002,
321120,
321124,
1773479967.779228,
70083385473300012
],
"nQuads": 613,
"child_modules": {
"DW_sync_0000": 1
},
"Compiled Times": 2,
"nRouts": 61,
"end_perf": [
1.9877560138702393,
0.12013799999999999,
0.018454000000000002,
321120,
321124,
70083385487386240,
717259538433,
0
],
"nMops": 1706
},
"crc32": {
"Compiled": "Yes",
"start_perf": [
1.9877939224243164,
0.12018,
0.018454000000000002,
321120,
321124,
1773479967.7842159,
70083385487443010
],
"nQuads": 253,
"child_modules": {},
"Compiled Times": 2,
"nRouts": 36,
"end_perf": [
1.9908270835876465,
0.12109200000000001,
0.020542000000000001,
321120,
321124,
70083385496084964,
523986010113,
0
],
"nMops": 579
},
"PRDW12SDGZ_H_G": {
"Compiled": "Yes",
"start_perf": [
2.0018460750579834,
0.12843199999999999,
0.023743,
321120,
321124,
1773479967.7982681,
70083385527300494
],
"nQuads": 148,
"child_modules": {},
"Compiled Times": 2,
"nRouts": 24,
"end_perf": [
2.0041220188140869,
0.13040299999999999,
0.023743,
321120,
321124,
70083385533790874,
231928233985,
0
],
"nMops": 349
},
"PDDW16SDGZ_H_G": {
"Compiled": "Yes",
"start_perf": [
1.99320387840271,
0.12220200000000001,
0.021628000000000001,
321120,
321124,
1773479967.7896259,
70083385502786556
],
"nQuads": 148,
"child_modules": {},
"Compiled Times": 2,
"nRouts": 24,
"end_perf": [
1.9955151081085205,
0.12442300000000001,
0.021638000000000001,
321120,
321124,
70083385509403236,
103079215105,
0
],
"nMops": 349
},
"PVSS3A_H_G": {
"Compiled": "Yes",
"start_perf": [
2.0134339332580566,
0.13711100000000001,
0.02699,
321120,
321124,
1773479967.8098559,
70083385560208336
],
"nQuads": 6,
"child_modules": {},
"Compiled Times": 2,
"nRouts": 8,
"end_perf": [
2.0147368907928467,
0.137577,
0.027945000000000001,
321120,
321124,
70083385563953816,
455266533377,
0
],
"nMops": 5
},
"PDUW16SDGZ_H_G": {
"Compiled": "Yes",
"start_perf": [
1.9977879524230957,
0.12537599999999999,
0.022696999999999998,
321120,
321124,
1773479967.79421,
70083385515792636
],
"nQuads": 148,
"child_modules": {},
"Compiled Times": 2,
"nRouts": 24,
"end_perf": [
2.0018129348754883,
0.12840099999999999,
0.023737999999999999,
321120,
321124,
70083385527244048,
171798691841,
0
],
"nMops": 349
},
"PDB3AC_H_G": {
"Compiled": "Yes",
"start_perf": [
2.0085549354553223,
0.13519,
0.023793000000000002,
321120,
321124,
1773479967.8049769,
70083385546329392
],
"nQuads": 6,
"child_modules": {},
"Compiled Times": 2,
"nRouts": 8,
"end_perf": [
2.0096580982208252,
0.13528599999999999,
0.024695000000000002,
321120,
321124,
70083385549493262,
34359738369,
0
],
"nMops": 5
},
"PRUW08SDGZ_H_G": {
"Compiled": "Yes",
"start_perf": [
2.0041561126708984,
0.130441,
0.023743,
321120,
321124,
1773479967.8005781,
70083385533852716
],
"nQuads": 148,
"child_modules": {},
"Compiled Times": 2,
"nRouts": 24,
"end_perf": [
2.0059390068054199,
0.132385,
0.023743,
321120,
321124,
70083385538943462,
266287972353,
0
],
"nMops": 349
},
"PDXOEDG_H_G": {
"Compiled": "Yes",
"start_perf": [
2.0077180862426758,
0.134327,
0.023743,
321120,
321124,
1773479967.8041401,
70083385543953454
],
"nQuads": 24,
"child_modules": {},
"Compiled Times": 2,
"nRouts": 11,
"end_perf": [
2.0085148811340332,
0.135153,
0.023786999999999999,
321120,
321124,
70083385546272148,
180388626433,
0
],
"nMops": 43
},
"PVDD2DGZ_H_G": {
"Compiled": "Yes",
"start_perf": [
2.0103480815887451,
0.13592299999999999,
0.024811,
321120,
321124,
1773479967.8067701,
70083385551411388
],
"nQuads": 6,
"child_modules": {},
"Compiled Times": 2,
"nRouts": 8,
"end_perf": [
2.0111320018768311,
0.13592299999999999,
0.025666000000000001,
321120,
321124,
70083385553669588,
352187318273,
0
],
"nMops": 5
},
"PVSS1A_H_G": {
"Compiled": "Yes",
"start_perf": [
2.0111629962921143,
0.13592299999999999,
0.025700000000000001,
321120,
321124,
1773479967.807585,
70083385553726880
],
"nQuads": 6,
"child_modules": {},
"Compiled Times": 2,
"nRouts": 8,
"end_perf": [
2.012037992477417,
0.136737,
0.025839999999999998,
321120,
321124,
70083385556322210,
386547056641,
0
],
"nMops": 5
},
"PVSS2A_H_G": {
"Compiled": "Yes",
"start_perf": [
2.0121040344238281,
0.136799,
0.025850999999999999,
321120,
321124,
1773479967.808526,
70083385556439972
],
"nQuads": 6,
"child_modules": {},
"Compiled Times": 2,
"nRouts": 8,
"end_perf": [
2.0133709907531738,
0.13705200000000001,
0.026977999999999999,
321120,
321124,
70083385560084316,
420906795009,
0
],
"nMops": 5
},
"sram_if_0001": {
"Compiled": "Yes",
"start_perf": [
2.0147950649261475,
0.13763,
0.027956000000000002,
321120,
321124,
1773479967.8112171,
70083385564068890
],
"nQuads": 30,
"child_modules": {},
"Compiled Times": 2,
"nRouts": 13,
"end_perf": [
2.0169260501861572,
0.13992499999999999,
0.027984999999999999,
321120,
321124,
70083385570174088,
605590388737,
0
],
"nMops": 73
}
},
"ObjArchives": [],
"stat": {
"ru_self_end": {
"ru_utime_sec": 0.14016899999999999,
"ru_nivcsw": 1,
"ru_majflt": 0,
"ru_stime_sec": 0.028032999999999999,
"ru_nvcsw": 14,
"ru_maxrss_kb": 60188,
"ru_minflt": 5823
},
"ru_childs_end": {
"ru_utime_sec": 0.0,
"ru_nivcsw": 0,
"ru_majflt": 0,
"ru_stime_sec": 0.0,
"ru_nvcsw": 0,
"ru_maxrss_kb": 0,
"ru_minflt": 0
},
"cpu_cycles_end": 70083385570830554,
"peak_mem_kb": 321124
}
}

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77
DA4008_V1.2/sim/chip_top/csrc/filelist.cu
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@ -1,71 +1,34 @@
PIC_LD=ld
ARCHIVE_OBJS=
ARCHIVE_OBJS += _32553_archive_1.so
_32553_archive_1.so : archive.0/_32553_archive_1.a
ARCHIVE_OBJS += _64094_archive_1.so
_64094_archive_1.so : archive.1/_64094_archive_1.a
@$(AR) -s $<
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_32553_archive_1.so --whole-archive $< --no-whole-archive
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_64094_archive_1.so --whole-archive $< --no-whole-archive
@rm -f $@
@ln -sf .//../simv.daidir//_32553_archive_1.so $@
@ln -sf .//../simv.daidir//_64094_archive_1.so $@
ARCHIVE_OBJS += _32573_archive_1.so
_32573_archive_1.so : archive.0/_32573_archive_1.a
ARCHIVE_OBJS += _64123_archive_1.so
_64123_archive_1.so : archive.1/_64123_archive_1.a
@$(AR) -s $<
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_32573_archive_1.so --whole-archive $< --no-whole-archive
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_64123_archive_1.so --whole-archive $< --no-whole-archive
@rm -f $@
@ln -sf .//../simv.daidir//_32573_archive_1.so $@
@ln -sf .//../simv.daidir//_64123_archive_1.so $@
ARCHIVE_OBJS += _32574_archive_1.so
_32574_archive_1.so : archive.0/_32574_archive_1.a
ARCHIVE_OBJS += _prev_archive_1.so
_prev_archive_1.so : archive.1/_prev_archive_1.a
@$(AR) -s $<
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_32574_archive_1.so --whole-archive $< --no-whole-archive
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_prev_archive_1.so --whole-archive $< --no-whole-archive
@rm -f $@
@ln -sf .//../simv.daidir//_32574_archive_1.so $@
ARCHIVE_OBJS += _32575_archive_1.so
_32575_archive_1.so : archive.0/_32575_archive_1.a
@$(AR) -s $<
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_32575_archive_1.so --whole-archive $< --no-whole-archive
@rm -f $@
@ln -sf .//../simv.daidir//_32575_archive_1.so $@
ARCHIVE_OBJS += _32576_archive_1.so
_32576_archive_1.so : archive.0/_32576_archive_1.a
@$(AR) -s $<
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_32576_archive_1.so --whole-archive $< --no-whole-archive
@rm -f $@
@ln -sf .//../simv.daidir//_32576_archive_1.so $@
ARCHIVE_OBJS += _32577_archive_1.so
_32577_archive_1.so : archive.0/_32577_archive_1.a
@$(AR) -s $<
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_32577_archive_1.so --whole-archive $< --no-whole-archive
@rm -f $@
@ln -sf .//../simv.daidir//_32577_archive_1.so $@
ARCHIVE_OBJS += _32578_archive_1.so
_32578_archive_1.so : archive.0/_32578_archive_1.a
@$(AR) -s $<
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_32578_archive_1.so --whole-archive $< --no-whole-archive
@rm -f $@
@ln -sf .//../simv.daidir//_32578_archive_1.so $@
ARCHIVE_OBJS += _32579_archive_1.so
_32579_archive_1.so : archive.0/_32579_archive_1.a
@$(AR) -s $<
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_32579_archive_1.so --whole-archive $< --no-whole-archive
@rm -f $@
@ln -sf .//../simv.daidir//_32579_archive_1.so $@
@ln -sf .//../simv.daidir//_prev_archive_1.so $@
VCS_ARC0 =_csrc0.so
VCS_OBJS0 =objs/amcQw_d.o
O0_OBJS =
@ -76,6 +39,12 @@ $(O0_OBJS) : %.o: %.c
%.o: %.c
$(CC_CG) $(CFLAGS_CG) -c -o $@ $<
$(VCS_ARC0) : $(VCS_OBJS0)
$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//$(VCS_ARC0) $(VCS_OBJS0)
rm -f $(VCS_ARC0)
@ln -sf .//../simv.daidir//$(VCS_ARC0) $(VCS_ARC0)
CU_UDP_OBJS = \
@ -83,7 +52,7 @@ CU_LVL_OBJS = \
SIM_l.o
MAIN_OBJS = \
objs/amcQw_d.o
CU_OBJS = $(MAIN_OBJS) $(ARCHIVE_OBJS) $(CU_UDP_OBJS) $(CU_LVL_OBJS)
CU_OBJS = $(MAIN_OBJS) $(ARCHIVE_OBJS) $(VCS_ARC0) $(CU_UDP_OBJS) $(CU_LVL_OBJS)

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8
DA4008_V1.2/sim/chip_top/simv.daidir/.vcs.timestamp
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@ -133,8 +133,8 @@ HSPICE_HOME=/opt/synopsys/hspice/N-2017.12-SP2
HOSTTYPE=x86_64-linux
HISTCONTROL=ignoredups
GROUP=cryo
GNOME_TERMINAL_SERVICE=:1.1458
GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/300489a5_6011_46a1_a329_83b2a6d46428
GNOME_TERMINAL_SERVICE=:1.1513
GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/461a392b_7deb_466e_bdba_86422bb75acb
GNOME_SHELL_SESSION_MODE=classic
GNOME_DESKTOP_SESSION_ID=this-is-deprecated
GENUS_HOME=/opt/cadence/GENUS152
@ -170,7 +170,7 @@ AMS_ENABLE_NOISE=YES
1773384753 ./../../rtl/define/../define/chip_undefine.v
1773384753 ./../../rtl/define/../define/chip_define.v
1773384753 ../../rtl/define/chip_undefine.v
1773384753 ../../sim/chip_top/TB.sv
1773479827 ../../sim/chip_top/TB.sv
1773384753 ../../model/DW_pulse_sync.v
1773384753 ../../model/DW_sync.v
1773384753 ../../model/DW_reset_sync.v
@ -226,5 +226,5 @@ AMS_ENABLE_NOISE=YES
1551421768 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so
1551421789 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so
1550752033 /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a
1773384887 simv.daidir
1773479969 simv.daidir
-1 partitionlib

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@ -5,5 +5,5 @@ PYTHONPATH=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/pylib27
export PYTHONPATH
LD_LIBRARY_PATH=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib:/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/pylib27
export LD_LIBRARY_PATH
/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/vcsfind_create_index.exe -z "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/./idents_X4vtNx.xml.gz" "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp"
/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/vcsfind_create_index.exe -z "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/./idents_E1cKA4.xml.gz" "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp"
\mv "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.db"

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