diff --git a/DA4008_V1.2/case/config/try/flattop.txt b/DA4008_V1.2/case/config/try/flattop.txt new file mode 100644 index 0000000..59e3d23 --- /dev/null +++ b/DA4008_V1.2/case/config/try/flattop.txt @@ -0,0 +1,71 @@ +00100000 +0000000c +04000002 +800003e8 +04004002 +00200000 +00000100 +04030100 +0b090706 +110f0e0c +17161412 +1d1c1a19 +2422211f +2a282725 +302f2d2c +37353332 +3d3b3a38 +4342403e +4a484645 +504e4d4b +56555351 +5c5b5958 +6361605e +69676664 +6f6e6c6b +76747271 +7c7a7977 +82817f7d +89878584 +8f8d8c8a +95949290 +9b9a9897 +a2a09f9d +a8a6a5a3 +aeadabaa +b5b3b1b0 +bbb9b8b6 +c1c0bebc +c8c6c4c3 +c3c4c6c8 +bcbec0c1 +b6b8b9bb +b0b1b3b5 +aaabadae +a3a5a6a8 +9d9fa0a2 +97989a9b +90929495 +8a8c8d8f +84858789 +7d7f8182 +77797a7c +71727476 +6b6c6e6f +64666769 +5e606163 +58595b5c +51535556 +4b4d4e50 +4546484a +3e404243 +383a3b3d +32333537 +2c2d2f30 +2527282a +1f212224 +191a1c1d +12141617 +0c0e0f11 +0607090b +00010304 diff --git a/DA4008_V1.2/case/config/try/sine_1g.txt b/DA4008_V1.2/case/config/try/sine_1g.txt new file mode 100644 index 0000000..a3d68dc --- /dev/null +++ b/DA4008_V1.2/case/config/try/sine_1g.txt @@ -0,0 +1,261 @@ +00100000 +00000004 +0c000010 +00200000 +00000400 +b9a79380 +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c80 +0e192635 +02010207 +26190e07 +6c584635 +b9a7937f +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c80 +0e192635 +02010207 +26190e07 +6c584635 +b9a7937f +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c80 +0e192635 +02010207 +26190e07 +6c584635 +b9a7937f +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c80 +0e192635 +02010207 +26190e07 +6c584635 +b9a7937f +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c80 +0e192635 +02010207 +26190e07 +6c584635 +b9a7937f +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c7f +0e192635 +02010207 +26190e07 +6c584635 +b9a7937f +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c80 +0e192635 +02010207 +26190e07 +6c584635 +b9a7937f +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c80 +0e192635 +02010207 +26190e07 +6c584635 +b9a7937f +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c7f +0e192635 +02010207 +26190e07 +6c584635 +b9a7937f +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c7f +0e192635 +02010207 +26190e07 +6c584635 +b9a7937f +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c7f +0e192635 +02010207 +26190e07 +6c584635 +b9a79380 +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c7f +0e192635 +02010207 +26190e07 +6c584635 +b9a7937f +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c80 +0e192635 +02010207 +26190e07 +6c584635 +b9a7937f +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c80 +0e192635 +02010207 +26190e07 +6c584635 +b9a7937f +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c80 +0e192635 +02010207 +26190e07 +6c584635 +b9a7937f +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c80 +0e192635 +02010207 +26190e07 +6c584635 +b9a7937f +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c80 +0e192635 +02010207 +26190e07 +6c584635 +b9a79380 +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c80 +0e192635 +02010207 +26190e07 +6c584635 +b9a7937f +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c80 +0e192635 +02010207 +26190e07 +6c584635 +b9a79380 +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c80 +0e192635 +02010207 +26190e07 +6c584635 +b9a7937f +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c80 +0e192635 +02010207 +26190e07 +6c584635 +b9a79380 +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c80 +0e192635 +02010207 +26190e07 +6c584635 +b9a79380 +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c80 +0e192635 +02010207 +26190e07 +6c584635 +b9a79380 +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c7f +0e192635 +02010207 +26190e07 +6c584635 +b9a7937f +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c80 +0e192635 +02010207 +26190e07 +6c584635 +b9a7937f +f1e6d9ca +fdfffdf8 +d9e6f1f8 +93a7b9ca +46586c80 diff --git a/DA4008_V1.2/sim/chip_top/case_temp.txt b/DA4008_V1.2/sim/chip_top/case_temp.txt new file mode 100644 index 0000000..227fba4 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/case_temp.txt @@ -0,0 +1,2 @@ + + ../../../../case/config/try//sine_1g.txt diff --git a/DA4008_V1.2/sim/chip_top/compile.log b/DA4008_V1.2/sim/chip_top/compile.log new file mode 100644 index 0000000..32c0b2b --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/compile.log @@ -0,0 +1,16 @@ +Command: vcs -full64 -j8 -sverilog +lint=TFIPC-L +v2k -debug_access+all -debug_region+cell+encrypt \ +-P /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab \ +/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a +define+DUMP_FSDB \ +-lca -q -timescale=1ns/1ps +nospecify -l compile.log -cm line+cond+fsm+tgl+branch \ +-cm_dir ./coverage/simv.vdb -f filelist_vlg.f +incdir+./../../rtl/define +incdir+./../../rtl/qubitmcu \ ++incdir+./../../model + +Warning-[LCA_FEATURES_ENABLED] Usage warning + LCA features enabled by '-lca' argument on the command line. For more + information regarding list of LCA features please refer to Chapter "LCA + features" in the VCS/VCS-MX Release Notes + +The design hasn't changed and need not be recompiled. +If you really want to, delete file simv.daidir/.vcs.timestamp and +run VCS again. + diff --git a/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/.cmoptions b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/.cmoptions new file mode 100644 index 0000000..aa3c928 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/.cmoptions @@ -0,0 +1,16 @@ +Instrument +cond 3 +line 3 +fsm 65539 +tgl 8 +assign 0 +obc 0 +path 0 +branch 3 +Count 0 +Glitch -1 +cm_tglmda 0 +cm_tglstructarr 0 +cm_tglcount 0 +cm_hier 0 +cm_assert_hier 0 \ No newline at end of file diff --git a/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/.mode64 b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/.mode64 new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/.vdb_version b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/.vdb_version new file mode 100644 index 0000000..7239f16 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/.vdb_version @@ -0,0 +1 @@ +O-2018.09-SP2 \ No newline at end of file diff --git a/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/dve_debug.xml b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/dve_debug.xml new file mode 100644 index 0000000..a58895a Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/dve_debug.xml differ diff --git a/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/verilog.instance_parameters.txt b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/verilog.instance_parameters.txt new file mode 100644 index 0000000..075a04e --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/verilog.instance_parameters.txt @@ -0,0 +1,11 @@ +TB.U_da4008_chip_top.digital_top.pulse_inst_sync.SM_IDLE0 +TB.U_da4008_chip_top.digital_top.pulse_inst_sync.SM_WAIT1 +TB.U_da4008_chip_top.digital_top.pulse_inst_sync.SM_WORK2 +TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.IDLE0 +TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.READ3 +TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.RECVCMD1 +TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.WRITE2 +TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.CMD1 +TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.HOLD3 +TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.IDLE0 +TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.WAVE2 diff --git a/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/verilog.sourceinfo.xml b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/verilog.sourceinfo.xml new file mode 100644 index 0000000..e3bb612 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/verilog.sourceinfo.xml @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/design/verilog.design.xml b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/design/verilog.design.xml new file mode 100644 index 0000000..96ef762 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/design/verilog.design.xml differ diff --git a/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/shape/branch.verilog.shape.xml b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/shape/branch.verilog.shape.xml new file mode 100644 index 0000000..eaf10e2 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/shape/branch.verilog.shape.xml differ diff --git a/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/shape/cond.verilog.exclude.xml b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/shape/cond.verilog.exclude.xml new file mode 100644 index 0000000..871fb0a Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/shape/cond.verilog.exclude.xml differ diff --git a/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/shape/cond.verilog.shape.xml b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/shape/cond.verilog.shape.xml new file mode 100644 index 0000000..0b5bb60 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/shape/cond.verilog.shape.xml differ diff --git a/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.exclude.xml b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.exclude.xml new file mode 100644 index 0000000..871fb0a Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.exclude.xml differ diff --git a/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.generated_config.txt b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.generated_config.txt new file mode 100644 index 0000000..d68fe22 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.generated_config.txt @@ -0,0 +1,132 @@ +// Synopsys, Inc. +// User: shbyang +// Date: Fri Mar 13 14:54:44 2026 + +// ================================================================================================== +// This config file prototype is produced from the last run using the complete list of extracted fsms. +// Please note that by providing your own description of the module you are enforcing what will be +// extracted for that module. +// Copy this file to your source directory and edit it as described below, +// then pass the file to VCS using the -cm_fsmcfg command line option. +// FSMs will be extracted normally for any module not mentioned in this file +// ================================================================================================== +// 1. For every module that you want to specify yourself, use: +// MODULE==name +// ----------------------------------------------------- +// The following options are defining the behavior on the module level. +// ----------------------------------------------------- +// 1.1 You can control what fsms should be used within this module: +// FSMS=AUTO +// this means that you want VCS to automatically extract all +// detectable FSMs from this module. +// ----------------------------------------------------- +// FSMS=EXCLUDE +// this means that you want all fsms except the ones from the list that follows +// if the list is empty, all fsms will be extracted for this module +// ----------------------------------------------------- +// FSMS=RESTRICT +// this means that you want only the fsms from the list that follows +// if the list is empty, no fsms will be extracted for this module +// ----------------------------------------------------- +// If none of these options are specified, the program will assume FSMS=RESTRICT +// ----------------------------------------------------- +// 1.2 You can specify that the state with the minimal value should be used as a +// start state for all sequences in every fsm in the module. +// FSMS=START_STATE_DFLT +// For any particular fsm you can overwrite this behavior inside its description. +// ----------------------------------------------------- +// 2. Each fsm description in the list of fsms should be specified as follows: +// 2.1 provide the current state variable declaration: +// CURRENT= name of the current state variable +// ----------------------------------------------------- +// 2.2 if next state variable is different from the current state provide: +// NEXT= next state variable +// if you don't use NEXT=, the program will assume that CURRENT and NEXT are the same +// ----------------------------------------------------- +// 2.3 if you want to provide the restrictive the list of states, provide: +// STATES= s0,s1 etc. where s0 is either a name or a value of the state +// if you don't use STATES=, the program will assume that you want to use all states +// ----------------------------------------------------- +// 2.4 if you want to ignore some states, specify them in the following list: +// STATES_X= s0,s1, etc. +// ----------------------------------------------------- +// 2.5 if you want to mark, that some states should never be reached, specify them as a list: +// STATES_NEVER= s0,s1, etc. +// ----------------------------------------------------- +// 2.6 similar to the STATES, if you want to provide the restrictive the list of transitions, specify: +// TRANSITIONS= s0->s1,s1->s2, etc. +// ----------------------------------------------------- +// 2.7 similar to the STATES_X, if you want to ignore some transitions, specify them in the following list: +// TRANSITIONS_X= s0->s1,s1->s2, etc. +// ----------------------------------------------------- +// 2.8 similar to the STATES_NEVER,if you want to mark, that some transitions should never occur, +// specify them as a list: +// TRANSITIONS_NEVER= s0->s1,s1->s2, etc. +// ----------------------------------------------------- +// 2.9 if you want to specify the start state use: +// START_STATE= s0 +// ----------------------------------------------------- +// Please note: +// - that a state in every list can be specified either by name or by value. +// - in specifying the transitions you can use * in order to refer to 'any' state. +// ================================================================================================== +// Uncomment and modify the following 2 line to override default FSM sequence limits for all FSMs in the design. +//SEQ_NUMBER_MAX=10000 +//SEQ_LENGTH_MAX=32 + +MODULE=pulse_generator +CURRENT=current_state +NEXT=current_state +STATES=SM_IDLE,SM_WAIT,SM_WORK +TRANSITIONS=SM_IDLE->SM_WAIT, +SM_WAIT->SM_IDLE, +SM_WAIT->SM_WORK, +SM_WORK->SM_IDLE +MODULE=spi_sys +CURRENT=state_c +NEXT=qout +STATES=IDLE,READ,RECVCMD,WRITE +TRANSITIONS=IDLE->RECVCMD, +READ->IDLE, +RECVCMD->IDLE, +RECVCMD->READ, +RECVCMD->WRITE, +WRITE->IDLE +MODULE=awg_ctrl +CURRENT=state_c +NEXT=qout +STATES=CMD,HOLD,IDLE,WAVE +TRANSITIONS=CMD->HOLD, +CMD->WAVE, +HOLD->IDLE, +HOLD->WAVE, +IDLE->CMD, +WAVE->HOLD, +WAVE->IDLE +MODULE=ulink_rx_train +CURRENT=state_c +NEXT=qout +STATES=SM_DOWN,SM_EXIT,SM_MATCH,SM_READY +TRANSITIONS=SM_DOWN->SM_MATCH, +SM_EXIT->SM_DOWN, +SM_EXIT->SM_READY, +SM_MATCH->SM_DOWN, +SM_MATCH->SM_EXIT, +SM_READY->SM_DOWN +MODULE=ulink_frame_receiver +CURRENT=word_state_c +NEXT=qout +STATES=S_IDLE,S_WORD0,S_WORD1,S_WORD2,S_WORD3 +TRANSITIONS=S_IDLE->S_WORD0, +S_WORD0->S_WORD1, +S_WORD1->S_WORD2, +S_WORD2->S_WORD3, +S_WORD3->S_IDLE +MODULE=ulink_frame_receiver +CURRENT=state_c +NEXT=qout +STATES=ST_CRC,ST_DATA,ST_HEAD,ST_IDLE +TRANSITIONS=ST_CRC->ST_IDLE, +ST_DATA->ST_CRC, +ST_HEAD->ST_DATA, +ST_IDLE->ST_HEAD diff --git a/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.shape.xml b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.shape.xml new file mode 100644 index 0000000..19fc93c --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.shape.xml @@ -0,0 +1,129 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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b/DA4008_V1.2/sim/chip_top/coverage/try.vdb/snps/coverage/db/testdata/sine_1g/tgl.verilog.data.xml new file mode 100644 index 0000000..72f63ad Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/coverage/try.vdb/snps/coverage/db/testdata/sine_1g/tgl.verilog.data.xml differ diff --git a/DA4008_V1.2/sim/chip_top/csrc/Makefile b/DA4008_V1.2/sim/chip_top/csrc/Makefile new file mode 100644 index 0000000..4dd7912 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/csrc/Makefile @@ -0,0 +1,116 @@ +# Makefile generated by VCS to build your model +# This file may be modified; VCS will not overwrite it unless -Mupdate is used + +# define default verilog source directory +VSRC=.. + +# Override TARGET_ARCH +TARGET_ARCH= + +# Choose name of executable +PRODUCTBASE=$(VSRC)/simv + +PRODUCT=$(PRODUCTBASE) + +# Product timestamp file. If product is newer than this one, +# we will also re-link the product. +PRODUCT_TIMESTAMP=product_timestamp + +# Path to runtime library +DEPLIBS= +VCSUCLI=-lvcsucli +RUNTIME=-lvcsnew -lsimprofile -lreader_common /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libBA.a -luclinative /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcs_tls.o $(DEPLIBS) + +VCS_SAVE_RESTORE_OBJ=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o + +# Select your favorite compiler + +# Linux: +VCS_CC=gcc + +# Internal CC for gen_c flow: +CC_CG=gcc +# User overrode default CC: +VCS_CC=gcc +# Loader +LD=g++ + +# Strip Flags for target product +STRIPFLAGS= + +PRE_LDFLAGS= # Loader Flags +LDFLAGS= -rdynamic -Wl,-rpath=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib -L/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib +# Picarchive Flags +PICLDFLAGS=-Wl,-rpath-link=./ -Wl,-rpath='$$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$$ORIGIN'/simv.daidir//scsim.db.dir + +# C run time startup +CRT0= +# C run time startup +CRTN= +# Machine specific libraries +SYSLIBS=/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lm -lc -lpthread -ldl + +# Default defines +SHELL=/bin/sh + +VCSTMPSPECARG= +VCSTMPSPECENV= +# NOTE: if you have little space in $TMPDIR, but plenty in /foo, +#and you are using gcc, uncomment the next line +#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo + +TMPSPECARG=$(VCSTMPSPECARG) +TMPSPECENV=$(VCSTMPSPECENV) +CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG) + +# C flags for compilation +CFLAGS=-w -pipe -fPIC -O -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include + +CFLAGS_O0=-w -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include -O0 -fno-strict-aliasing + +CFLAGS_CG=-w -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include -O -fno-strict-aliasing + +LD_PARTIAL_LOADER=ld +# Partial linking +LD_PARTIAL=$(LD_PARTIAL_LOADER) -r -o +ASFLAGS= +LIBS=-lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a +# Note: if make gives you errors about include, either get gmake, or +# replace the following line with the contents of the file filelist, +# EACH TIME IT CHANGES +# included file defines OBJS, and is automatically generated by vcs +include filelist + +OBJS=$(VLOG_OBJS) $(SYSC_OBJS) $(VHDL_OBJS) + +product : $(PRODUCT_TIMESTAMP) + @echo $(PRODUCT) up to date + +objects : $(OBJS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) + +clean : + rm -f $(VCS_OBJS) $(CU_OBJS) + +clobber : clean + rm -f $(PRODUCT) $(PRODUCT_TIMESTAMP) + +picclean : + @rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so + @rm -f $(PRODUCT).daidir/_[0-9]*_archive_*.so 2>/dev/null + +product_clean_order : + @$(MAKE) -f Makefile --no-print-directory picclean + @$(MAKE) -f Makefile --no-print-directory product_order + +product_order : $(PRODUCT) + +$(PRODUCT_TIMESTAMP) : product_clean_order + @-if [ -x $(PRODUCT) ]; then chmod -x $(PRODUCT); fi + @$(LD) $(CRT0) -o $(PRODUCT) $(PRE_LDFLAGS) $(STRIPFLAGS) $(PCLDFLAGS) $(PICLDFLAGS) $(LDFLAGS) $(OBJS) $(LIBS) $(RUNTIME) -Wl,-whole-archive $(VCSUCLI) -Wl,-no-whole-archive $(LINK_TB) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(VCS_SAVE_RESTORE_OBJ) $(SYSLIBS) $(CRTN) + @rm -f csrc[0-9]*.o + @touch $(PRODUCT_TIMESTAMP) + @-if [ -d ./objs ]; then find ./objs -type d -empty -delete; fi + +$(PRODUCT) : $(LD_VERSION_CHECK) $(OBJS) $(DOTLIBS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(CMODLIB) /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvcsnew.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsimprofile.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libreader_common.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libBA.a /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libuclinative.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcs_tls.o /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvcsucli.so $(VCS_SAVE_RESTORE_OBJ) + @touch $(PRODUCT) + diff --git a/DA4008_V1.2/sim/chip_top/csrc/Makefile.hsopt b/DA4008_V1.2/sim/chip_top/csrc/Makefile.hsopt new file mode 100644 index 0000000..dcb7127 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/csrc/Makefile.hsopt @@ -0,0 +1,47 @@ +# Makefile generated by VCS to build rmapats.so for your model +VSRC=.. + +# Override TARGET_ARCH +TARGET_ARCH= + +# Select your favorite compiler + +# Linux: +VCS_CC=gcc + +# Internal CC for gen_c flow: +CC_CG=gcc + +# User overrode default CC: +VCS_CC=gcc +# Loader +LD=g++ +# Loader Flags +LDFLAGS= + +# Default defines +SHELL=/bin/sh + +VCSTMPSPECARG= +VCSTMPSPECENV= +# NOTE: if you have little space in $TMPDIR, but plenty in /foo, +#and you are using gcc, uncomment the next line +#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo + +TMPSPECARG=$(VCSTMPSPECARG) +TMPSPECENV=$(VCSTMPSPECENV) +CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG) + +# C flags for compilation +CFLAGS=-w -pipe -fPIC -O -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include + +CFLAGS_CG=-w -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include -O -fno-strict-aliasing + +ASFLAGS= +LIBS= + +include filelist.hsopt + + +rmapats.so: $(HSOPT_OBJS) + @$(VCS_CC) $(LDFLAGS) $(LIBS) -shared -o ./../simv.daidir/rmapats.so $(HSOPT_OBJS) diff --git a/DA4008_V1.2/sim/chip_top/csrc/SIM_l.o b/DA4008_V1.2/sim/chip_top/csrc/SIM_l.o new file mode 100644 index 0000000..8fd683e Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/csrc/SIM_l.o differ diff --git a/DA4008_V1.2/sim/chip_top/csrc/_32553_archive_1.so b/DA4008_V1.2/sim/chip_top/csrc/_32553_archive_1.so new file mode 120000 index 0000000..b828283 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/csrc/_32553_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_32553_archive_1.so \ No newline at end of file diff --git a/DA4008_V1.2/sim/chip_top/csrc/_32573_archive_1.so b/DA4008_V1.2/sim/chip_top/csrc/_32573_archive_1.so new file mode 120000 index 0000000..d21a2a4 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/csrc/_32573_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_32573_archive_1.so \ No newline at end of file diff --git a/DA4008_V1.2/sim/chip_top/csrc/_32574_archive_1.so b/DA4008_V1.2/sim/chip_top/csrc/_32574_archive_1.so new file mode 120000 index 0000000..fb39da5 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/csrc/_32574_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_32574_archive_1.so \ No newline at end of file diff --git a/DA4008_V1.2/sim/chip_top/csrc/_32575_archive_1.so b/DA4008_V1.2/sim/chip_top/csrc/_32575_archive_1.so new file mode 120000 index 0000000..bc1dea6 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/csrc/_32575_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_32575_archive_1.so \ No newline at end of file diff --git a/DA4008_V1.2/sim/chip_top/csrc/_32576_archive_1.so b/DA4008_V1.2/sim/chip_top/csrc/_32576_archive_1.so new file mode 120000 index 0000000..eb06837 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/csrc/_32576_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_32576_archive_1.so \ No newline at end of file diff --git a/DA4008_V1.2/sim/chip_top/csrc/_32577_archive_1.so b/DA4008_V1.2/sim/chip_top/csrc/_32577_archive_1.so new file mode 120000 index 0000000..140ec21 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/csrc/_32577_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_32577_archive_1.so \ No newline at end of file diff --git a/DA4008_V1.2/sim/chip_top/csrc/_32578_archive_1.so b/DA4008_V1.2/sim/chip_top/csrc/_32578_archive_1.so new file mode 120000 index 0000000..9089074 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/csrc/_32578_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_32578_archive_1.so \ No newline at end of file diff --git a/DA4008_V1.2/sim/chip_top/csrc/_32579_archive_1.so b/DA4008_V1.2/sim/chip_top/csrc/_32579_archive_1.so new file mode 120000 index 0000000..7ffb732 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/csrc/_32579_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_32579_archive_1.so \ No newline at end of file diff --git a/DA4008_V1.2/sim/chip_top/csrc/_vcs_pli_stub_.c b/DA4008_V1.2/sim/chip_top/csrc/_vcs_pli_stub_.c new file mode 100644 index 0000000..e4d8eaa --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/csrc/_vcs_pli_stub_.c @@ -0,0 +1,964 @@ +#ifndef _GNU_SOURCE +#define _GNU_SOURCE +#endif +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern void* VCS_dlsymLookup(const char *); +extern void vcsMsgReportNoSource1(const char *, const char*); + +/* PLI routine: $fsdbDumpvars:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvars +#define __VCS_PLI_STUB_novas_call_fsdbDumpvars +extern void novas_call_fsdbDumpvars(int data, int reason); +#pragma weak novas_call_fsdbDumpvars +void novas_call_fsdbDumpvars(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvars"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvars"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvars"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvars)(int data, int reason) = novas_call_fsdbDumpvars; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvars */ + +/* PLI routine: $fsdbDumpvars:misc */ +#ifndef __VCS_PLI_STUB_novas_misc +#define __VCS_PLI_STUB_novas_misc +extern void novas_misc(int data, int reason, int iparam ); +#pragma weak novas_misc +void novas_misc(int data, int reason, int iparam ) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason, int iparam ) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) dlsym(RTLD_NEXT, "novas_misc"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) VCS_dlsymLookup("novas_misc"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason, iparam ); + } +} +void (*__vcs_pli_dummy_reference_novas_misc)(int data, int reason, int iparam ) = novas_misc; +#endif /* __VCS_PLI_STUB_novas_misc */ + +/* PLI routine: $fsdbDumpvarsByFile:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile +#define __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile +extern void novas_call_fsdbDumpvarsByFile(int data, int reason); +#pragma weak novas_call_fsdbDumpvarsByFile +void novas_call_fsdbDumpvarsByFile(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvarsByFile"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvarsByFile"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvarsByFile"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvarsByFile)(int data, int reason) = novas_call_fsdbDumpvarsByFile; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile */ + +/* PLI routine: $fsdbAddRuntimeSignal:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal +#define __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal +extern void novas_call_fsdbAddRuntimeSignal(int data, int reason); +#pragma weak novas_call_fsdbAddRuntimeSignal +void novas_call_fsdbAddRuntimeSignal(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbAddRuntimeSignal"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbAddRuntimeSignal"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbAddRuntimeSignal"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbAddRuntimeSignal)(int data, int reason) = novas_call_fsdbAddRuntimeSignal; +#endif /* __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal */ + +/* PLI routine: $sps_create_transaction_stream:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_create_transaction_stream +#define __VCS_PLI_STUB_novas_call_sps_create_transaction_stream +extern void novas_call_sps_create_transaction_stream(int data, int reason); +#pragma weak novas_call_sps_create_transaction_stream +void novas_call_sps_create_transaction_stream(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_create_transaction_stream"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_create_transaction_stream"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_create_transaction_stream"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_create_transaction_stream)(int data, int reason) = novas_call_sps_create_transaction_stream; +#endif /* __VCS_PLI_STUB_novas_call_sps_create_transaction_stream */ + +/* PLI routine: $sps_begin_transaction:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_begin_transaction +#define __VCS_PLI_STUB_novas_call_sps_begin_transaction +extern void novas_call_sps_begin_transaction(int data, int reason); +#pragma weak novas_call_sps_begin_transaction +void novas_call_sps_begin_transaction(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_begin_transaction"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_begin_transaction"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_begin_transaction"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_begin_transaction)(int data, int reason) = novas_call_sps_begin_transaction; +#endif /* __VCS_PLI_STUB_novas_call_sps_begin_transaction */ + +/* PLI routine: $sps_end_transaction:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_end_transaction +#define __VCS_PLI_STUB_novas_call_sps_end_transaction +extern void novas_call_sps_end_transaction(int data, int reason); +#pragma weak novas_call_sps_end_transaction +void novas_call_sps_end_transaction(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_end_transaction"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_end_transaction"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_end_transaction"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_end_transaction)(int data, int reason) = novas_call_sps_end_transaction; +#endif /* __VCS_PLI_STUB_novas_call_sps_end_transaction */ + +/* PLI routine: $sps_free_transaction:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_free_transaction +#define __VCS_PLI_STUB_novas_call_sps_free_transaction +extern void novas_call_sps_free_transaction(int data, int reason); +#pragma weak novas_call_sps_free_transaction +void novas_call_sps_free_transaction(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_free_transaction"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_free_transaction"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_free_transaction"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_free_transaction)(int data, int reason) = novas_call_sps_free_transaction; +#endif /* __VCS_PLI_STUB_novas_call_sps_free_transaction */ + +/* PLI routine: $sps_add_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_add_attribute +#define __VCS_PLI_STUB_novas_call_sps_add_attribute +extern void novas_call_sps_add_attribute(int data, int reason); +#pragma weak novas_call_sps_add_attribute +void novas_call_sps_add_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_add_attribute)(int data, int reason) = novas_call_sps_add_attribute; +#endif /* __VCS_PLI_STUB_novas_call_sps_add_attribute */ + +/* PLI routine: $sps_update_label:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_update_label +#define __VCS_PLI_STUB_novas_call_sps_update_label +extern void novas_call_sps_update_label(int data, int reason); +#pragma weak novas_call_sps_update_label +void novas_call_sps_update_label(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_update_label"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_update_label"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_update_label"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_update_label)(int data, int reason) = novas_call_sps_update_label; +#endif /* __VCS_PLI_STUB_novas_call_sps_update_label */ + +/* PLI routine: $sps_add_relation:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_add_relation +#define __VCS_PLI_STUB_novas_call_sps_add_relation +extern void novas_call_sps_add_relation(int data, int reason); +#pragma weak novas_call_sps_add_relation +void novas_call_sps_add_relation(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_relation"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_relation"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_relation"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_add_relation)(int data, int reason) = novas_call_sps_add_relation; +#endif /* __VCS_PLI_STUB_novas_call_sps_add_relation */ + +/* PLI routine: $fsdbWhatif:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbWhatif +#define __VCS_PLI_STUB_novas_call_fsdbWhatif +extern void novas_call_fsdbWhatif(int data, int reason); +#pragma weak novas_call_fsdbWhatif +void novas_call_fsdbWhatif(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbWhatif"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbWhatif"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbWhatif"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbWhatif)(int data, int reason) = novas_call_fsdbWhatif; +#endif /* __VCS_PLI_STUB_novas_call_fsdbWhatif */ + +/* PLI routine: $paa_init:call */ +#ifndef __VCS_PLI_STUB_novas_call_paa_init +#define __VCS_PLI_STUB_novas_call_paa_init +extern void novas_call_paa_init(int data, int reason); +#pragma weak novas_call_paa_init +void novas_call_paa_init(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_init"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_init"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_init"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_paa_init)(int data, int reason) = novas_call_paa_init; +#endif /* __VCS_PLI_STUB_novas_call_paa_init */ + +/* PLI routine: $paa_sync:call */ +#ifndef __VCS_PLI_STUB_novas_call_paa_sync +#define __VCS_PLI_STUB_novas_call_paa_sync +extern void novas_call_paa_sync(int data, int reason); +#pragma weak novas_call_paa_sync +void novas_call_paa_sync(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_sync"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_sync"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_sync"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_paa_sync)(int data, int reason) = novas_call_paa_sync; +#endif /* __VCS_PLI_STUB_novas_call_paa_sync */ + +/* PLI routine: $fsdbDumpClassMethod:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod +#define __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod +extern void novas_call_fsdbDumpClassMethod(int data, int reason); +#pragma weak novas_call_fsdbDumpClassMethod +void novas_call_fsdbDumpClassMethod(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassMethod"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassMethod"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassMethod"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassMethod)(int data, int reason) = novas_call_fsdbDumpClassMethod; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod */ + +/* PLI routine: $fsdbSuppressClassMethod:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod +#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod +extern void novas_call_fsdbSuppressClassMethod(int data, int reason); +#pragma weak novas_call_fsdbSuppressClassMethod +void novas_call_fsdbSuppressClassMethod(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassMethod"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassMethod"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassMethod"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassMethod)(int data, int reason) = novas_call_fsdbSuppressClassMethod; +#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod */ + +/* PLI routine: $fsdbSuppressClassProp:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp +#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp +extern void novas_call_fsdbSuppressClassProp(int data, int reason); +#pragma weak novas_call_fsdbSuppressClassProp +void novas_call_fsdbSuppressClassProp(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassProp"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassProp"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassProp"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassProp)(int data, int reason) = novas_call_fsdbSuppressClassProp; +#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp */ + +/* PLI routine: $fsdbDumpMDAByFile:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile +#define __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile +extern void novas_call_fsdbDumpMDAByFile(int data, int reason); +#pragma weak novas_call_fsdbDumpMDAByFile +void novas_call_fsdbDumpMDAByFile(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpMDAByFile"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpMDAByFile"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpMDAByFile"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpMDAByFile)(int data, int reason) = novas_call_fsdbDumpMDAByFile; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile */ + +/* PLI routine: $fsdbTrans_create_stream_begin:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin +#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin +extern void novas_call_fsdbEvent_create_stream_begin(int data, int reason); +#pragma weak novas_call_fsdbEvent_create_stream_begin +void novas_call_fsdbEvent_create_stream_begin(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_begin"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_begin"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_begin"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_begin)(int data, int reason) = novas_call_fsdbEvent_create_stream_begin; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin */ + +/* PLI routine: $fsdbTrans_define_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute +extern void novas_call_fsdbEvent_add_stream_attribute(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_stream_attribute +void novas_call_fsdbEvent_add_stream_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_stream_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_stream_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_stream_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_stream_attribute)(int data, int reason) = novas_call_fsdbEvent_add_stream_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute */ + +/* PLI routine: $fsdbTrans_create_stream_end:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end +#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end +extern void novas_call_fsdbEvent_create_stream_end(int data, int reason); +#pragma weak novas_call_fsdbEvent_create_stream_end +void novas_call_fsdbEvent_create_stream_end(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_end"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_end"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_end"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_end)(int data, int reason) = novas_call_fsdbEvent_create_stream_end; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end */ + +/* PLI routine: $fsdbTrans_begin:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_begin +#define __VCS_PLI_STUB_novas_call_fsdbEvent_begin +extern void novas_call_fsdbEvent_begin(int data, int reason); +#pragma weak novas_call_fsdbEvent_begin +void novas_call_fsdbEvent_begin(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_begin"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_begin"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_begin"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_begin)(int data, int reason) = novas_call_fsdbEvent_begin; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_begin */ + +/* PLI routine: $fsdbTrans_set_label:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_set_label +#define __VCS_PLI_STUB_novas_call_fsdbEvent_set_label +extern void novas_call_fsdbEvent_set_label(int data, int reason); +#pragma weak novas_call_fsdbEvent_set_label +void novas_call_fsdbEvent_set_label(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_set_label"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_set_label"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_set_label"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_set_label)(int data, int reason) = novas_call_fsdbEvent_set_label; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_set_label */ + +/* PLI routine: $fsdbTrans_add_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute +extern void novas_call_fsdbEvent_add_attribute(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_attribute +void novas_call_fsdbEvent_add_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_attribute)(int data, int reason) = novas_call_fsdbEvent_add_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute */ + +/* PLI routine: $fsdbTrans_add_tag:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag +extern void novas_call_fsdbEvent_add_tag(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_tag +void novas_call_fsdbEvent_add_tag(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_tag"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_tag"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_tag"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_tag)(int data, int reason) = novas_call_fsdbEvent_add_tag; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag */ + +/* PLI routine: $fsdbTrans_end:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_end +#define __VCS_PLI_STUB_novas_call_fsdbEvent_end +extern void novas_call_fsdbEvent_end(int data, int reason); +#pragma weak novas_call_fsdbEvent_end +void novas_call_fsdbEvent_end(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_end"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_end"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_end"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_end)(int data, int reason) = novas_call_fsdbEvent_end; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_end */ + +/* PLI routine: $fsdbTrans_add_relation:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation +extern void novas_call_fsdbEvent_add_relation(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_relation +void novas_call_fsdbEvent_add_relation(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_relation"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_relation"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_relation"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_relation)(int data, int reason) = novas_call_fsdbEvent_add_relation; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation */ + +/* PLI routine: $fsdbTrans_get_error_code:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code +#define __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code +extern void novas_call_fsdbEvent_get_error_code(int data, int reason); +#pragma weak novas_call_fsdbEvent_get_error_code +void novas_call_fsdbEvent_get_error_code(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_get_error_code"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_get_error_code"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_get_error_code"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_get_error_code)(int data, int reason) = novas_call_fsdbEvent_get_error_code; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code */ + +/* PLI routine: $fsdbTrans_add_stream_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute +#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute +extern void novas_call_fsdbTrans_add_stream_attribute(int data, int reason); +#pragma weak novas_call_fsdbTrans_add_stream_attribute +void novas_call_fsdbTrans_add_stream_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_stream_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_stream_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_stream_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_stream_attribute)(int data, int reason) = novas_call_fsdbTrans_add_stream_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute */ + +/* PLI routine: $fsdbTrans_add_scope_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute +#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute +extern void novas_call_fsdbTrans_add_scope_attribute(int data, int reason); +#pragma weak novas_call_fsdbTrans_add_scope_attribute +void novas_call_fsdbTrans_add_scope_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_scope_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_scope_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_scope_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_scope_attribute)(int data, int reason) = novas_call_fsdbTrans_add_scope_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute */ + +/* PLI routine: $sps_interactive:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_interactive +#define __VCS_PLI_STUB_novas_call_sps_interactive +extern void novas_call_sps_interactive(int data, int reason); +#pragma weak novas_call_sps_interactive +void novas_call_sps_interactive(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_interactive"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_interactive"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_interactive"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_interactive)(int data, int reason) = novas_call_sps_interactive; +#endif /* __VCS_PLI_STUB_novas_call_sps_interactive */ + +/* PLI routine: $sps_test:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_test +#define __VCS_PLI_STUB_novas_call_sps_test +extern void novas_call_sps_test(int data, int reason); +#pragma weak novas_call_sps_test +void novas_call_sps_test(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_test"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_test"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_test"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_test)(int data, int reason) = novas_call_sps_test; +#endif /* __VCS_PLI_STUB_novas_call_sps_test */ + +/* PLI routine: $fsdbDumpClassObject:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObject +#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObject +extern void novas_call_fsdbDumpClassObject(int data, int reason); +#pragma weak novas_call_fsdbDumpClassObject +void novas_call_fsdbDumpClassObject(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObject"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObject"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObject"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObject)(int data, int reason) = novas_call_fsdbDumpClassObject; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObject */ + +/* PLI routine: $fsdbDumpClassObjectByFile:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile +#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile +extern void novas_call_fsdbDumpClassObjectByFile(int data, int reason); +#pragma weak novas_call_fsdbDumpClassObjectByFile +void novas_call_fsdbDumpClassObjectByFile(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObjectByFile"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObjectByFile"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObjectByFile"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObjectByFile)(int data, int reason) = novas_call_fsdbDumpClassObjectByFile; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile */ + +/* PLI routine: $ridbDump:call */ +#ifndef __VCS_PLI_STUB_novas_call_ridbDump +#define __VCS_PLI_STUB_novas_call_ridbDump +extern void novas_call_ridbDump(int data, int reason); +#pragma weak novas_call_ridbDump +void novas_call_ridbDump(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_ridbDump"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_ridbDump"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_ridbDump"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_ridbDump)(int data, int reason) = novas_call_ridbDump; +#endif /* __VCS_PLI_STUB_novas_call_ridbDump */ + +/* PLI routine: $sps_flush_file:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_flush_file +#define __VCS_PLI_STUB_novas_call_sps_flush_file +extern void novas_call_sps_flush_file(int data, int reason); +#pragma weak novas_call_sps_flush_file +void novas_call_sps_flush_file(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_flush_file"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_flush_file"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_flush_file"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_flush_file)(int data, int reason) = novas_call_sps_flush_file; +#endif /* __VCS_PLI_STUB_novas_call_sps_flush_file */ + +/* PLI routine: $fsdbDumpSingle:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpSingle +#define __VCS_PLI_STUB_novas_call_fsdbDumpSingle +extern void novas_call_fsdbDumpSingle(int data, int reason); +#pragma weak novas_call_fsdbDumpSingle +void novas_call_fsdbDumpSingle(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpSingle"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpSingle"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpSingle"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpSingle)(int data, int reason) = novas_call_fsdbDumpSingle; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpSingle */ + +/* PLI routine: $fsdbDumpIO:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpIO +#define __VCS_PLI_STUB_novas_call_fsdbDumpIO +extern void novas_call_fsdbDumpIO(int data, int reason); +#pragma weak novas_call_fsdbDumpIO +void novas_call_fsdbDumpIO(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpIO"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpIO"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpIO"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpIO)(int data, int reason) = novas_call_fsdbDumpIO; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpIO */ + +#ifdef __cplusplus +} +#endif diff --git a/DA4008_V1.2/sim/chip_top/csrc/_vcs_pli_stub_.o b/DA4008_V1.2/sim/chip_top/csrc/_vcs_pli_stub_.o new file mode 100644 index 0000000..7927935 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/csrc/_vcs_pli_stub_.o differ diff --git a/DA4008_V1.2/sim/chip_top/csrc/archive.0/_32553_archive_1.a b/DA4008_V1.2/sim/chip_top/csrc/archive.0/_32553_archive_1.a new file mode 100644 index 0000000..ea52135 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/csrc/archive.0/_32553_archive_1.a differ diff --git a/DA4008_V1.2/sim/chip_top/csrc/archive.0/_32553_archive_1.a.info b/DA4008_V1.2/sim/chip_top/csrc/archive.0/_32553_archive_1.a.info new file mode 100644 index 0000000..b601eec --- /dev/null +++ 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"_vcs_unit__348857874": [ + "_vcs_unit__348857874", + "FgDcH", + "module", + 1 + ], + "PDUW16SDGZ_H_G": [ + "PDUW16SDGZ_H_G", + "iWZrk", + "module", + 40 + ], + "PDXOEDG_V_G": [ + "PDXOEDG_V_G", + "EZF3t", + "module", + 43 + ], + "PENDCAPA_G": [ + "PENDCAPA_G", + "wpYca", + "module", + 45 + ], + "sirv_gnrl_dffl": [ + "sirv_gnrl_dffl", + "BM4bj", + "module", + 127 + ], + "spi_bus_decoder_0000": [ + "spi_bus_decoder_0000", + "qLaCg", + "module", + 142 + ], + "PDDW08DGZ_H_G": [ + "PDDW08DGZ_H_G", + "C0gYT", + "module", + 14 + ], + "std": [ + "std", + "reYIK", + "module", + 2 + ], + "PVDD2ANA_V_G": [ + "PVDD2ANA_V_G", + "J6VbG", + "module", + 81 + ], + "PDUW12SDGZ_V_G": [ + "PDUW12SDGZ_V_G", + "qCQFW", + "module", + 37 + ], + "PDB3A_H_G": [ + "PDB3A_H_G", + "dfLHW", + "module", + 6 + ], + "PVSS1DGZ_H_G": [ + "PVSS1DGZ_H_G", + "Zp1LH", + "module", + 96 + ], + "PRUW16SDGZ_V_G": [ + "PRUW16SDGZ_V_G", + "psjSY", + "module", + 71 + ], + "PRDW16SDGZ_V_G": [ + "PRDW16SDGZ_V_G", + "YRh5I", + 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b/DA4008_V1.2/sim/chip_top/csrc/filelist @@ -0,0 +1,32 @@ + + +AR=ar +DOTLIBS=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libzerosoft_rt_stubs.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvirsim.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/liberrorinf.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a + +# This file is automatically generated by VCS. Any changes you make to it +# will be overwritten the next time VCS is run +VCS_LIBEXT= +XTRN_OBJS= + +DPI_WRAPPER_OBJS = +DPI_STUB_OBJS = +# filelist.dpi will populate DPI_WRAPPER_OBJS and DPI_STUB_OBJS +include filelist.dpi +PLI_STUB_OBJS = +include filelist.pli + +include filelist.hsopt + +include filelist.cu + +VCS_MISC_OBJS= +VCS_INCR_OBJS= + + +AUGDIR= +AUG_LDFLAGS= +SHARED_OBJ_SO= + + + +VLOG_OBJS= $(VCS_OBJS) $(CU_OBJS) $(VCS_ARC0) $(XTRN_OBJS) $(DPI_WRAPPER_OBJS) $(VCS_INCR_OBJS) $(SHARED_OBJ_SO) $(HSOPT_OBJS) diff --git a/DA4008_V1.2/sim/chip_top/csrc/filelist.cu b/DA4008_V1.2/sim/chip_top/csrc/filelist.cu new file mode 100644 index 0000000..6fc6c6f --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/csrc/filelist.cu @@ -0,0 +1,89 @@ +PIC_LD=ld + +ARCHIVE_OBJS= +ARCHIVE_OBJS += _32553_archive_1.so +_32553_archive_1.so : archive.0/_32553_archive_1.a + @$(AR) -s $< + @$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_32553_archive_1.so --whole-archive $< --no-whole-archive + @rm -f $@ + @ln -sf .//../simv.daidir//_32553_archive_1.so $@ + + +ARCHIVE_OBJS += _32573_archive_1.so +_32573_archive_1.so : archive.0/_32573_archive_1.a + @$(AR) -s $< + @$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_32573_archive_1.so --whole-archive $< --no-whole-archive + @rm -f $@ + @ln -sf .//../simv.daidir//_32573_archive_1.so $@ + + +ARCHIVE_OBJS += _32574_archive_1.so +_32574_archive_1.so : archive.0/_32574_archive_1.a + @$(AR) -s $< + @$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_32574_archive_1.so --whole-archive $< --no-whole-archive + @rm -f $@ + @ln -sf .//../simv.daidir//_32574_archive_1.so $@ + + +ARCHIVE_OBJS += _32575_archive_1.so +_32575_archive_1.so : archive.0/_32575_archive_1.a + @$(AR) -s $< + @$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_32575_archive_1.so --whole-archive $< --no-whole-archive + @rm -f $@ + @ln -sf .//../simv.daidir//_32575_archive_1.so $@ + + +ARCHIVE_OBJS += _32576_archive_1.so +_32576_archive_1.so : archive.0/_32576_archive_1.a + @$(AR) -s $< + @$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_32576_archive_1.so --whole-archive $< --no-whole-archive + @rm -f $@ + @ln -sf .//../simv.daidir//_32576_archive_1.so $@ + + +ARCHIVE_OBJS += _32577_archive_1.so +_32577_archive_1.so : archive.0/_32577_archive_1.a + @$(AR) -s $< + @$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_32577_archive_1.so --whole-archive $< --no-whole-archive + @rm -f $@ + @ln -sf .//../simv.daidir//_32577_archive_1.so $@ + + +ARCHIVE_OBJS += _32578_archive_1.so +_32578_archive_1.so : archive.0/_32578_archive_1.a + @$(AR) -s $< + @$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_32578_archive_1.so --whole-archive $< --no-whole-archive + @rm -f $@ + @ln -sf .//../simv.daidir//_32578_archive_1.so $@ + + +ARCHIVE_OBJS += _32579_archive_1.so +_32579_archive_1.so : archive.0/_32579_archive_1.a + @$(AR) -s $< + @$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_32579_archive_1.so --whole-archive $< --no-whole-archive + @rm -f $@ + @ln -sf .//../simv.daidir//_32579_archive_1.so $@ + + + + + +O0_OBJS = + +$(O0_OBJS) : %.o: %.c + $(CC_CG) $(CFLAGS_O0) -c -o $@ $< + + +%.o: %.c + $(CC_CG) $(CFLAGS_CG) -c -o $@ $< +CU_UDP_OBJS = \ + + +CU_LVL_OBJS = \ +SIM_l.o + +MAIN_OBJS = \ +objs/amcQw_d.o + +CU_OBJS = $(MAIN_OBJS) $(ARCHIVE_OBJS) $(CU_UDP_OBJS) $(CU_LVL_OBJS) + diff --git a/DA4008_V1.2/sim/chip_top/csrc/filelist.dpi b/DA4008_V1.2/sim/chip_top/csrc/filelist.dpi new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/csrc/filelist.hsopt b/DA4008_V1.2/sim/chip_top/csrc/filelist.hsopt new file mode 100644 index 0000000..468b268 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/csrc/filelist.hsopt @@ -0,0 +1,13 @@ +rmapats_mop.o: rmapats.m + @/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/cgmop1 -tls_initexe -pic -gen_obj rmapats.m rmapats_mop.o; rm -f rmapats.m; touch rmapats.m; touch rmapats_mop.o + +rmapats.o: rmapats.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmapats.o rmapats.c +rmapats%.o: rmapats%.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $< +rmar.o: rmar.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmar.o rmar.c +rmar%.o: rmar%.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $< + +include filelist.hsopt.objs diff --git a/DA4008_V1.2/sim/chip_top/csrc/filelist.hsopt.llvm2_0.objs b/DA4008_V1.2/sim/chip_top/csrc/filelist.hsopt.llvm2_0.objs new file mode 100644 index 0000000..4c31419 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/csrc/filelist.hsopt.llvm2_0.objs @@ -0,0 +1 @@ +LLVM_OBJS += rmar_llvm_0_1.o rmar_llvm_0_0.o diff --git a/DA4008_V1.2/sim/chip_top/csrc/filelist.hsopt.objs b/DA4008_V1.2/sim/chip_top/csrc/filelist.hsopt.objs new file mode 100644 index 0000000..f40e57c --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/csrc/filelist.hsopt.objs @@ -0,0 +1,7 @@ +HSOPT_OBJS +=rmapats_mop.o \ + rmapats.o \ + rmar.o rmar_nd.o + +include filelist.hsopt.llvm2_0.objs +HSOPT_OBJS += $(LLVM_OBJS) + diff --git a/DA4008_V1.2/sim/chip_top/csrc/filelist.pli b/DA4008_V1.2/sim/chip_top/csrc/filelist.pli new file mode 100644 index 0000000..653944b --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/csrc/filelist.pli @@ -0,0 +1,4 @@ +PLI_STUB_OBJS += _vcs_pli_stub_.o +_vcs_pli_stub_.o: _vcs_pli_stub_.c + @$(CC) -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include -fPIC -c -o _vcs_pli_stub_.o _vcs_pli_stub_.c + @strip -g _vcs_pli_stub_.o diff --git a/DA4008_V1.2/sim/chip_top/csrc/hsim/hsim.sdb b/DA4008_V1.2/sim/chip_top/csrc/hsim/hsim.sdb new file mode 100644 index 0000000..482ee07 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/csrc/hsim/hsim.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/csrc/import_dpic.h b/DA4008_V1.2/sim/chip_top/csrc/import_dpic.h new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/csrc/objs/amcQw_d.o b/DA4008_V1.2/sim/chip_top/csrc/objs/amcQw_d.o new file mode 100644 index 0000000..c8ebb61 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/csrc/objs/amcQw_d.o differ diff --git a/DA4008_V1.2/sim/chip_top/csrc/product_timestamp b/DA4008_V1.2/sim/chip_top/csrc/product_timestamp new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/csrc/rmapats.c b/DA4008_V1.2/sim/chip_top/csrc/rmapats.c new file mode 100644 index 0000000..0c43907 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/csrc/rmapats.c @@ -0,0 +1,43 @@ +// file = 0; split type = patterns; threshold = 100000; total count = 0. +#include +#include +#include +#include "rmapats.h" + +void hsG_0__0 (struct dummyq_struct * I1289, EBLK * I1283, U I685); +void hsG_0__0 (struct dummyq_struct * I1289, EBLK * I1283, U I685) +{ + U I1547; + U I1548; + U I1549; + struct futq * I1550; + struct dummyq_struct * pQ = I1289; + I1547 = ((U )vcs_clocks) + I685; + I1549 = I1547 & ((1 << fHashTableSize) - 1); + I1283->I727 = (EBLK *)(-1); + I1283->I731 = I1547; + if (I1547 < (U )vcs_clocks) { + I1548 = ((U *)&vcs_clocks)[1]; + sched_millenium(pQ, I1283, I1548 + 1, I1547); + } + else if ((peblkFutQ1Head != ((void *)0)) && (I685 == 1)) { + I1283->I733 = (struct eblk *)peblkFutQ1Tail; + peblkFutQ1Tail->I727 = I1283; + peblkFutQ1Tail = I1283; + } + else if ((I1550 = pQ->I1190[I1549].I745)) { + I1283->I733 = (struct eblk *)I1550->I744; + I1550->I744->I727 = (RP )I1283; + I1550->I744 = (RmaEblk *)I1283; + } + else { + sched_hsopt(pQ, I1283, I1547); + } +} +#ifdef __cplusplus +extern "C" { +#endif +void SinitHsimPats(void); +#ifdef __cplusplus +} +#endif diff --git a/DA4008_V1.2/sim/chip_top/csrc/rmapats.h b/DA4008_V1.2/sim/chip_top/csrc/rmapats.h new file mode 100644 index 0000000..6fd37cc --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/csrc/rmapats.h @@ -0,0 +1,2986 @@ +#ifndef __DO_RMAHDR_ +#define __DO_RMAHDR_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define VCS_RTLIB_TLS_MODEL __attribute__((tls_model("initial-exec"))) + +typedef unsigned long UP; +typedef unsigned U; +typedef unsigned char UB; +typedef unsigned char scalar; +typedef struct vec32 vec32; +typedef unsigned short US; +typedef unsigned char SVAL; +typedef unsigned char TYPEB; +typedef struct qird QIRD; +typedef unsigned char UST_e; +typedef unsigned uscope_t; +typedef U NumLibs_t; +struct vec32 { + U I1; + U I2; +}; +typedef unsigned long RP; +typedef unsigned long RO; +typedef unsigned long long ULL; +typedef U GateCount; +typedef U NodeCount; +typedef unsigned short HsimEdge; +typedef unsigned char HsimExprChar; +typedef struct { + U I706; + RP I707; +} RmaReceiveClock1; +typedef NodeCount FlatNodeNum; +typedef U InstNum; +typedef unsigned ProcessNum; +typedef unsigned long long TimeStamp64; +typedef unsigned long long TimeStamp; +typedef enum { + PD_SING = 0, + PD_RF = 1, + PD_PLSE = 2, + PD_PLSE_RF = 3, + PD_NULL = 4 +} PD_e; +typedef TimeStamp RmaTimeStamp; +typedef TimeStamp64 RmaTimeStamp64; +typedef struct { + int * I708; + int * I709; + int I710; + union { + long long enumDesc; + long long classId; + } I711; +} TypeData; +struct etype { + U I586 :8; + U I587; + U I588; + U I589 :1; + U I590 :1; + U I591 :1; + U I592 :1; + U I593 :1; + U I594 :1; + U I595 :1; + U I596 :1; + U I597 :1; + U I598 :4; + U I599 :1; + U I600 :1; + U I601 :1; + U I602 :1; + U I603 :1; + U I604 :1; + U I605 :1; + U I606 :1; + U I607 :2; + U I608 :1; + U I609 :2; + U I610 :1; + U I611 :1; + U I612 :1; + U I613 :1; + U I614 :1; + U I615 :1; + TypeData * I616; + U I617; + U I618; + U I619 :1; + U I620 :1; + U I621 :1; + U I622 :1; + U I623 :2; + U I624 :2; + U I625 :1; + U I626 :1; + U I627 :1; + U I628 :1; + U I629 :1; + U I630 :1; + U I631 :1; + U I632 :1; + U I633 :1; + U I634 :1; + U I635 :1; + U I636 :13; +}; +typedef union { + double I718; + unsigned long long I719; + unsigned I720[2]; +} rma_clock_struct; +typedef struct eblk EBLK; +typedef int (* E_fn)(void); +typedef struct eblk { + struct eblk * I727; + E_fn I728; + struct iptmpl * I729; + unsigned I731; + unsigned I732; + struct eblk * I733; +} eblk_struct; +typedef struct { + RP I727; + RP I728; + RP I729; + unsigned I731; + unsigned I732; + RP I733; +} RmaEblk; +typedef struct { + RP I727; + RP I728; + RP I729; + unsigned I731; + unsigned I732; + RP I733; + unsigned val; +} RmaEblklq; +typedef union { + double I718; + unsigned long long I719; + unsigned I720[2]; +} clock_struct; +typedef clock_struct RmaClockStruct; +typedef struct RmaRetain_t RmaRetain; +struct RmaRetain_t { + RP I769; + RmaEblk I726; + U I771; + US I772 :1; + US I773 :4; + US I181 :2; + US state :2; + US I775 :1; + US I776 :2; + US I777 :2; + US fHsim :1; + US I569 :1; + scalar newval; + scalar I780; + RP I781; +}; +struct retain_t { + struct retain_t * I769; + EBLK I726; + U I771; + US I772 :1; + US I773 :4; + US I181 :2; + US state :2; + US I775 :1; + US I776 :2; + US I777 :2; + US fHsim :1; + US I778 :1; + scalar newval; + scalar I780; + void * I781; +}; +typedef struct MPSched MPS; +typedef struct RmaMPSched RmaMps; +struct MPSched { + MPS * I760; + scalar I761; + scalar I762; + scalar I763; + scalar fHsim :1; + scalar I181 :6; + U I765; + EBLK I766; + void * I767; + UP I768[1]; +}; +struct RmaMPSched { + RP I760; + scalar I761; + scalar I762; + scalar I763; + scalar fHsim :1; + scalar I181 :6; + U I765; + RmaEblk I766; + RP I767; + RP I768[1]; +}; +typedef struct RmaMPSchedPulse RmaMpsp; +struct RmaMPSchedPulse { + RP I760; + scalar I761; + scalar I762; + scalar I763; + scalar I181; + U I765; + RmaEblk I766; + scalar I777; + scalar I786; + scalar I787; + scalar I788; + U I789; + RmaClockStruct I790; + RmaClockStruct I791; + U state; + U I792; + RP I729; + RP I793; + RP I794; + RP I768[1]; +}; +typedef struct MPItem MPI; +struct MPItem { + U * I796; + void * I797; +}; +typedef struct { + RmaEblk I726; + RP I798; + scalar I799; + scalar I777; + scalar I800; +} RmaTransEventHdr; +typedef struct RmaMPSchedPulseNewCsdf RmaMpspNewCsdf; +struct RmaMPSchedPulseNewCsdf { + RP I760; + scalar I761; + scalar I762; + scalar I763; + scalar fHsim :1; + scalar I181 :6; + U I765; + RmaEblk I766; + scalar I777; + scalar I786; + scalar I787; + scalar I788; + U state :4; + U I802 :28; + RmaClockStruct I790; + RmaClockStruct I791; + RP I803; + RP I729; + RP I804; + RP I768[1]; +}; +typedef struct red_t { + U I805; + U I806; + U I685; +} RED; +typedef struct predd { + PD_e I181; + RED I807[0]; +} PREDD; +union rhs_value { + vec32 I808; + scalar I799; + vec32 * I777; + double I809; + U I810; +}; +typedef struct nbs_t { + struct nbs_t * I811; + struct nbs_t * I813; + void (* I814)(struct nbs_t * I781); + U I815 :1; + U I816 :1; + U I817 :1; + U I818 :1; + U I819 :1; + U I820 :1; + U I821 :26; + U I822; + void * I823; + union rhs_value I824; + vec32 I718; + union { + struct nbs_t * first; + struct nbs_t * last; + } I826; +} NBS; +typedef struct { + RP I827; + RP I793; + RP I729; + RP I794; + RmaEblk I726; + RmaEblk I828; + RP I829; + scalar I799; + scalar I777; + char state; + uscope_t I830; + U I831; + RP I832; + scalar I786; + scalar I787; + scalar I788; + RmaClockStruct I790; + RmaClockStruct I791; + RP I767; +} RmaPulse; +typedef enum { + QIRDModuleC = 1, + QIRDSVPackageC = 2, + QIRDSpiceModuleC = 3 +} QIRDModuleType; +typedef struct { + U I836 :1; + U I837 :1; + U I838 :1; + U I839 :1; + U I840 :1; + U I841 :1; + U I842 :1; + U I843 :1; + U I844 :1; + U I845 :1; + U I846 :1; + U I847 :1; + U I848 :1; + U I849 :1; + U I850 :1; + U I851 :1; + U I852 :1; + U I853 :1; + QIRDModuleType I854 :2; + U I855 :1; + U I856 :1; + U I857 :1; + U I858 :1; + U I859 :1; + U I860 :1; + U I861 :1; + U I862 :1; + U I863 :1; + U I864 :1; + U I865 :1; + U I866 :1; + U I867 :1; + U I868 :1; + U I869 :1; + U I870 :1; + U I871 :1; + U I872 :1; + U I873 :1; + U I874 :1; +} BitFlags; +struct qird { + US I4; + US I5; + U I6; + U I7; + char * I8; + char * I9; + U * I10; + char * I11; + char * I12; + U I13; + U I14; + struct vcd_rt * I15; + U I17; + struct _vcdOffset_rt * I18; + U I20; + U I21; + U * I22; + U * I23; + void * I24; + void * I25; + U I26; + int I27; + UP I28; + U I29; + U I30; + U I31; + UP I32; + U * I33; + UP I34; + U I35; + BitFlags I36; + U I37; + U I38; + U I39; + U I40; + U I41; + U * I42; + U I43; + U * I44; + U I45; + U I46; + U I47; + U I48; + U I49; + U I50; + U I51; + U * I52; + U * I53; + U I54; + U I55; + U * I56; + U I57; + U * I58; + U I59; + U I60; + U I61; + U I62; + U * I63; + U I64; + U * I65; + U I66; + U I67; + U I68; + U I69; + U I70; + U I71; + U * I72; + char * I73; + U I74; + U I75; + U I76; + U I77; + U I78; + U * I79; + U I80; + U I81; + U I82; + UP * I83; + U I84; + U I85; + U I86; + U I87; + U I88; + U I89; + U * I90; + U I91; + U I92; + U * I93; + U * I94; + U * I95; + U * I96; + U * I97; + U I98; + U I99; + struct taskInfo * I100; + U I102; + U I103; + U I104; + int * I105; + U * I106; + UP * I107; + U * I108; + U I109; + U I110; + U I111; + U I112; + U I113; + struct qrefer * I114; + U * I116; + unsigned * I117; + void * I118; + U I119; + U I120; + struct classStaticReferData * I121; + U I123; + U * I124; + U I125; + U * I126; + U I127; + struct wakeupInfoStruct * I128; + U I130; + U I131; + U I132; + U * I133; + U I134; + U * I135; + U I136; + U I137; + U I138; + U * I139; + U I140; + U * I141; + U I142; + U I143; + U * I144; + U I145; + U I146; + U * I147; + U * I148; + U * I149; + U I150; + U I151; + U I152; + U I153; + U I154; + struct qrefee * I155; + U * I157; + U I158; + struct qdefrefee * I159; + U * I161; + int (* I162)(void); + char * I163; + U I164; + U I165; + void * I166; + void * I167; + NumLibs_t I168; + char * I169; + U * I170; + U I171; + U I172; + U I173; + U I174; + U I175; + U * I176; + U * I177; + int I178; + struct clock_load * I179; + int I194; + struct clock_data * I195; + int I211; + struct clock_hiconn * I212; + U I216; + U I217; + U I218; + U I219; + U * I220; + U * I221; + U I222; + void * I223; + U I224; + U I225; + UP * I226; + void * I227; + U I228; + UP * I229; + U * I230; + int (* I231)(void); + U * I232; + UP * I233; + U * I234; + U I235 :1; + U I236 :31; + U I237; + U I238; + UP * I239; + U * I240; + U I241 :1; + U I242 :1; + U I243 :1; + U I244 :1; + U I245 :28; + U I246; + U I247; + U I248; + U I249 :31; + U I250 :1; + UP * I251; + UP * I252; + U * I253; + U * I254; + U * I255; + U * I256; + UP * I257; + UP * I258; + UP * I259; + U * I260; + UP * I261; + UP * I262; + UP * I263; + UP * I264; + char * I265; + U I266; + U I267; + U I268; + UP * I269; + U I270; + UP * I271; + UP * I272; + UP * I273; + UP * I274; + UP * I275; + UP * I276; + UP * I277; + UP * I278; + UP * I279; + UP * I280; + UP * I281; + UP * I282; + UP * I283; + UP * I284; + U * I285; + U * I286; + UP * I287; + U I288; + U I289; + U I290; + U I291; + U I292; + U I293; + U I294; + U I295; + char * I296; + U * I297; + U I298; + U I299; + U I300; + U I301; + U I302; + UP * I303; + UP * I304; + UP * I305; + UP * I306; + struct daidirInfo * I307; + struct vcs_tftable * I309; + U I311; + UP * I312; + UP * I313; + U I314; + U I315; + U I316; + UP * I317; + U * I318; + UP * I319; + UP * I320; + struct qird_hil_data * I321; + UP (* I323)(void); + UP (* I324)(void); + UP (* I325)(void); + UP (* I326)(void); + UP (* I327)(void); + int * I328; + int (* I329)(void); + char * I330; + UP * I331; + UP * I332; + UP (* I333)(void); + int (* I334)(void); + int * I335; + int (* I336)(void); + int * I337; + char * I338; + U * I339; + U * I340; + U * I341; + U * I342; + void * I343; + U I344; + void * I345; + U I346; + U I347; + U I348; + U I349; + U I350; + U I351; + char * I352; + UP * I353; + U * I354; + U * I355; + U I356 :15; + U I357 :14; + U I358 :1; + U I359 :1; + U I360 :1; + U I361 :3; + U I362 :1; + U I363 :1; + U I364 :17; + U I365 :3; + U I366 :5; + U I367 :1; + U I368 :1; + U I369; + U I370; + struct scope * I371; + U I373; + U I374; + U I375; + U * I376; + U * I377; + U * I378; + U I379; + U I380; + U I381; + struct pcbt * I382; + U I392; + U I393; + U I394; + U I395; + void * I396; + void * I397; + void * I398; + int I399; + U * I400; + U I401; + U I402; + U I403; + U I404; + U I405; + U I406; + U I407; + void * I408; + UP * I409; + U I410; + U I411; + void * I412; + U I413; + void * I414; + U I415; + void * I416; + U I417; + int (* I418)(void); + int (* I419)(void); + void * I420; + void * I421; + void * I422; + U I423; + U I424; + U I425; + U I426; + U I427; + U I428; + char * I429; + U I430; + U * I431; + U I432; + U * I433; + U I434; + U I435; + U I436; + U I437; + U I438; + U I439; + U * I440; + U I441; + U I442; + U * I443; + U I444; + U I445; + U I446; + U * I447; + char * I448; + U I449; + U I450; + U I451; + U I452; + U * I453; + U * I454; + U I455; + U * I456; + U * I457; + U I458; + U I459; + U I460; + UP * I461; + U I462; + U I463; + U I464; + struct cosim_info * I465; + U I467; + U * I468; + U I469; + void * I470; + U I471; + U * I472; + U I473; + struct hybridSimReferrerData * I474; + U I476; + U * I477; + U I478; + U I479; + U * I480; + U I481; + U * I482; + U I483; + U * I484; + U I485; + U I486; + U I487; + U I488; + U I489; + U I490; + U I491; + U I492; + U I493; + U * I494; + U * I495; + void (* I496)(void); + U * I497; + UP * I498; + struct mhdl_outInfo * I499; + UP * I501; + U I502; + UP * I503; + U I504; + void * I505; + U * I506; + void * I507; + char * I508; + int (* I509)(void); + U * I510; + char * I511; + char * I512; + U I513; + U * I514; + char * I515; + U I516; + struct regInitInfo * I517; + UP * I519; + U * I520; + char * I521; + U I522; + U I523; + U I524; + U I525; + U I526; + U I527; + U I528; + U I529; + UP * I530; + U I531; + U I532; + U I533; + U I534; + UP * I535; + U I536; + UP * I537; + U I538; + U I539; + U I540; + U * I541; + U I542; + U I543; + U I544; + U * I545; + U * I546; + UP * I547; + UP * I548; + void * I549; + UP I550; + void * I551; + void * I552; + void * I553; + void * I554; + void * I555; + UP I556; + U * I557; + U * I558; + void * I559; + U I560 :1; + U I561 :31; + U I562; + U I563; + U I564; + int I565; + U I566 :1; + U I567 :1; + U I568 :1; + U I569 :29; + void * I570; + void * I571; + void * I572; + void * I573; + void * I574; + UP * I575; + U * I576; + U I577; + char * I578; + U * I579; + U * I580; + char * I581; + int * I582; + UP * I583; + struct etype * I584; + U I637; + U I638; + U * I639; + struct etype * I640; + U I641; + U I642; + U I643; + U * I644; + void * I645; + U I646; + U I647; + void * I648; + U I649; + U I650; + U * I651; + U * I652; + char * I653; + U I654; + struct covreg_rt * I655; + U I657; + U I658; + U * I659; + U I660; + U * I661; + U I662; + U I663; + U * I664; +}; +typedef struct pcbt { + U * I384; + UP I385; + U I386; + U I387; + U I388; + U I389; + U I390; + U I391; +} PCBT; +struct iptmpl { + QIRD * I734; + struct vcs_globals_t * I735; + void * I737; + UP I738; + UP I739; + struct iptmpl * I729[2]; +}; +typedef unsigned long long FileOffset; +typedef struct _RmaMultiInputTable { + U I881 :1; + U I882 :1; + U I672 :2; + U I673 :4; + U I674 :5; + U I883 :1; + U I884 :1; + U I885 :1; + U I886 :1; + U I887 :1; + U I888 :1; + U I889; + U I890; + U I203; + U I891; + U I892 :1; + U I893 :31; + union { + U utable; + U edgeInputNum; + } I699; + U I894 :4; + U I895 :4; + U I896 :4; + U I897 :4; + U I898 :4; + U I899 :4; + U I900 :1; + U I901 :1; + U I902 :1; + U I903 :1; + U I904 :5; + HsimExprChar * I905; + UB * I906; + UB * I907; + struct _RmaMultiInputTable * I880; + struct _RmaMultiInputTable * I909; +} RmaMultiInputTable; +typedef struct _HsCgPeriod { + U I955; + U I956; +} HsCgPeriod; +typedef struct { + U I957[2]; + U I958 :1; + U I959 :1; + U I960 :8; + U I961 :8; + U I962 :8; + U I963 :4; + U I964 :1; + U I965 :1; + unsigned long long I966; + unsigned long long I967; + unsigned long long I968; + unsigned long long I969; + unsigned long long I956; + U I955; + U I970; + U I971; + U I972; + U I973; + U I974; + HsCgPeriod * I975[10]; +} HsimSignalMonitor; +typedef struct { + FlatNodeNum I976; + InstNum I977; + U I915; + scalar I978; + UB I979; + UB I980; + UB I981; + UB I982; + UB I983; + UB I984; + U I985; + U I986; + U I987; + U I988; + U I989; + U I990; + U I991; + U I992; + U I993; + HsimSignalMonitor * I994; + RP I995; + RmaTimeStamp64 I996; + U I997; + RmaTimeStamp64 I998; + U I999; + UB I1000; +} HsimNodeRecord; +typedef RP RCICODE; +typedef struct { + RP I1005; + RP I729; +} RmaIbfIp; +typedef struct { + RP I1005; + RP pcode; +} RmaIbfPcode; +typedef struct { + RmaEblk I726; +} RmaEvTriggeredOrSyncLoadCg; +typedef struct { + RO I877; + RP pcode; +} SchedGateFanout; +typedef struct { + RO I877; + RP pcode; + U I936[4]; +} SchedSelectGateFanout; +typedef struct { + RP pcode; + RmaEblklq I726; +} SchedGateEblk; +typedef struct { + RP pcode; + RmaEblklq I726; + UB * I1006; +} SchedSelectGateEblk; +typedef struct { + RP I1007; + RP pfn; + RP pcode; +} RmaSeqPrimOutputEblkData; +typedef struct { + RmaEblk I726; + RP I1008; +} RmaAnySchedSampleSCg; +typedef struct { + RmaEblk I726; + RP I1006; + RP I1008; + vec32 I1009; +} RmaAnySchedVCg; +typedef struct { + RmaEblk I726; + RP I1006; + RP I1008; + vec32 I776[1]; +} RmaAnySchedWCg; +typedef struct { + RmaEblk I726; + RP I1006; + RP I1008; + scalar I1010[1]; +} RmaAnySchedECg; +typedef struct { + U I1011; + U I714; + U I915; + U I1012; + RmaIbfIp * I1013; + EBLK I726; + void * val; +} RmaThreadSchedCompiledLoads; +typedef struct { + U I714; + U I722; + RmaThreadSchedCompiledLoads * I1014; +} RmaSchedCompileLoadsCg; +typedef struct { + RP I1015; +} RmaRootCbkCg; +typedef struct { + RP I1016; +} RmaRootForceCbkCg; +typedef struct { + RmaEblk I726; + RP I1017; +} RmaForceCbkJmpCg; +typedef struct { + U I5; + U I722 :31; + U I1018 :1; + vec32 I808; + U I1019; + RP I1020; + RP I1021; +} RmaForceSelectorV; +typedef struct { + U I5; + RmaIbfPcode I1027; +} RmaNetTypeDriverGate; +typedef struct { + U I5; + U I668; + RmaIbfPcode I1027[1]; +} RmaNetTypeScatterGate; +typedef struct { + U I5; + RmaIbfPcode I1027; +} RmaNetTypeGatherGate; +typedef struct { + RmaIbfPcode I1028; + U I1029 :3; + U I1030 :1; + U I1031 :1; + U I890 :16; +} RmaNbaGateOfn; +typedef struct { + U I5; + NBS I1032; + RmaIbfPcode I1028; +} RmaNbaGate1; +typedef struct { + RP ptable; + RP pfn; + RP pcode; +} Rma1InputGateFaninCgS; +typedef struct RmaSeqPrimOutputS_ RmaSeqPrimOutputOnClkS; +struct RmaSeqPrimOutputS_ { + RP pfn; + RP I1035; + U state; + U I1036; + RP I1037; + U I706; + scalar val; +}; +typedef struct { + U I5; + U iinput; + UB I1039; + RP I1040; +} RmaCondOptLoad; +typedef struct { + U I5; + U iinput; + UB I1039; + RP I1040; +} RmaMacroStateUpdate; +typedef struct { + U I5; + U state; + U I1041; + UB I1039; + U * I1042; +} RmaMacroState; +typedef struct { + U iinput; + RP I1043; +} RmaMultiInputLogicGateCg; +typedef struct { + U iinput; + RP ptable; + RP I1043; +} RmaSeqPrimEdgeInputCg; +typedef struct { + RmaEblk I726; + RP pcode; +} RmaSched0GateCg; +typedef struct { + RmaEblk I726; + RP pcode; + RP pfn; +} RmaUdpDeltaGateCg; +typedef struct { + RmaEblk I726; + RP pcode; + RP pfn; + scalar I1044; +} RmaSchedDeltaGateCg; +typedef struct { + UB I1045; + RP I1046; + RP I1047; +} RmaPropNodeSeqLhsSCg; +typedef struct { + RmaEblk I726; + RP pcode; + U I915; + U I715[1]; +} RmaBitEdgeEblk; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaGateDelay; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaGateBehavioralDelay; +typedef struct { + U I5; + union { + RP I1290; + RP I1578; + RP I1592; + } I781; + RmaIbfPcode I1028; +} RmaMPDelay; +typedef struct { + U I5; + RmaPulse I1048; + RmaIbfPcode I1028; +} RmaMPPulseHybridDelay; +typedef struct { + U I5; + RmaIbfPcode I1028; + RmaMps I1049; +} RmaMPHybridDelay; +typedef struct { + U I5; + U I1050; + RmaIbfPcode I1028; + RmaEblk I766; +} RmaMPHybridDelayPacked; +typedef struct { + U I5; + RmaIbfPcode I1028; + RmaMpspNewCsdf I1051; +} RmaMPPulseDelay; +typedef struct { + U I5; + RmaMpsp I1051; + RmaIbfPcode I1028; +} RmaMPPulseOptHybridDelay; +typedef struct _RmaBehavioralTransportDelay { + U I5; + RP I685; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaBehavioralTransportDelayS; +typedef struct { + U I5; + U I685; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaNtcTransDelay; +typedef struct { + U I5; + U I685; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaNtcTransMpwOptDelay; +typedef struct { + U I5; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaNtcTransZeroDelay; +typedef struct { + U I5; + U I1052; + U I1053; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaNtcTransDelayRF; +typedef struct { + U I5; + U I1052; + U I1053; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaNtcTransMpwOptDelayRF; +typedef struct { + U I5; + RP I1054; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaICTransDelay; +typedef struct { + U I5; + RP I1054; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaICTransMpwOptDelay; +typedef struct { + U I5; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaICTransZeroDelay; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaICSimpleDelay; +typedef struct { + U I5; + union { + RP psimple; + RP I1578; + RP I1592; + } I781; + RmaIbfPcode I1028; +} RmaICDelay; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaPortDelay; +typedef struct { + U I890; + RP I1058; +} RmaRtlXEdgesLoad; +typedef struct { + U I5; + RmaRtlXEdgesLoad I1058[(5)]; +} RmaRtlXEdgesHdr; +typedef struct { + U I5; + US I1059; + US I1060 :1; + US I904 :15; + RP I1061; + RP I1062; + RP I1063; +} RmaRtlEdgeBlockHdr; +typedef struct { + RP I1064; + RP I1065; +} RemoteDbsedLoad; +typedef struct { + RmaEblk I726; + RP I1066; + RP I1067; + U I1068 :16; + U I1069 :2; + U I1070 :2; + U I1071 :1; + U I1072 :8; + U I904 :3; + U I471; + RP I1073; + RP I811[(5)]; + RP I813[(5)]; + US I1074; + US I1075; + RemoteDbsedLoad I1076[1]; +} RmaRtlEdgeBlock; +typedef struct TableAssign_ { + struct TableAssign_ * I880; + struct TableAssign_ * I798; + U I5; + U I1078 :1; + U I1079 :1; + U I1080 :2; + U I1081 :1; + U I706 :8; + U I1082 :1; + U I1083 :1; + U I1084 :1; + U I1085 :1; + U I1086 :1; + U I1087 :1; + U I904 :13; + RP ptable; + RP I1043; +} TableAssign; +typedef struct TableAssignLayoutOnClk_ { + struct TableAssignLayoutOnClk_ * I880; + struct TableAssignLayoutOnClk_ * I798; + U I5; + U I1078 :1; + U I1079 :1; + U I1080 :2; + U I1081 :1; + U I706 :8; + U I1082 :1; + U I1083 :1; + U I1084 :1; + U I1085 :1; + U I1086 :1; + U I1087 :1; + U I904 :13; + RP ptable; + RmaSeqPrimOutputOnClkS I1089; + RmaEblk I726; +} TableAssignLayoutOnClk; +typedef struct { + U state; + U I1090; +} RmaSeqPrimOutputOnClkOpt; +typedef struct TableAssignLayoutOnClkOpt_ { + struct TableAssignLayoutOnClkOpt_ * I880; + struct TableAssignLayoutOnClkOpt_ * I798; + U I1092; + U I1078 :1; + U I1079 :1; + U I1080 :2; + U I1081 :1; + U I706 :8; + U I1082 :1; + U I1083 :1; + U I1084 :1; + U I1085 :1; + U I1086 :1; + U I1087 :1; + U I904 :13; + RmaSeqPrimOutputOnClkOpt I1089; + RmaSeqPrimOutputEblkData I1093; +} TableAssignLayoutOnClkOpt; +typedef struct { + U I5; + RP I798; + RP I1094; +} RmaTableAssignList; +typedef struct { + U I5; + RP I798; + RP I1094; + RP I1095; + RP I1037; + US I706; + UB I978; + UB I1096; + UB I1097; + UB I772; + RP I1098[0]; +} RmaThreadTableAssignList; +typedef struct { + RP I1095; + RP I1037; + US I706; + UB I978; + UB I1096; + UB I1097; + UB I772; +} RmaThreadTableHeader; +typedef struct { + RP I1064; +} RmaWakeupListCg; +typedef struct { + RP I1064; +} RmaWakeupArrayCg; +typedef struct { + RP I1064; + RP I1099; +} RmaPreCheckWakeupListCg; +typedef struct { + RP I1064; + RP I1099; +} RmaPreCheckWakeupArrayCg; +typedef struct { + U I1100; + U I706; + RmaTimeStamp I1101[1]; +} RmaTsArray; +typedef struct { + U iinput; + RP I1102; +} RmaConditionsMdb; +typedef struct { + RP I1103; + RP I1104; + U I1105; +} RmaTcListHeader; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; +} RmaTcCoreSimple; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; +} RmaTcCoreConditional; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; + RP I1118; +} RmaTcCoreConditionalOpt; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1118; + RP I1119; + U I1120; + RmaConditionsMdb arr[1]; +} RmaTcCoreConditionalMtc; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; +} RmaTcCoreSimpleNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1035; +} RmaTcCoreSimpleNoListMdb; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; +} RmaTcCoreConditionalNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; + RP I1118; +} RmaTcCoreConditionalOptNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1118; + RP I1119; + U I1120; + RmaConditionsMdb arr[1]; +} RmaTcCoreConditionalMtcNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1118; + RP I1119; + RP I1035; + U I1120; + RmaConditionsMdb arr[1]; +} RmaTcCoreConditionalMtcNoListMdb; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; + RP I1035; +} RmaTcCoreConditionalNoListMdb; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + U I1122; + RP I1123; + RP I1124; + RP I1117; + RP I1125; + RP I1126; + RmaTimeStamp I1127; +} RmaTcCoreNochange; +typedef struct { + RP I1128; + RP I880; +} RmaTcCoreNochangeList; +typedef struct { + RP I1102; + RmaTimeStamp I1129; + scalar I1130; +} RmaConditionalTSLoadNoList; +typedef struct { + RP I880; + RP I1102; + RmaTimeStamp I1129; + scalar I1130; +} RmaConditionalTSLoad; +typedef struct { + RmaTimeStamp I1129; + scalar I1130; + US I890; + RP I1118; +} RmaConditionalTSLoadOptNoList; +typedef struct { + RP I880; + RmaTimeStamp I1129; + scalar I1130; + US I890; + RP I1118; +} RmaConditionalTSLoadOpt; +typedef struct { + RP I1118; + RP I1131; + U I1120; + RmaConditionsMdb arr[1]; +} RmaConditionalTSLoadMtcNoList; +typedef struct { + RP I1035; + RP I1118; + RP I1131; + U I1120; + RmaConditionsMdb arr[1]; +} RmaConditionalTSLoadMtcNoListMdb; +typedef struct { + RP I880; + RP I1118; + RP I1131; + U I1120; + RmaConditionsMdb arr[1]; +} RmaConditionalTSLoadMtc; +typedef struct { + U I1132; + U I1133; + FlatNodeNum I1004; + U I915; + U I1134; + U I1135; + RmaIbfPcode I1028; + union { + scalar I1136; + vec32 I1137; + scalar * I1138; + vec32 * I1139; + } val; +} RmaScanSwitchData; +typedef struct { + RP I880; + RP I798; + RP I1140; +} RmaDoublyLinkedListElem; +typedef struct { + RP I1141; + U I1142 :1; + U I1143 :1; + U I1144 :1; + U I1145 :4; + U I904 :25; + U I1146; +} RmaSwitchGateInCbkListInfo; +typedef struct { + union { + RmaDoublyLinkedListElem I1640; + RmaSwitchGateInCbkListInfo I2; + } I699; + RmaIbfPcode I1028; +} RmaSwitchGate; +typedef struct RmaNonEdgeLoadData1_ { + US I1147; + scalar val; + scalar I1148 :1; + scalar I1149 :1; + scalar I1150 :1; + scalar I1151 :1; + scalar I1152 :1; + U I1153; + RP I811; + RP I1154; + RP I1004; + RP I1155; + RP I1156; +} RmaNonEdgeLoadData1; +typedef struct RmaNonEdgeLoadHdr1_ { + UB I1148; + UB I1157; + UB I978; + RmaNonEdgeLoadData1 * I1058; + RmaNonEdgeLoadData1 * I798; + void * I1158; +} RmaNonEdgeLoadHdr1; +typedef struct RmaNonEdgeLoadHdrPrl1_ { + U I1159; + RP I721; +} RmaNonEdgeLoadHdrPrl1; +typedef struct RmaChildClockProp_ { + RP I811; + RP I1160; + RP I1004; + RP pcode; + scalar val; +} RmaChildClockProp; +typedef struct RmaChildClockPropList1_ { + RmaChildClockProp * I1058; + RmaChildClockProp * I798; +} RmaChildClockPropList1; +typedef struct { + U I5; + U I1161; +} RmaHDLCosimDUTGate; +typedef struct { + UB I1162; + UB I1163 :1; + UB I1164 :1; + UB I1165 :1; + UB I1166 :1; + UB I904 :4; + US cedges; +} RmaMasterXpropLoadHdr; +typedef struct { + UB I1167; + UB I1168; + UB I1169; + UB I1170; + U cedges :30; + U I1164 :1; + U I1171 :1; + U I1172; + U I1173; + RP I1174; + RP I1175; + RmaRtlEdgeBlockHdr * I1176; +} RmaChildXpropLoadHdr; +struct clock_load { + U I181 :5; + U I182 :12; + U I183 :1; + U I184 :2; + U I185 :1; + U I186 :1; + U I187 :1; + U I188 :9; + U I189; + U I190; + void (* pfn)(void * I192, char val); +}; +typedef struct clock_data { + U I197 :1; + U I198 :1; + U I199 :1; + U I200 :1; + U I181 :5; + U I182 :12; + U I201 :6; + U I202 :1; + U I184 :2; + U I185 :1; + U I188 :1; + U I203; + U I204; + U I205; + U I189; + U I206; + U I207; + U I208; + U I209; + U I210; +} HdbsClockData; +struct clock_hiconn { + U I214; + U I215; + U I189; + U I184; +}; +typedef struct _RmaDaiCg { + RP I1177; + RP I1178; + U I1179; +} RmaDaiCg; +typedef union _RmaCbkMemOptUnion { + RP I1177; + RP I1180; + RP I1181; +} RmaCbkMemOptUnion; +typedef struct _RmaDaiOptCg { + RmaCbkMemOptUnion I1182; +} RmaDaiOptCg; +struct futq_slot2 { + U I758; + U I759[32]; +}; +struct futq_slot1 { + U I755; + struct futq_slot2 I756[32]; +}; +struct futq_info { + scalar * I750; + U I751; + U I752; + struct futq_slot1 I753[32]; +}; +struct futq { + struct futq * I740; + struct futq * I742; + RmaEblk * I743; + RmaEblk * I744; + U I731; + U I1; +}; +struct sched_table { + struct futq * I745; + struct futq I746; + struct hash_bucket * I747; + struct hash_bucket * I749; +}; +struct dummyq_struct { + clock_struct I1183; + EBLK * I1184; + EBLK * I1185; + EBLK * I1186; + struct futq * I1187; + struct futq * I1188; + struct futq * I1189; + struct sched_table * I1190; + struct futq_info * I1192; + struct futq_info * I1194; + U I1195; + U I1196; + U I1197; + U I1198; + U I1199; + U I1200; + U I1201; + struct millenium * I1202; + EBLK * I1204; + EBLK * I1205; + EBLK * I1206; + EBLK * I1207; + EBLK * I1208; + EBLK * I1209; + EBLK * I1210; + EBLK * I1211; + EBLK * I1212; + EBLK * I1213; + EBLK * I1214; + EBLK * I1215; + EBLK * I1216; + EBLK * I1217; + EBLK * I1218; + EBLK * I1219; + EBLK * I1220; + EBLK * I1221; + MPS * I1222; + struct retain_t * I1223; + EBLK * I1224; + EBLK * I1225; + EBLK * I1226; + EBLK * I1227; + EBLK * I1228; + EBLK * I1229; + EBLK * I1230; + EBLK * I1231; + EBLK * I1232; + EBLK * I1233; + EBLK * I1234; + EBLK * I1235; + EBLK * I1236; + EBLK * I1237; + EBLK * I1238; + EBLK * I1239; + EBLK * I1240; + EBLK * I1241; + EBLK * I1242; + EBLK * I1243; + EBLK * I1244; + EBLK * I1245; + EBLK * I1246; + EBLK * I1247; + EBLK * I1248; + EBLK * I1249; + EBLK I1250; + EBLK * I1251; + EBLK * I1252; + EBLK * I1253; + EBLK * I1254; + int I1255; + int I1256; + struct vcs_globals_t * I1257; + clock_struct I1258; + unsigned long long I1259; + EBLK * I1260; + EBLK * I1261; + void * I1262; +}; +typedef void (* FP)(void * , scalar ); +typedef void (* FP1)(void * ); +typedef void (* FPRAP)(void * , vec32 * , U ); +typedef U (* FPU1)(void * ); +typedef void (* FPV)(void * , UB * ); +typedef void (* FPVU)(void * , UB * , U ); +typedef void (* FPLSEL)(void * , scalar , U ); +typedef void (* FPLSELV)(void * , vec32 * , U , U ); +typedef void (* FPFPV)(UB * , UB * , U , U , U , U , U , UB * , U ); +typedef void (* FPFA)(UB * , UB * , U , U , U , U , U , U , UB * , U ); +typedef void (* FPRPV)(UB * , U , U , U ); +typedef void (* FPEVCDLSEL)(void * , scalar , U , UB * ); +typedef void (* FPEVCDLSELV)(void * , vec32 * , U , U , UB * ); +typedef void (* FPNTYPE_L)(void * , void * , U , U , UB * , UB * , UB * , UB * , UB * , UB * , UB * , U ); +typedef void (* FPNTYPE_H)(void * , void * , U , U , UB * , UB * , UB * , UB * , U ); +typedef void (* FPNTYPE_LPAP)(void * , void * , void * , U , U , UB * , UB * , U ); +typedef void (* FPNTYPE_HPAP)(void * , void * , void * , U , U , UB * , UB * , UB * , UB * , U ); +typedef struct _lqueue { + EBLK * I727; + EBLK * I1263; + int I1264; + struct _lqueue * I769; +} Queue; +typedef struct { + void * I1266; + void * I1267; + void * I1268[2]; + void * I1269; +} ClkLevel; +typedef struct { + unsigned long long I1270; + EBLK I1171; + U I1271; + U I1272; + union { + void * pHeap; + Queue * pList; + } I699; + unsigned long long I1273; + ClkLevel I1274; + Queue I1275[1]; +} Qhdr; +extern UB Xvalchg[]; +extern UB X4val[]; +extern UB X3val[]; +extern UB X2val[]; +extern UB XcvtstrTR[]; +extern UB Xcvtstr[]; +extern UB Xbuf[]; +extern UB Xbitnot[]; +extern UB Xwor[]; +extern UB Xwand[]; +extern U Xbitnot4val[]; +extern UB globalTable1Input[]; +extern __thread unsigned long long vcs_clocks; +extern UB Xunion[]; +extern U fRTFrcRelCbk; +extern FP txpFnPtr; +extern FP rmaFunctionArray[]; +extern UP rmaFunctionRtlArray[]; +extern FP rmaFunctionLRArray[]; +extern U rmaFunctionCount; +extern U rmaFunctionLRCount; +extern U rmaFunctionLRDummyCount; +extern UP rmaFunctionDummyEndPtr; +extern FP rmaFunctionFanoutArray[]; +extern __thread UB dummyScalar; +extern __thread UB fScalarIsForced; +extern __thread UB fScalarIsReleased; +extern U fNotimingchecks; +extern U fFsdbDumpOn; +extern RP * iparr; +extern FP1 * rmaPostAnySchedFnPtr; +extern FP1 * rmaPostAnySchedFnSamplePtr; +extern FP1 * rmaPostAnySchedVFnPtr; +extern FP1 * rmaPostAnySchedWFnPtr; +extern FP1 * rmaPostAnySchedEFnPtr; +extern FP1 * rmaPostSchedUpdateClockStatusFnPtr; +extern FP1 * rmaPostSchedUpdateClockStatusNonCongruentFnPtr; +extern FP1 * rmaPostSchedUpdateEvTrigFnPtr; +extern FP1 * rmaSched0UpdateEvTrigFnPtr; +extern FP1 * rmaPostSchedRecoveryResetDbsFnPtr; +extern U fGblDataOrTime0Prop; +extern UB rmaEdgeStatusValArr[]; +extern FP1 * propForceCbkSPostSchedCgFnPtr; +extern FP1 * propForceCbkMemoptSPostSchedCgFnPtr; +extern UB * ptableGbl; +extern U * vcs_ptableOffsetsGbl; +extern UB * expandedClkValues; +extern __thread Qhdr * lvlQueue; +extern __thread unsigned threadIndex; +extern int cPeblkThreads; +extern US xedges[]; +extern U mhdl_delta_count; +extern U ignoreSchedForScanOpt; +extern U fignoreSchedForDeadComboCloud; +extern int fZeroUser; +extern U fEveBusPullVal; +extern U fEveBusPullFlag; +extern U fFutEventPRL; +extern U fParallelEBLK; +extern U fBufferingEvent; +extern __thread UB fNettypeIsForced; +extern __thread UB fNettypeIsReleased; +extern EBLK * peblkFutQ1Head; +extern EBLK * peblkFutQ1Tail; +extern US * edgeActionT; +extern unsigned long long * derivedClk; +extern U fHashTableSize; +extern U fSkipStrChangeOnDelay; +extern U fHsimTcheckOpt; +extern scalar edgeChangeLookUp[4][4]; +extern U fDoingTime0Prop; +extern U fLoopDetectMode; +extern int gFLoopDectCodeEna; +extern U fLoopReportRT; + + +extern void *mempcpy(void* s1, void* s2, unsigned n); +extern UB* rmaEvalDelays(UB* pcode, scalar val); +extern UB* rmaEvalDelaysV(UB* pcode, vec32* pval); +extern void rmaPopTransEvent(UB* pcode); +extern void rmaSetupFuncArray(UP* ra, U c, U w); +extern void rmaSetupRTLoopReportPtrs(UP* funcs, UP* rtlFuncs, U cnt, U cntDummy, UP end); +extern void SinitHsimPats(void); +extern void VVrpDaicb(void* ip, U nIndex); +extern int SDaicb(void *ip, U nIndex); +extern void SDaicbForHsimNoFlagScalar(void* pDaiCb, unsigned char value); +extern void SDaicbForHsimNoFlagStrengthScalar(void* pDaiCb, unsigned char value); +extern void SDaicbForHsimNoFlag(void* pRmaDaiCg, unsigned char value); +extern void SDaicbForHsimNoFlag2(void* pRmaDaiCg, unsigned char value); +extern void SDaicbForHsimWithFlag(void* pRmaDaiCg, unsigned char value); +extern void SDaicbForHsimNoFlagFrcRel(void* pRmaDaiCg, unsigned char reason, int msb, int lsb, int ndx); +extern void SDaicbForHsimNoFlagFrcRel2(void* pRmaDaiCg, unsigned char reason, int msb, int lsb, int ndx); +extern void VcsHsimValueChangeCB(void* pRmaDaiCg, void* pValue, unsigned int valueFormat); +extern U isNonDesignNodeCallbackList(void* pRmaDaiCg); +extern void SDaicbForHsimCbkMemOptNoFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptWithFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptNoFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptWithFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void VVrpNonEventNonRegdScalarForHsimOptCbkMemopt(void* ip, U nIndex); +extern void SDaicbForHsimCbkMemOptNoFlagDynElabScalar(U* mem, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptWithFlagDynElabScalar(U* mem, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptNoFlagDynElabFrcRel(U* mem, unsigned char reason, int msb, int lsb, int ndx); +extern void SDaicbForHsimCbkMemOptNoFlagFrcRel(void* pDaiCb, unsigned char reason, int msb, int lsb, int ndx); +extern void hsimDispatchCbkMemOptForVcd(RP p, U val); +extern void* hsimGetCbkMemOptCallback(RP p); +extern void hsimDispatchCbkMemOptNoDynElabS(RP* p, U val, U isStrength); +extern void* hsimGetCbkPtrNoDynElab(RP p); +extern void hsimDispatchCbkMemOptDynElabS(U** pvcdarr, U** pcbkarr, U val, U isScalForced, U isScalReleased, U isStrength); +extern void hsimDispatchCbkMemOptNoDynElabVector(RP* /*RmaDaiOptCg* */p, void* pval, U /*RmaValueType*/ vt, U cbits); +extern void copyAndPropRootCbkCgS(RmaRootCbkCg* pRootCbk, scalar val); +extern void copyAndPropRootCbkCgV(RmaRootCbkCg* rootCbk, vec32* pval); +extern void copyAndPropRootCbkCgW(RmaRootCbkCg* rootCbk, vec32* pval); +extern void copyAndPropRootCbkCgE(RmaRootCbkCg* rootCbk, scalar* pval); +extern void Wsvvar_callback_non_dynamic1(RP* ptr, int); +extern void rmaExecEvSyncList(RP plist); +extern void Wsvvar_callback_virt_intf(RP* ptr); +extern void Wsvvar_callback_hsim_var(RP* ptr); +extern void checkAndConvertVec32To2State(vec32* value, vec32* svalue, U cbits, U* pforcedBits); +extern unsigned int fGblDataOrTime0Prop; +extern void SchedSemiLerMP1(UB* pmps, U partId); +extern void SchedSemiLerMPO(UB* pmpso, U partId); +extern void rmaDummyPropagate(void); +extern RP rmaTestCg(RP pcode, U vt, UB* value); +extern void hsUpdateModpathTimeStamp(UB* pmps); +extern void doMpd32One(UB* pmps); +extern void doMpdCommon(MPS* pmps); +extern TimeStamp GET_DIFF_DELAY_FUNC(TimeStamp ts); +extern void SchedSemiLerMP(UB* ppulse, U partId); +extern EBLK *peblkFutQ1Head; +extern EBLK *peblkFutQ1Tail; +extern void scheduleuna(UB *e, U t); +extern void scheduleuna_mp(EBLK *e, unsigned t); +extern void schedule(UB *e, U t); +extern void sched_hsopt(struct dummyq_struct * pQ, EBLK *e, U t); +extern void sched_millenium(struct dummyq_struct * pQ, void *e, U thigh, U t); +extern void schedule_1(EBLK *e); +extern void sched0(UB *e); +extern void sched0Raptor(UB *e); +extern void sched0lq(EBLK *e); +extern void sched0lqnc(EBLK *e); +extern void sched0una(UB *e); +extern void sched0una_th(struct dummyq_struct *pq, UB *e); +extern void hsopt_sched0u_th(struct dummyq_struct *pq, UB *e); +extern void scheduleuna_mp_th(struct dummyq_struct *pq, EBLK *e, unsigned t); +extern void schedal(UB *e); +extern void sched0_th(struct dummyq_struct * pQ, EBLK *e); +extern void sched0u(UB *e); +extern void sched0u_th(struct dummyq_struct *pq, UB *e); +extern void sched0_hsim_front_th(struct dummyq_struct * pQ, UB *e); +extern void sched0_hsim_frontlq_th(struct dummyq_struct * pQ, UB *e); +extern void sched0lq_th(struct dummyq_struct * pQ, UB *e); +extern void schedal_th(struct dummyq_struct * pQ, UB *e); +extern void scheduleuna_th(struct dummyq_struct * pQ, void *e, U t); +extern void schedule_th(struct dummyq_struct * pQ, UB *e, U t); +extern void schedule_1_th(struct dummyq_struct * pQ, EBLK *peblk); +extern void SetupLER_th(struct dummyq_struct * pQ, EBLK *e); +extern void FsdbReportClkGlitch(UB*,U); +extern void AddToClkGLitchArray(EBLK*); +extern void SchedSemiLer_th(struct dummyq_struct * pQ, EBLK *e); +extern void SchedSemiLerTXP_th(struct dummyq_struct * pQ, EBLK *e); +extern void SchedSemiLerTXPFreeVar_th(struct dummyq_struct * pQ, EBLK *e); +extern U getVcdFlags(UB *ip); +extern void VVrpNonEventNonRegdScalarForHsimOpt(void* ip, U nIndex); +extern void VVrpNonEventNonRegdScalarForHsimOpt2(void* ip, U nIndex); +extern void SchedSemiLerTBReactiveRegion(struct eblk* peblk); +extern void SchedSemiLerTBReactiveRegion_th(struct eblk* peblk, U partId); +extern void SchedSemiLerTr(UB* peblk, U partId); +extern void SchedSemiLerNBA(UB* peblk, U partId); +extern void NBA_Semiler(void *ip, void *pNBS); +extern void sched0sd_hsim(UB* peblk); +extern void vcs_sched0sd_hsim_udpclk(UB* peblk); +extern void vcs_sched0sd_hsim_udpclkopt(UB* peblk); +extern void sched0sd_hsim_PRL(UB* peblk); +extern void sched0lq_parallel_clk(EBLK* peblk); +extern U isRtlClockScheduled(EBLK* peblk); +extern void doFgpRaceCheck(UB* pcode, UB* p, U flag); +extern void doSanityLvlCheck(); +extern void sched0lq_parallel_ova(EBLK* peblk); +extern void sched0lq_parallel_ova_precheck(EBLK* peblk); +extern void rmaDlpEvalSeqPrim(UB* peblk, UB val, UB preval); +extern void appendNtcEvent(UB* phdr, scalar s, U schedDelta); +extern void appendTransEventS(RmaTransEventHdr* phdr, scalar s, U schedDelta); +extern void schedRetainHsim(MPS* pMPS, scalar sv, scalar pv); +extern void updateRetainHsim(MPS* pMPS,scalar sv, scalar pv); +extern void hsimCountXEdges(void* record, scalar s); +extern void hsimRegisterEdge(void* sm, scalar s); +extern U pvcsGetPartId(); +extern void HsimPVCSPartIdCheck(U instNo); +extern void debug_func(U partId, struct dummyq_struct* pQ, EBLK* EblkLastEventx); +extern struct dummyq_struct* pvcsGetQ(U thid); +extern EBLK* pvcsGetLastEventEblk(U thid); +extern void insertTransEvent(RmaTransEventHdr* phdr, scalar s, scalar pv, scalar resval, U schedDelta, int re, UB* predd, U fpdd); +extern void insertNtcEventRF(RmaTransEventHdr* phdr, scalar s, scalar pv, scalar resval, U schedDelta, U* delays); +extern U doTimingViolation(RmaTimeStamp ts,RP* pdata, U fskew, U limit, U floaded, U fcondopt, RmaTimeStamp tsNochange); +extern void sched_gate_hsim(EBLK* peblk, unsigned t, RP* offset, U gd_info, U encodeInPcode, void* propValue); +extern int getCurSchedRegion(); +extern FP getRoutPtr(RP, U); +extern U rmaChangeCheckAndUpdateE(scalar* pvalDst, scalar* pvalSrc, U cbits); +extern void rmaUpdateE(scalar* pvalDst, scalar* pvalSrc, U cbits); +extern U rmaChangeCheckAndUpdateEFromW(scalar* pvalDst, vec32* pvalSrc, U cbits); +extern void rmaLhsPartSelUpdateE(scalar* pvalDst, scalar* pvalSrc, U index, U width); +extern void rmaUpdateWithForceSelectorE(scalar* pvalDst, scalar* pvalSrc, U cbits, U* pforceSelector); +extern void rmaUpdateWFromE(vec32* pvalDst, scalar* pvalSrc, U cbits); +extern U rmaLhsPartSelWithChangeCheckE(scalar* pvalDst, scalar* pvalSrc, U index, U width); +extern void rmaLhsPartSelWFromE(vec32* pvalDst, scalar* pvalSrc, U index,U width); +extern U rmaChangeCheckAndUpdateW(vec32* pvalDst, vec32* pvalSrc, U cbits); +extern void rmaUpdateW(vec32* pvalDst, vec32* pvalSrc, U cbits); +extern void rmaUpdateEFromW(scalar* pvalDst, vec32* pvalSrc, U cbits); +extern void *VCSCalloc(size_t size, size_t count); +extern void *VCSMalloc(size_t size); +extern void VCSFree(void *ptr); +extern U rmaLhsPartSelWithChangeCheckW(vec32* pvalDst, vec32* pvalSrc, U index,U width); +extern void rmaLhsPartSelEFromW(scalar* pvalDst, vec32* pvalSrc, U index,U width); +extern U rmaLhsPartSelWithChangeCheckEFromW(scalar* pvalDst, vec32* pvalSrc, U index,U width); +extern void rmaLhsPartSelUpdateW(vec32* pvalDst, vec32* pvalSrc, U index, U width); +extern void rmaEvalWunionW(vec32* dst, vec32* src, U cbits, U count); +extern void rmaEvalWorW(vec32* dst, vec32* src, U cbits, U count); +extern void rmaEvalWandW(vec32* dst, vec32* src, U cbits, U count); +extern void rmaEvalUnionE(scalar* dst, scalar* src, U cbits, U count, RP ptable); +typedef U RmaCgFunctionType; +extern RmaIbfPcode* rmaEvalPartSelectsW(vec32* pvec32, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce, UB* pevcdStatus); +extern RmaIbfPcode* rmaEvalPartSelectsWLe32(vec32* pvec32, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce, UB* pevcdStatus); +extern RmaIbfPcode* rmaEvalPartSelectsWToE(vec32* pvec32, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce); +extern RmaIbfPcode* rmaEvalPartSelectsEToE(scalar* pv, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce, UB* pevcdStatus); +extern RmaIbfPcode* rmaEvalPartSelectsEToW(scalar* pv, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce); +extern U rmaEvalBitPosEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitNegEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitChangeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U VcsForceVecVCg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U/*RmaValueConvType*/ convtype, U/*RmaForceType*/ frcType, UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsReleaseVecVCg(UB* pcode, UB* pvDst, U fullcbits, U ibeginDst, U width, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsForceVecWCg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U/*RmaValueConvType*/ convtype, U /*RmaForceType*/ frcType, UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsReleaseVecWCg(UB* pcode, UB* pvDst, U fullcbits, U ibeginDst, U width, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsForceVecECg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U /*RmaValueConvType*/ convtype, U /*RmaForceType*/ frcType,UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsForceVecACg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U /*RmaValueConvType*/ convtype, U /*RmaForceType*/ frcType,UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsReleaseVecCg(UB* pcode, UB* pvDst, U ibeginDst, U width, U /*RmaValueType*/ type,U fisRoot, UB* prhsDst, U frhs, U* pforcedbits); +extern U VcsDriveBitsAndDoChangeCheckV(vec32* pvSel, vec32* pvCur, U fullcbits, U* pforcedbits, U isRoot); +extern U VcsDriveBitsAndDoChangeCheckW(vec32* pvSel, vec32* pvCur, U fullcbits, U* pforcedbits, U isRoot); +extern U VcsDriveBitsAndDoChangeCheckE(scalar* pvSel, scalar* pvCur, U fullcbits, U* pforcedbits, U isRoot); +extern void cgvecDebug_Eblk(UB* pcode); +extern U rmaCmpW(vec32* pvalDst, vec32* pvalSrc, U index, U width); +extern void copyVec32ArrMask(vec32* pv1, vec32* pv2, U len, U* mask); +extern void* memcpy(void*, const void*, size_t); +extern int memcmp(const void*, const void*, size_t); +extern void propagateScanOptPathVal(EBLK *peblk); +extern UB* rmaProcessScanSwitches(UB* pcode, scalar val); +extern UB* rmaProcessScanSwitchesV(UB* pcode, vec32 *pval); +extern UB* rmaProcessScanoptDump(UB* pcode, scalar val); +extern UB* rmaProcessScanoptDumpV(UB* pcode, vec32 *pval); +extern UB* rmaProcessScanChainOptSeqPrims(UB* pcode, scalar val); +extern void rmaProcessPvcsCcn(UB* pcode, scalar val); +extern void rmaProcessPvcsCcnE(UB* pcode, scalar* val); +extern void rmaProcessPvcsCcnW(UB* pcode, vec32* val); +extern void rmaProcessPvcsCcnV(UB* pcode, vec32* val); +extern void rmaProcessPvcsCcnCompiledS(UB* pcode, U offset, scalar ibnval); +extern void rmaProcessPvcsCcnCompiledV(UB* pcode, U offset, vec32* pval); +extern void schedResetRecoveryDbs(U cedges, EBLK* peblkFirst); +extern UB* rmaEvalUnaryOpV(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpV(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpVOneFanoutCount(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpVLargeFanoutCount(UB* pcode, vec32* pval); +extern UB* rmaEvalAndOpVOneFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalAndOpVLargeFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalAndOpV(UB* pcode, vec32* value); +extern UB* rmaEvalOrOpVOneFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalOrOpVLargeFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalOrOpV(UB* pcode, vec32* value); +extern UB* rmaEvalTernaryOpV(UB* pcode, vec32* pval); +extern UB* rmaEvalUnaryOpW(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpW(UB* pcode, vec32* pval); +extern UB* rmaEvalTernaryOpW(UB* pcode, vec32* pval); +extern UB* rmaEvalUnaryOpE(UB* pcode, scalar* pv); +extern UB* rmaEvalBinaryOpE(UB* pcode, scalar* pv); +extern UB* rmaEvalTernaryOpE(UB* pcode, scalar* pv); +extern UB* rmaEvalTernaryOpS(UB* pcode, scalar val); +extern scalar rmaGetScalarFromWCg(vec32* pval, U index); +extern void rmaSetScalarInWCg(vec32* pval, U index, scalar s); +extern void rmaSetWInW(vec32* dst, vec32* src, U index, U indexSrc, U width); +extern void rmaCountRaptorBits(void* pval, void* pvalPrev, U cbits, U vt); +extern void setHsimFunc(void* ip); +extern void unsetHsimFunc(void* ip); +extern UB* getEvcdStatusByFlagsE(scalar* pscalar, UB* pevcdTBDriverFlags, U cdrivers, UB* table, U cbits); +extern UB* getEvcdStatusByFlagsV(vec32* pvec32, UB* pevcdTBDriverFlags, U cdrivers, UB* table, U cbits); +extern UB* getEvcdStatusByFlagsW(vec32* pvec32, UB* pevcdTBDriverFlags, U cdrivers, UB* table, U cbits); +extern UB* getEvcdStatusByFlagsS(scalar* pscalar, UB* pevcdTBDriverFlags, U cdrivers, UB* table); +extern UB* getSingleDrvEvcdStatusS(UB value, U fTBDriver); +extern UB* getSingleDrvEvcdStatusE(scalar* pscalars, U fTBDriver, U cbits); +extern UB* getSingleDrvEvcdStatusV(scalar* pscalars, U fTBDriver, U cbits); +extern UB* getSingleDrvEvcdStatusW(scalar* pscalars, U fTBDriver, U cbits); +extern UB* getEvcdStatusByDrvEvcdStatus(UB* pdrvevcdStatus, U cdrivers, UB* table, U cbits); +extern void evcdCallback(UP pcode, U cbits); +extern UB* getSavedEvcdStatus(void); +extern void saveEvcdStatus(UB*); +extern void mhdlMarkExport(void*, U); +extern void levelInsertQueue(int); +extern void VcsRciRtl(RP pcode); +extern U fLoopDetectMode; +extern int gFLoopDectCodeEna; +extern U fLoopReportRT; +extern void rtSched0LoopDectDumpProcess(void* e, void* rtn, void* PQ); +extern void pushHsimRtnCtxt(void* pcode); +extern void popHsimRtnCtxt(); +extern EBLK* loopReportInlinedSched0Wrapper(EBLK *peblk); +extern void loopReportSched0Wrapper(EBLK *peblk, unsigned int sfType, unsigned int fTH, struct dummyq_struct* pq); +extern void loopReportSchedSemiLerWrapper(EBLK *peblk, int sfType); +extern void CallGraphPushNodeAndAddToGraph(UP flatNode, UP instNum, U dummy); +extern void CallGraphPopNode(void); +extern RP elabGetIpTpl(U in); +extern U rmaEvalBitBothEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ1W(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQXW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ0W(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval01EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval0XEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval10EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval1XEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalX1EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalX0EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitPosEdgeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitNegEdgeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitBothEdgeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ1E(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ0E(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitChangeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern void rmaScheduleNbaGate(RP pcode, scalar val); +extern void rmaEvalRtlEdgeLoads(RmaRtlEdgeBlockHdr *phdr, US clkEdge, scalar clkVal, scalar prevClkVal, scalar val4, scalar prevval4, scalar master4val); +extern void rmaEvaluateDynamicGateLoadsCg(RP p, scalar s); +extern void rmaEvaluateFusedWithDynamicGateLoadsCg(RP p, scalar s); +extern void rmaScheduleGatedClockEdgeLoadNew(UB* p, US* ea, U flags, UB* plist, UB* pprevlist, scalar v); +extern void rmaScheduleGatedClockEdgeLoad(UB* p, US* ea, U flags, UB* plist, UB* pprevlist, scalar v); +extern void rmaRemoveNonEdgeLoads(UB* pcode); +extern void rmaRecordEvents(HsimNodeRecord *pnr); +extern void handlePCBs(UB* p, U i); +extern void markMasterClkOvaLists(U fdbs, RP p); +extern void rmaChildClockPropAfterWrite(UB* p); +extern void rmaSchedChildClockPropAfterWrite(UB* p, UB* pmasterList, UB val); +extern void HDLCosimProcessDUTInputChange(U inputId, void* val); +extern void rmaChangeListForMovedGates(UB clkVal, UB f10Edge, UB* subMasterVal, UB* plist, RP* p, U count); +extern void rmaEvalSeqPrimLoadsByteArray(UB* pcode, UB val, UB prevval4); +extern void rmaEvalSeqPrimLoadsByteArrayX(UB* pcode, UB val, UB prevval4); +extern void vcsRmaEvalSeqPrimLoadsByteArraySCT(UB* pcode, UB val, UB prevval4, U c); +extern void vcsAbortForBadEBlk(void); +extern scalar edgeChangeLookUp[4][4]; +extern void Wsvvar_sched_virt_intf_eval(RP* ptr); +extern void vcs_hwcosim_drive_dut_scalar(uint id, char val); +extern void vcs_hwcosim_drive_dut_vector_4state(uint id, vec32* val); +extern U vcs_rmaGetClkValForSeqUdpLayoutOnClkOpt(UB* poutput); +extern U rmaIsS2State(scalar s); +extern U rmaIsV2State(vec32* pval, U cbits); +extern U rmaIsW2State(vec32* pval, U cbits); +extern U rmaIsE2State(scalar* pval, U cbits); +extern void rmaUpdateRecordFor2State(HsimNodeRecord* record, U f2state); +typedef void (*FuncPtr)(); +static inline U asm_bsf (U in) +{ +#if defined(linux) + U out; +#if !defined(__aarch64__) + asm ("movl %1, %%eax; bsf %%eax, %%eax; movl %%eax, %0;" + :"=r"(out) + :"r"(in) + :"%eax" + ); +#else + out = ffs(in) - 1; +#endif + return out; +#else + return 0; +#endif +} + + +#ifdef __cplusplus +extern "C" { +#endif +void hs_0_M_6_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_6_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_6_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_6_2__simv_daidir (UB * pcode); +void hs_0_M_6_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_8_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_8_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_8_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_8_2__simv_daidir (UB * pcode); +void hs_0_M_8_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_9_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_9_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_9_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_9_2__simv_daidir (UB * pcode); +void hs_0_M_9_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_9_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_10_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_10_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_10_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_10_2__simv_daidir (UB * pcode); +void hs_0_M_10_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_11_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_11_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_11_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_11_2__simv_daidir (UB * pcode); +void hs_0_M_11_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_12_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_12_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_12_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_12_2__simv_daidir (UB * pcode); +void hs_0_M_12_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_13_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_13_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_13_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_13_2__simv_daidir (UB * pcode); +void hs_0_M_13_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_13_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_14_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_14_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_14_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_14_2__simv_daidir (UB * pcode); +void hs_0_M_14_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_15_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_15_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_15_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_15_2__simv_daidir (UB * pcode); +void hs_0_M_15_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_16_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_16_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_16_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_16_2__simv_daidir (UB * pcode); +void hs_0_M_16_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_17_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_17_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_17_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_17_2__simv_daidir (UB * pcode); +void hs_0_M_17_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_17_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_18_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_18_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_18_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_18_2__simv_daidir (UB * pcode); +void hs_0_M_18_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_19_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_19_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_19_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_19_2__simv_daidir (UB * pcode); +void hs_0_M_19_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_19_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_20_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_20_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_20_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_20_2__simv_daidir (UB * pcode); +void hs_0_M_20_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_20_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_21_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_21_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_21_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_21_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_22_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_22_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_22_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_22_2__simv_daidir (UB * pcode); +void hs_0_M_22_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_22_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_23_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_23_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_23_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_23_2__simv_daidir (UB * pcode); +void hs_0_M_23_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_23_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_25_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_25_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_25_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_25_2__simv_daidir (UB * pcode); +void hs_0_M_25_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_25_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_26_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_26_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_26_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_26_2__simv_daidir (UB * pcode); +void hs_0_M_26_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_26_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_28_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_28_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_28_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_28_2__simv_daidir (UB * pcode); +void hs_0_M_28_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_28_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_29_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_29_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_29_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_29_2__simv_daidir (UB * pcode); +void hs_0_M_29_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_29_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_34_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_34_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_34_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_34_2__simv_daidir (UB * pcode); +void hs_0_M_34_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_34_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_35_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_35_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_35_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_35_2__simv_daidir (UB * pcode); +void hs_0_M_35_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_35_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_36_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_36_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_36_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_36_2__simv_daidir (UB * pcode); +void hs_0_M_36_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_37_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_37_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_37_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_37_2__simv_daidir (UB * pcode); +void hs_0_M_37_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_38_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_38_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_38_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_38_2__simv_daidir (UB * pcode); +void hs_0_M_38_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_39_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_39_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_39_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_39_2__simv_daidir (UB * pcode); +void hs_0_M_39_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_40_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_40_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_40_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_40_2__simv_daidir (UB * pcode); +void hs_0_M_40_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_41_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_41_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_41_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_41_2__simv_daidir (UB * pcode); +void hs_0_M_41_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_42_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_42_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_42_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_42_2__simv_daidir (UB * pcode); +void hs_0_M_42_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_43_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_43_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_43_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_43_2__simv_daidir (UB * pcode); +void hs_0_M_43_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_44_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_44_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_44_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_44_2__simv_daidir (UB * pcode); +void hs_0_M_44_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_44_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_45_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_45_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_45_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_45_2__simv_daidir (UB * pcode); +void hs_0_M_45_9__simv_daidir (UB * pcode, scalar val); +void hs_0_M_45_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_46_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_47_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_47_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_47_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_47_2__simv_daidir (UB * pcode); +void hs_0_M_47_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_48_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_48_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_48_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_48_2__simv_daidir (UB * pcode); +void hs_0_M_48_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_49_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_49_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_49_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_49_2__simv_daidir (UB * pcode); +void hs_0_M_49_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_50_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_50_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_50_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_50_2__simv_daidir (UB * pcode); +void hs_0_M_50_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_51_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_51_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_51_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_51_2__simv_daidir (UB * pcode); +void hs_0_M_51_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_58_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_58_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_58_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_58_2__simv_daidir (UB * pcode); +void hs_0_M_58_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_59_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_59_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_59_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_59_2__simv_daidir (UB * pcode); +void hs_0_M_59_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_60_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_60_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_60_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_60_2__simv_daidir (UB * pcode); +void hs_0_M_60_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_61_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_61_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_61_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_61_2__simv_daidir (UB * pcode); +void hs_0_M_61_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_67_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_67_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_67_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_84_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_84_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_84_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_89_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_92_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_92_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_92_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_93_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_93_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_93_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_93_2__simv_daidir (UB * pcode); +void hs_0_M_93_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_93_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_94_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_94_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_94_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_94_2__simv_daidir (UB * pcode); +void hs_0_M_94_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_94_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_95_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_95_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_95_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_95_2__simv_daidir (UB * pcode); +void hs_0_M_95_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_95_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_96_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_96_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_96_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_96_2__simv_daidir (UB * pcode); +void hs_0_M_96_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_96_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_97_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_97_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_97_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_97_2__simv_daidir (UB * pcode); +void hs_0_M_97_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_98_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_98_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_98_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_98_2__simv_daidir (UB * pcode); +void hs_0_M_98_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_99_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_99_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_99_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_99_2__simv_daidir (UB * pcode); +void hs_0_M_99_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_100_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_100_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_100_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_100_2__simv_daidir (UB * pcode); +void hs_0_M_100_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_101_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_101_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_101_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_101_2__simv_daidir (UB * pcode); +void hs_0_M_101_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_102_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_102_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_102_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_102_2__simv_daidir (UB * pcode); +void hs_0_M_102_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_104_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_104_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_104_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_104_2__simv_daidir (UB * pcode); +void hs_0_M_104_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_105_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_105_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_105_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_105_2__simv_daidir (UB * pcode); +void hs_0_M_105_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_106_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_106_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_106_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_106_2__simv_daidir (UB * pcode); +void hs_0_M_106_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_107_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_107_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_107_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_107_2__simv_daidir (UB * pcode); +void hs_0_M_107_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_108_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_108_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_108_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_108_2__simv_daidir (UB * pcode); +void hs_0_M_108_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_108_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_109_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_109_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_109_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_109_2__simv_daidir (UB * pcode); +void hs_0_M_109_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_110_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_110_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_110_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_110_2__simv_daidir (UB * pcode); +void hs_0_M_110_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_113_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_113_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_113_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_114_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_114_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_114_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_114_2__simv_daidir (UB * pcode); +void hs_0_M_114_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_114_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_115_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_115_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_116_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_116_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_116_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_116_2__simv_daidir (UB * pcode); +void hs_0_M_116_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_116_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_117_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_117_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_117_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_117_2__simv_daidir (UB * pcode); +void hs_0_M_117_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_118_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_119_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_119_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_119_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_119_2__simv_daidir (UB * pcode); +void hs_0_M_119_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_120_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_120_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_120_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_120_2__simv_daidir (UB * pcode); +void hs_0_M_120_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_121_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_121_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_121_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_121_2__simv_daidir (UB * pcode); +void hs_0_M_121_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_122_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_123_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_124_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_125_21__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_125_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_125_5__simv_daidir (UB * pcode, U I915); +void hs_0_M_126_21__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_126_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_126_5__simv_daidir (UB * pcode, U I915); +void hs_0_M_127_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_128_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_128_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_129_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_129_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_129_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_129_2__simv_daidir (UB * pcode); +void hs_0_M_129_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_130_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_130_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_130_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_130_2__simv_daidir (UB * pcode); +void hs_0_M_130_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_131_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_131_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_131_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_131_2__simv_daidir (UB * pcode); +void hs_0_M_131_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_134_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_134_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_134_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_134_2__simv_daidir (UB * pcode); +void hs_0_M_134_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_135_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_135_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_135_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_135_2__simv_daidir (UB * pcode); +void hs_0_M_135_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_136_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_136_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_136_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_136_2__simv_daidir (UB * pcode); +void hs_0_M_136_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_137_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_137_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_137_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_137_2__simv_daidir (UB * pcode); +void hs_0_M_137_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_138_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_138_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_138_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_138_2__simv_daidir (UB * pcode); +void hs_0_M_138_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_139_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_139_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_139_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_139_2__simv_daidir (UB * pcode); +void hs_0_M_139_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_140_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_140_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_140_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_140_2__simv_daidir (UB * pcode); +void hs_0_M_140_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_143_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_143_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_143_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_143_2__simv_daidir (UB * pcode); +void hs_0_M_143_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_144_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_144_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_144_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_144_2__simv_daidir (UB * pcode); +void hs_0_M_144_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_145_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_145_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_145_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_145_2__simv_daidir (UB * pcode); +void hs_0_M_145_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_146_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_146_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_146_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_146_2__simv_daidir (UB * pcode); +void hs_0_M_146_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_147_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_147_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_147_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_147_2__simv_daidir (UB * pcode); +void hs_0_M_147_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_148_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_150_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_150_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_150_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_150_2__simv_daidir (UB * pcode); +void hs_0_M_150_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_151_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_151_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_151_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_151_2__simv_daidir (UB * pcode); +void hs_0_M_151_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_152_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_152_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_152_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_152_2__simv_daidir (UB * pcode); +void hs_0_M_152_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_153_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_153_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_153_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_153_2__simv_daidir (UB * pcode); +void hs_0_M_153_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_153_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_154_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_154_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_154_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_154_2__simv_daidir (UB * pcode); +void hs_0_M_154_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_154_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_155_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_155_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_155_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_155_2__simv_daidir (UB * pcode); +void hs_0_M_155_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_156_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_156_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_156_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_156_2__simv_daidir (UB * pcode); +void hs_0_M_156_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_157_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_157_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_157_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_159_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_159_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_159_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_160_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_160_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_160_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_160_2__simv_daidir (UB * pcode); +void hs_0_M_160_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_163_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_163_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_163_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_165_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_165_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_165_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_169_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_169_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_169_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_169_2__simv_daidir (UB * pcode); +void hs_0_M_169_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_170_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_170_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_170_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_170_2__simv_daidir (UB * pcode); +void hs_0_M_170_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_171_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_171_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_171_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_171_2__simv_daidir (UB * pcode); +void hs_0_M_171_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_172_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_172_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_172_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_172_2__simv_daidir (UB * pcode); +void hs_0_M_172_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_173_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_173_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_173_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_173_2__simv_daidir (UB * pcode); +void hs_0_M_173_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_174_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_174_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_174_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_174_2__simv_daidir (UB * pcode); +void hs_0_M_174_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_175_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_175_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_175_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_175_2__simv_daidir (UB * pcode); +void hs_0_M_175_11__simv_daidir (UB * pcode, scalar val); +void hsG_0__0 (struct dummyq_struct * I1289, EBLK * I1283, U I685); +#ifdef __cplusplus +} +#endif + +#ifdef __cplusplus + } +#endif +#endif /*__DO_RMAHDR_*/ + diff --git a/DA4008_V1.2/sim/chip_top/csrc/rmapats.m b/DA4008_V1.2/sim/chip_top/csrc/rmapats.m new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/csrc/rmapats.o b/DA4008_V1.2/sim/chip_top/csrc/rmapats.o new file mode 100644 index 0000000..d0c32e0 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/csrc/rmapats.o differ diff --git a/DA4008_V1.2/sim/chip_top/csrc/rmapats_mop.o b/DA4008_V1.2/sim/chip_top/csrc/rmapats_mop.o new file mode 100644 index 0000000..1c7e27c Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/csrc/rmapats_mop.o differ diff --git a/DA4008_V1.2/sim/chip_top/csrc/rmar.c b/DA4008_V1.2/sim/chip_top/csrc/rmar.c new file mode 100644 index 0000000..21b81fa --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/csrc/rmar.c @@ -0,0 +1,13 @@ +#include +#include +#include "rmar0.h" + +// stubs for Hil functions +#ifdef __cplusplus +extern "C" { +#endif +void __Hil__Static_Init_Func__(void) {} +#ifdef __cplusplus +} +#endif + diff --git a/DA4008_V1.2/sim/chip_top/csrc/rmar.h b/DA4008_V1.2/sim/chip_top/csrc/rmar.h new file mode 100644 index 0000000..77865aa --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/csrc/rmar.h @@ -0,0 +1,18 @@ +#ifndef _RMAR1_H_ +#define _RMAR1_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __DO_RMAHDR_ +#include "rmar0.h" +#endif /*__DO_RMAHDR_*/ + +extern UP rmaFunctionRtlArray[]; + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/DA4008_V1.2/sim/chip_top/csrc/rmar.o b/DA4008_V1.2/sim/chip_top/csrc/rmar.o new file mode 100644 index 0000000..1989370 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/csrc/rmar.o differ diff --git a/DA4008_V1.2/sim/chip_top/csrc/rmar0.h b/DA4008_V1.2/sim/chip_top/csrc/rmar0.h new file mode 100644 index 0000000..48e8516 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/csrc/rmar0.h @@ -0,0 +1,13 @@ +#ifndef _RMAR0_H_ +#define _RMAR0_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/DA4008_V1.2/sim/chip_top/csrc/rmar_llvm_0_0.o b/DA4008_V1.2/sim/chip_top/csrc/rmar_llvm_0_0.o new file mode 100644 index 0000000..3663b36 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/csrc/rmar_llvm_0_0.o differ diff --git a/DA4008_V1.2/sim/chip_top/csrc/rmar_llvm_0_1.o b/DA4008_V1.2/sim/chip_top/csrc/rmar_llvm_0_1.o new file mode 100644 index 0000000..0119f49 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/csrc/rmar_llvm_0_1.o differ diff --git a/DA4008_V1.2/sim/chip_top/csrc/rmar_nd.o b/DA4008_V1.2/sim/chip_top/csrc/rmar_nd.o new file mode 100644 index 0000000..99927ba Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/csrc/rmar_nd.o differ diff --git a/DA4008_V1.2/sim/chip_top/csrc/vcspieces.incr b/DA4008_V1.2/sim/chip_top/csrc/vcspieces.incr new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/data_RTL/try/flattop.txt b/DA4008_V1.2/sim/chip_top/data_RTL/try/flattop.txt new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/data_RTL/try/sine_1g.txt b/DA4008_V1.2/sim/chip_top/data_RTL/try/sine_1g.txt new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/data_temp.txt b/DA4008_V1.2/sim/chip_top/data_temp.txt new file mode 100644 index 0000000..005ef24 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/data_temp.txt @@ -0,0 +1,2 @@ + +../../data_RTL/try/sine_1g.txt diff --git a/DA4008_V1.2/sim/chip_top/regress.csh b/DA4008_V1.2/sim/chip_top/regress.csh old mode 100644 new mode 100755 diff --git a/DA4008_V1.2/sim/chip_top/result/try/flattop.txt b/DA4008_V1.2/sim/chip_top/result/try/flattop.txt new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/result/try/flattop.txt @@ -0,0 +1 @@ + diff --git a/DA4008_V1.2/sim/chip_top/result/try/sine_1g.txt b/DA4008_V1.2/sim/chip_top/result/try/sine_1g.txt new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/result/try/sine_1g.txt @@ -0,0 +1 @@ + diff --git a/DA4008_V1.2/sim/chip_top/result_temp.txt b/DA4008_V1.2/sim/chip_top/result_temp.txt new file mode 100644 index 0000000..7e22574 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/result_temp.txt @@ -0,0 +1,2 @@ + + ../../result/try//sine_1g.txt diff --git a/DA4008_V1.2/sim/chip_top/simv b/DA4008_V1.2/sim/chip_top/simv new file mode 100755 index 0000000..0036aa9 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/.daidir_complete b/DA4008_V1.2/sim/chip_top/simv.daidir/.daidir_complete new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/.normal_done b/DA4008_V1.2/sim/chip_top/simv.daidir/.normal_done new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/.vcs.timestamp b/DA4008_V1.2/sim/chip_top/simv.daidir/.vcs.timestamp new file mode 100644 index 0000000..0d4e6bb --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/simv.daidir/.vcs.timestamp @@ -0,0 +1,230 @@ +4 +0 ../define/chip_define.v +0 /opt/synopsys/vcs-mx/O-2018.09-SP2/etc/systemverilog/../define/chip_define.v +0 ../define/chip_undefine.v +0 /opt/synopsys/vcs-mx/O-2018.09-SP2/etc/systemverilog/../define/chip_undefine.v +48 ++define+DUMP_FSDB ++incdir+./../../model ++incdir+./../../rtl/define ++incdir+./../../rtl/qubitmcu ++itf+/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab ++lint=TFIPC-L ++nospecify ++v2k ++vcsd1 ++vpi +-Mamsrun= +-Masflags= +-Mcc=gcc +-Mcfl= -pipe -fPIC -O -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include +-Mcplusplus=g++ +-Mcrt0= +-Mcrtn= +-Mcsrc= +-Mexternalobj= +-Mldflags= -rdynamic +-Mobjects= /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvirsim.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/liberrorinf.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a +-Mout=simv +-Msaverestoreobj=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o +-Msyslibs=/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lm +-Mvcsaceobjs= +-Mxcflags= -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include +-P +-P +-cm +-cm_dir +-debug_access+all +-debug_region+cell+encrypt +-f filelist_vlg.f +-fsdb +-full64 +-gen_obj +-l +-lca +-picarchive +-q +-sverilog +-timescale=1ns/1ps +./coverage/simv.vdb +/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/vcs1 +/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +compile.log +line+cond+fsm+tgl+branch +110 +sysc_uni_pwd=/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top +starRC_HOME=/opt/synopsys/starrc/O-2018.06-SP1 +XMODIFIERS=@im=ibus +XILINX_VIVADO=/opt/xilinx/Vivado/2019.2 +XILINX_HOME=/opt/xilinx +XDG_SESSION_ID=c34 +XDG_RUNTIME_DIR=/run/user/1019 +XDG_MENU_PREFIX=gnome- +XDG_DATA_DIRS=/home/shbyang/.local/share/flatpak/exports/share:/var/lib/flatpak/exports/share:/usr/local/share:/usr/share +XDG_CURRENT_DESKTOP=GNOME +WV_HOME=/opt/synopsys/wv/N-2017.12-SP2 +WAVE=1 +W3264_NO_HOST_CHECK=1 +VTE_VERSION=5204 +VRST_HOME=/opt/cadence/INCISIVE152 +VNCDESKTOP=cryo1:17 (shbyang) +VMR_MODE_FLAG=64 +VIVADO_HOME=/opt/xilinx/Vivado/2019.2/ +VERDI_HOME=/opt/synopsys/verdi/Verdi_O-2018.09-SP2 +VENDOR=unknown +VC_STATIC_HOME=/opt/synopsys/vc_stat/vc_static/V-2023.12 +VCS_MX_HOME_INTERNAL=1 +VCS_MODE_FLAG=64 +VCS_LOG_FILE=compile.log +VCS_LCAMSG_PRINT_OFF=1 +VCS_HOME=/opt/synopsys/vcs-mx/O-2018.09-SP2 +VCS_DEPTH=0 +VCS_ARG_ADDED_FOR_TMP=1 +VCS_ARCH=linux64 +UNAME=/bin/uname +TXS_HOME=/opt/synopsys/txs/O-2018.06-SP1 +TOOL_HOME=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64 +SYN_HOME=/opt/synopsys/syn/O-2018.06-SP1 +SYNOPSYS=/opt/synopsys +SSH_AUTH_SOCK=/run/user/1019/keyring/ssh +SSH_AGENT_PID=24257 +SPECTRE_HOME=/opt/cadence/SPECTRE181 +SPECTRE_DEFAULTS=-E +SPECMAN_HOME=/opt/cadence/INCISIVE152/components/sn +SPECMAN_DIR=/opt/cadence/INCISIVE152/components/sn +SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/24088,unix/unix:/tmp/.ICE-unix/24088 +SCRNAME=vcs +SCRIPT_NAME=vcs +SCL_HOME=/opt/synopsys/scl/2018.06 +QT_IM_MODULE=ibus +QT_GRAPHICSSYSTEM_CHECKED=1 +QTLIB=/usr/lib64/qt-3.3/lib +QTINC=/usr/lib64/qt-3.3/include +QTDIR=/usr/lib64/qt-3.3 +PWR_HOME=/opt/synopsys/pwr/O-2018.06-SP3 +PT_HOME=/opt/synopsys/pts/O-2018.06-SP1 +OVA_UUM=0 +OSTYPE=linux +OA_UNSUPPORTED_PLAT=linux_rhel50_gcc44x +NOVAS_HOME=/opt/synopsys/verdi/Verdi_O-2018.09-SP2 +MOZILLA_HOME=/usr/bin/firefox +MGLS_LICENSE_FILE=/opt/mentor/license/license.dat +MGC_PDF_REDER=evince +MGC_LIB_PATH=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/lib +MGC_HOME=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11 +MGC_CALIBRE_SAVE_ALL_RUNSET_VALUES=1 +MGC_CALIBRE_REALTIME_VIRTUOSO_SAVE_MESSENGER_CELL=1 +MGC_CALIBRE_REALTIME_VIRTUOSO_ENABLED=1 +MFLAGS=-s +MENTOR_HOME=/opt/mentor +MAKEOVERRIDES=${-*-command-variables-*-} +MAKELEVEL=2 +MAKEFLAGS=s -- WAVE=1 +LESSOPEN=||/usr/bin/lesspipe.sh %s +LC_HOME=/opt/synopsys/lc/O-2018.06-SP1 +LC_ALL=C +INNOVUS_HOME=/opt/cadence/INNOVUS181 +INCISIVE_HOME=/opt/cadence/INCISIVE152 +IMSETTINGS_MODULE=none +IMSETTINGS_INTEGRATE_DESKTOP=yes +IDQ_HOME=/opt/synopsys/idq/O-2018.06-SP1 +HSPICE_HOME=/opt/synopsys/hspice/N-2017.12-SP2 +HOSTTYPE=x86_64-linux +HISTCONTROL=ignoredups +GROUP=cryo +GNOME_TERMINAL_SERVICE=:1.1458 +GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/300489a5_6011_46a1_a329_83b2a6d46428 +GNOME_SHELL_SESSION_MODE=classic +GNOME_DESKTOP_SESSION_ID=this-is-deprecated +GENUS_HOME=/opt/cadence/GENUS152 +FPGA_HOME=/opt/synopsys/fpga/K-2015.09 +FM_HOME=/opt/synopsys/fm/L-2016.03-SP1 +DBUS_STARTER_BUS_TYPE=session +DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-pbYbSoHCDo,guid=6bec37f851a0ec63831138606819dc51 +DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-pbYbSoHCDo,guid=6bec37f851a0ec63831138606819dc51 +COLORTERM=truecolor +CDS_SPECTRE_FBENABLE=1 +CDS_SPECTRERF_FBENABLE=1 +CDS_ROOT=/opt/cadence/IC618 +CDS_Netlisting_Mode=Analog +CDS_LOAD_ENV=CWD +CDS_LIC_ONLY=1 +CDS_LIC_FILE=/opt/cadence/license/license.dat +CDS_INST_DIR=/opt/cadence/IC618 +CDS_ENABLE_VMS=1 +CDS_AUTO_64BIT=ALL +CDSROOT=/opt/cadence/IC618 +CDSHOME=/opt/cadence/IC618 +CDSDIR=/opt/cadence/IC618 +CDS=/opt/cadence/IC618 +CALIBRE_HOME=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11 +CALIBRE_ENABLE_SKILL_PEXBA_MODE=1 +CADHOME=/opt/cadence +CADENCE_DIR=/opt/cadence/IC618 +AMS_ENABLE_NOISE=YES +0 +55 +1773384753 ../../model/LVDS_DRIVER.sv +1773384753 ../../model/SPI_DRIVER.sv +1773384753 ./../../rtl/define/../define/chip_undefine.v +1773384753 ./../../rtl/define/../define/chip_define.v +1773384753 ../../rtl/define/chip_undefine.v +1773384753 ../../sim/chip_top/TB.sv +1773384753 ../../model/DW_pulse_sync.v +1773384753 ../../model/DW_sync.v +1773384753 ../../model/DW_reset_sync.v +1773384753 ../../model/DW_stream_sync.v +1773384753 ../../model/reset_tb.v +1773384753 ../../model/DEM_Reverse.v +1773384753 ../../model/DEM_Reverse_64CH.v +1773384753 ../../model/clk_gen.v +1773384753 ../../model/spi_if.sv +1773384753 ../../model/clock_tb.v +1773384753 ../../rtl/spi/spi_sys.v +1773384753 ../../rtl/spi/spi_pll.v +1773384753 ../../rtl/spi/spi_slave.v +1773384753 ../../rtl/spi/spi_bus_decoder.sv +1773384753 ../../rtl/top/digital_top.sv +1773384753 ../../rtl/top/da4008_chip_top.sv +1773384753 ../../rtl/dem/DA4008_DEM_Parallel_PRBS_64CH.v +1773384753 ../../rtl/dem/DA4008_DEM_Parallel_PRBS_1CH.v +1773384753 ../../rtl/dem/DEM_PhaseSync_4008.sv +1773384753 ../../rtl/awg/awg_ctrl.v +1773384753 ../../rtl/awg/awg_top.sv +1773384753 ../../rtl/clk/clk_regfile.v +1773384753 ../../rtl/memory/spram.v +1773384753 ../../rtl/memory/bhv_spram.v +1773384753 ../../rtl/memory/dpram.v +1773384753 ../../rtl/memory/sram_dmux.sv +1773384753 ../../rtl/memory/sram_if.sv +1773384753 ../../rtl/memory/tsmc_dpram.v +1773384753 ../../rtl/comm/ramp_gen.v +1773384753 ../../rtl/comm/syncer.v +1773384753 ../../rtl/comm/sirv_gnrl_dffs.v +1773384753 ../../rtl/comm/pulse_generator.sv +1773384753 ../../rtl/comm/sirv_gnrl_xchecker.v +1773384753 ../../rtl/rstgen/rst_sync.v +1773384753 ../../rtl/rstgen/rst_gen_unit.v +1773384753 ../../rtl/lvds/ulink_rx.sv +1773384753 ../../rtl/dac_regfile/dac_regfile.v +1773384753 ../../rtl/fifo/syn_fwft_fifo.v +1773384753 ../../rtl/dacif/dacif.v +1773384753 ../../rtl/systemregfile/systemregfile.v +1773384753 ../../rtl/io/iopad.v +1773384753 ../../lib/tsdn28hpcpuhdb4096x128m4mw_170a_ffg0p99v0c.v +1773384753 ../../lib/tphn28hpcpgv18.v +1773384753 ../../rtl/define/chip_define.v +1551421444 /opt/synopsys/vcs-mx/O-2018.09-SP2/include/cm_vcsd.tab +1773384753 filelist_vlg.f +1550753332 /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +1550753332 /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +1551421246 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab +5 +1551422344 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvirsim.so +1551421792 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/liberrorinf.so +1551421768 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so +1551421789 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so +1550752033 /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a +1773384887 simv.daidir +-1 partitionlib diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/_32553_archive_1.so b/DA4008_V1.2/sim/chip_top/simv.daidir/_32553_archive_1.so new file mode 100755 index 0000000..fd59063 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/_32553_archive_1.so differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/_32573_archive_1.so b/DA4008_V1.2/sim/chip_top/simv.daidir/_32573_archive_1.so new file mode 100755 index 0000000..a1f01d7 Binary files /dev/null and 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file mode 100755 index 0000000..4ddf76b Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/_32577_archive_1.so differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/_32578_archive_1.so b/DA4008_V1.2/sim/chip_top/simv.daidir/_32578_archive_1.so new file mode 100755 index 0000000..5d72698 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/_32578_archive_1.so differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/_32579_archive_1.so b/DA4008_V1.2/sim/chip_top/simv.daidir/_32579_archive_1.so new file mode 100755 index 0000000..e0da35f Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/_32579_archive_1.so differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/binmap.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/binmap.sdb new file mode 100644 index 0000000..54897d5 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/binmap.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/build_db b/DA4008_V1.2/sim/chip_top/simv.daidir/build_db new file mode 100755 index 0000000..558da36 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/simv.daidir/build_db @@ -0,0 +1,4 @@ +#!/bin/sh -e +# This file is automatically generated by VCS. Any changes you make +# to it will be overwritten the next time VCS is run. +vcs '-full64' '-j8' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+all' '-debug_region+cell+encrypt' '-P' '/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab' '/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a' '+define+DUMP_FSDB' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-cm' 'line+cond+fsm+tgl+branch' '-cm_dir' './coverage/simv.vdb' '-f' 'filelist_vlg.f' '+incdir+./../../rtl/define' '+incdir+./../../rtl/qubitmcu' '+incdir+./../../model' -static_dbgen_only -daidir=$1 2>&1 diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/cc/cc_bcode.db b/DA4008_V1.2/sim/chip_top/simv.daidir/cc/cc_bcode.db new file mode 100644 index 0000000..757c06d --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/simv.daidir/cc/cc_bcode.db @@ -0,0 +1,561 @@ +sid sirv_gnrl_xchecker +bcid 0 0 WIDTH,32 CALL_ARG_VAL,2,0 WIDTH,1 XOR_REDUCE OPT_CONST_4ST,1,1 NEQU RET +sid clk_gen +bcid 1 0 WIDTH,4 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU RET +sid spi_sys_0000 +bcid 2 0 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 3 1 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 4 2 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 M_EQU AND CALL_ARG_VAL,4,0 OR RET +bcid 5 3 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 6 4 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,26 WIDTH,1 M_EQU AND RET +bcid 7 5 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,30 WIDTH,1 M_EQU AND AND RET +bcid 8 6 WIDTH,5 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_EQU RET +bcid 9 7 WIDTH,5 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_NEQU RET +bcid 10 8 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 AND AND RET +bcid 11 9 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 AND AND RET +bcid 12 10 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 NOT CALL_ARG_VAL,5,0 AND AND AND RET +bcid 13 11 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 AND AND AND RET +bcid 14 12 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND RET +bcid 15 13 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND RET +bcid 16 14 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND WIDTH,2 OPT_CONST,1 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,4,0 AND WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,5,0 AND WIDTH,2 OPT_CONST,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,6,0 AND WIDTH,2 OPT_CONST,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,7,0 AND WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,8,0 AND WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 17 15 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND OR CALL_ARG_VAL,4,0 WIDTH,5 CALL_ARG_VAL,5,0 OPT_CONST,27 WIDTH,1 M_EQU AND AND RET +bcid 18 16 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,25 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,25 CALL_ARG_VAL,4,0 WIDTH,1 CALL_ARG_VAL,5,0 WIDTH,25 CALL_ARG_VAL,6,0 OPT_CONST,4 ADD CALL_ARG_VAL,6,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 19 17 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,31 WIDTH,1 M_EQU AND AND RET +bcid 20 18 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND CALL_ARG_VAL,4,0 WIDTH,5 CALL_ARG_VAL,5,0 OPT_CONST,28 WIDTH,1 M_EQU AND AND RET +bcid 21 19 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,30 WIDTH,1 M_EQU AND AND RET +bcid 22 20 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,31 WIDTH,1 M_EQU AND AND RET +bcid 23 21 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 WIDTH,2 CALL_ARG_VAL,4,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,5,0 AND WIDTH,32 CALL_ARG_VAL,6,0 OPT_CONST,0 WIDTH,31 SLICE,1 WIDTH,1 OPT_CONST,0 WIDTH,32 CONCATENATE,2 CALL_ARG_VAL,6,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 24 22 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_NEQU RET +sid spi_slave +bcid 25 0 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 26 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 M_EQU AND RET +bcid 27 2 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 28 3 WIDTH,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,26 WIDTH,1 M_EQU AND AND RET +bcid 29 4 WIDTH,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,30 WIDTH,1 M_EQU AND AND RET +bcid 30 5 WIDTH,5 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 M_EQU WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 NOT WIDTH,5 CALL_ARG_VAL,4,0 WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,5 SLICE,1 WIDTH,1 M_EQU AND AND RET +bcid 31 6 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,30 WIDTH,1 M_EQU CALL_ARG_VAL,4,0 AND AND RET +bcid 32 7 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND CALL_ARG_VAL,4,0 OR CALL_ARG_VAL,5,0 WIDTH,5 CALL_ARG_VAL,6,0 OPT_CONST,29 WIDTH,1 M_EQU AND AND RET +bcid 33 8 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,8 CALL_ARG_VAL,4,0 OPT_CONST,4 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 CALL_ARG_VAL,5,0 MITECONDNOINSTR,4 RET +bcid 34 9 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 RET +bcid 35 10 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,30 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 36 11 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,29 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 37 12 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,28 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,2 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 38 13 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,27 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,3 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 39 14 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,26 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,4 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 40 15 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,25 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,5 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 41 16 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,24 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,6 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 42 17 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,23 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,7 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 43 18 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,22 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,8 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 44 19 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,21 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,9 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 45 20 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,20 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,10 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 46 21 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,19 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,11 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 47 22 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,13 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,18 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,12 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 48 23 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,17 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,13 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 49 24 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,14 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 50 25 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,15 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 51 26 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,17 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,16 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 52 27 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,18 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,13 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,17 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 53 28 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,19 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,12 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,18 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 54 29 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,19 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 55 30 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,21 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,20 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 56 31 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,22 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,9 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,21 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 57 32 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,23 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,8 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,22 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 58 33 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,24 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,7 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,23 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 59 34 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,6 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,24 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 60 35 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,26 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,25 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 61 36 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,27 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,26 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 62 37 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,28 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,27 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 63 38 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,29 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,28 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 64 39 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,30 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,29 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 65 40 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,30 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +sid spi_bus_decoder_0000 +bcid 66 0 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,20 MULTI_CONCATENATE,1,20 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 AND RET +bcid 67 1 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,20 MULTI_CONCATENATE,1,20 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 AND RET +bcid 68 2 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,20 MULTI_CONCATENATE,1,20 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 AND RET +bcid 69 3 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,20 MULTI_CONCATENATE,1,20 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 AND RET +bcid 70 4 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 71 5 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 72 6 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 73 7 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 74 8 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,4 MULTI_CONCATENATE,1,4 AND RET +sid systemregfile +bcid 75 0 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,8 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,19,0 OPT_CONST,1 EQU WIDTH,8 OPT_CONST,32 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,8 OPT_CONST,88 WIDTH,1 CALL_ARG_VAL,21,0 OPT_CONST,1 EQU WIDTH,8 OPT_CONST,218 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 76 1 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,4 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,21,0 OPT_CONST,1 EQU WIDTH,4 OPT_CONST,2 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,4 OPT_CONST,4 WIDTH,1 CALL_ARG_VAL,23,0 OPT_CONST,1 EQU WIDTH,4 OPT_CONST,4 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 77 2 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU OPT_CONST,0 CALL_ARG_VAL,23,0 OPT_CONST,1 EQU OPT_CONST,0 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU OPT_CONST,0 CALL_ARG_VAL,25,0 OPT_CONST,1 EQU OPT_CONST,0 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 78 3 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,19 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,11 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,25,0 OPT_CONST,1 EQU WIDTH,11 OPT_CONST,1541 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,11 OPT_CONST,1109 WIDTH,1 CALL_ARG_VAL,27,0 OPT_CONST,1 EQU WIDTH,11 OPT_CONST,8 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 79 4 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,19 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,27,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,29,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 80 5 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,19 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,31,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,2 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,33,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,0 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 81 6 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,19 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,35,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,37,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 82 7 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU CALL_ARG_VAL,11,0 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU CALL_ARG_VAL,13,0 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU CALL_ARG_VAL,27,0 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU CALL_ARG_VAL,29,0 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU CALL_ARG_VAL,31,0 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,19 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 EQU OPT_CONST,1 CALL_ARG_VAL,45,0 OPT_CONST,1 EQU OPT_CONST,0 CALL_ARG_VAL,46,0 OPT_CONST,1 EQU OPT_CONST,0 CALL_ARG_VAL,47,0 OPT_CONST,1 EQU OPT_CONST,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 83 8 WIDTH,6 CALL_ARG_VAL,2,0 WIDTH,32 PAD RET +bcid 84 9 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 85 10 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 86 11 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 87 12 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 88 13 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 M_EQU RET +bcid 89 14 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 M_EQU RET +bcid 90 15 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 M_EQU RET +bcid 91 16 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 M_EQU RET +bcid 92 17 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU RET +bcid 93 18 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 M_EQU RET +bcid 94 19 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,10 WIDTH,1 M_EQU RET +bcid 95 20 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,11 WIDTH,1 M_EQU RET +bcid 96 21 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,1 M_EQU RET +bcid 97 22 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,13 WIDTH,1 M_EQU RET +bcid 98 23 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,14 WIDTH,1 M_EQU RET +bcid 99 24 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,1 M_EQU RET +bcid 100 25 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,19 WIDTH,1 M_EQU RET +bcid 101 26 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 M_EQU RET +bcid 102 27 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,21 WIDTH,1 M_EQU RET +bcid 103 28 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 M_EQU RET +bcid 104 29 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,17 WIDTH,1 M_EQU RET +bcid 105 30 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,18 WIDTH,1 M_EQU RET +bcid 106 31 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,22 WIDTH,1 M_EQU RET +bcid 107 32 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,23 WIDTH,1 M_EQU RET +bcid 108 33 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,24 WIDTH,1 M_EQU RET +bcid 109 34 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,1 M_EQU RET +bcid 110 35 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU AND RET +bcid 111 36 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 112 37 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_NEQU RET +sid DW_sync_0000 +bcid 113 0 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +sid DW_pulse_sync_0000 +bcid 114 0 WIDTH,32 PARAMETER,2 OPT_CONST,0 WIDTH,1 EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 XOR WIDTH,32 PARAMETER,2 OPT_CONST,1 WIDTH,1 EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,5,0 NOT AND CALL_ARG_VAL,4,0 XOR WIDTH,32 PARAMETER,2 OPT_CONST,2 WIDTH,1 EQU CALL_ARG_VAL,3,0 NOT CALL_ARG_VAL,5,0 AND CALL_ARG_VAL,4,0 XOR WIDTH,32 PARAMETER,2 OPT_CONST,3 WIDTH,1 EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,5,0 CALL_ARG_VAL,4,0 XOR XOR OPT_CONST_4ST,1,1 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 115 1 WIDTH,32 PARAMETER,2 OPT_CONST,0 WIDTH,1 M_NEQU WIDTH,2 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,2 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 XOR MITECONDNOINSTR,4 RET +sid ulink_descrambler_32 +bcid 116 0 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND WIDTH,32 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 XOR CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +sid syn_fwft_fifo +bcid 117 0 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,62 WIDTH,1 M_GT RET +bcid 118 1 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,59 WIDTH,1 M_GT RET +bcid 119 2 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,510 WIDTH,1 M_GT RET +bcid 120 3 WIDTH,7 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 121 4 WIDTH,7 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_LT RET +bcid 122 5 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,17 WIDTH,1 M_LT RET +bcid 123 6 WIDTH,6 CALL_ARG_VAL,2,0 WIDTH,4 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 LNOT AND WIDTH,5 CONCATENATE,2 WIDTH,6 PAD ADD RET +bcid 124 7 WIDTH,6 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_NEQU RET +bcid 125 8 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,128 CONST,0,0 CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +sid ulink_frame_receiver_0000 +bcid 126 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,16 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,16 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 127 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,4 MULTI_CONCATENATE,1,4 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,4 MULTI_CONCATENATE,1,4 NOT OR RET +bcid 128 2 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 WIDTH,1 M_NEQU AND RET +sid ulink_rx +bcid 129 0 WIDTH,20 CALL_ARG_VAL,2,0 OPT_CONST,10000 WIDTH,1 M_NEQU RET +bcid 130 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,20 CALL_ARG_VAL,3,0 OPT_CONST,9999 WIDTH,1 M_EQU AND RET +bcid 131 2 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,20 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,20 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 132 3 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 133 4 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 M_EQU AND RET +bcid 134 5 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 135 6 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,1751543404 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1751543404 WIDTH,1 M_EQU AND WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1751543404 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,1751543404 WIDTH,1 M_EQU AND AND RET +bcid 136 7 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,1702390132 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1702390132 WIDTH,1 M_EQU AND WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1702390132 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,1702390132 WIDTH,1 M_EQU AND AND RET +bcid 137 8 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,20 CALL_ARG_VAL,3,0 WIDTH,32 PAD WIDTH,20 CALL_ARG_VAL,4,0 WIDTH,32 PAD OPT_CONST,2 SUBTRACT WIDTH,1 M_EQU AND RET +bcid 138 9 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,3 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 CALL_ARG_VAL,3,0 ADD MITECONDNOINSTR,4 RET +bcid 139 10 WIDTH,128 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 SLICE,1 OPT_CONST,-1128481604 WIDTH,1 M_EQU RET +bcid 140 11 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND OPT_CONST,1 CALL_ARG_VAL,4,0 OPT_CONST,0 CALL_ARG_VAL,5,0 OPT_CONST,0 CALL_ARG_VAL,6,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 141 12 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 M_EQU AND CALL_ARG_VAL,4,0 OR RET +bcid 142 13 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,3 MULTI_CONCATENATE,1,3 RET +sid pulse_generator +bcid 143 0 WIDTH,16 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_EQU RET +sid tsdn28hpcpuhdb4096x128m4mw_170a +bcid 144 0 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 145 1 WIDTH,1 OPT_CONST,0 RET +bcid 146 2 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 147 3 WIDTH,1 OPT_CONST,0 RET +bcid 148 4 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 149 5 WIDTH,1 OPT_CONST,0 RET +bcid 150 6 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 151 7 WIDTH,1 OPT_CONST,0 RET +bcid 152 8 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 153 9 WIDTH,1 OPT_CONST,0 RET +bcid 154 10 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 155 11 WIDTH,1 OPT_CONST,0 RET +bcid 156 12 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 157 13 WIDTH,1 OPT_CONST,0 RET +bcid 158 14 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 159 15 WIDTH,1 OPT_CONST,0 RET +bcid 160 16 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 161 17 WIDTH,1 OPT_CONST,0 RET +bcid 162 18 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 163 19 WIDTH,1 OPT_CONST,0 RET +bcid 164 20 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 165 21 WIDTH,1 OPT_CONST,0 RET +bcid 166 22 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 167 23 WIDTH,1 OPT_CONST,0 RET +bcid 168 24 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 169 25 WIDTH,1 OPT_CONST,0 RET +bcid 170 26 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 171 27 WIDTH,1 OPT_CONST,0 RET +bcid 172 28 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 173 29 WIDTH,1 OPT_CONST,0 RET +bcid 174 30 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 175 31 WIDTH,1 OPT_CONST,0 RET +bcid 176 32 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 177 33 WIDTH,1 OPT_CONST,0 RET +bcid 178 34 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 179 35 WIDTH,1 OPT_CONST,0 RET +bcid 180 36 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 181 37 WIDTH,1 OPT_CONST,0 RET +bcid 182 38 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 183 39 WIDTH,1 OPT_CONST,0 RET +bcid 184 40 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 185 41 WIDTH,1 OPT_CONST,0 RET +bcid 186 42 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 187 43 WIDTH,1 OPT_CONST,0 RET +bcid 188 44 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 189 45 WIDTH,1 OPT_CONST,0 RET +bcid 190 46 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 191 47 WIDTH,1 OPT_CONST,0 RET +bcid 192 48 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 193 49 WIDTH,1 OPT_CONST,0 RET +bcid 194 50 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 195 51 WIDTH,1 OPT_CONST,0 RET +bcid 196 52 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 197 53 WIDTH,1 OPT_CONST,0 RET +bcid 198 54 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 199 55 WIDTH,1 OPT_CONST,0 RET +bcid 200 56 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 201 57 WIDTH,1 OPT_CONST,0 RET +bcid 202 58 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 203 59 WIDTH,1 OPT_CONST,0 RET +bcid 204 60 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 205 61 WIDTH,1 OPT_CONST,0 RET +bcid 206 62 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 207 63 WIDTH,1 OPT_CONST,0 RET +bcid 208 64 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 209 65 WIDTH,1 OPT_CONST,0 RET +bcid 210 66 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 211 67 WIDTH,1 OPT_CONST,0 RET +bcid 212 68 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 213 69 WIDTH,1 OPT_CONST,0 RET +bcid 214 70 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 215 71 WIDTH,1 OPT_CONST,0 RET +bcid 216 72 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 217 73 WIDTH,1 OPT_CONST,0 RET +bcid 218 74 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 219 75 WIDTH,1 OPT_CONST,0 RET +bcid 220 76 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 221 77 WIDTH,1 OPT_CONST,0 RET +bcid 222 78 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 223 79 WIDTH,1 OPT_CONST,0 RET +bcid 224 80 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 225 81 WIDTH,1 OPT_CONST,0 RET +bcid 226 82 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 227 83 WIDTH,1 OPT_CONST,0 RET +bcid 228 84 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 229 85 WIDTH,1 OPT_CONST,0 RET +bcid 230 86 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 231 87 WIDTH,1 OPT_CONST,0 RET +bcid 232 88 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 233 89 WIDTH,1 OPT_CONST,0 RET +bcid 234 90 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 235 91 WIDTH,1 OPT_CONST,0 RET +bcid 236 92 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 237 93 WIDTH,1 OPT_CONST,0 RET +bcid 238 94 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 239 95 WIDTH,1 OPT_CONST,0 RET +bcid 240 96 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 241 97 WIDTH,1 OPT_CONST,0 RET +bcid 242 98 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 243 99 WIDTH,1 OPT_CONST,0 RET +bcid 244 100 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 245 101 WIDTH,1 OPT_CONST,0 RET +bcid 246 102 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 247 103 WIDTH,1 OPT_CONST,0 RET +bcid 248 104 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 249 105 WIDTH,1 OPT_CONST,0 RET +bcid 250 106 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 251 107 WIDTH,1 OPT_CONST,0 RET +bcid 252 108 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 253 109 WIDTH,1 OPT_CONST,0 RET +bcid 254 110 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 255 111 WIDTH,1 OPT_CONST,0 RET +bcid 256 112 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 257 113 WIDTH,1 OPT_CONST,0 RET +bcid 258 114 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 259 115 WIDTH,1 OPT_CONST,0 RET +bcid 260 116 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 261 117 WIDTH,1 OPT_CONST,0 RET +bcid 262 118 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 263 119 WIDTH,1 OPT_CONST,0 RET +bcid 264 120 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 265 121 WIDTH,1 OPT_CONST,0 RET +bcid 266 122 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 267 123 WIDTH,1 OPT_CONST,0 RET +bcid 268 124 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 269 125 WIDTH,1 OPT_CONST,0 RET +bcid 270 126 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 271 127 WIDTH,1 OPT_CONST,0 RET +bcid 272 128 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 273 129 WIDTH,1 OPT_CONST,0 RET +bcid 274 130 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 275 131 WIDTH,1 OPT_CONST,0 RET +bcid 276 132 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 277 133 WIDTH,1 OPT_CONST,0 RET +bcid 278 134 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 279 135 WIDTH,1 OPT_CONST,0 RET +bcid 280 136 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 281 137 WIDTH,1 OPT_CONST,0 RET +bcid 282 138 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 283 139 WIDTH,1 OPT_CONST,0 RET +bcid 284 140 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 285 141 WIDTH,1 OPT_CONST,0 RET +bcid 286 142 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 287 143 WIDTH,1 OPT_CONST,0 RET +bcid 288 144 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 289 145 WIDTH,1 OPT_CONST,0 RET +bcid 290 146 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 291 147 WIDTH,1 OPT_CONST,0 RET +bcid 292 148 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 293 149 WIDTH,1 OPT_CONST,0 RET +bcid 294 150 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 295 151 WIDTH,1 OPT_CONST,0 RET +bcid 296 152 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 297 153 WIDTH,1 OPT_CONST,0 RET +bcid 298 154 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 299 155 WIDTH,1 OPT_CONST,0 RET +bcid 300 156 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 301 157 WIDTH,1 OPT_CONST,0 RET +bcid 302 158 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 303 159 WIDTH,1 OPT_CONST,0 RET +bcid 304 160 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 305 161 WIDTH,1 OPT_CONST,0 RET +bcid 306 162 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 307 163 WIDTH,1 OPT_CONST,0 RET +bcid 308 164 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 309 165 WIDTH,1 OPT_CONST,0 RET +bcid 310 166 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 311 167 WIDTH,1 OPT_CONST,0 RET +bcid 312 168 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 313 169 WIDTH,1 OPT_CONST,0 RET +bcid 314 170 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 315 171 WIDTH,1 OPT_CONST,0 RET +bcid 316 172 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 317 173 WIDTH,1 OPT_CONST,0 RET +bcid 318 174 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 319 175 WIDTH,1 OPT_CONST,0 RET +bcid 320 176 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 321 177 WIDTH,1 OPT_CONST,0 RET +bcid 322 178 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 323 179 WIDTH,1 OPT_CONST,0 RET +bcid 324 180 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 325 181 WIDTH,1 OPT_CONST,0 RET +bcid 326 182 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 327 183 WIDTH,1 OPT_CONST,0 RET +bcid 328 184 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 329 185 WIDTH,1 OPT_CONST,0 RET +bcid 330 186 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 331 187 WIDTH,1 OPT_CONST,0 RET +bcid 332 188 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 333 189 WIDTH,1 OPT_CONST,0 RET +bcid 334 190 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 335 191 WIDTH,1 OPT_CONST,0 RET +bcid 336 192 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 337 193 WIDTH,1 OPT_CONST,0 RET +bcid 338 194 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 339 195 WIDTH,1 OPT_CONST,0 RET +bcid 340 196 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 341 197 WIDTH,1 OPT_CONST,0 RET +bcid 342 198 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 343 199 WIDTH,1 OPT_CONST,0 RET +bcid 344 200 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 345 201 WIDTH,1 OPT_CONST,0 RET +bcid 346 202 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 347 203 WIDTH,1 OPT_CONST,0 RET +bcid 348 204 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 349 205 WIDTH,1 OPT_CONST,0 RET +bcid 350 206 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 351 207 WIDTH,1 OPT_CONST,0 RET +bcid 352 208 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 353 209 WIDTH,1 OPT_CONST,0 RET +bcid 354 210 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 355 211 WIDTH,1 OPT_CONST,0 RET +bcid 356 212 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 357 213 WIDTH,1 OPT_CONST,0 RET +bcid 358 214 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 359 215 WIDTH,1 OPT_CONST,0 RET +bcid 360 216 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 361 217 WIDTH,1 OPT_CONST,0 RET +bcid 362 218 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 363 219 WIDTH,1 OPT_CONST,0 RET +bcid 364 220 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 365 221 WIDTH,1 OPT_CONST,0 RET +bcid 366 222 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 367 223 WIDTH,1 OPT_CONST,0 RET +bcid 368 224 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 369 225 WIDTH,1 OPT_CONST,0 RET +bcid 370 226 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 371 227 WIDTH,1 OPT_CONST,0 RET +bcid 372 228 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 373 229 WIDTH,1 OPT_CONST,0 RET +bcid 374 230 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 375 231 WIDTH,1 OPT_CONST,0 RET +bcid 376 232 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 377 233 WIDTH,1 OPT_CONST,0 RET +bcid 378 234 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 379 235 WIDTH,1 OPT_CONST,0 RET +bcid 380 236 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 381 237 WIDTH,1 OPT_CONST,0 RET +bcid 382 238 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 383 239 WIDTH,1 OPT_CONST,0 RET +bcid 384 240 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 385 241 WIDTH,1 OPT_CONST,0 RET +bcid 386 242 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 387 243 WIDTH,1 OPT_CONST,0 RET +bcid 388 244 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 389 245 WIDTH,1 OPT_CONST,0 RET +bcid 390 246 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 391 247 WIDTH,1 OPT_CONST,0 RET +bcid 392 248 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 393 249 WIDTH,1 OPT_CONST,0 RET +bcid 394 250 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 395 251 WIDTH,1 OPT_CONST,0 RET +bcid 396 252 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 397 253 WIDTH,1 OPT_CONST,0 RET +bcid 398 254 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 399 255 WIDTH,1 OPT_CONST,0 RET +sid dpram +bcid 400 0 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU WIDTH,512 MULTI_CONCATENATE,1,512 CALL_ARG_VAL,3,0 AND WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU WIDTH,512 MULTI_CONCATENATE,1,512 CALL_ARG_VAL,4,0 AND OR RET +bcid 401 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 MULTI_CONCATENATE,1,8 RET +sid awg_top +bcid 402 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,13 CALL_ARG_VAL,3,0 WIDTH,6 OPT_CONST,0 WIDTH,19 CONCATENATE,2 WIDTH,13 CALL_ARG_VAL,4,0 WIDTH,6 OPT_CONST,0 WIDTH,19 CONCATENATE,2 MITECONDNOINSTR,4 RET +bcid 403 1 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,62 WIDTH,1 M_GT RET +bcid 404 2 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,59 WIDTH,1 M_GT RET +bcid 405 3 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,30 WIDTH,1 M_GT RET +bcid 406 4 WIDTH,7 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 407 5 WIDTH,7 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_LT RET +bcid 408 6 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,17 WIDTH,1 M_LT RET +bcid 409 7 WIDTH,6 CALL_ARG_VAL,2,0 WIDTH,4 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 LNOT AND WIDTH,5 CONCATENATE,2 WIDTH,6 PAD ADD RET +bcid 410 8 WIDTH,6 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_NEQU RET +bcid 411 9 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 412 10 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND RET +bcid 413 11 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 SLICE,1 NOT AND RET +bcid 414 12 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 SLICE,1 AND RET +bcid 415 13 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,31 WIDTH,1 SLICE,1 CALL_ARG_VAL,5,0 NOT AND AND RET +bcid 416 14 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 AND AND RET +bcid 417 15 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,31 WIDTH,1 SLICE,1 CALL_ARG_VAL,5,0 OR NOT AND RET +bcid 418 16 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 AND AND RET +bcid 419 17 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND WIDTH,3 OPT_CONST,1 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,4,0 AND WIDTH,3 OPT_CONST,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,5,0 AND WIDTH,3 OPT_CONST,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,6,0 AND WIDTH,3 OPT_CONST,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,7,0 AND WIDTH,3 OPT_CONST,0 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,8,0 AND WIDTH,3 OPT_CONST,2 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,9,0 AND WIDTH,3 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 420 18 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 OR OR CALL_ARG_VAL,5,0 NOT AND RET +bcid 421 19 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 422 20 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,13 CALL_ARG_VAL,3,0 WIDTH,32 PAD WIDTH,13 CALL_ARG_VAL,4,0 WIDTH,32 PAD OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU AND RET +bcid 423 21 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,13 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,13 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 424 22 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 WIDTH,32 PAD WIDTH,5 CALL_ARG_VAL,4,0 WIDTH,32 PAD OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 M_NEQU AND AND RET +bcid 425 23 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 426 24 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 427 25 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,31 CALL_ARG_VAL,3,0 WIDTH,32 PAD WIDTH,31 CALL_ARG_VAL,4,0 WIDTH,32 PAD OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU AND RET +bcid 428 26 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,31 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,31 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 429 27 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,512 CALL_ARG_VAL,3,0 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,8 CALL_ARG_VAL,5,0 WIDTH,512 MULTI_CONCATENATE,1,64 CONST,0,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 430 28 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU OR RET +bcid 431 29 WIDTH,13 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 ADD RET +sid ramp_gen_0000 +bcid 432 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU AND RET +bcid 433 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 434 2 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,8 SHIFT_L RET +bcid 435 3 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,8 SHIFT_L RET +bcid 436 4 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,8 SHIFT_L RET +bcid 437 5 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,4 WIDTH,8 SHIFT_L RET +bcid 438 6 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,5 WIDTH,8 SHIFT_L RET +bcid 439 7 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,6 WIDTH,8 SHIFT_L RET +sid dac_regfile +bcid 440 0 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,46,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,48,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU CALL_ARG_VAL,49,0 CALL_ARG_VAL,50,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,51,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 441 1 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,46,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,48,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,50,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,51,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 442 2 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,44,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,46,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,48,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,50,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,51,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 443 3 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,44,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,46,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,48,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,50,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,51,0 OPT_CONST,10 WIDTH,22 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 444 4 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,44,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,46,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,48,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,50,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,51,0 OPT_CONST,4 WIDTH,6 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 445 5 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 OPT_CONST,539362576 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,3,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,5,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,6,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,7,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,8,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,9,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,10,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,11,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,12,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,13,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,14,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,15,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,16,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,17,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,18,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,19,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,20,0 OPT_CONST,10 WIDTH,22 SLICE,1 CALL_ARG_VAL,21,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 446 6 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 OPT_CONST,539362576 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,3,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,5,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,6,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,7,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,10 CALL_ARG_VAL,8,0 WIDTH,32 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,9,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,10,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,11,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,12,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,13,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,14,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,15,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,16,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,17,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,18,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,19,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,20,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,21,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,22,0 OPT_CONST,4 WIDTH,6 SLICE,1 CALL_ARG_VAL,23,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 447 7 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 OPT_CONST,539362576 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,3,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,5,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,6,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,7,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,8,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,9,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,10,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,11,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,10 CALL_ARG_VAL,12,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,13,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,14,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,15,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,16,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,17,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,18,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,19,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,20,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,21,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,22,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,23,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,24,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,25,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,26,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,27,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,28,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,29,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 448 8 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 OPT_CONST,539362576 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,3,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,5,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,6,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,7,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,8,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,9,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,10,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,11,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,10 CALL_ARG_VAL,12,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,13,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,14,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,15,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,16,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,17,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,18,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,19,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,20,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,21,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,22,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,23,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,24,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,25,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,26,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,27,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,28,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,29,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,30,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,31,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,32,0 OPT_CONST,1 WIDTH,2 SLICE,1 CALL_ARG_VAL,33,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 449 9 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 OPT_CONST,539362576 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,3,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,5,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,6,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,7,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,8,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,9,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,10,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,11,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,10 CALL_ARG_VAL,12,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,13,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,14,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,15,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,16,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,17,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,18,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,19,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,20,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,21,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,22,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,23,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,24,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,25,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,26,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,27,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,28,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,29,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,30,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,31,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,32,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,33,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,34,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,35,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 450 10 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 451 11 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 452 12 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 453 13 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 454 14 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 M_EQU RET +bcid 455 15 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 M_EQU RET +bcid 456 16 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 M_EQU RET +bcid 457 17 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 M_EQU RET +bcid 458 18 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU RET +bcid 459 19 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 M_EQU RET +bcid 460 20 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,10 WIDTH,1 M_EQU RET +bcid 461 21 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,11 WIDTH,1 M_EQU RET +bcid 462 22 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,1 M_EQU RET +bcid 463 23 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,13 WIDTH,1 M_EQU RET +bcid 464 24 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,14 WIDTH,1 M_EQU RET +bcid 465 25 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,1 M_EQU RET +bcid 466 26 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 M_EQU RET +bcid 467 27 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,17 WIDTH,1 M_EQU RET +bcid 468 28 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,18 WIDTH,1 M_EQU RET +bcid 469 29 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,19 WIDTH,1 M_EQU RET +bcid 470 30 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 M_EQU RET +bcid 471 31 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,21 WIDTH,1 M_EQU RET +bcid 472 32 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,22 WIDTH,1 M_EQU RET +bcid 473 33 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,23 WIDTH,1 M_EQU RET +bcid 474 34 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,24 WIDTH,1 M_EQU RET +bcid 475 35 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,1 M_EQU RET +bcid 476 36 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,26 WIDTH,1 M_EQU RET +bcid 477 37 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,27 WIDTH,1 M_EQU RET +bcid 478 38 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,28 WIDTH,1 M_EQU RET +bcid 479 39 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,29 WIDTH,1 M_EQU RET +bcid 480 40 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,30 WIDTH,1 M_EQU RET +bcid 481 41 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 M_EQU RET +bcid 482 42 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,32 WIDTH,1 M_EQU RET +bcid 483 43 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,33 WIDTH,1 M_EQU RET +bcid 484 44 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,34 WIDTH,1 M_EQU RET +bcid 485 45 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,35 WIDTH,1 M_EQU RET +bcid 486 46 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,36 WIDTH,1 M_EQU RET +bcid 487 47 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,37 WIDTH,1 M_EQU RET +bcid 488 48 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,38 WIDTH,1 M_EQU RET +bcid 489 49 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,39 WIDTH,1 M_EQU RET +bcid 490 50 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,40 WIDTH,1 M_EQU RET +bcid 491 51 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,41 WIDTH,1 M_EQU RET +sid clk_regfile +bcid 492 0 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,24 WIDTH,8 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 493 1 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,20 WIDTH,4 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 494 2 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,16 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,16 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,16 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,16 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,16 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,16 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,16 WIDTH,4 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 495 3 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 496 4 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 497 5 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 498 6 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 499 7 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,39,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 500 8 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,39,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,41,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 501 9 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,39,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU CALL_ARG_VAL,41,0 CALL_ARG_VAL,42,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,43,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 EQU CALL_ARG_VAL,45,0 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 502 10 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 503 11 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 504 12 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 505 13 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 506 14 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 M_EQU RET +bcid 507 15 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 M_EQU RET +bcid 508 16 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 M_EQU RET +bcid 509 17 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 M_EQU RET +bcid 510 18 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU RET +bcid 511 19 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 M_EQU RET +bcid 512 20 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,10 WIDTH,1 M_EQU RET +bcid 513 21 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,11 WIDTH,1 M_EQU RET +bcid 514 22 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,1 M_EQU RET +bcid 515 23 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,13 WIDTH,1 M_EQU RET +bcid 516 24 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,14 WIDTH,1 M_EQU RET +bcid 517 25 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,1 M_EQU RET +bcid 518 26 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 M_EQU RET +bcid 519 27 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,17 WIDTH,1 M_EQU RET +bcid 520 28 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,18 WIDTH,1 M_EQU RET +bcid 521 29 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,19 WIDTH,1 M_EQU RET +bcid 522 30 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 M_EQU RET +bcid 523 31 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,21 WIDTH,1 M_EQU RET +sid da4008_chip_top +bcid 524 0 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 NOT AND OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,2 WIDTH,1 EQU OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD MITECONDNOINSTR,4 WIDTH,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 AND OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 EQU OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 OPT_CONST,1 SUBTRACT MITECONDNOINSTR,4 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 525 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 526 2 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 527 3 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 WIDTH,32 PAD OPT_CONST,31 WIDTH,1 NEQU WIDTH,5 MULTI_CONCATENATE,1,5 CALL_ARG_VAL,3,0 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,5 SLICE,1 ADD AND CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 528 4 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,31 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 SLICE,1 NOT WIDTH,32 CONCATENATE,2 CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 529 5 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 EQU AND CALL_ARG_VAL,4,0 NOT CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 530 6 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST_4ST,1,1 EQU CALL_ARG_VAL,3,0 OPT_CONST_4ST,1,1 EQU OR OPT_CONST_4ST,1,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 OPT_CONST,16 WIDTH,5 CALL_ARG_VAL,4,0 WIDTH,32 PAD WIDTH,1 M_GT AND OPT_CONST,1 WIDTH,5 CALL_ARG_VAL,4,0 WIDTH,32 PAD OPT_CONST,15 WIDTH,1 M_GT OPT_CONST,0 CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 531 7 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST_4ST,1,1 EQU WIDTH,4 OPT_CONST_4ST,15,15 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG,3 CALL_ARG_VAL,5,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 532 8 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 533 9 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 M_EQU AND RET +bcid 534 10 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1 WIDTH,1 M_EQU AND RET +bcid 535 11 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 NOT AND OPT_CONST,1 CALL_ARG_VAL,3,0 OPT_CONST,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 536 12 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND OPT_CONST,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 NOT CALL_ARG_VAL,4,0 AND AND OPT_CONST,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 537 13 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 SM_GT RET +bcid 538 14 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1 WIDTH,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 EQU AND AND RET +sid TB +bcid 539 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,6 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,6 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/cc/cc_dummy_file b/DA4008_V1.2/sim/chip_top/simv.daidir/cc/cc_dummy_file new file mode 100644 index 0000000..9ec9235 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/simv.daidir/cc/cc_dummy_file @@ -0,0 +1,2 @@ +Dummy_file +Missing line/file info diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/cgname.json b/DA4008_V1.2/sim/chip_top/simv.daidir/cgname.json new file mode 100644 index 0000000..39f08d3 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/simv.daidir/cgname.json @@ -0,0 +1,920 @@ +{ + "PDDW04SDGZ_H_G": [ + "PDDW04SDGZ_H_G", + "CQ4ek", + "module", + 12 + ], + "PDB3AC_V_G": [ + "PDB3AC_V_G", + "dviib", + "module", + 9 + ], + "PCLAMP_G": [ + "PCLAMP_G", + "DA1Pu", + "module", + 3 + ], + "PDUW04DGZ_H_G": [ + "PDUW04DGZ_H_G", + "YTwQz", + "module", + 26 + ], + "PVSS1ANA_V_G": [ + "PVSS1ANA_V_G", + "gL5Pd", + "module", + 95 + ], + "PVDD3A_H_G": [ + "PVDD3A_H_G", + "DTJPF", + "module", + 86 + ], + "PDDW08DGZ_V_G": [ + "PDDW08DGZ_V_G", + "K0TuH", + "module", + 15 + ], + "PRCUTA_G": [ + "PRCUTA_G", + "uuDJt", + "module", + 47 + ], + "dpram": [ + "dpram", + "bQxt6", + "module", + 135 + ], + "PRDW08DGZ_V_G": [ + "PRDW08DGZ_V_G", + "ZZxj5", + "module", + 49 + ], + "_vcs_unit__348857874": [ + "_vcs_unit__348857874", + "FgDcH", + "module", + 1 + ], + "PDUW16SDGZ_H_G": [ + "PDUW16SDGZ_H_G", + "iWZrk", + "module", + 40 + ], + "PDXOEDG_V_G": [ + "PDXOEDG_V_G", + "EZF3t", + "module", + 43 + ], + "PENDCAPA_G": [ + "PENDCAPA_G", + "wpYca", + "module", + 45 + ], + "sirv_gnrl_dffl": [ + "sirv_gnrl_dffl", + "BM4bj", + "module", + 127 + ], + "spi_bus_decoder_0000": [ + "spi_bus_decoder_0000", + "qLaCg", + "module", + 142 + ], + "PDDW08DGZ_H_G": [ + "PDDW08DGZ_H_G", + "C0gYT", + "module", + 14 + ], + "std": [ + "std", + "reYIK", + "module", + 2 + ], + "PVDD2ANA_V_G": [ + "PVDD2ANA_V_G", + "J6VbG", + "module", + 81 + ], + "PDUW12SDGZ_V_G": [ + "PDUW12SDGZ_V_G", + "qCQFW", + "module", + 37 + ], + "PDB3A_H_G": [ + "PDB3A_H_G", + "dfLHW", + "module", + 6 + ], + "PVSS1DGZ_H_G": [ + "PVSS1DGZ_H_G", + "Zp1LH", + "module", + 96 + ], + "PRUW16SDGZ_V_G": [ + "PRUW16SDGZ_V_G", + "psjSY", + "module", + 71 + ], + "PRDW16SDGZ_V_G": [ + "PRDW16SDGZ_V_G", + "YRh5I", + "module", + 59 + ], + "PDDW04SDGZ_V_G": [ + "PDDW04SDGZ_V_G", + "J6fGD", + "module", + 13 + ], + "PCLAMPC_H_G": [ + "PCLAMPC_H_G", + "UyGax", + "module", + 4 + ], + "PDDW04DGZ_V_G": [ + "PDDW04DGZ_V_G", + "sZaSM", + "module", + 11 + ], + "PCLAMPC_V_G": [ + "PCLAMPC_V_G", + "EyyeT", + "module", + 5 + ], + "PVDD1ANA_V_G": [ + "PVDD1ANA_V_G", + "BL1m7", + "module", + 77 + ], + "PDB3A_V_G": [ + "PDB3A_V_G", + "xqWfY", + "module", + 7 + ], + "PDDW12DGZ_H_G": [ + "PDDW12DGZ_H_G", + "atFKr", + "module", + 18 + ], + "PDB3AC_H_G": [ + "PDB3AC_H_G", + "LsJ1x", + "module", + 8 + ], + "PDDW04DGZ_H_G": [ + "PDDW04DGZ_H_G", + "Z62Gy", + "module", + 10 + ], + "PVSS1A_H_G": [ + "PVSS1A_H_G", + "aYKwj", + "module", + 90 + ], + "PRDW16SDGZ_H_G": [ + "PRDW16SDGZ_H_G", + "V63WF", + "module", + 58 + ], + "PDUW08DGZ_V_G": [ + "PDUW08DGZ_V_G", + "aEWK6", + "module", + 31 + ], + "PDUW12DGZ_V_G": [ + "PDUW12DGZ_V_G", + "NkwYe", + "module", + 35 + ], + "PDDW08SDGZ_H_G": [ + "PDDW08SDGZ_H_G", + "QjV6F", + "module", + 16 + ], + "PDUW16SDGZ_V_G": [ + "PDUW16SDGZ_V_G", + "qePm9", + "module", + 41 + ], + "PDDW12DGZ_V_G": [ + "PDDW12DGZ_V_G", + "eR5Zz", + "module", + 19 + ], + "rst_gen_unit": [ + "rst_gen_unit", + "anuMN", + "module", + 124 + ], + "PDUW16DGZ_H_G": [ + "PDUW16DGZ_H_G", + "M7qR3", + "module", + 38 + ], + "PDDW08SDGZ_V_G": [ + "PDDW08SDGZ_V_G", + "N1ndr", + "module", + 17 + ], + "ramp_gen_0000": [ + "ramp_gen_0000", + "AyqFm", + "module", + 129 + ], + "PDDW12SDGZ_H_G": [ + "PDDW12SDGZ_H_G", + "KpuhN", + "module", + 20 + ], + "ulink_descrambler_32": [ + "ulink_descrambler_32", + "yuek5", + "module", + 120 + ], + "PDDW12SDGZ_V_G": [ + "PDDW12SDGZ_V_G", + "Pzaun", + "module", + 21 + ], + "PDDW16DGZ_H_G": [ + "PDDW16DGZ_H_G", + "GzkJA", + "module", + 22 + ], + "systemregfile": [ + "systemregfile", + "qcK8J", + "module", + 115 + ], + "PRDW16DGZ_V_G": [ + "PRDW16DGZ_V_G", + "Jztd6", + "module", + 57 + ], + "PRUW08SDGZ_V_G": [ + "PRUW08SDGZ_V_G", + "VJ8Wg", + "module", + 63 + ], + "PRUW16SDGZ_H_G": [ + "PRUW16SDGZ_H_G", + "riJVY", + "module", + 70 + ], + "PVDD2ANA_H_G": [ + "PVDD2ANA_H_G", + "mZVHG", + "module", + 80 + ], + "PDDW16DGZ_V_G": [ + "PDDW16DGZ_V_G", + "StNiL", + "module", + 23 + ], + "PDDW16SDGZ_H_G": [ + "PDDW16SDGZ_H_G", + "HiTWu", + "module", + 24 + ], + "PDDW16SDGZ_V_G": [ + "PDDW16SDGZ_V_G", + "ebe78", + "module", + 25 + ], + "ulink_frame_receiver_0000": [ + "ulink_frame_receiver_0000", + "P3BwM", + "module", + 123 + ], + "PRDW08SDGZ_H_G": [ + "PRDW08SDGZ_H_G", + "S90qD", + "module", + 50 + ], + "PDUW04SDGZ_V_G": [ + "PDUW04SDGZ_V_G", + "mJZpP", + "module", + 29 + ], + "PVDD2DGZ_H_G": [ + "PVDD2DGZ_H_G", + "nULrd", + "module", + 82 + ], + "PDUW04DGZ_V_G": [ + "PDUW04DGZ_V_G", + "QGhk6", + "module", + 27 + ], + "syn_fwft_fifo": [ + "syn_fwft_fifo", + "gzftm", + "module", + 117 + ], + "reset_tb": [ + "reset_tb", + "Q3Wk7", + "module", + 148 + ], + "PDUW04SDGZ_H_G": [ + "PDUW04SDGZ_H_G", + "wGYhm", + "module", + 28 + ], + "PDUW08DGZ_H_G": [ + "PDUW08DGZ_H_G", + "KkPJH", + "module", + 30 + ], + "PRUW12SDGZ_V_G": [ + "PRUW12SDGZ_V_G", + "yt645", + "module", + 67 + ], + "PRDW12SDGZ_V_G": [ + "PRDW12SDGZ_V_G", + "zIUFF", + "module", + 55 + ], + "PDUW08SDGZ_H_G": [ + "PDUW08SDGZ_H_G", + "gxqJp", + "module", + 32 + ], + "pulse_generator": [ + "pulse_generator", + "aJYLF", + "module", + 126 + ], + "PRCUT_G": [ + "PRCUT_G", + "uQmb5", + "module", + 46 + ], + "PDUW12DGZ_H_G": [ + "PDUW12DGZ_H_G", + "HYpLe", + "module", + 34 + ], + "PDUW08SDGZ_V_G": [ + "PDUW08SDGZ_V_G", + "UxPrL", + "module", + 33 + ], + "PDUW12SDGZ_H_G": [ + "PDUW12SDGZ_H_G", + "uKPxf", + "module", + 36 + ], + "spi_sys_0000": [ + "spi_sys_0000", + "QT8j3", + "module", + 144 + ], + "PVDD1DGZ_V_G": [ + "PVDD1DGZ_V_G", + "sPggV", + "module", + 79 + ], + "iopad": [ + "iopad", + "ga3jL", + "module", + 114 + ], + "PRDW08DGZ_H_G": [ + "PRDW08DGZ_H_G", + "swWa5", + "module", + 48 + ], + "PDUW16DGZ_V_G": [ + "PDUW16DGZ_V_G", + "FDqaf", + "module", + 39 + ], + "PVSS1AC_H_G": [ + "PVSS1AC_H_G", + "EZJLH", + "module", + 92 + ], + "PRUW12DGZ_H_G": [ + "PRUW12DGZ_H_G", + "hpMjC", + "module", + 64 + ], + "PDXOEDG_H_G": [ + "PDXOEDG_H_G", + "IYQDs", + "module", + 42 + ], + "crc32": [ + "crc32", + "T59nH", + "module", + 122 + ], + "PVDD2POC_H_G": [ + "PVDD2POC_H_G", + "avdwk", + "module", + 84 + ], + "PENDCAP_G": [ + "PENDCAP_G", + "bhWYh", + "module", + 44 + ], + "PRDW08SDGZ_V_G": [ + "PRDW08SDGZ_V_G", + "JznNw", + "module", + 51 + ], + "PVSS3A_H_G": [ + "PVSS3A_H_G", + "jsR1C", + "module", + 106 + ], + "sirv_gnrl_xchecker": [ + "sirv_gnrl_xchecker", + "CjC7H", + "module", + 125 + ], + "PRDW16DGZ_H_G": [ + "PRDW16DGZ_H_G", + "EEqKt", + "module", + 56 + ], + "PRDW12DGZ_H_G": [ + "PRDW12DGZ_H_G", + "VaZm2", + "module", + 52 + ], + "PRDW12DGZ_V_G": [ + "PRDW12DGZ_V_G", + "ZKk4u", + "module", + 53 + ], + "da4008_chip_top": [ + "da4008_chip_top", + "ircEj", + "module", + 141 + ], + "PRDW12SDGZ_H_G": [ + "PRDW12SDGZ_H_G", + "fTzb4", + "module", + 54 + ], + "PRUW08DGZ_H_G": [ + "PRUW08DGZ_H_G", + "fLemy", + "module", + 60 + ], + "PVSS2ANA_H_G": [ + "PVSS2ANA_H_G", + "g8kcb", + "module", + 102 + ], + "PRUW08DGZ_V_G": [ + "PRUW08DGZ_V_G", + "EtT2L", + "module", + 61 + ], + "PRUW08SDGZ_H_G": [ + "PRUW08SDGZ_H_G", + "gwpgC", + "module", + 62 + ], + "PRUW12DGZ_V_G": [ + "PRUW12DGZ_V_G", + "pucZW", + "module", + 65 + ], + "PVDD3A_V_G": [ + "PVDD3A_V_G", + "t6fPF", + "module", + 87 + ], + "PRUW12SDGZ_H_G": [ + "PRUW12SDGZ_H_G", + "EkH6u", + "module", + 66 + ], + "PRUW16DGZ_H_G": [ + "PRUW16DGZ_H_G", + "AVYgt", + "module", + 68 + ], + "PRUW16DGZ_V_G": [ + "PRUW16DGZ_V_G", + "ErxQ3", + "module", + 69 + ], + "PVDD1A_H_G": [ + "PVDD1A_H_G", + "zNPu5", + "module", + 72 + ], + "PVDD1A_V_G": [ + "PVDD1A_V_G", + "CNBi6", + "module", + 73 + ], + "sirv_gnrl_ltch": [ + "sirv_gnrl_ltch", + "UTi0b", + "module", + 128 + ], + "PVDD1AC_H_G": [ + "PVDD1AC_H_G", + "W9VnM", + "module", + 74 + ], + "PVDD1AC_V_G": [ + "PVDD1AC_V_G", + "qn6Yx", + "module", + 75 + ], + "PVDD1ANA_H_G": [ + "PVDD1ANA_H_G", + "fEWTj", + "module", + 76 + ], + "awg_top": [ + "awg_top", + "J5zQK", + "module", + 137 + ], + "PVDD1DGZ_H_G": [ + "PVDD1DGZ_H_G", + "Eie6s", + "module", + 78 + ], + "PVSS2AC_V_G": [ + "PVSS2AC_V_G", + "YBQ1m", + "module", + 101 + ], + "PVSS3AC_V_G": [ + "PVSS3AC_V_G", + "i0k2A", + "module", + 109 + ], + "PVDD3AC_V_G": [ + "PVDD3AC_V_G", + "rZC3e", + "module", + 89 + ], + "PVDD2DGZ_V_G": [ + "PVDD2DGZ_V_G", + "LSxxn", + "module", + 83 + ], + "PVDD2POC_V_G": [ + "PVDD2POC_V_G", + "urn8Q", + "module", + 85 + ], + "PVDD3AC_H_G": [ + "PVDD3AC_H_G", + "U0PST", + "module", + 88 + ], + "tsdn28hpcpuhdb4096x128m4mw_170a_Int_Array": [ + "tsdn28hpcpuhdb4096x128m4mw_170a_Int_Array", + "bghMB", + "module", + 113 + ], + "PVSS1A_V_G": [ + "PVSS1A_V_G", + "ZmPik", + "module", + 91 + ], + "PVSS1AC_V_G": [ + "PVSS1AC_V_G", + "I7RzE", + "module", + 93 + ], + "PVSS1ANA_H_G": [ + "PVSS1ANA_H_G", + "HtwuV", + "module", + 94 + ], + "PVSS1DGZ_V_G": [ + "PVSS1DGZ_V_G", + "jHcbf", + "module", + 97 + ], + "PVSS2A_H_G": [ + "PVSS2A_H_G", + "usz4x", + "module", + 98 + ], + "PVSS2A_V_G": [ + "PVSS2A_V_G", + "fMI2k", + "module", + 99 + ], + "PVSS2AC_H_G": [ + "PVSS2AC_H_G", + "TqmdJ", + "module", + 100 + ], + "PVSS2ANA_V_G": [ + "PVSS2ANA_V_G", + "Md441", + "module", + 103 + ], + "PVSS2DGZ_H_G": [ + "PVSS2DGZ_H_G", + "ke5cH", + "module", + 104 + ], + "PVSS2DGZ_V_G": [ + "PVSS2DGZ_V_G", + "S5Dr6", + "module", + 105 + ], + "PVSS3A_V_G": [ + "PVSS3A_V_G", + "VSdee", + "module", + 107 + ], + "tsdn28hpcpuhdb4096x128m4mw_170a": [ + "tsdn28hpcpuhdb4096x128m4mw_170a", + "UJ4u7", + "module", + 112 + ], + "PVSS3AC_H_G": [ + "PVSS3AC_H_G", + "B0f3F", + "module", + 108 + ], + "PVSS3DGZ_H_G": [ + "PVSS3DGZ_H_G", + "rq1J0", + "module", + 110 + ], + "PVSS3DGZ_V_G": [ + "PVSS3DGZ_V_G", + "IZu3i", + "module", + 111 + ], + "DEM_PhaseSync_4008": [ + "DEM_PhaseSync_4008", + "sIRhK", + "module", + 138 + ], + "dacif_0000": [ + "dacif_0000", + "yeRHW", + "module", + 116 + ], + "dac_regfile": [ + "dac_regfile", + "LR0zI", + "module", + 118 + ], + "ulink_rx": [ + "ulink_rx", + "dteMU", + "module", + 119 + ], + "ulink_descrambler_128": [ + "ulink_descrambler_128", + "qxEhc", + "module", + 121 + ], + "sram_if": [ + "sram_if", + "NABmh", + "module", + 130 + ], + "sram_if_0000": [ + "sram_if_0000", + "nJgqZ", + "module", + 131 + ], + "sram_if_0001": [ + "sram_if_0001", + "z4wk8", + "module", + 132 + ], + "sram_if_0002": [ + "sram_if_0002", + "bEAZ8", + "module", + 133 + ], + "sram_dmux_w_0000": [ + "sram_dmux_w_0000", + "dc6nH", + "module", + 134 + ], + "clk_regfile": [ + "clk_regfile", + "jAdLC", + "module", + 136 + ], + "DA4008_DEM_Parallel_PRBS_1CH": [ + "DA4008_DEM_Parallel_PRBS_1CH", + "cQW1k", + "module", + 139 + ], + "DA4008_DEM_Parallel_PRBS_64CH": [ + "DA4008_DEM_Parallel_PRBS_64CH", + "q09PC", + "module", + 140 + ], + "spi_slave": [ + "spi_slave", + "eAsJz", + "module", + 143 + ], + "spi_if": [ + "spi_if", + "IHYdB", + "module", + 145 + ], + "clk_gen": [ + "clk_gen", + "MEIvW", + "module", + 146 + ], + "DEM_Reverse_64CH_0000": [ + "DEM_Reverse_64CH_0000", + "YnCHV", + "module", + 147 + ], + "DW_sync_0000": [ + "DW_sync_0000", + "zVfcK", + "module", + 149 + ], + "DW_pulse_sync_0000": [ + "DW_pulse_sync_0000", + "Ss3zK", + "module", + 150 + ], + "lvds_if": [ + "lvds_if", + "nS0i0", + "module", + 151 + ], + "TB": [ + "TB", + "sH4Fc", + "module", + 152 + ], + "...MASTER...": [ + "SIM", + "amcQw", + "module", + 153 + ] +} \ No newline at end of file diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/constraint.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/constraint.sdb new file mode 100644 index 0000000..82e87e8 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/constraint.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/covg_defs b/DA4008_V1.2/sim/chip_top/simv.daidir/covg_defs new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/.version b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/.version new file mode 100644 index 0000000..ed555f5 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/.version @@ -0,0 +1,4 @@ +O-2018.09-SP2_Full64 +Build Date = Feb 28 2019 22:34:30 +RedHat +Compile Location: /home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/AllModulesSkeletons.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/AllModulesSkeletons.sdb new file mode 100644 index 0000000..645927b Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/AllModulesSkeletons.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/HsimSigOptDb.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/HsimSigOptDb.sdb new file mode 100644 index 0000000..a582302 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/HsimSigOptDb.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/dumpcheck.db b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/dumpcheck.db new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/dve_debug.db.gz b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/dve_debug.db.gz new file mode 100644 index 0000000..a58895a Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/dve_debug.db.gz differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db new file mode 100755 index 0000000..0efe198 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db @@ -0,0 +1,9 @@ +#!/bin/sh -h +PYTHONHOME=/opt/synopsys/vcs-mx/O-2018.09-SP2/etc/search/pyh +export PYTHONHOME +PYTHONPATH=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/pylib27 +export PYTHONPATH +LD_LIBRARY_PATH=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib:/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/pylib27 +export LD_LIBRARY_PATH +/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/vcsfind_create_index.exe -z "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/./idents_X4vtNx.xml.gz" "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" +\mv "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.db" diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/check_fsearch_db b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/check_fsearch_db new file mode 100755 index 0000000..1c1ff54 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/check_fsearch_db @@ -0,0 +1,57 @@ +#!/bin/sh -h + +FILE_PATH="/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch" +lockfile="${FILE_PATH}"/lock + +FSearch_lock_release() { + echo "" > /dev/null +} +create_fsearch_db_ctrl() { + if [ -s "${FILE_PATH}"/fsearch.stat ]; then + if [ -s "${FILE_PATH}"/fsearch.log ]; then + echo "ERROR building identifier database failed. Check ${FILE_PATH}/fsearch.log" + else + cat "${FILE_PATH}"/fsearch.stat + fi + return + fi + nohup "$1" > "${FILE_PATH}"/fsearch.log 2>&1 193>/dev/null & + MY_PID=`echo $!` + BUILDER="pid ${MY_PID} ${USER}@${hostname}" + echo "INFO Started building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." + echo "INFO Still building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." > "${FILE_PATH}"/fsearch.stat + return +} + +dir_name=`/bin/dirname "$0"` +if [ "${dir_name}" = "." ]; then + cd $dir_name + dir_name=`/bin/pwd` +fi +if [ -d "$dir_name"/../../../../../../../../../../.. ]; then + cd "$dir_name"/../../../../../../../../../../.. +fi + +if [ -f "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db" ]; then + if [ ! -f "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.db" ]; then + if [ "$#" -eq 1 ] && [ "x$1" == "x-background" ]; then + trap FSearch_lock_release EXIT + ( + flock 193 + create_fsearch_db_ctrl "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db" + exit 193 + ) 193> "$lockfile" + rstat=$? + if [ "${rstat}"x != "193x" ]; then + exit $rstat + fi + else + "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db" + if [ -f "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then + rm -f "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" + fi + fi + elif [ -f "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then + rm -f "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" + fi +fi diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/idents_X4vtNx.xml.gz b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/idents_X4vtNx.xml.gz new file mode 100644 index 0000000..56532b3 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/idents_X4vtNx.xml.gz differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz new file mode 100644 index 0000000..f24a0fd Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/src_files_verilog b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/src_files_verilog new file mode 100644 index 0000000..376b419 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/src_files_verilog @@ -0,0 +1,48 @@ +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/lib/tphn28hpcpgv18.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/lib/tsdn28hpcpuhdb4096x128m4mw_170a_ffg0p99v0c.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/DEM_Reverse.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/DEM_Reverse_64CH.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/DW_pulse_sync.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/DW_reset_sync.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/DW_stream_sync.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/DW_sync.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/LVDS_DRIVER.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/SPI_DRIVER.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/clk_gen.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/clock_tb.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/reset_tb.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/spi_if.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/awg/awg_ctrl.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/awg/awg_top.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/clk/clk_regfile.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/comm/pulse_generator.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/comm/ramp_gen.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/comm/sirv_gnrl_dffs.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/comm/sirv_gnrl_xchecker.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/comm/syncer.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/dac_regfile/dac_regfile.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/dacif/dacif.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/define/chip_define.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/define/chip_undefine.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/dem/DA4008_DEM_Parallel_PRBS_1CH.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/dem/DA4008_DEM_Parallel_PRBS_64CH.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/dem/DEM_PhaseSync_4008.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/fifo/syn_fwft_fifo.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/io/iopad.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/lvds/ulink_rx.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/memory/bhv_spram.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/memory/dpram.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/memory/spram.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/memory/sram_dmux.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/memory/sram_if.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/memory/tsmc_dpram.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/rstgen/rst_gen_unit.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/rstgen/rst_sync.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/spi/spi_bus_decoder.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/spi/spi_pll.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/spi/spi_slave.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/spi/spi_sys.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/systemregfile/systemregfile.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/top/da4008_chip_top.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/top/digital_top.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/TB.sv diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/topmodules b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/topmodules new file mode 100644 index 0000000..5dce012 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/topmodules @@ -0,0 +1 @@ +r’LžD•B’–\ƒ$…c–Cšs°1´S¤ ¦%ºg¿)!©t¬x"µ.º<8¦Y©S9Iƒ:“>­B°;“?»¹¨5¨7¥2›AŸ*')°.´Q)*¤ ¦$*+Ÿs£xB“Iµ,º8D“O¦X©PE“P‰6Ž›tŸn§ª7¯\³2¤[¦e¬Z¯>$ m‹Ž=¤¦:†2ˆB ;¤§Rªe¯i´ †F‰)¤B¦L¤m¦w¬l¯O†LŠ"¦V©I¨n¬Aµ»l ¥¶O \ No newline at end of file diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/vir.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/vir.sdb new file mode 100644 index 0000000..9b4dea7 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/vir.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/eblklvl.db b/DA4008_V1.2/sim/chip_top/simv.daidir/eblklvl.db new file mode 100644 index 0000000..2870040 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/eblklvl.db differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/elabmoddb.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/elabmoddb.sdb new file mode 100644 index 0000000..4d03f67 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/elabmoddb.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/external_functions b/DA4008_V1.2/sim/chip_top/simv.daidir/external_functions new file mode 100644 index 0000000..394a9dd --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/simv.daidir/external_functions @@ -0,0 +1,129 @@ +pli $fsdbDumpvars novas_call_fsdbDumpvars - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpvarsES novas_call_fsdbDumpvarsES - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpMDA novas_call_fsdbDumpMDA - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpSVA novas_call_fsdbDumpSVA - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpvarsByFile novas_call_fsdbDumpvarsByFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbSuppress novas_call_fsdbSuppress - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpon novas_call_fsdbDumpon - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpoff novas_call_fsdbDumpoff - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbSwitchDumpfile novas_call_fsdbSwitchDumpfile - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpfile novas_call_fsdbDumpfile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbAutoSwitchDumpfile novas_call_fsdbAutoSwitchDumpfile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpFinish novas_call_fsdbDumpFinish - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpflush novas_call_fsdbDumpflush - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbLog novas_call_fsdbLog - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbAddRuntimeSignal novas_call_fsdbAddRuntimeSignal - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpSC novas_call_fsdbDumpSC - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpvarsToFile novas_call_fsdbDumpvarsToFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_create_transaction_stream novas_call_sps_create_transaction_stream - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_begin_transaction novas_call_sps_begin_transaction - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_end_transaction novas_call_sps_end_transaction - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_free_transaction novas_call_sps_free_transaction - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_add_attribute novas_call_sps_add_attribute - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_update_label novas_call_sps_update_label - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_add_relation novas_call_sps_add_relation - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbWhatif novas_call_fsdbWhatif - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $paa_init novas_call_paa_init - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $paa_sync novas_call_paa_sync - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpClassMethod novas_call_fsdbDumpClassMethod - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbSuppressClassMethod novas_call_fsdbSuppressClassMethod - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbSuppressClassProp novas_call_fsdbSuppressClassProp - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpMDAByFile novas_call_fsdbDumpMDAByFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_create_stream_begin novas_call_fsdbEvent_create_stream_begin - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_define_attribute novas_call_fsdbEvent_add_stream_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_create_stream_end novas_call_fsdbEvent_create_stream_end - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_begin novas_call_fsdbEvent_begin - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_set_label novas_call_fsdbEvent_set_label - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_attribute novas_call_fsdbEvent_add_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_tag novas_call_fsdbEvent_add_tag - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_end novas_call_fsdbEvent_end - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_relation novas_call_fsdbEvent_add_relation - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_get_error_code novas_call_fsdbEvent_get_error_code - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_stream_attribute novas_call_fsdbTrans_add_stream_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_scope_attribute novas_call_fsdbTrans_add_scope_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_interactive novas_call_sps_interactive - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_test novas_call_sps_test - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpClassObject novas_call_fsdbDumpClassObject - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpClassObjectByFile novas_call_fsdbDumpClassObjectByFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $ridbDump novas_call_ridbDump - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_flush_file novas_call_sps_flush_file - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpPSL novas_call_fsdbDumpPSL - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumplimit novas_call_fsdbDumplimit - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpvars novas_call_fsdbDumpvars - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsES novas_call_fsdbDumpvarsES - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDA novas_call_fsdbDumpMDA - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVA novas_call_fsdbDumpSVA - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsByFile novas_call_fsdbDumpvarsByFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppress novas_call_fsdbSuppress - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpon novas_call_fsdbDumpon - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpoff novas_call_fsdbDumpoff - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSwitchDumpfile novas_call_fsdbSwitchDumpfile - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpfile novas_call_fsdbDumpfile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbAutoSwitchDumpfile novas_call_fsdbAutoSwitchDumpfile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpFinish novas_call_fsdbDumpFinish - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpflush novas_call_fsdbDumpflush - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbLog novas_call_fsdbLog - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbAddRuntimeSignal novas_call_fsdbAddRuntimeSignal - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSC novas_call_fsdbDumpSC - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsToFile novas_call_fsdbDumpvarsToFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_create_transaction_stream novas_call_sps_create_transaction_stream - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_begin_transaction novas_call_sps_begin_transaction - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_end_transaction novas_call_sps_end_transaction - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_free_transaction novas_call_sps_free_transaction - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_add_attribute novas_call_sps_add_attribute - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_update_label novas_call_sps_update_label - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_add_relation novas_call_sps_add_relation - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbWhatif novas_call_fsdbWhatif - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $paa_init novas_call_paa_init - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $paa_sync novas_call_paa_sync - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassMethod novas_call_fsdbDumpClassMethod - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppressClassMethod novas_call_fsdbSuppressClassMethod - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppressClassProp novas_call_fsdbSuppressClassProp - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAByFile novas_call_fsdbDumpMDAByFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_create_stream_begin novas_call_fsdbEvent_create_stream_begin - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_define_attribute novas_call_fsdbEvent_add_stream_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_create_stream_end novas_call_fsdbEvent_create_stream_end - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_begin novas_call_fsdbEvent_begin - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_set_label novas_call_fsdbEvent_set_label - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_attribute novas_call_fsdbEvent_add_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_tag novas_call_fsdbEvent_add_tag - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_end novas_call_fsdbEvent_end - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_relation novas_call_fsdbEvent_add_relation - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_get_error_code novas_call_fsdbEvent_get_error_code - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_stream_attribute novas_call_fsdbTrans_add_stream_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_scope_attribute novas_call_fsdbTrans_add_scope_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_interactive novas_call_sps_interactive - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_test novas_call_sps_test - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassObject novas_call_fsdbDumpClassObject - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassObjectByFile novas_call_fsdbDumpClassObjectByFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $ridbDump novas_call_ridbDump - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_flush_file novas_call_sps_flush_file - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSL novas_call_fsdbDumpPSL - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDisplay novas_call_fsdbDisplay - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumplimit novas_call_fsdbDumplimit - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMem novas_call_fsdbDumpMem - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemNow novas_call_fsdbDumpMemNow - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemInScope novas_call_fsdbDumpMemInScope - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDANow novas_call_fsdbDumpMDANow - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAOnChange novas_call_fsdbDumpMDAOnChange - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAInScope novas_call_fsdbDumpMDAInScope - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemInFile novas_call_fsdbDumpMemInFile - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSLon novas_call_fsdbDumpPSLon - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSLoff novas_call_fsdbDumpPSLoff - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVAon novas_call_fsdbDumpSVAon - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVAoff novas_call_fsdbDumpSVAoff - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpStrength novas_call_fsdbDumpStrength - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSingle novas_call_fsdbDumpSingle - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpIO novas_call_fsdbDumpIO - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPattern novas_call_fsdbDumpPattern - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSubstituteHier novas_call_fsdbSubstituteHier - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $dumpports DumpPortsIeeeCALL - DumpPortsMISC +pli $lsi_dumpports DumpPortsLsiCALL - DumpPortsMISC +pli $dumpportson DumpPortsOnCALL - DumpPortsMISC +pli $dumpportsoff DumpPortsOffCALL - DumpPortsMISC +pli $dumpportsflush DumpPortsFlushCALL - DumpPortsMISC +pli $simlearn simLearnCall simLearnCheck simLearnMisc +pli $dumpportsall DumpPortsAllCALL - DumpPortsMISC +pli $dumpportslimit DumpPortsLimitCALL - DumpPortsMISC +pli $countdrivers CountDriversCALL - - +pli $vcsmemprof DMMemProfCALL DMMemProfCheck DMMemProfMISC diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/hslevel_callgraph.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/hslevel_callgraph.sdb new file mode 100644 index 0000000..a00346b Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/hslevel_callgraph.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/hslevel_level.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/hslevel_level.sdb new file mode 100644 index 0000000..4cd2f62 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/hslevel_level.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/hslevel_rtime_level.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/hslevel_rtime_level.sdb new file mode 100644 index 0000000..8153356 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/hslevel_rtime_level.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/hsscan_cfg.dat b/DA4008_V1.2/sim/chip_top/simv.daidir/hsscan_cfg.dat new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/indcall.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/indcall.sdb new file mode 100644 index 0000000..c8ddf48 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/indcall.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32553.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32553.sdb new file mode 100644 index 0000000..50736b6 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32553.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32573.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32573.sdb new file mode 100644 index 0000000..520f26d Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32573.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32574.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32574.sdb new file mode 100644 index 0000000..35d2e97 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32574.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32575.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32575.sdb new file mode 100644 index 0000000..db9d5d6 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32575.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32576.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32576.sdb new file mode 100644 index 0000000..574a192 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32576.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32577.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32577.sdb new file mode 100644 index 0000000..c482d66 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32577.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32578.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32578.sdb new file mode 100644 index 0000000..0e5abe3 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32578.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32579.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32579.sdb new file mode 100644 index 0000000..5dd9049 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/indcall_32579.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/nsparam.dat b/DA4008_V1.2/sim/chip_top/simv.daidir/nsparam.dat new file mode 100644 index 0000000..1afe863 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/nsparam.dat differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/pcc.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/pcc.sdb new file mode 100644 index 0000000..d7c1589 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/pcc.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/pcxpxmr.dat b/DA4008_V1.2/sim/chip_top/simv.daidir/pcxpxmr.dat new file mode 100644 index 0000000..ee5778d Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/pcxpxmr.dat differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/prof.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/prof.sdb new file mode 100644 index 0000000..76179fc Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/prof.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/rmapats.dat b/DA4008_V1.2/sim/chip_top/simv.daidir/rmapats.dat new file mode 100644 index 0000000..cc1f304 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/rmapats.dat differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/rmapats.so b/DA4008_V1.2/sim/chip_top/simv.daidir/rmapats.so new file mode 100755 index 0000000..6df9faa Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/rmapats.so differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/saifNetInfo.db b/DA4008_V1.2/sim/chip_top/simv.daidir/saifNetInfo.db new file mode 100644 index 0000000..a69d3f9 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/simv.daidir/saifNetInfo.db @@ -0,0 +1,22 @@ +7 +TB.U_da4008_chip_top.U_iopad.PDDW08SDGZ_V_G_sync_out +C +Scal +TB.U_da4008_chip_top.U_iopad.PDUW08SDGZ_V_G_irq +C +Scal +TB.U_da4008_chip_top.U_iopad.PDUW08SDGZ_V_G_miso +C +Scal +tsmc_dpram +spram_512X8192_generation®BWEBA +All +tsmc_dpram +spram_512X8192_generation®BWEBB +All +tsmc_dpram +spram_512X8192_generation®U_CEBA +All +tsmc_dpram +spram_512X8192_generation®U_CEBB +All diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/simv.kdb b/DA4008_V1.2/sim/chip_top/simv.daidir/simv.kdb new file mode 100644 index 0000000..68eacf4 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/simv.daidir/simv.kdb @@ -0,0 +1,16 @@ +rc file Version 1.0 + +[Design] +COMPILE_PATH=/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top +SystemC=FALSE +UUM=FALSE +KDB=FALSE +USE_NOVAS_HOME=FALSE +COSIM=FALSE +TOP=PCLAMP_G PCLAMPC_H_G PCLAMPC_V_G PDB3A_H_G PDB3A_V_G PDB3AC_H_G PDB3AC_V_G PDDW04DGZ_H_G PDDW04DGZ_V_G PDDW04SDGZ_H_G PDDW08DGZ_H_G PDDW08DGZ_V_G PDDW08SDGZ_H_G PDDW08SDGZ_V_G PDDW12DGZ_H_G PDDW12DGZ_V_G PDDW12SDGZ_H_G PDDW12SDGZ_V_G PDDW16DGZ_H_G PDDW16DGZ_V_G PDDW16SDGZ_H_G PDDW16SDGZ_V_G PDUW04DGZ_H_G PDUW04DGZ_V_G PDUW04SDGZ_H_G PDUW08DGZ_H_G PDUW08DGZ_V_G PDUW08SDGZ_H_G PDUW12DGZ_H_G PDUW12DGZ_V_G PDUW12SDGZ_H_G PDUW12SDGZ_V_G PDUW16DGZ_H_G PDUW16DGZ_V_G PDUW16SDGZ_H_G PDUW16SDGZ_V_G PDXOEDG_H_G PDXOEDG_V_G PENDCAP_G PENDCAPA_G PRCUT_G PRCUTA_G PRDW08DGZ_H_G PRDW08DGZ_V_G PRDW08SDGZ_H_G PRDW08SDGZ_V_G PRDW12DGZ_H_G PRDW12DGZ_V_G PRDW12SDGZ_H_G PRDW12SDGZ_V_G PRDW16DGZ_H_G PRDW16DGZ_V_G PRDW16SDGZ_H_G PRDW16SDGZ_V_G PRUW08DGZ_H_G PRUW08DGZ_V_G PRUW08SDGZ_H_G PRUW08SDGZ_V_G PRUW12DGZ_H_G PRUW12DGZ_V_G PRUW12SDGZ_H_G PRUW12SDGZ_V_G PRUW16DGZ_H_G PRUW16DGZ_V_G PRUW16SDGZ_H_G PRUW16SDGZ_V_G PVDD1A_H_G PVDD1A_V_G PVDD1AC_H_G PVDD1AC_V_G PVDD1ANA_H_G PVDD1ANA_V_G PVDD1DGZ_H_G PVDD1DGZ_V_G PVDD2ANA_H_G PVDD2ANA_V_G PVDD2DGZ_H_G PVDD2DGZ_V_G PVDD2POC_H_G PVDD2POC_V_G PVDD3A_H_G PVDD3A_V_G PVDD3AC_H_G PVDD3AC_V_G PVSS1A_H_G PVSS1A_V_G PVSS1AC_H_G PVSS1AC_V_G PVSS1ANA_H_G PVSS1ANA_V_G PVSS1DGZ_H_G PVSS1DGZ_V_G PVSS2A_H_G PVSS2A_V_G PVSS2AC_H_G PVSS2AC_V_G PVSS2ANA_H_G PVSS2ANA_V_G PVSS2DGZ_H_G PVSS2DGZ_V_G PVSS3A_H_G PVSS3A_V_G PVSS3AC_H_G PVSS3AC_V_G PVSS3DGZ_H_G PVSS3DGZ_V_G sirv_gnrl_xchecker sirv_gnrl_dffl sirv_gnrl_ltch clk_gen reset_tb TB +OPTION=-ssz -ssv -ssy +ELAB_OPTION=-ssz -ssv -ssy + +[Value] +WREALX=ffff534e50535f58 +WREALZ=ffff534e50535f5a diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/stitch_nsparam.dat b/DA4008_V1.2/sim/chip_top/simv.daidir/stitch_nsparam.dat new file mode 100644 index 0000000..0357d47 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/stitch_nsparam.dat differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/tt.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/tt.sdb new file mode 100644 index 0000000..f118f49 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/tt.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/ttIncr_32553.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/ttIncr_32553.sdb new file mode 100644 index 0000000..698630c Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/ttIncr_32553.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/ttIncr_32573.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/ttIncr_32573.sdb new file mode 100644 index 0000000..fe16d76 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/ttIncr_32573.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/ttIncr_32574.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/ttIncr_32574.sdb new file mode 100644 index 0000000..84f865e Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/ttIncr_32574.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/ttIncr_32575.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/ttIncr_32575.sdb new file mode 100644 index 0000000..25fe685 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/ttIncr_32575.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/ttIncr_32576.sdb b/DA4008_V1.2/sim/chip_top/simv.daidir/ttIncr_32576.sdb new file mode 100644 index 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mode 100755 index 0000000..403c9c0 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/simv.daidir/vcs_rebuild @@ -0,0 +1,4 @@ +#!/bin/sh -e +# This file is automatically generated by VCS. Any changes you make +# to it will be overwritten the next time VCS is run. +vcs '-full64' '-j8' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+all' '-debug_region+cell+encrypt' '-P' '/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab' '/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a' '+define+DUMP_FSDB' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-cm' 'line+cond+fsm+tgl+branch' '-cm_dir' './coverage/simv.vdb' '-f' 'filelist_vlg.f' '+incdir+./../../rtl/define' '+incdir+./../../rtl/qubitmcu' '+incdir+./../../model' 2>&1 diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_master_hsim_elabout.db b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_master_hsim_elabout.db new file mode 100644 index 0000000..d941a4e --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_master_hsim_elabout.db @@ -0,0 +1,691 @@ +hsDirType 1 +fHsimDesignHasDebugNodes 63 +fNSParam 1024 +fLargeSizeSdfTest 0 +fHsimDelayGateMbme 0 +fNoMergeDelays 0 +fHsimAllMtmPat 0 +fHsimCertRaptMode 0 +fSharedMasterElab 0 +hsimLevelizeDone 1 +fHsimCompressDiag 1 +fHsimPowerOpt 0 +fLoopReportElab 0 +fHsimRtl 0 +fHsimCbkOptVec 1 +fHsimDynamicCcnHeur 1 +fHsimPvcs 0 +fHsimPvcsCcn 0 +fHsimOldLdr 0 +fHsimSingleDB 1 +uVfsGcLimit 50 +fHsimCompatSched 0 +fHsimCompatOrder 0 +fHsimTransUsingdoMpd32 0 +fHsimDynamicElabForGates 1 +fHsimDynamicElabForVectors 0 +fHsimDynamicElabForVectorsAlways 0 +fHsimDynamicElabForVectorsMinputs 0 +fHsimDeferForceSelTillReElab 0 +fHsimModByModElab 1 +fSvNettRealResType 0 +fHsimExprID 1 +fHsimSequdpon 0 +fHsimDatapinOpt 0 +fHsimExprPrune 0 +fHsimMimoGate 0 +fHsimNewChangeCheckFrankch 1 +fHsimNoSched0Front 0 +fHsimNoSched0FrontForMd 1 +fHsimScalReg 0 +fHsimNtbVl 0 +fHsimICTimeStamp 0 +fHsimICDiag 0 +fHsimNewCSDF 1 +vcselabIncrMode 2 +fHsimMPPackDelay 0 +fHsimMultDriver 0 +fHsimPart 0 +fHsimPrlComp 0 +fHsimPartTest 0 +fHsimTestChangeCheck 0 +fHsimTestFlatNodeOrder 0 +fHsimTestNState 0 +fHsimPartDebug 0 +fHsimPartFlags 0 +fHsimOdeSched0 0 +fHsimNewRootSig 1 +fHsimDisableRootSigModeOpt 0 +fHsimTestRootSigModeOpt 0 +fHsimIncrWriteOnce 0 +fHsimUnifInterfaceFlow 1 +fHsimUnifInterfaceFlowDiag 0 +fHsimUnifInterfaceFlowXmrDiag 0 +fHsimUnifInterfaceMultiDrvChk 1 +fHsimXVirForGenerateScope 0 +fHsimCongruencyIntTestI 0 +fHsimCongruencySVA 0 +fHsimCongruencySVADbg 0 +fHsimCongruencyLatchEdgeFix 0 +fHsimCongruencyFlopEdgeFix 0 +fHsimCongruencyXprop 0 +fHsimCongruencyXpropFix 0 +fHsimCongruencyXpropDbsEdge 0 +fHsimCongruencyResetRecoveryDbs 0 +fHsimCongruencyClockControlDiag 0 +fHsimCongruencySampleUpdate 0 +fHsimCongruencyFFDbsFix 0 +fHsimCongruency 0 +fHsimCongruencySlave 0 +fHsimCongruencyCombinedLoads 0 +fHsimCongruencyFGP 0 +fHsimDeraceClockDataUdp 0 +fHsimDeraceClockDataLERUpdate 0 +fHsimCongruencyPC 0 +fHsimCongruencyPCInl 0 +fHsimCongruencyPCDbg 0 +fHsimCongruencyPCNoReuse 0 +fHsimCongruencyDumpHier 0 +fHsimCongruencyResolution 0 +fHsimCongruencyEveBus 0 +fHsimHcExpr 0 +fHsCgOptModOpt 0 +fHsCgOptSlowProp 0 +fHsimCcnOpt 1 +fHsimCcnOpt2 1 +fHsimCcnOpt3 0 +fHsimSmdMap 0 +fHsimSmdDiag 0 +fHsimSmdSimProf 0 +fHsimSgdDiag 0 +fHsimRtDiagLite 0 +fHsimRtDiagLiteCevent 100 +fHsimRtDiag 0 +fHsimSkRtDiag 0 +fHsimDDBSRtdiag 0 +fHsimDbg 0 +fHsimCompWithGates 0 +fHsimMdbDebugOpt 0 +fHsimMdbDebugOptP1 0 +fHsimMdbDebugOptP2 0 +fHsimMdbPruneOpt 1 +fHsimMdbMemOpt 0 +hsimRandValue 0 +fHsimSimMemProfile 0 +fHsimSimTimeProfile 0 +fHsimElabMemProfile 0 +fHsimElabTimeProfile 0 +fHsimElabMemNodesProfile 0 +fHsimElabMemAllNodesProfile 0 +fHsimDisableVpdGatesProfile 0 +fHsimFileProfile 0 +fHsimCountProfile 0 +fHsimXmrDefault 1 +fHsimFuseWireAndReg 0 +fHsimFuseSelfDrvLogic 0 +fHsimFuseProcess 0 +fHsimNoStitchDump 0 +fHsimAllExtXmrs 0 +fHsimAllXmrs 1 +fHsimMvsimDb 0 +fHsimTaskFuncXmrs 0 +fHsimTaskFuncXmrsDbg 0 +fHsimAllTaskFuncXmrs 0 +fHsimPageArray 16383 +fHsimPageControls 16383 +hsDfsNodePageElems 0 +hsNodePageElems 0 +hsFlatNodePageElems 0 +hsGateMapPageElems 0 +hsGateOffsetPageElems 0 +hsGateInputOffsetPageElems 0 +hsDbsOffsetPageElems 0 +hsMinPulseWidthPageElems 0 +hsNodeUpPatternPageElems 0 +hsNodeDownPatternPageElems 0 +hsNodeUpOffsetPageElems 0 +hsNodeEblkOffsetPageElems 0 +hsNodeDownOffsetPageElems 0 +hsNodeUpdateOffsetPageElems 0 +hsSdfOffsetPageElems 0 +fHsimPageAllLevelData 0 +fHsimAggrCg 0 +fHsimViWire 1 +fHsimPcCbOpt 1 +fHsimAmsTunneling 0 +fHsimAmsTunnelingDiag 0 +fHsimScUpwardXmrNoSplit 1 +fHsimOrigNdbViewOnly 0 +fHsimVcsInterface 1 +fHsimVcsInterfaceAlias 1 +fHsimSVTypesIntf 1 +fUnifiedAssertCtrlDiag 0 +fHsimEnable2StateScal 0 +fHsimDisable2StateScalIbn 0 +fHsimVcsInterfaceAliasDbg 0 +fHsimVcsInterfaceDbg 0 +fHsimVcsVirtIntfDbg 0 +fHsimVcsAllIntfVarMem 0 +fHsimCheckVIDynLoadOffsets 0 +fHsimModInline 1 +fHsimModInlineDbg 0 +fHsimPCDrvLoadDbg 0 +fHsimDrvChk 1 +fHsimRtlProcessingNeeded 0 +fHsimGrpByGrpElab 0 +fHsimGrpByGrpElabMaster 0 +fHsimNoParentSplitPC 0 +fHsimNusymMode 0 +fHsimOneIntfPart 0 +fHsimCompressInSingleDb 2 +fHsimCompressFlatDb 0 +fHsimNoTime0Sched 1 +fHsimMdbVectorizeInstances 0 +fHsimMdbSplitGates 0 +fHsimDeleteInstances 0 +fHsimUserDeleteInstances 0 +fHsimDeleteGdb 0 +fHsimDeleteInstancesMdb 0 +fHsimShortInstMap 0 +fHsimMdbVectorizationDump 0 +fHsimScanVectorize 0 +fHsimParallelScanVectorize 0 +noInstsInVectorization 0 +cHsimNonReplicatedInstances 0 +fHsimScanRaptor 0 +fHsimConfigFileCount 0 +fHsimVectorConstProp 0 +fHsimPromoteParam 0 +fHsimNoVecInRaptor 0 +fRaptorDumpVal 0 +fRaptorVecNodes 0 +fRaptorVecNodes2 0 +fRaptorNonVecNodes 0 +fRaptorBdrNodes 0 +fRaptorVecGates 0 +fRaptorNonVecGates 0 +fRaptorTotalNodesBeforeVect 0 +fRaptorTotalGatesBeforeVect 0 +fHsimCountRaptorBits 0 +fHsimNewEvcd 1 +fHsimNewEvcdMX 0 +fHsimNewEvcdVecRoot 1 +fHsimNewEvcdForce 1 +fHsimNewEvcdTest 0 +fHsimNewEvcdObnDrv 1 +fHsimNewEvcdW 1 +fHsimNewEvcdWTest 0 +fHsimEvcdDbgFlags 0 +fHsimNewEvcdMultiDrvFmt 1 +fHsimDumpOffsetData 1 +fFlopGlitchDetect 0 +fHsimClkGlitch 0 +fHsimGlitchDumpOnce 0 +fHsimDynamicElab 1 +fHsimCgVectors2Debug 0 +fHsimOdeDynElab 0 +fHsimOdeDynElabDiag 0 +fHsimOdeSeqUdp 0 +fHsimOdeSeqUdpXEdge 0 +fHsimOdeSeqUdpDbg 0 +fHsimOdeRmvSched0 0 +fHsimAllLevelSame 0 +fHsimRtlDbsList 0 +fHsimPePort 0 +fHsimPeXmr 0 +fHsimPePortDiag 0 +fHsimUdpDbs 0 +fHsimRemoveDbgCaps 0 +fFsdbGateOnepassTraverse 0 +fHsimAllowVecGateInVpd 1 +fHsimAllowAllVecGateInVpd 0 +fHsimAllowUdpInVpd 1 +fHsimAllowAlwaysCombInVpd 1 +fHsimAllowAlwaysCombCmpDvcSimv 0 +fHsimAllowAlwaysCombDbg 0 +fHsimMakeAllP2SPrimary 0 +fHsimMakeAllSeqPrimary 0 +fHsimNoCcnDump 0 +fHsimFsdbProfDiag 0 +fVpdSeqGate 0 +fVpdUseMaxBCode 0 +fVpdHsIntVecGate 0 +fVpdHsCmplxVecGate 0 +fVpdHsVecGateDiags 0 +fSeqGateCodePatch 0 +fVpdLongFaninOpt 0 +fVpdSeqLongFaninOpt 0 +fVpdNoLoopDetect 0 +fVpdNoSeqLoopDetect 0 +fVpdOptAllowConstDriver 0 +fVpdAllowCellReconstruction 0 +fVpdRtlForSharedLib 0 +fHsimVpdOptGate 1 +fHsimVpdOptDelay 0 +fHsimVpdOptMPDelay 0 +fHsimCbkOptDiag 0 +fHsimSK 0 +fHsimSharedKernel 1 +fHsimOnepass 0 +fHsimStitchNew 0 +fHsimParallelLevelize 0 +fHsimParallelLevelizeDbg 0 +fHsimSeqUdpDbsByteArray 0 +fHsimCoLocate 0 +fHsimSeqUdpEblkOpt 0 +fHsimSeqUdpEblkOptDiag 0 +fHsimGateInputAndDbsOffsetsOpt 1 +fHsimUdpDynElab 0 +fHsimCompressData 4 +fHsimIgnoreZForDfuse 1 +fHsimIgnoreDifferentCaps 0 +fHandleGlitchQC 1 +fGlitchDetectForAllRtlLoads 0 +fHsimFuseConstDriversOpt 1 +fHsimMdSchedTr 0 +fHsimIgnoreReElab 0 +fHsimFuseMultiDrivers 0 +fHsimNoSched0Reg 0 +fHsimAmsFusionEnabled 0 +fHsimRtlDbs 0 +fHsimWakeupId 0 +fHsimPassiveIbn 0 +fHsimBcOpt 1 +fHsimCertitude 0 +fHsimCertRapAutoTest 0 +fHsimRaceDetect 0 +fCheckTcCond 0 +fHsimScanOptRelaxDbg 0 +fHsimScanOptRelaxDbgDynamic 0 +fHsimScanOptRelaxDbgDynamicPli 0 +fHsimScanOptRelaxDbgDiag 0 +fHsimScanOptRelaxDbgDiagHi 0 +fHsimScanOptNoErrorOnPliAccess 0 +fHsimScanOptTiming 0 +fRelaxIbnSchedCheck 0 +fHsimScanOptNoDumpCombo 0 +fHsimScanOptPrintSwitchState 0 +fHsimScanOptSelectiveSwitchOn 0 +fHsimScanOptSingleSEPliOpt 1 +fHsimScanOptDesignHasDebugAccessOnly 0 +fHsimScanOptPrintPcode 0 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+cElabProcs 0 +hf_fHsimElabJ 0 +fHsimElabJOpt 0 +fHsimElabJMMFactor 0 +fHsimOneInstCap 0 +fHsimSchedMinput 0 +fHsimSchedSeqPrim 0 +fHsimSchedRandom 0 +fHsimSchedAll 0 +fHsimSchedSelectFanout 0 +fHsimSchedSelectFanoutDebug 0 +fHsimSchedSelectFanoutRandom 0 +fFgpDynamicReadOn 0 +fHsCgOptAllUc 0 +fHsimNoReconvergenceSched0 0 +fHsimXmrRepl 0 +fZoix 0 +fHsimDfuseNewOpt 0 +fHsimBfuseNewOpt 0 +fFgpMbme 0 +fFgpXmrSched 0 +fHsimClearClkCaps 0 +fFgpHideXmrNodes 0 +fHsimDiagClkConfig 0 +fHsimDiagClkConfigDebug 0 +fHsimDiagClkConfigDumpAll 0 +fHsDiagClkConfigPara 0 +fHsimDiagClkConfigAn 0 +fHsimCanDumpClkConfig 0 +fFgpInitRout 0 +fFgpIgnoreExclSD 0 +fHsimAggrTCOpt 0 +fFgpNewAggrXmrIterFlow 0 +fFgpNoLocalReferer 0 +fHsCgOptNoClockFusing 0 +fHsClkWheelLimit 50000 +fHsFgpSchedCgUcLoads 1 +fHsimAdvanceUdpInfer 0 +fFgpIbnSchedIntf 0 +fHsCgOptNewSelCheck 1 +fFgpReportUnsafeFuncs 0 +fHsCgOptUncPrlThreshold 4 +fHsimCosimGatesProp 0 +fHsSVNettypePerfOpt 0 +fHsCgOptHashFixMap 1 +fHsimLowPowerRetAnalysisInChild 0 +fRetainWithDelayedSig 0 +fHsimChargeDecay 0 +fHsimCongruencyConfigFile 0 +fHsimCongruencyLogFile 0 +fHsimCoverageEnabled 1 +fHsimCoverageOptions 279 +fHsimCoverageDir ./coverage/simv.vdb diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_hsim_fegate.db b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_hsim_fegate.db new file mode 100644 index 0000000..8be0045 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_hsim_fegate.db differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_hsim_lvl.db b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_hsim_lvl.db new file mode 100644 index 0000000..861898a Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_hsim_lvl.db differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_hsim_merge.db b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_hsim_merge.db new file mode 100644 index 0000000..3e9e254 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_hsim_merge.db differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_hsim_name.db b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_hsim_name.db new file mode 100644 index 0000000..2c3116f Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_hsim_name.db differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_hsim_uds.db b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_hsim_uds.db new file mode 100644 index 0000000..12a2348 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_hsim_uds.db @@ -0,0 +1,5 @@ +vcselab_misc_midd.db 57445 +vcselab_misc_mnmn.db 2715 +vcselab_misc_hsim_name.db 18117 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1349204 diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_midd.db b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_midd.db new file mode 100644 index 0000000..3b682e9 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_midd.db differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_mnmn.db b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_mnmn.db new file mode 100644 index 0000000..d30eaa6 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_mnmn.db differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_partition.db b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_partition.db new file mode 100644 index 0000000..45c0dfb Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_partition.db differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_partitionDbg.db b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_partitionDbg.db new file mode 100644 index 0000000..410c022 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_partitionDbg.db differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_vcselabref.db b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_vcselabref.db new file mode 100644 index 0000000..f76dd23 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_vcselabref.db differ diff --git a/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_vpdnodenums b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_vpdnodenums new file mode 100644 index 0000000..c7400e4 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/simv.daidir/vcselab_misc_vpdnodenums differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/Makefile b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/Makefile new file mode 100644 index 0000000..b1f80ac --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/Makefile @@ -0,0 +1,72 @@ + +WAVE ?= 0 + +SIM = RTL + +folder = simv + +ifeq ($(WAVE),1) + WAVE_OPTS = -debug_access+all -debug_region+cell+encrypt -P $(NOVAS_HOME)/share/PLI/VCS/linux64/novas_new_dumper.tab $(NOVAS_HOME)/share/PLI/VCS/linux64/pli.a +define+DUMP_FSDB + WAVE_SIM_OPTS = -fsdbDumpfile=sim.fsdb + else + WAVE_OPTS = -debug_access+pp +endif + +ifeq ($(SIM),PostPr) +VCS = vcs -full64 -sverilog -Mupdate +lint=TFIPC-L +v2k +warn=noSDFCOM_IWSBA,noNTCDNC -notice +mindelays +tchk+edge+warn +neg_tchk -negdelay +overlap +sdfverbose -sdfretain +optconfigfile+notimingcheck.cfg -override_timescale=1ns/1ps -debug_access+all $(WAVE_OPTS) -lca -q -l compile.log -cm line+cond+fsm+tgl+branch -cm_dir ./coverage/simv.vdb |tee +else +VCS = vcs -full64 -j8 -sverilog +lint=TFIPC-L +v2k $(WAVE_OPTS) -lca -q -timescale=1ns/1ps +nospecify -l compile.log -cm line+cond+fsm+tgl+branch -cm_dir ./coverage/simv.vdb +endif + +ifeq ($(SIM),PostPr) + post_dir = ./data_PostPr +else + post_dir = ./data_PostSyn +endif + + +ifeq ($(SIM),PostSyn) +FileList = filelist_syn.f +else + ifeq ($(SIM),PostPr) + FileList = filelist_pr.f + else + FileList = filelist_vlg.f + endif +endif + +SIMV = ./simv sync:busywait -Xdprof=timeline $(WAVE_SIM_OPTS) -l |tee sim.log + +all:comp run + +comp: + ${VCS} -f $(FileList) +incdir+./../../rtl/define +incdir+./../../rtl/qubitmcu +incdir+./../../model + +run: + ${SIMV} + +dbg: + verdi -sverilog -f $(FileList) -top TB -ssf *.fsdb -nologo & + +clean: + rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *fsdb* *.dat *.daidir *.vdb *~ + +compare: + ./compare_files.csh ${post_dir} ./data_RTL ./compare.txt + +regress: + ./regress.csh $(SIM) + +rmwork: + rm -rf ./work* + +rmdata: + rm -rf ./data* +cov: + verdi -cov -covdir coverage/merged.vdb & +cov_d: + dve -full64 -covdir coverage/*.vdb & +merge: + urg -full64 -dbname coverage/merged.vdb -flex_merge union -dir coverage/simv.vdb -parallel -maxjobs 64& +merge_i: + urg -full64 -flex_merge union -dir coverage/merged.vdb -dir coverage/$(folder) -dbname coverage/merged.vdb -parallel -maxjobs 64& diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/cm.log b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/cm.log new file mode 100644 index 0000000..8b71164 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/cm.log @@ -0,0 +1,1428 @@ +: // Synopsys, Inc. +: // + +: // Generated by: VCS Coverage Metrics O-2018.09-SP2_Full64 +: // User: shbyang +: // Date: Fri Mar 13 16:24:00 2026 + +: Disabling fsm sequence coverage for module \$unit::../../lib/tphn28hpcpgv18.v::../../lib/tsdn28hpcpuhdb4096x128m4mw_170a_ffg0p99v0c.v...@348857874 ... +: Disabling fsm sequence coverage for module PCLAMP_G ... +: Disabling fsm sequence coverage for module PCLAMPC_H_G ... +: Disabling fsm sequence coverage for module PCLAMPC_V_G ... +: Disabling fsm sequence coverage for module PDB3A_H_G ... +: Disabling fsm sequence coverage for module PDB3A_V_G ... +: Disabling fsm sequence coverage for module PDB3AC_H_G ... +: Disabling fsm sequence coverage for module PDB3AC_V_G ... +: Disabling fsm sequence coverage for module PDDW04DGZ_H_G ... +: Disabling fsm sequence coverage for module PDDW04DGZ_V_G ... +: Disabling fsm sequence coverage for module PDDW04SDGZ_H_G ... +: Disabling fsm sequence coverage for module PDDW08DGZ_H_G ... +: Disabling fsm sequence coverage for module PDDW08DGZ_V_G ... +: Disabling fsm sequence coverage for module PDDW08SDGZ_H_G ... +: Disabling fsm sequence coverage for module PDDW08SDGZ_V_G ... +: Disabling fsm sequence coverage for module PDDW12DGZ_H_G ... +: Disabling fsm sequence coverage for module PDDW12DGZ_V_G ... +: Disabling fsm sequence coverage for module PDDW12SDGZ_H_G ... +: Disabling fsm sequence coverage for module PDDW12SDGZ_V_G ... +: Disabling fsm sequence coverage for module PDDW16DGZ_H_G ... +: Disabling fsm sequence coverage for module PDDW16DGZ_V_G ... +: Disabling fsm sequence coverage for module PDDW16SDGZ_H_G ... +: Disabling fsm sequence coverage for module PDDW16SDGZ_V_G ... +: Disabling fsm sequence coverage for module PDUW04DGZ_H_G ... +: Disabling fsm sequence coverage for module PDUW04DGZ_V_G ... +: Disabling fsm sequence coverage for module PDUW04SDGZ_H_G ... +: Disabling fsm sequence coverage for module PDUW08DGZ_H_G ... +: Disabling fsm sequence coverage for module PDUW08DGZ_V_G ... +: Disabling fsm sequence coverage for module PDUW08SDGZ_H_G ... +: Disabling fsm sequence coverage for module PDUW12DGZ_H_G ... +: Disabling fsm sequence coverage for module PDUW12DGZ_V_G ... +: Disabling fsm sequence coverage for module PDUW12SDGZ_H_G ... +: Disabling fsm sequence coverage for module PDUW12SDGZ_V_G ... +: Disabling fsm sequence coverage for module PDUW16DGZ_H_G ... +: Disabling fsm sequence coverage for module PDUW16DGZ_V_G ... +: Disabling fsm sequence coverage for module PDUW16SDGZ_H_G ... +: Disabling fsm sequence coverage for module PDUW16SDGZ_V_G ... +: Disabling fsm sequence coverage for module PDXOEDG_H_G ... +: Disabling fsm sequence coverage for module PDXOEDG_V_G ... +: Disabling fsm sequence coverage for module PENDCAP_G ... +: Disabling fsm sequence coverage for module PENDCAPA_G ... +: Disabling fsm sequence coverage for module PRCUT_G ... +: Disabling fsm sequence coverage for module PRCUTA_G ... +: Disabling fsm sequence coverage for module PRDW08DGZ_H_G ... +: Disabling fsm sequence coverage for module PRDW08DGZ_V_G ... +: Disabling fsm sequence coverage for module PRDW08SDGZ_H_G ... +: Disabling fsm sequence coverage for module PRDW08SDGZ_V_G ... +: Disabling fsm sequence coverage for module PRDW12DGZ_H_G ... +: Disabling fsm sequence coverage for module PRDW12DGZ_V_G ... +: Disabling fsm sequence coverage for module PRDW12SDGZ_H_G ... +: Disabling fsm sequence coverage for module PRDW12SDGZ_V_G ... +: Disabling fsm sequence coverage for module PRDW16DGZ_H_G ... +: Disabling fsm sequence coverage for module PRDW16DGZ_V_G ... +: Disabling fsm sequence coverage for module PRDW16SDGZ_H_G ... +: Disabling fsm sequence coverage for module PRDW16SDGZ_V_G ... +: Disabling fsm sequence coverage for module PRUW08DGZ_H_G ... +: Disabling fsm sequence coverage for module PRUW08DGZ_V_G ... +: Disabling fsm sequence coverage for module PRUW08SDGZ_H_G ... +: Disabling fsm sequence coverage for module PRUW08SDGZ_V_G ... +: Disabling fsm sequence coverage for module PRUW12DGZ_H_G ... +: Disabling fsm sequence coverage for module PRUW12DGZ_V_G ... +: Disabling fsm sequence coverage for module PRUW12SDGZ_H_G ... +: Disabling fsm sequence coverage for module PRUW12SDGZ_V_G ... +: Disabling fsm sequence coverage for module PRUW16DGZ_H_G ... +: Disabling fsm sequence coverage for module PRUW16DGZ_V_G ... +: Disabling fsm sequence coverage for module PRUW16SDGZ_H_G ... +: Disabling fsm sequence coverage for module PRUW16SDGZ_V_G ... +: Disabling fsm sequence coverage for module PVDD1A_H_G ... +: Disabling fsm sequence coverage for module PVDD1A_V_G ... +: Disabling fsm sequence coverage for module PVDD1AC_H_G ... +: Disabling fsm sequence coverage for module PVDD1AC_V_G ... +: Disabling fsm sequence coverage for module PVDD1ANA_H_G ... +: Disabling fsm sequence coverage for module PVDD1ANA_V_G ... +: Disabling fsm sequence coverage for module PVDD1DGZ_H_G ... +: Disabling fsm sequence coverage for module PVDD1DGZ_V_G ... +: Disabling fsm sequence coverage for module PVDD2ANA_H_G ... +: Disabling fsm sequence coverage for module PVDD2ANA_V_G ... +: Disabling fsm sequence coverage for module PVDD2DGZ_H_G ... +: Disabling fsm sequence coverage for module PVDD2DGZ_V_G ... +: Disabling fsm sequence coverage for module PVDD2POC_H_G ... +: Disabling fsm sequence coverage for module PVDD2POC_V_G ... +: Disabling fsm sequence coverage for module PVDD3A_H_G ... +: Disabling fsm sequence coverage for module PVDD3A_V_G ... +: Disabling fsm sequence coverage for module PVDD3AC_H_G ... +: Disabling fsm sequence coverage for module PVDD3AC_V_G ... +: Disabling fsm sequence coverage for module PVSS1A_H_G ... +: Disabling fsm sequence coverage for module PVSS1A_V_G ... +: Disabling fsm sequence coverage for module PVSS1AC_H_G ... +: Disabling fsm sequence coverage for module PVSS1AC_V_G ... +: Disabling fsm sequence coverage for module PVSS1ANA_H_G ... +: Disabling fsm sequence coverage for module PVSS1ANA_V_G ... +: Disabling fsm sequence coverage for module PVSS1DGZ_H_G ... +: Disabling fsm sequence coverage for module PVSS1DGZ_V_G ... +: Disabling fsm sequence coverage for module PVSS2A_H_G ... +: Disabling fsm sequence coverage for module PVSS2A_V_G ... +: Disabling fsm sequence coverage for module PVSS2AC_H_G ... +: Disabling fsm sequence coverage for module PVSS2AC_V_G ... +: Disabling fsm sequence coverage for module PVSS2ANA_H_G ... +: Disabling fsm sequence coverage for module PVSS2ANA_V_G ... +: Disabling fsm sequence coverage for module PVSS2DGZ_H_G ... +: Disabling fsm sequence coverage for module PVSS2DGZ_V_G ... +: Disabling fsm sequence coverage for module PVSS3A_H_G ... +: Disabling fsm sequence coverage for module PVSS3A_V_G ... +: Disabling fsm sequence coverage for module PVSS3AC_H_G ... +: Disabling fsm sequence coverage for module PVSS3AC_V_G ... +: Disabling fsm sequence coverage for module PVSS3DGZ_H_G ... +: Disabling fsm sequence coverage for module PVSS3DGZ_V_G ... +: Disabling fsm sequence coverage for module sirv_gnrl_xchecker ... +: Disabling fsm sequence coverage for module sirv_gnrl_dffl ... +: Disabling fsm sequence coverage for module sirv_gnrl_ltch ... +: Disabling fsm sequence coverage for module clk_gen ... +: Disabling fsm sequence coverage for module reset_tb ... +: Disabling fsm sequence coverage for module TB ... +: Disabling fsm sequence coverage for module TB.clk_inst ... +: Disabling fsm sequence coverage for module TB.clk_40g_inst ... +: Disabling fsm sequence coverage for module TB.spi_bus ... +: Disabling fsm sequence coverage for module TB.lvds_bus ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_iopad ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_iopad.PDUW08SDGZ_V_G_async_rstn ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_iopad.PDDW04SDGZ_V_G_sync_in ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_iopad.PDDW08SDGZ_V_G_sync_out ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_iopad.PDUW04SDGZ_V_G_sclk ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_iopad.PDUW04SDGZ_V_G_csn ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_iopad.PDUW08SDGZ_V_G_mosi ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_iopad.PDUW08SDGZ_V_G_miso ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_iopad.PDUW08SDGZ_V_G_irq ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.mst ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.bit_cnt_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.bit_cnt_r_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.cmd_or_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.second_falling_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.wnr_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.addr_m5b_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.addr_l8b_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.chipid_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.rddata_update_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.addr_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.oen_dffrs ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.miso_reg_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[0].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[1].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[2].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[3].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[4].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[5].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[6].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[7].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[8].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[9].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[10].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[11].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[12].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[13].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[14].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[15].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[16].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[17].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[18].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[19].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[20].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[21].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[22].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[23].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[24].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[25].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[26].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[27].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[28].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[29].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[30].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[31].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.sclk_reg_dffrs ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.csn_reg_dffrs ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.mosi_reg_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.cnt_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.initaddr_vld_r_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.initaddr_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.cmd_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.chipid_vld_r_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.chipid_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.state_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.second_falling_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.addr_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.wrdata_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.wren_r_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.wren_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.rden_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.rddata_reg_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_dout_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.oen_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[0].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[1].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[2].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[3].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[4].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[5].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[6].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[7].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[8].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[9].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[10].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[11].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[12].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[13].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[14].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[15].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[16].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[17].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[18].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[19].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[20].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[21].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[22].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[23].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[24].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[25].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[26].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[27].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[28].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[29].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[30].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[31].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[0].CMD_REG.rwaddr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[0].CMD_REG.wrdata_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[0].CMD_REG.wren_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[0].CMD_REG.reen_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[1].CMD_REG.rwaddr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[1].CMD_REG.wrdata_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[1].CMD_REG.wren_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[1].CMD_REG.reen_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[2].CMD_REG.rwaddr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[2].CMD_REG.wrdata_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[2].CMD_REG.wren_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[2].CMD_REG.reen_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[3].CMD_REG.rwaddr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[3].CMD_REG.wrdata_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[3].CMD_REG.wren_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[3].CMD_REG.reen_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.testr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.sfrtr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.syncr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.syncr16_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.syncr16_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.sync_oen_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.rampctr_dfflrs ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.ramp_ifs_dfflrs ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.doselr_dfflrs ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdsftr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdstfr_dfflrs ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdstsr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdsthr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdstamr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdsdser_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdstaor_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.llvdssr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdsfcsr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdscecr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdsfstr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdststr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.imr_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.cnt_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.sys_soft_rstn_r_dffls ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.rddata_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.train_ready_r_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.crc_error_r_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.cphase_adj_req_r_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.link_down_r_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.cmd_fifo_full_r_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.cmd_fifo_empty_r_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.isr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.misr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.irq_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_rst_gen_unit ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_rst_gen_unit.ch0_rstn_sync ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_rst_gen_unit.ch1_rstn_sync ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_rst_gen_unit.ch2_rstn_sync ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_rst_gen_unit.ch3_rstn_sync ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_SRC_INIT ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_SRC_INIT.SIM ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_SYNC_CLR_S ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_DEST_INIT ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_DEST_INIT.SIM ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_FB_DEST ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_FB_DEST.SIM ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_ACK ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_ACK.SIM ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_SYNC ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.U_prefill ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.U_prefill.delay_counter_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.U_prefill.prefill_start_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.U_prefill.prefilling_r_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.U_prefill.prefill_done_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.lane0_reg_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.lane1_reg_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.lane2_reg_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.lane3_reg_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.bit_counter_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.match_counter_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.state_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.delay_tap_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.tap_adj_req_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.link_down_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.train_ready_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.data_buf_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.match_head_start_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.data_counter_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.valid_int_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.descram_valid_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.data_in_reg_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.train_status_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_descrambler ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_descrambler.u0 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_descrambler.u1 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_descrambler.u2 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_descrambler.u3 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.u_fifo ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.u_fifo.spram ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.u_fifo.spram.bhv_spram ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.word_state_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.current_fifo_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.current_word_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.word_valid_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.data_len_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.data_cnt_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.state_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.cur_block_offset_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.block_done_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.base_addr_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.cur_block_addr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.cur_block_addr_r_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.wr_addr_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.wr_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.byte_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.wr_en_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.frame_done_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.u_crc32 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.crc_clear_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.crc_error_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.frame_status_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[0].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[1].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[2].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[3].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[4].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[5].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[6].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[7].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[8].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[9].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[10].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[11].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[12].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[13].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[14].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[15].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[0].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[1].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[2].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[3].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[4].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[5].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[6].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[7].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[8].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[9].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[10].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[11].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[12].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[13].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[14].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[15].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.sync_in_syncer ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.sync_in_syncer.data_temp0_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.sync_in_syncer.SYNCER[1].data_tempn0_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.sync_out_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.pulse_inst_sync ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.start_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.sync_start_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.state_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.cycle_num_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.base_addr_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.wave_leng_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.hold_leng_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.addr_cnt_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.wave_cnt_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.hold_cnt_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.sram_rd_en_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.sram_rd_addr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.last_sram_rd_en_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.last_wave_data_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.last_rddata_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.wave_vld_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.hold_vld_n_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.hold_vld_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.wave_valid_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.wave_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.cmd_fifo_inst ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.cmd_fifo_inst.spram ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.cmd_fifo_inst.spram.bhv_spram ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_sram_muxin ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_sram_muxout ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.U_sram_dmux_w ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U0_tsdn28hpcpuhdb4096x128m4mw_170a ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U0_tsdn28hpcpuhdb4096x128m4mw_170a.MX ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U1_tsdn28hpcpuhdb4096x128m4mw_170a ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U1_tsdn28hpcpuhdb4096x128m4mw_170a.MX ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U2_tsdn28hpcpuhdb4096x128m4mw_170a ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U2_tsdn28hpcpuhdb4096x128m4mw_170a.MX ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U3_tsdn28hpcpuhdb4096x128m4mw_170a ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U3_tsdn28hpcpuhdb4096x128m4mw_170a.MX ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U0_tsdn28hpcpuhdb4096x128m4mw_170a ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U0_tsdn28hpcpuhdb4096x128m4mw_170a.MX ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U1_tsdn28hpcpuhdb4096x128m4mw_170a ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U1_tsdn28hpcpuhdb4096x128m4mw_170a.MX ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U2_tsdn28hpcpuhdb4096x128m4mw_170a ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U2_tsdn28hpcpuhdb4096x128m4mw_170a.MX ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U3_tsdn28hpcpuhdb4096x128m4mw_170a ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U3_tsdn28hpcpuhdb4096x128m4mw_170a.MX ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_ramp_gen ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.dacif_vld_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[0].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[1].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[2].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[3].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[4].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[5].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[6].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[7].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[8].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[9].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[10].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[11].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[12].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[13].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[14].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[15].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[16].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[17].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[18].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[19].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[20].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[21].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[22].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[23].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[24].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[25].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[26].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[27].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[28].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[29].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[30].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[31].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[32].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[33].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[34].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[35].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[36].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[37].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[38].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[39].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[40].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[41].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[42].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[43].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[44].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[45].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[46].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[47].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[48].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[49].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[50].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[51].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[52].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[53].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[54].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[55].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[56].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[57].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[58].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[59].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[60].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[61].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[62].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[63].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[0].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[1].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[2].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[3].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[4].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[5].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[6].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[7].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[8].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[9].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[10].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[11].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[12].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[13].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[14].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[15].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[16].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[17].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[18].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[19].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[20].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[21].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[22].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[23].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[24].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[25].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[26].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[27].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[28].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[29].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[30].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[31].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[32].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[33].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[34].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[35].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[36].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[37].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[38].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[39].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[40].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[41].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[42].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[43].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[44].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[45].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[46].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[47].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[48].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[49].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[50].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[51].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[52].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[53].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[54].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[55].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[56].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[57].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[58].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[59].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[60].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[61].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[62].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[63].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.rtermr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.prbsr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set0r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set1r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set2r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set3r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set4r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set5r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set6r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set7r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set8r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set9r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set10r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set11r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set12r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set13r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set14r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set15r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set16r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set17r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set18r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set19r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set20r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set21r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set22r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set23r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set24r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set25r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set26r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set27r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set28r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set29r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set30r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set31r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.casaddrr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.casdwr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.imctr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.ibleedctr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.iclkcmlr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.currsvr0_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.currsvr1_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.rddata_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalrstnr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.cclkdccenr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.casclkctr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccaldccqecpir_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalqecctr1_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.biasct3r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalpictr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalcrossctr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalrsvr0_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalrsvr1_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.selck10gdr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.selck2p5gdr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.selck625mdr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.p2sdataenr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.enallpr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.enpipr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.clkdivrstnr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.p2srsvr0_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.p2srsvr1_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ckrxswr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.rstckr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ctrzinr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.rddata_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.slv[0] ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.slv[1] ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.slv[2] ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.slv[3] ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.DEM_VLD_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_0 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_1 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_2 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_3 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_4 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_5 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_6 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_7 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_8 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_9 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_10 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_11 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_12 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_13 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_14 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_15 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_16 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_17 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_18 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_19 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_20 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_21 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_22 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_23 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_24 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_25 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_26 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_27 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_28 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_29 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_30 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_31 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_32 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_33 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_34 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_35 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_36 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_37 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_38 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_39 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_40 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_41 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_42 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_43 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_44 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_45 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_46 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_47 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_48 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_49 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_50 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_51 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_52 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_53 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_54 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_55 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_56 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_57 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_58 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_59 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_60 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_61 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_62 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_63 ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[0].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[1].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[2].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[3].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[4].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[5].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[6].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[7].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[8].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[9].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[10].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[11].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[12].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[13].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[14].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[15].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[16].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[17].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[18].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[19].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[20].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[21].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[22].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[23].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[24].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[25].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[26].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[27].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[28].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[29].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[30].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[31].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[32].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[33].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[34].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[35].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[36].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[37].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[38].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[39].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[40].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[41].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[42].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[43].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[44].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[45].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[46].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[47].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[48].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[49].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[50].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[51].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[52].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[53].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[54].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[55].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[56].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[57].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[58].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[59].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[60].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[61].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[62].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[63].U_DEM_Reverse ... +: Starting toggle coverage for module sirv_gnrl_xchecker +: Starting toggle coverage for module sirv_gnrl_dffl +: Starting toggle coverage for module sirv_gnrl_ltch +: Starting toggle coverage for module clk_gen +: Starting toggle coverage for module reset_tb +: Starting toggle coverage for module TB +: Starting toggle coverage for module TB.clk_inst +: Starting toggle coverage for module TB.clk_40g_inst +: Starting toggle coverage for module TB.spi_bus +: Starting toggle coverage for module TB.lvds_bus +: Starting toggle coverage for module TB.U_da4008_chip_top +: Starting toggle coverage for module TB.U_da4008_chip_top.U_iopad +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.mst +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.bit_cnt_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.bit_cnt_r_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.cmd_or_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.second_falling_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.wnr_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.addr_m5b_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.addr_l8b_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.chipid_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.rddata_update_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.addr_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.oen_dffrs +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.miso_reg_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[0].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[1].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[2].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[3].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[4].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[5].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[6].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[7].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[8].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[9].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[10].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[11].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[12].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[13].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[14].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[15].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[16].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[17].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[18].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[19].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[20].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[21].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[22].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[23].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[24].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[25].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[26].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[27].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[28].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[29].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[30].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[31].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.sclk_reg_dffrs +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.csn_reg_dffrs +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.mosi_reg_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.cnt_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.initaddr_vld_r_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.initaddr_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.cmd_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.chipid_vld_r_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.chipid_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.state_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.second_falling_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.addr_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.wrdata_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.wren_r_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.wren_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.rden_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.rddata_reg_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_dout_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.oen_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[0].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[1].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[2].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[3].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[4].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[5].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[6].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[7].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[8].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[9].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[10].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[11].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[12].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[13].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[14].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[15].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[16].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[17].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[18].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[19].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[20].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[21].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[22].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[23].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[24].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[25].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[26].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[27].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[28].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[29].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[30].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[31].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[0].CMD_REG.rwaddr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[0].CMD_REG.wrdata_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[0].CMD_REG.wren_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[0].CMD_REG.reen_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[1].CMD_REG.rwaddr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[1].CMD_REG.wrdata_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[1].CMD_REG.wren_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[1].CMD_REG.reen_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[2].CMD_REG.rwaddr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[2].CMD_REG.wrdata_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[2].CMD_REG.wren_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[2].CMD_REG.reen_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[3].CMD_REG.rwaddr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[3].CMD_REG.wrdata_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[3].CMD_REG.wren_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[3].CMD_REG.reen_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.testr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.sfrtr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.syncr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.syncr16_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.syncr16_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.sync_oen_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.rampctr_dfflrs +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.ramp_ifs_dfflrs +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.doselr_dfflrs +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdsftr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdstfr_dfflrs +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdstsr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdsthr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdstamr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdsdser_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdstaor_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.llvdssr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdsfcsr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdscecr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdsfstr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdststr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.imr_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.cnt_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.sys_soft_rstn_r_dffls +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.rddata_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.train_ready_r_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.crc_error_r_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.cphase_adj_req_r_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.link_down_r_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.cmd_fifo_full_r_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.cmd_fifo_empty_r_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.isr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.misr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.irq_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_rst_gen_unit +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_rst_gen_unit.ch0_rstn_sync +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_rst_gen_unit.ch1_rstn_sync +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_rst_gen_unit.ch2_rstn_sync +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_rst_gen_unit.ch3_rstn_sync +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_SRC_INIT +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_SRC_INIT.SIM +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_SYNC_CLR_S +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_DEST_INIT +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_DEST_INIT.SIM +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_FB_DEST +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_FB_DEST.SIM +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_ACK +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_ACK.SIM +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_SYNC +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.U_prefill +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.U_prefill.delay_counter_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.U_prefill.prefill_start_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.U_prefill.prefilling_r_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.U_prefill.prefill_done_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.lane0_reg_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.lane1_reg_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.lane2_reg_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.lane3_reg_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.bit_counter_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.match_counter_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.state_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.delay_tap_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.tap_adj_req_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.link_down_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.train_ready_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.data_buf_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.match_head_start_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.data_counter_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.valid_int_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.descram_valid_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.data_in_reg_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.train_status_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_descrambler +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_descrambler.u0 +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_descrambler.u1 +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_descrambler.u2 +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_descrambler.u3 +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.u_fifo +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.u_fifo.spram +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.u_fifo.spram.bhv_spram +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.word_state_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.current_fifo_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.current_word_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.word_valid_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.data_len_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.data_cnt_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.state_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.cur_block_offset_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.block_done_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.base_addr_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.cur_block_addr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.cur_block_addr_r_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.wr_addr_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.wr_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.byte_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.wr_en_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.frame_done_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.u_crc32 +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.crc_clear_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.crc_error_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.frame_status_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[0].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[1].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[2].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[3].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[4].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[5].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[6].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[7].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[8].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[9].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[10].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[11].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[12].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[13].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[14].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[15].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[0].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[1].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[2].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[3].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[4].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[5].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[6].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[7].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[8].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[9].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[10].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[11].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[12].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[13].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[14].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[15].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.sync_in_syncer +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.sync_in_syncer.data_temp0_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.sync_in_syncer.SYNCER[1].data_tempn0_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.sync_out_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.pulse_inst_sync +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.start_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.sync_start_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.state_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.cycle_num_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.base_addr_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.wave_leng_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.hold_leng_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.addr_cnt_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.wave_cnt_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.hold_cnt_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.sram_rd_en_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.sram_rd_addr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.last_sram_rd_en_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.last_wave_data_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.last_rddata_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.wave_vld_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.hold_vld_n_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.hold_vld_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.wave_valid_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.wave_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.cmd_fifo_inst +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.cmd_fifo_inst.spram +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.cmd_fifo_inst.spram.bhv_spram +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_sram_muxin +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_sram_muxout +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.U_sram_dmux_w +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U0_tsdn28hpcpuhdb4096x128m4mw_170a.MX +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U1_tsdn28hpcpuhdb4096x128m4mw_170a.MX +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U2_tsdn28hpcpuhdb4096x128m4mw_170a.MX +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U3_tsdn28hpcpuhdb4096x128m4mw_170a.MX +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U0_tsdn28hpcpuhdb4096x128m4mw_170a.MX +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U1_tsdn28hpcpuhdb4096x128m4mw_170a.MX +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U2_tsdn28hpcpuhdb4096x128m4mw_170a.MX +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U3_tsdn28hpcpuhdb4096x128m4mw_170a.MX +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_ramp_gen +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.dacif_vld_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[0].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[1].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[2].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[3].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[4].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[5].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[6].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[7].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[8].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[9].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[10].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[11].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[12].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[13].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[14].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[15].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[16].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[17].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[18].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[19].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[20].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[21].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[22].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[23].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[24].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[25].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[26].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[27].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[28].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[29].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[30].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[31].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[32].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[33].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[34].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[35].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[36].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[37].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[38].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[39].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[40].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[41].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[42].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[43].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[44].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[45].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[46].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[47].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[48].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[49].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[50].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[51].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[52].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[53].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[54].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[55].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[56].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[57].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[58].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[59].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[60].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[61].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[62].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[63].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[0].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[1].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[2].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[3].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[4].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[5].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[6].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[7].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[8].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[9].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[10].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[11].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[12].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[13].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[14].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[15].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[16].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[17].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[18].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[19].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[20].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[21].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[22].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[23].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[24].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[25].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[26].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[27].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[28].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[29].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[30].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[31].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[32].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[33].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[34].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[35].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[36].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[37].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[38].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[39].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[40].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[41].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[42].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[43].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[44].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[45].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[46].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[47].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[48].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[49].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[50].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[51].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[52].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[53].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[54].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[55].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[56].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[57].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[58].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[59].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[60].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[61].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[62].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[63].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.rtermr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.prbsr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set0r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set1r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set2r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set3r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set4r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set5r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set6r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set7r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set8r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set9r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set10r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set11r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set12r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set13r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set14r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set15r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set16r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set17r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set18r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set19r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set20r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set21r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set22r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set23r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set24r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set25r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set26r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set27r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set28r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set29r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set30r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set31r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.casaddrr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.casdwr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.imctr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.ibleedctr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.iclkcmlr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.currsvr0_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.currsvr1_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.rddata_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalrstnr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.cclkdccenr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.casclkctr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccaldccqecpir_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalqecctr1_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.biasct3r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalpictr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalcrossctr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalrsvr0_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalrsvr1_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.selck10gdr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.selck2p5gdr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.selck625mdr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.p2sdataenr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.enallpr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.enpipr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.clkdivrstnr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.p2srsvr0_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.p2srsvr1_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ckrxswr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.rstckr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ctrzinr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.rddata_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.slv[0] +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.slv[1] +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.slv[2] +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.slv[3] +: Starting toggle coverage for module TB.U_da4008_chip_top.DEM_VLD_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_0 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_1 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_2 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_3 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_4 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_5 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_6 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_7 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_8 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_9 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_10 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_11 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_12 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_13 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_14 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_15 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_16 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_17 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_18 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_19 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_20 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_21 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_22 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_23 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_24 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_25 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_26 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_27 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_28 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_29 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_30 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_31 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_32 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_33 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_34 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_35 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_36 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_37 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_38 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_39 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_40 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_41 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_42 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_43 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_44 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_45 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_46 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_47 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_48 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_49 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_50 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_51 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_52 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_53 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_54 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_55 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_56 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_57 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_58 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_59 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_60 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_61 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_62 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_63 +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[0].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[1].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[2].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[3].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[4].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[5].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[6].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[7].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[8].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[9].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[10].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[11].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[12].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[13].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[14].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[15].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[16].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[17].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[18].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[19].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[20].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[21].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[22].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[23].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[24].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[25].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[26].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[27].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[28].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[29].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[30].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[31].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[32].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[33].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[34].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[35].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[36].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[37].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[38].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[39].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[40].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[41].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[42].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[43].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[44].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[45].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[46].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[47].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[48].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[49].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[50].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[51].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[52].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[53].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[54].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[55].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[56].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[57].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[58].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[59].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[60].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[61].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[62].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[63].U_DEM_Reverse +: Reporting line coverage at the end of simulation ... +: End of Line Coverage ... +: Reporting condition coverage at the end of simulation ... +: End of Condition Coverage ... +: Reporting branch coverage at the end of simulation ... +: End of Branch Coverage ... +: Coverage status: End of All Coverages ... + diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/filelist_syn.f b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/filelist_syn.f new file mode 100644 index 0000000..59d68ec --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/filelist_syn.f @@ -0,0 +1,23 @@ +../../../../rtl/define/chip_define.v +../../../../sim/chip_top/TB.sv +../../../../model/spi_if.sv +../../../../model/DW01_addsub.v +../../../../model/DW02_mult.v +../../../../model/DW_mult_pipe.v +../../../../model/clk_gen.v +../../../../model/clock_tb.v +../../../../model/reset_tb.v +../../../../model/thermo2binary_top.v +../../../../model/thermo7_binary3.v +../../../../model/thermo15_binary4.v +../../../../model/glbl.v +../../../../rtl/memory/tsdn28hpcpuhdb128x128m4mw_170a_ffg0p99v0c.v +../../../../rtl/memory/tsdn28hpcpuhdb4096x32m4mw_170a_ffg0p99v0c.v +../../../../rtl/memory/tsdn28hpcpuhdb64x32m4mw_170a_ffg0p99v0c.v +../../../../rtl/memory/tsdn28hpcpuhdb512x128m4mwr_170a_ffg0p99v0c.v +../../../../rtl/memory/tsdn28hpcpuhdb4096x128m4mw_170a_ffg0p99v0c.v +../../../../rtl/dem/DEM_31MSB_decoder_1ch.v +../../../../rtl/dem/DEM_31MSB_decoder_16ch_XY.v +/data/pdk/TSMCHOME/digital/Front_End/verilog/tphn28hpcpgv18_110a/tphn28hpcpgv18.v +../../../../lib/tcbn28hpcplusbwp7t35p140.v +../../../../syn/current/outputs/xyz_chip_top.syn.v diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/filelist_vlg.f b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/filelist_vlg.f new file mode 100644 index 0000000..c92f7d1 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/filelist_vlg.f @@ -0,0 +1,46 @@ +../../../../rtl/define/chip_define.v +../../../../lib/tphn28hpcpgv18.v +../../../../lib/tsdn28hpcpuhdb4096x128m4mw_170a_ffg0p99v0c.v +../../../../rtl/io/iopad.v +../../../../rtl/systemregfile/systemregfile.v +../../../../rtl/dacif/dacif.v +../../../../rtl/fifo/syn_fwft_fifo.v +../../../../rtl/dac_regfile/dac_regfile.v +../../../../rtl/lvds/ulink_rx.sv +../../../../rtl/rstgen/rst_gen_unit.v +../../../../rtl/rstgen/rst_sync.v +../../../../rtl/comm/sirv_gnrl_xchecker.v +../../../../rtl/comm/pulse_generator.sv +../../../../rtl/comm/sirv_gnrl_dffs.v +../../../../rtl/comm/syncer.v +../../../../rtl/comm/ramp_gen.v +../../../../rtl/memory/tsmc_dpram.v +../../../../rtl/memory/sram_if.sv +../../../../rtl/memory/sram_dmux.sv +../../../../rtl/memory/dpram.v +../../../../rtl/memory/bhv_spram.v +../../../../rtl/memory/spram.v +../../../../rtl/clk/clk_regfile.v +../../../../rtl/awg/awg_top.sv +../../../../rtl/awg/awg_ctrl.v +../../../../rtl/dem/DEM_PhaseSync_4008.sv +../../../../rtl/dem/DA4008_DEM_Parallel_PRBS_1CH.v +../../../../rtl/dem/DA4008_DEM_Parallel_PRBS_64CH.v +../../../../rtl/top/da4008_chip_top.sv +../../../../rtl/top/digital_top.sv +../../../../rtl/spi/spi_bus_decoder.sv +../../../../rtl/spi/spi_slave.v +../../../../rtl/spi/spi_pll.v +../../../../rtl/spi/spi_sys.v +../../../../model/clock_tb.v +../../../../model/spi_if.sv +../../../../model/clk_gen.v +../../../../model/DEM_Reverse_64CH.v +../../../../model/DEM_Reverse.v +../../../../model/reset_tb.v +../../../../model/DW_stream_sync.v +../../../../model/DW_reset_sync.v +../../../../model/DW_sync.v +../../../../model/DW_pulse_sync.v +../../../../sim/chip_top/TB.sv +../../../../rtl/define/chip_undefine.v diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/novas.conf b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/novas.conf new file mode 100644 index 0000000..448722c --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/novas.conf @@ -0,0 +1,338 @@ +[qBaseWindowStateGroup] +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false 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+10=/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/novas_autosave.ses + +[qDockerWindow_C] +Verdi_1\position.x=-1 +Verdi_1\position.y=27 +Verdi_1\width=1920 +Verdi_1\height=977 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/novas.rc b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/novas.rc new file mode 100644 index 0000000..4245d1d --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/novas.rc @@ -0,0 +1,1310 @@ +@verdi rc file Version 1.0 +[Library] +work = ./work +[Annotation] +3D_Active_Annotation = FALSE +[CommandSyntax.finsim] +InvokeCommand = +FullFileName = TRUE +Separator = . +SimPromptSign = ">" +HierNameLevel = 1 +RunContinue = "continue" +Finish = "quit" +UseAbsTime = FALSE +NextTime = "run 1" +NextNTime = "run ${SimBPTime}" +NextEvent = "run 1" +Reset = +ObjPosBreak = "break posedge ${SimBPObj}" +ObjNegBreak = "break negedge ${SimBPObj}" +ObjAnyBreak = "break change ${SimBPObj}" +ObjLevelBreak = +LineBreak = "breakline ${SimBPFile} ${SimBPLine}" +AbsTimeBreak = "break abstimeaf ${SimBPTime}" +RelTimeBreak = "break reltimeaf ${SimBPTime}" +EnableBP = "breakon ${SimBPId}" +DisableBP = "breakoff ${SimBPId}" +DeleteBP = "breakclr ${SimBPId}" +DeleteAllBP = "breakclr" +SimSetScope = "cd ${SimDmpObj}" +[CommandSyntax.ikos] +InvokeCommand = "setvar debussy true;elaborate -p ${SimTop} -s ${SimArch}; run until 0;fsdbInteractive; " +FullFileName = TRUE +NeedTimeUnit = TRUE +NormalizeTimeUnit = TRUE +Separator = / +HierNameLevel = 2 +RunContinue = "run" +Finish = "exit" +NextTime = "run ${SimBPTime} ${SimTimeUnit}" +NextNTime = "run for ${SimBPTime} ${SimTimeUnit}" +NextEvent = "step 1" +Reset = "reset" +ObjPosBreak = "stop if ${SimBPObj} = \"'1'\"" +ObjNegBreak = "stop if ${SimBPObj} = \"'0'\"" +ObjAnyBreak = +ObjLevelBreak = "stop if ${SimBPObj} = ${SimBPValue}" +LineBreak = "stop at ${SimBPFile}:${SimBPLine}" +AbsTimeBreak = +RelTimeBreak = +EnableBP = "enable ${SimBPId}" +DisableBP = "disable ${SimBPId}" +DeleteBP = "delete ${SimBPId}" +DeleteAllBP = "delete *" +[CommandSyntax.verisity] +InvokeCommand = +FullFileName = FALSE +Separator = . +SimPromptSign = "> " +HierNameLevel = 1 +RunContinue = "." +Finish = "$finish;" +NextTime = "$db_steptime(1);" +NextNTime = "$db_steptime(${SimBPTime});" +NextEvent = "$db_step;" +SimSetScope = "$scope(${SimDmpObj});" +Reset = "$reset;" +ObjPosBreak = "$db_breakonposedge(${SimBPObj});" +ObjNegBreak = "$db_breakonnegedge(${SimBPObj});" +ObjAnyBreak = "$db_breakwhen(${SimBPObj});" +ObjLevelBreak = "$db_breakwhen(${SimBPObj}, ${SimBPValue});" +LineBreak = "$db_breakatline(${SimBPLine}, ${SimBPScope}, \"${SimBPFile}\");" +AbsTimeBreak = "$db_breakbeforetime(${SimBPTime});" +RelTimeBreak = "$db_breakbeforetime(${SimBPTime});" +EnableBP = "$db_enablebreak(${SimBPId});" +DisableBP = "$db_disablebreak(${SimBPId});" +DeleteBP = "$db_deletebreak(${SimBPId});" +DeleteAllBP = "$db_deletebreak;" +FSDBInit = "$novasInteractive;" +FSDBDumpvars = "$novasDumpvars(0, ${SimDmpObj});" +FSDBDumpsingle = "$novasDumpsingle(${SimDmpObj});" +FSDBDumpvarsInFile = "$novasDumpvarsToFile(\"${SimDmpFile}\");" +FSDBDumpMem = "$novasDumpMemNow(${SimDmpObj}, ${SimDmpBegin}, ${SimDmpSize});" +[CoverageDetail] +cross_filter_limit = 1000 +branch_limit_vector_display = 50 +showgrid = TRUE +reuseFirst = TRUE +justify = TRUE +scrollbar_mode = per pane +test_combo_left_truncate = TRUE +instance_combo_left_truncate = TRUE +loop_navigation = TRUE +condSubExpr = 20 +tglMda = 1000 +linecoverable = 100000 +lineuncovered = 50000 +tglcoverable = 30000 +tgluncovered = 30000 +pendingMax = 1000 +show_full_more = FALSE +[CoverageHier] +showgrid = FALSE +[CoverageWeight] +Assert = 1 +Covergroup = 1 +Line = 1 +Condition = 1 +Toggle = 1 +FSM = 1 +Branch = 1 +[DesignTree] +IfShowModule = {TRUE, FALSE} +[DisabledMessages] +version = Verdi_O-2018.09-SP2 +[Editor] +editorName = TurboEditor +[Emacs] +EmacsFont = "Clean 14" +EmacsBG = white +EmacsFG = black +[Exclusion] +enableAsDefault = TRUE +saveAsDefault = TRUE +saveManually = TRUE +illegalBehavior = FALSE +DisplayExcludedItem = FALSE +adaptiveExclusion = TRUE +warningExcludeInstance = TRUE +favorite_exclude_annotation = "" +[FSM] +viewport = 65 336 387 479 +WndBk-FillColor = Gray3 +Background-FillColor = gray5 +prefKey_Link-FillColor = yellow4 +prefKey_Link-TextColor = black +Trap = red3 +Hilight = blue4 +Window = Gray3 +Selected = white +Trans. = green2 +State = black +Init. = black +SmartTips = TRUE +VectorFont = FALSE +StopAskBkgndColor = FALSE +ShowStateAction = FALSE +ShowTransAction = FALSE +ShowTransCond = FALSE +StateLable = NAME +StateValueRadix = ORIG +State-LineColor = ID_BLACK +State-LineWidth = 1 +State-FillColor = ID_BLUE2 +State-TextColor = ID_WHITE +Init_State-LineColor = ID_BLACK +Init_State-LineWidth = 2 +Init_State-FillColor = ID_YELLOW2 +Init_State-TextColor = ID_BLACK +Reset_State-LineColor = ID_BLACK +Reset_State-LineWidth = 2 +Reset_State-FillColor = ID_YELLOW7 +Reset_State-TextColor = ID_BLACK +Trap_State-LineColor = ID_RED2 +Trap_State-LineWidth = 2 +Trap_State-FillColor = ID_CYAN5 +Trap_State-TextColor = ID_RED2 +State_Action-LineColor = ID_BLACK +State_Action-LineWidth = 1 +State_Action-FillColor = ID_WHITE +State_Action-TextColor = ID_BLACK +Junction-LineColor = ID_BLACK +Junction-LineWidth = 1 +Junction-FillColor = ID_GREEN2 +Junction-TextColor = ID_BLACK +Connection-LineColor = ID_BLACK +Connection-LineWidth = 1 +Connection-FillColor = ID_GRAY5 +Connection-TextColor = ID_BLACK +prefKey_Port-LineColor = ID_BLACK +prefKey_Port-LineWidth = 1 +prefKey_Port-FillColor = ID_ORANGE6 +prefKey_Port-TextColor = ID_YELLOW2 +Transition-LineColor = ID_BLACK +Transition-LineWidth = 1 +Transition-FillColor = ID_WHITE +Transition-TextColor = ID_BLACK +Trans_Condition-LineColor = ID_BLACK +Trans_Condition-LineWidth = 1 +Trans_Condition-FillColor = ID_WHITE +Trans_Condition-TextColor = ID_ORANGE2 +Trans_Action-LineColor = ID_BLACK +Trans_Action-LineWidth = 1 +Trans_Action-FillColor = ID_WHITE +Trans_Action-TextColor = ID_GREEN2 +SelectedSet-LineColor = ID_RED2 +SelectedSet-LineWidth = 1 +SelectedSet-FillColor = ID_RED2 +SelectedSet-TextColor = ID_WHITE +StickSet-LineColor = ID_ORANGE5 +StickSet-LineWidth = 1 +StickSet-FillColor = ID_PURPLE6 +StickSet-TextColor = ID_BLACK +HilightSet-LineColor = ID_RED5 +HilightSet-LineWidth = 1 +HilightSet-FillColor = ID_RED7 +HilightSet-TextColor = ID_BLUE5 +ControlPoint-LineColor = ID_BLACK +ControlPoint-LineWidth = 1 +ControlPoint-FillColor = ID_WHITE +Bundle-LineColor = ID_BLACK +Bundle-LineWidth = 1 +Bundle-FillColor = ID_WHITE +Bundle-TextColor = ID_BLUE4 +QtBackground-FillColor = ID_GRAY6 +prefKey_Link-LineColor = ID_ORANGE2 +prefKey_Link-LineWidth = 1 +Selection-LineColor = ID_BLUE2 +Selection-LineWidth = 1 +[FSM_Dlg-Print] +Orientation = Landscape +[Form] +version = Verdi_O-2018.09-SP2 +[General] +autoSaveSession = FALSE +TclAutoSource = +cmd_enter_form = FALSE +SyncBrowserDir = TRUE +version = Verdi_O-2018.09-SP2 +SignalCaseInSensitive = FALSE +ShowWndCtntDuringResizing = FALSE +[GlobalProp] +ErrWindow_Font = Helvetica_M_R_12 +[Globals] +app_default_font = Bitstream Vera Sans,10,-1,5,50,0,0,0,0,0 +app_fixed_width_font = Courier,10,-1,5,50,0,0,0,0,0 +text_encoding = Unicode(utf8) +smart_resize = TRUE +smart_resize_child_limit = 2000 +tooltip_max_width = 200 +tooltip_max_height = 20 +tooltip_viewer_key = F3 +tooltip_display_time = 1000 +bookmark_name_length_limit = 12 +disable_tooltip = FALSE +auto_load_source = TRUE +max_array_size = 4096 +filter_when_typing = TRUE +filter_keep_children = TRUE +filter_syntax = Wildcards +filter_keystroke_interval = 800 +filter_case_sensitive = FALSE +filter_full_path = FALSE +load_detail_for_funcov = FALSE +sort_limit = 100000 +ignoreDBVersionChecking = FALSE +[HB] +ViewSchematic = FALSE +windowLayout = 0 0 804 500 182 214 804 148 +import_filter = *.v; *.vc; *.f +designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +import_filter_vhdl = *.vhd; *.vhdl; *.f +import_default_language = Verilog +import_filter_verilog = *.v; *.vc; *.f +simulation_file_type = *.fsdb;*.fsdb.gz;*.fsdb.bz2;*.ff;*.dump +PrefetchViewableAnnot = TRUE +[Hier] +filterTimeout = 1500 +[ImportLiberty] +SearchPriority = .lib++ +bSkipStateCell = False +bImportPowerInfo = False +bSkipFFCell = False +bScpecifyCellNameCase = False +bSpecifyPinNameCase = False +CellNameToCase = +PinNameToCase = +[Language] +EditWindow_Font = COURIER12 +Background = ID_WHITE +Comment = ID_GRAY4 +Keyword = ID_BLUE5 +UserKeyword = ID_GREEN2 +Text = ID_BLACK +SelText = ID_WHITE +SelBackground = ID_BLUE2 +[Library.Ikos] +pack = ./work.lib++ +vital = ./work.lib++ +work = ./work.lib++ +std = ${dls_std}.lib++ +ieee = ${dls_ieee}.lib++ +synopsys = ${dls_synopsys}.lib++ +silc = ${dls_silc}.lib++ +ikos = ${dls_ikos}.lib++ +novas = ${VOYAGER_LIB_VHDL}/${VOYAGER_MACHINE}/novas.lib++ +[MDT] +ART_RF_SP = spr[0-9]*bx[0-9]* +ART_RF_2P = dpr[0-9]*bx[0-9]* +ART_SRAM_SP = spm[0-9]*bx[0-9]* +ART_SRAM_DP = dpm[0-9]*bx[0-9]* +VIR_SRAM_SP = hdsd1_[0-9]*x[0-9]*cm4sw1 +VIR_SRAM_DP = hdsd2_[0-9]*x[0-9]*cm4sw1 +VIR_RF_SP = rfsd1_[0-9]*x[0-9]*cm2sw0 +VIR_RF_DP = rfsd2_[0-9]*x[0-9]*cm2sw1 +VIR_STAR_SRAM_SP = shsd1_[0-9]*x[0-9]*cm4sw0 +[NPExpanding] +functiongroups = FALSE +modules = FALSE +[NPFilter] +showAssertion = TRUE +showCoverGroup = TRUE +showProperty = TRUE +showSequence = TRUE +showDollarUnit = TRUE +[OldFontRC] +Wave_legend_window_font = -f COURIER12 -c ID_CYAN5 +Wave_value_window_font = -f COURIER12 -c ID_CYAN5 +Wave_curve_window_font = -f COURIER12 -c ID_CYAN5 +Wave_group_name_font = -f COURIER12 -c ID_GREEN5 +Wave_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_comment_string_font = -f COURIER12 -c ID_RED5 +HB_designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +Text_font = COURIER12 +nMemory_font = Fixed 14 +Wave_getsignal_form_font = -f COURIER12 +Text_annotFont = Helvetica_M_R_10 +[OtherEditor] +cmd1 = "xterm -font 9x15 -fg black -bg gray -e" +name = "vi" +options = "+${CurLine} ${CurFullFileName}" +[Power] +PowerDownInstance = ID_GRAY1 +RetentionSignal = ID_YELLOW2 +IsolationSignal = ID_RED6 +LevelShiftedSignal = ID_GREEN6 +PowerSwitchObject = ID_ORANGE5 +AlwaysOnObject = ID_GREEN5 +PowerNet = ID_RED2 +GroundNet = ID_RED2 +SimulationOnly = ID_CYAN3 +SRSN/SPA = ID_CYAN3 +CNSSignal = ID_CYAN3 +RPTRSignal = ID_CYAN3 +AcknowledgeSignal = ID_CYAN3 +BoundaryPort = ID_CYAN3 +DisplayInstrumentedCell = TRUE +ShowCmdByFile = FALSE +ShowPstAnnot = FALSE +ShowIsoSymbol = TRUE +ExtractIsoSameNets = FALSE +AnnotateSignal = TRUE +HighlightPowerObject = TRUE +HighlightPowerDomain = TRUE +TraceThroughInstruLowPower = FALSE +BrightenPowerColorInSchematicWindow = FALSE +ShowAlias = FALSE +ShowVoltage = TRUE +MatchTreeNodesCaseInsensitive = FALSE +SearchHBNodeDynamically = FALSE +ContinueTracingSupplyOrLogicNet = FALSE +[Print] +PrinterName = lp +FileName = test.ps +PaperSize = A4 - 210x297 (mm) +ColorPrint = FALSE +[PropertyTools] +saveWaveformStat = TRUE +savePropStat = FALSE +savePropDtl = TRUE +[QtDialog] +EventReportDialog = 590,405,720,280 +QwUserAskDlg = 798,487,324,134 +[Relationship] +hideRecursiceNode = FALSE +[Session Cache] +3 = string (session file name) +4 = string (session file name) +5 = string (session file name) +1 = /home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/novas_autosave.ses +2 = /home/shbyang/verdiLog/novas_autosave.ses +[Simulation] +scsPath = scsim +scsOption = +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +osciPath = gdb +osciOption = +vcsPath = simv +vcsOption = +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +speedsimPath = +speedsimOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +interactiveDebugging = {True, False} +KeepBreakPoints = False +ScsDebugAll = False +simType = {vcssv, xl, nc, vcs, mti, mti_vlog, vhnc, scs, mixnc} +thirdpartyIdx = -1 +iscCmdSep = FALSE +NoAppendOption = False +[SimulationPlus] +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +vcsPath = simv +vcsOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +speedsimPath = verilog +speedsimOption = +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +scsPath = scsim +scsOption = +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +vcs_svPath = simv +vcs_svOption = +simType = vcssv +thirdpartyIdx = -1 +interactiveDebugging = FALSE +KeepBreakPoints = FALSE +iscCmdSep = FALSE +ScsDebugAll = FALSE +NoAppendOption = FALSE +invokeSimPath = work +[SimulationPlus2] +eventDumpUnfinish = FALSE +[Source] +wordWrapOn = TRUE +viewReuse = TRUE +lineNumberOn = TRUE +warnOutdatedDlg = TRUE +showEncrypt = FALSE +loadInclude = FALSE +showColorForActive = FALSE +tabWidth = 8 +editor = vi +reload = Never +sync_active_to_source = TRUE +navigateAsColored = FALSE +navigateCovered = FALSE +navigateUncovered = TRUE +navigateExcluded = FALSE +not_ask_for_source_path = FALSE +expandMacroOn = TRUE +expandMacroInstancesThreshold = 10000 +[SourceVHDL] +vhSimType = ModelSim +ohSimType = VCS +[TclShell] +nLineSize = 1024 +[Test] +verbose_progress = FALSE +[TestBenchBrowser] +-showUVMDynamicHierTreeWin = FALSE +[Text] +hdlTypeName = blue4 +hdlLibrary = blue4 +viewport = 396 392 445 487 +hdlOther = ID_BLACK +hdlComment = ID_GRAY1 +hdlKeyword = ID_BLUE5 +hdlEntity = ID_BLACK +hdlEntityInst = ID_BLACK +hdlSignal = ID_RED2 +hdlInSignal = ID_RED2 +hdlOutSignal = ID_RED2 +hdlInOutSignal = ID_RED2 +hdlOperator = ID_BLACK +hdlMinus = ID_BLACK +hdlSymbol = ID_BLACK +hdlString = ID_BLACK +hdlNumberBase = ID_BLACK +hdlNumber = ID_BLACK +hdlLiteral = ID_BLACK +hdlIdentifier = ID_BLACK +hdlSystemTask = ID_BLACK +hdlParameter = ID_BLACK +hdlIncFile = ID_BLACK +hdlDataFile = ID_BLACK +hdlCDSkipIf = ID_GRAY1 +hdlMacro = ID_BLACK +hdlMacroValue = ID_BLACK +hdlPlainText = ID_BLACK +hdlOvaId = ID_PURPLE2 +hdlPslId = ID_PURPLE2 +HvlEId = ID_BLACK +HvlVERAId = ID_BLACK +hdlEscSignal = ID_BLACK +hdlEscInSignal = ID_BLACK +hdlEscOutSignal = ID_BLACK +hdlEscInOutSignal = ID_BLACK +textBackgroundColor = ID_GRAY6 +textHiliteBK = ID_BLUE5 +textHiliteText = ID_WHITE +textTracedMark = ID_GREEN2 +textLineNo = ID_BLACK +textFoldedLineNo = ID_RED5 +textUserKeyword = ID_GREEN2 +textParaAnnotText = ID_BLACK +textFuncAnnotText = ID_BLUE2 +textAnnotText = ID_BLACK +textUserDefAnnotText = ID_BLACK +ComputedSignal = ID_PURPLE5 +textAnnotTextShadow = ID_WHITE +parenthesisBGColor = ID_YELLOW5 +codeInParenthesis = ID_CYAN5 +text3DLight = ID_WHITE +text3DShadow = ID_BLACK +textHvlDriver = ID_GREEN3 +textHvlLoad = ID_YELLOW3 +textHvlDriverLoad = ID_BLUE3 +irOutline = ID_RED2 +irDriver = ID_YELLOW5 +irLoad = ID_BLACK +irBookMark = ID_YELLOW2 +irIndicator = ID_WHITE +irBreakpoint = ID_GREEN5 +irCurLine = ID_BLUE5 +hdlVhEntity = ID_BLACK +hdlArchitecture = ID_BLACK +hdlPackage = ID_BLUE5 +hdlRefPackage = ID_BLUE5 +hdlAlias = ID_BLACK +hdlGeneric = ID_BLUE5 +specialAnnotShadow = ID_BLUE1 +hdlZeroInHead = ID_GREEN2 +hdlZeroInComment = ID_GREEN2 +hdlPslHead = ID_BLACK +hdlPslComment = ID_BLACK +hdlSynopsysHead = ID_GREEN2 +hdlSynopsysComment = ID_GREEN2 +pdmlIdentifier = ID_BLACK +pdmlCommand = ID_BLACK +pdmlMacro = ID_BLACK +font = COURIER12 +annotFont = Helvetica_M_R_10 +[Text.1] +viewport = -1 27 1920 977 45 +[TextPrinter] +Orientation = Landscape +Indicator = FALSE +LineNum = TRUE +FontSize = 7 +Column = 2 +Annotation = TRUE +[Texteditor] +TexteditorFont = "Clean 14" +TexteditorBG = white +TexteditorFG = black +[ThirdParty] +ThirdPartySimTool = verisity surefire ikos finsim +[TurboEditor] +autoBackup = TRUE +[UserButton.mixnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +Button8 = "FSDB Ver" "call fsdbVersion" +Button9 = "Dump On" "call fsdbDumpon" +Button10 = "Dump Off" "call fsdbDumpoff" +Button11 = "All Tasks" "call" +Button12 = "Dump Selected Instance" "call fsdbDumpvars 1 ${SelInst}" +[UserButton.mti] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.mti_vlog] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.nc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.scs] +Button1 = "Dump All Signals" "call fsdbDumpvars(0, \"${TopScope}\");\n" +Button2 = "Next 1000 Time" "run 1000 \n" +Button3 = "Next ? Time" "run ${Arg:Next Time} \n" +Button4 = "Run Step" "step\n" +Button5 = "Show Variables" "ls -v {${SelVars}}\n" +[UserButton.vhnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.xl] +Button13 = "Dump Off" "$fsdbDumpoff;\n" +Button12 = "Dump On" "$fsdbDumpon;\n" +Button11 = "Delete Focus" "$db_deletefocus(${treeSelScope});\n" +Button10 = "Set Focus" "$db_setfocus(${treeSelScope});\n" +Button9 = "Deposit Variable" "$deposit(${SelVar},${Arg:New Value});\n" +Button8 = "Release Variable" "release ${SelVar};\n" +Button7 = "Force Variable" "force ${SelVar} = ${Arg:New Value};\n" +Button6 = "Show Variables" "$showvars(${SelVars});\n" +Button5 = "Next ? Event" "$db_step(${Arg:Next Event});\n" +Button4 = "Next Event" "$db_step(1);\n" +Button3 = "Next ? Time" "#${Arg:Next Time} $stop;.\n" +Button2 = "Next 1000 Time" "#1000 $stop;.\n" +Button1 = "Dump All Signals" "$fsdbDumpvars;\n" +[VIA] +viaLogViewerDefaultRuleOneSearchForm = "share/VIA/Apps/PredefinedRules/Misc/Onesearch_rule.rc" +[VIA.oneSearch.preference] +DefaultDisplayTimeUnit = "1.000000ns" +DefaultLogTimeUnit = "1.000000ns" +[VIA.oneSearch.preference.vgifColumnSettingRC] +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0] +parRuleSets = "" +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column0] +name = Time +width = 60 +visualIndex = 0 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column1] +name = Message +width = 2000 +visualIndex = 4 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column2] +name = Severity +width = 60 +visualIndex = 1 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column3] +name = Code +width = 60 +visualIndex = 2 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column4] +name = Type +width = 60 +visualIndex = 3 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[Vi] +ViFont = "Clean 14" +ViBG = white +ViFG = black +[Wave] +ovaEventSuccessColor = -c ID_CYAN5 +ovaEventFailureColor = -c ID_RED5 +ovaBooleanSuccessColor = -c ID_CYAN5 +ovaBooleanFailureColor = -c ID_RED5 +ovaAssertSuccessColor = -c ID_GREEN5 +ovaAssertFailureColor = -c ID_RED5 +ovaForbidSuccessColor = -c ID_GREEN5 +SigGroupRuleFile = +DisplayFileName = FALSE +waveform_vertical_scroll_bar = TRUE +scope_to_save_with_macro +open_file_dir +open_rc_file_dir +getSignalForm = 0 0 800 479 100 30 100 30 +viewPort = 0 27 1920 392 100 65 +signalSpacing = 5 +digitalSignalHeight = 15 +analogSignalHeight = 98 +commentSignalHeight = 98 +transactionSignalHeight = 98 +messageSignalHeight = 98 +minCompErrWidth = 4 +DragZoomTolerance = 4 +maxTransExpandedLayer = 10 +WaveMaxPoint = 512 +legendBackground = -c ID_BLACK +valueBackground = -c ID_BLACK +curveBackground = -c ID_BLACK +getSignalSignalList_BackgroundColor = -c ID_GRAY6 +glitchColor = -c ID_RED5 +cursor = -c ID_YELLOW5 -lw 1 -ls long_dashed +marker = -c ID_WHITE -lw 1 -ls dash_dot_l +usermarker = -c ID_GREEN5 -lw 1 -ls long_dashed +trace = -c ID_GRAY5 -lw 1 -ls long_dashed +grid = -c ID_WHITE -lw 1 -ls short_dashed +rulerBackground = -c ID_GRAY3 +rulerForeground = -c ID_YELLOW5 +busTextColor = -c ID_ORANGE8 +legendForeground = -c ID_CYAN5 +valueForeground = -c ID_CYAN5 +curveForeground = -c ID_CYAN5 +groupNameColor = -c ID_GREEN5 +commentStringColor = -c ID_RED5 +region(Active)Background = -c ID_YELLOW1 +region(NBA)Background = -c ID_RED1 +region(Re-Active)Background = -c ID_YELLOW3 +region(Re-NBA)Background = -c ID_RED3 +region(VHDL-Delta)Background = -c ID_ORANGE3 +region(Dump-Off)Background = -c ID_GRAY4 +High_Light = -c ID_GRAY2 +Input_Signal = -c ID_RED5 +Output_Signal = -c ID_GREEN5 +InOut_Signal = -c ID_BLUE5 +Net_Signal = -c ID_YELLOW5 +Register_Signal = -c ID_PURPLE5 +Verilog_Signal = -c ID_CYAN5 +VHDL_Signal = -c ID_ORANGE5 +SystemC_Signal = -c ID_BLUE7 +Dump_Off_Color = -c ID_BLUE2 +Compress_Bar_Color = -c ID_YELLOW4 +Vector_Dense_Block_Color = -c ID_ORANGE8 +Scalar_Dense_Block_Color = -c ID_GREEN6 +Analog_Dense_Block_Color = -c ID_PURPLE2 +Composite_Dense_Block_Color = -c ID_ORANGE5 +RPTR_Power_Off_Layer = -c ID_CYAN3 -stipple dots +DB_Power_Off_Layer = -c ID_BLUE4 -stipple dots +SPA_Driver_Power_Off_Layer = -c ID_ORANGE4 -stipple dots +SPA_Receiver_Power_Off_Layer = -c ID_GREEN5 -stipple dots +SRSN_Power_Off_Layer = -c ID_GREEN4 -stipple dots +Isolation_Power_Off_Layer = -c ID_RED4 -stipple dots +PD_Power_Off_Layer = -c ID_GRAY4 -stipple dots +Isolation_Layer = -c ID_RED4 -stipple vLine +Retention_Level_Trigger_Layer = -c ID_ORANGE1 -stipple fill_solid +Retention_Edge_Trigger_Layer = -c ID_YELLOW6 -stipple fill_solid +Driving_Power_Off_Layer = -c ID_YELLOW2 -stipple x +Toggle_Layer = -c ID_YELLOW4 -stipple slash +analogRealStyle = pwl +analogVoltageStyle = pwl +analogCurrentStyle = pwl +analogOthersStyle = pwl +busSignalLayer = -c ID_ORANGE8 +busXLayer = -c ID_RED5 +busZLayer = -c ID_ORANGE6 +busMixedLayer = -c ID_GREEN5 +busNotComputedLayer = -c ID_GRAY1 +busNoValueLayer = -c ID_BLUE2 +signalGridLayer = -c ID_WHITE +analogGridLayer = -c ID_GRAY6 +analogRulerLayer = -c ID_GRAY6 +keywordLayer = -c ID_RED5 +loadedLayer = -c ID_BLUE5 +loadingLayer = -c ID_BLACK +qdsCurMarkerLayer = -c ID_BLUE5 +qdsBrkMarkerLayer = -c ID_GREEN5 +qdsTrgMarkerLayer = -c ID_RED5 +arrowDefaultColor = -c ID_ORANGE6 +startNodeArrowColor = -c ID_WHITE +endNodeArrowColor = -c ID_YELLOW5 +propertyEventMatchColor = -c ID_GREEN5 +propertyEventNoMatchColor = -c ID_RED5 +propertyVacuousSuccessMatchColor = -c ID_YELLOW2 +propertyStatusBoundaryColor = -c ID_WHITE +propertyBooleanSuccessColor = -c ID_CYAN5 +propertyBooleanFailureColor = -c ID_RED5 +propertyAssertSuccessColor = -c ID_GREEN5 +propertyAssertFailureColor = -c ID_RED5 +propertyForbidSuccessColor = -c ID_GREEN5 +transactionForegroundColor = -c ID_YELLOW8 +transactionBackgroundColor = -c ID_BLACK +transactionHighLightColor = -c ID_CYAN6 +transactionRelationshipColor = -c ID_PURPLE6 +transactionErrorTypeColor = -c ID_RED5 +coverageFullyCoveredColor = -c ID_GREEN5 +coverageNoCoverageColor = -c ID_RED5 +coveragePartialCoverageColor = -c ID_YELLOW5 +coverageReferenceLineColor = -c ID_GRAY4 +messageForegroundColor = -c ID_YELLOW4 +messageBackgroundColor = -c ID_PURPLE1 +messageHighLightColor = -c ID_CYAN6 +messageInformationColor = -c ID_RED5 +ComputedAnnotColor = -c ID_PURPLE5 +fsvSecurityDataColor = -c ID_PURPLE3 +qdsAutoBusGroup = TRUE +qdsTimeStampMode = FALSE +qdsVbfBusOrderAscending = FALSE +openDumpFilter = *.fsdb;*.vf;*.jf +DumpFileFilter = *.vcd +RestoreSignalFilter = *.rc +SaveSignalFilter = *.rc +AddAliasFilter = *.alias;*.adb +CompareSignalFilter = *.err +ConvertFFFilter = *.vcd;*.out;*.tr0;*.xp;*.raw;*.wfm +Scroll_Ratio = 100 +Zoom_Ratio = 10 +EventSequence_SyncCursorTime = TRUE +EventSequence_Sorting = FALSE +EventSequence_RemoveGrid = FALSE +EventSequence_IsGridMode = FALSE +SetDefaultRadix_global = FALSE +DefaultRadix = Hex +SigSearchSignalMatchCase = FALSE +SigSearchSignalScopeOption = FALSE +SigSearchSignalSamenetInterface = FALSE +SigSearchSignalFullScope = FALSE +SigSearchSignalWithRegExp = FALSE +SigSearchDynamically = FALSE +SigDisplayBySelectionOrder = FALSE +SigDisplayRowMajor = FALSE +SigDragSelFollowColumn = FALSE +SigDisplayHierarchyBox = TRUE +SigDisplaySubscopeBox = TRUE +SigDisplayEmptyScope = TRUE +SigDisplaySignalNavigationBox = FALSE +SigDisplayFormBus = TRUE +SigShowSubProgram = TRUE +SigSearchScopeDynamically = TRUE +SigCollapseSubtreeNodes = FALSE +activeFileApplyToAnnotation = FALSE +GrpSelMode = TRUE +dispGridCount = FALSE +hierarchyName = FALSE +partial_level_name = FALSE +partial_level_head = 1 +partial_level_tail = 1 +displayMessageLabelOnly = TRUE +autoInsertDumpoffs = TRUE +displayMessageCallStack = FALSE +displayCallStackWithFullSections = TRUE +displayCallStackWithLastSection = FALSE +limitMessageMaxWidth = FALSE +messageMaxWidth = 50 +displayTransBySpecificColor = FALSE +fittedTransHeight = FALSE +snap = TRUE +gravitySnap = FALSE +displayLeadingZero = FALSE +displayGlitchs = FALSE +allfileTimeRange = FALSE +fixDelta = FALSE +displayCursorMarker = FALSE +autoUpdate = FALSE +restoreFromActiveFile = TRUE +restoreToEnd = FALSE +dispCompErr = TRUE +showMsgDes = TRUE +anaAutoFit = FALSE +anaAutoPattn = FALSE +anaAuto100VertFit = FALSE +displayDeltaY = FALSE +centerCursor = FALSE +denseBlockDrawing = TRUE +relativeFreqPrecision = 3 +showMarkerAbsolute = FALSE +showMarkerAdjacent = FALSE +showMarkerRelative = FALSE +showMarkerFrequency = FALSE +stickCursorMarkerOnWaveform = TRUE +keepMarkerAtEndTimeOfTransaction = FALSE +doubleClickToExpandTransaction = TRUE +expandTransactionAssociatedSignals = TRUE +expandTransactionAttributeSignals = FALSE +WaveExtendLastTick = TRUE +InOutSignal = FALSE +NetRegisterSignal = FALSE +VerilogVHDLSignal = FALSE +LabelMarker = TRUE +ResolveSymbolicLink = TRUE +signal_rc_abspath = TRUE +signal_rc_no_natural_bus_range = FALSE +save_scope_with_macro = FALSE +TipInSignalWin = FALSE +DisplayPackedSiganlInBitwiseManner = FALSE +DisplaySignalTypeAheadOfSignalName = TRUE ICON +TipInCurveWin = FALSE +MouseGesturesInCurveWin = TRUE +DisplayLSBsFirst = FALSE +PaintSpecificColorPattern = TRUE +ModuleName = TRUE +form_all_memory_signal = FALSE +formBusSignalFromPartSelects = FALSE +read_value_change_on_demand_for_drawing = FALSE +load_scopes_on_demand = on 5 +TransitionMode = TRUE +DisplayRadix = FALSE +SchemaX = FALSE +Hilight = TRUE +UseBeforeValue = FALSE +DisplayFileNameAheadOfSignalName = FALSE +DisplayFileNumberAheadOfSignalName = FALSE +DisplayValueSpace = TRUE +FitAnaByBusSize = FALSE +displayTransactionAttributeName = FALSE +expandOverlappedTrans = FALSE +dispSamplePointForAttrSig = TRUE +dispClassName = TRUE +ReloadActiveFileOnly = FALSE +NormalizeEVCD = FALSE +OverwriteAliasWithRC = TRUE +overlay_added_analog_signals = FALSE +case_insensitive = FALSE +vhdlVariableCalculate = TRUE +showError = TRUE +signal_vertical_scroll_bar = TRUE +showPortNameForDroppedInstance = FALSE +truncateFilePathInTitleBar = TRUE +filterPropVacuousSuccess = FALSE +includeLocalSignals = FALSE +encloseSignalsByGroup = TRUE +resaveSignals = TRUE +adjustBusPrefix = adjustBus_ +adjustBusBits = 1 +adjustBusSettings = 69889 +maskPowerOff = TRUE +maskIsolation = TRUE +maskRetention = TRUE +maskDrivingPowerOff = TRUE +maskToggle = TRUE +autoBackupSignals = off 5 "\"/home/shbyang/verdiLog\"" "\"novas_autosave_sig\"" +signal_rc_attribute = 65535 +signal_rc_alias_attribute = 0 +ConvertAttr1 = -inc FALSE +ConvertAttr2 = -hier FALSE +ConvertAttr3 = -ucase FALSE +ConvertAttr4 = -lcase FALSE +ConvertAttr5 = -org FALSE +ConvertAttr6 = -mem 24 +ConvertAttr7 = -deli . +ConvertAttr8 = -hier_scope FALSE +ConvertAttr9 = -inst_array FALSE +ConvertAttr10 = -vhdlnaming FALSE +ConvertAttr11 = -orgScope FALSE +analogFmtPrecision = Automatic 2 +confirmOverwrite = TRUE +confirmExit = TRUE +confirmGetAll = TRUE +printTimeRange = TRUE 0.000000 0.000000 0.000000 +printPageRange = TRUE 1 1 +printOption = 0 +printBasic = 1 0 0 FALSE FALSE +printDest = -printer {} +printSignature = {%f %h %t} {} +curveWindow_Drag&Drop_Mode = TRUE +hspiceIncOpenMode = TRUE +pcSelectMode = TRUE +hierarchyDelimiter = / +RecentFile1 = "\"/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdplus_000.fsdb\"" +open_file_time_range = FALSE +value_window_aligment = Right +signal_window_alignment = Auto +ShowDeltaTime = TRUE +legend_window_font = -f COURIER12 -c ID_CYAN5 +value_window_font = -f COURIER12 -c ID_CYAN5 +curve_window_font = -f COURIER12 -c ID_CYAN5 +group_name_font = -f COURIER12 -c ID_GREEN5 +ruler_value_font = -f COURIER12 -c ID_CYAN5 +analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +comment_string_font = -f COURIER12 -c ID_RED5 +getsignal_form_font = -f COURIER12 +SigsCheckNum = on 1000 +filter_synthesized_net = off n +filterOutNet = on +filter_synthesized_instance = off +filterOutInstance = on +showGroupTree = TRUE +hierGroupDelim = / +MsgSeverityColor = {y \"Severity\"==\"1\" ID_RED5} {y \"Severity\"==\"2\" ID_RED6} {y \"Severity\"==\"3\" ID_RED7} {y \"Severity\"==\"4\" ID_RED8} {y \"Severity\"==\"5\" ID_ORANGE5} {y \"Severity\"==\"6\" ID_ORANGE6} {y \"Severity\"==\"7\" ID_ORANGE7} {y \"Severity\"==\"8\" \ +ID_GREEN7} {y \"Severity\"==\"9\" ID_GREEN6} {y \"Severity\"==\"10\" ID_GREEN5} +AutoApplySeverityColor = TRUE +AutoAdjustMsgWidthByLabel = off +verilogStrengthDispType = type1 +waveDblClkActiveTrace = on +autoConnectTBrowser = FALSE +connectTBrowserInContainer = TRUE +SEQShowComparisonIcon = TRUE +SEQAddDriverLoadInSameGroup = TRUE +autoSyncCursorMarker = FALSE +autoSyncHorizontalRange = FALSE +autoSyncVerticalScroll = FALSE +[cov_hier_name_column] +justify = TRUE +[coverageColors] +sou_uncov = TRUE +sou_pc = TRUE +sou_cov = TRUE +sou_exuncov = TRUE +sou_excov = TRUE +sou_unreach = TRUE +sou_unreachcon = TRUE +sou_fillColor_uncov = red +sou_fillColor_pc = yellow +sou_fillColor_cov = green3 +sou_fillColor_exuncov = grey +sou_fillColor_excov = #3C9371 +sou_fillColor_unreach = grey +sou_fillColor_unreachcon = orange +numberOfBins = 6 +rangeMin_0 = 0 +rangeMax_0 = 20 +fillColor_0 = #FF6464 +rangeMin_1 = 20 +rangeMax_1 = 40 +fillColor_1 = #FF9999 +rangeMin_2 = 40 +rangeMax_2 = 60 +fillColor_2 = #FF8040 +rangeMin_3 = 60 +rangeMax_3 = 80 +fillColor_3 = #FFFF99 +rangeMin_4 = 80 +rangeMax_4 = 100 +fillColor_4 = #99FF99 +rangeMin_5 = 100 +rangeMax_5 = 100 +fillColor_5 = #64FF64 +[coveragesetting] +assertTopoMode = FALSE +urgAppendOptions = +group_instance_new_format_name = TRUE +showvalue = FALSE +computeGroupsScoreByRatio = FALSE +computeGroupsScoreByInst = FALSE +showConditionId = FALSE +showfullhier = FALSE +nameLeftAlignment = TRUE +showAllInfoInTooltips = FALSE +copyItemHvpName = TRUE +ignoreGroupWeight = FALSE +absTestName = FALSE +HvpMergeTool = +ShowMergeMenuItem = FALSE +fsmScoreMode = transition +[eco] +NameRule = +IsFreezeSilicon = FALSE +cellQuantityManagement = FALSE +ManageMode = INSTANCE_NAME +SpareCellsPinsManagement = TRUE +LogCommitReport = FALSE +InputPinStatus = 1 +OutputPinStatus = 2 +RevisedComponentColor = ID_BLUE5 +SpareCellColor = ID_RED5 +UserName = shbyang +CommentFormat = Novas ECO updated by ${UserName} ${Date} ${Time} +PrefixN = eco_n +PrefixP = eco_p +PrefixI = eco_i +DefaultTieUpNet = 1'b1 +DefaultTieDownNet = 1'b0 +MultipleInstantiations = TRUE +KeepClockPinConnection = FALSE +KeepAsyncResetPinConnection = FALSE +ScriptFileModeType = 1 +MagmaScriptPower = VDD +MagmaScriptGround = GND +ShowModeMsg = TRUE +AstroScriptPower = VDD +AstroScriptGround = VSS +ClearFloatingPorts = FALSE +[eco_connection] +Port/NetIsUnique = TRUE +SerialNet = 0 +SerialPort = 0 +SerialInst = 0 +[finsim] +TPLanguage = Verilog +TPName = Super-FinSim +TPPath = TOP.sim +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[hvpsetting] +importExcelXMLOptions = +use_test_loca_as_source = FALSE +autoTurnOffHideMeetGoalInit = FALSE +autoTurnOffHideMeetGoal = TRUE +autoTurnOffModifierInit = FALSE +autoTurnOffModifier = TRUE +enableNumbering = TRUE +autoSaveCheck = TRUE +autoSaveTime = 5 +ShowMissingScore = TRUE +enableFeatureId = FALSE +enable_HVP_FEAT_ID = FALSE +enableMeasureConcealment = FALSE +HvpCloneHierShowMsgAgain = 1 +HvpCloneHierType = tree +HvpCloneHierMetrics = Line,Cond,FSM,Toggle,Branch,Assert +autoRecalPlanAfterLoadingCovDBUserDataPlan = false +warnMeAutoRecalPlanAfterLoadingCovDBUserDataPlan = true +autoRecalExclWithPlan = false +warnMeAutoRecalExclWithPlan = true +autoRecalPlanWithExcl = false +warnMeAutoRecalPlanWithExcl = true +warnPopupWarnWhenMultiFilters = true +warnPopupWarnIfHvpReadOnly = true +unmappedObjsReportLevel = def_var_inst +unmappedObjsReportInst = true +unmappedObjsNumOfObjs = High +[ikos] +TPLanguage = VHDL +TPName = Voyager +TPPath = vsh +TPOption = -X +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[imp] +options = NULL +libPath = NULL +libDir = NULL +[nCompare] +ErrorViewport = 80 180 800 550 +EditorViewport = 409 287 676 475 +EditorHeightWidth = 802 380 +WaveCommand = "novas" +WaveArgs = "-nWave" +[nCompare.Wnd0] +ViewByHier = FALSE +[nMemory] +dispMode = ADDR_HINT +addrColWidth = 120 +valueColWidth = 100 +showCellBitRangeWithAddr = TRUE +wordsShownInOneRow = 8 +syncCursorTime = FALSE +fixCellColumnWidth = FALSE +font = Courier 12 +[planColors] +plan_fillColor_inactive = lightGray +plan_fillColor_warning = orange +plan_fillColor_error = red +plan_fillColor_invalid = #F0DCDB +plan_fillColor_subplan = lightGray +[schematics] +viewport = 178 262 638 516 +schBackgroundColor = black lineSolid +schBackgroundColor_qt = #000000 qt_solidLine 1 +schBodyColor = orange6 lineSolid +schBodyColor_qt = #ffb973 qt_solidLine 1 +schAsmBodyColor = blue7 lineSolid +schAsmBodyColor_qt = #a5a5ff qt_solidLine 1 +schPortColor = orange6 lineSolid +schPortColor_qt = #ffb973 qt_solidLine 1 +schCellNameColor = Gray6 lineSolid +schCellNameColor_qt = #e0e0e0 qt_solidLine 1 +schCLKNetColor = red6 lineSolid +schCLKNetColor_qt = #ff7373 qt_solidLine 1 +schPWRNetColor = red4 lineSolid +schPWRNetColor_qt = #ff0101 qt_solidLine 1 +schGNDNetColor = cyan4 lineSolid +schGNDNetColor_qt = #01ffff qt_solidLine 1 +schSIGNetColor = green8 lineSolid +schSIGNetColor_qt = #cdffcd qt_solidLine 1 +schTraceColor = yellow4 lineSolid +schTraceColor_qt = #ffff01 qt_solidLine 2 +schBackAnnotateColor = white lineSolid +schBackAnnotateColor_qt = #ffffff qt_solidLine 1 +schValue0 = yellow4 lineSolid +schValue0_qt = #ffff01 qt_solidLine 1 +schValue1 = green3 lineSolid +schValue1_qt = #008000 qt_solidLine 1 +schValueX = red4 lineSolid +schValueX_qt = #ff0101 qt_solidLine 1 +schValueZ = purple7 lineSolid +schValueZ_qt = #ffcdff qt_solidLine 1 +dimColor = cyan2 lineSolid +dimColor_qt = #008080 qt_solidLine 1 +schPreSelColor = green4 lineDash +schPreSelColor_qt = #01ff01 qt_dashLine 2 +schSIGBusNetColor = green8 lineSolid +schSIGBusNetColor_qt = #cdffcd qt_solidLine +schGNDBusNetColor = cyan4 lineSolid +schGNDBusNetColor_qt = #01ffff qt_solidLine +schPWRBusNetColor = red4 lineSolid +schPWRBusNetColor_qt = #ff0101 qt_solidLine +schCLKBusNetColor = red6 lineSolid +schCLKBusNetColor_qt = #ff7373 qt_solidLine +schEdgeSensitiveColor = orange6 lineSolid +schEdgeSensitiveColor_qt = #ffb973 qt_solidLine +schAnnotColor = cyan4 lineSolid +schAnnotColor_qt = #01ffff qt_solidLine +schInstNameColor = orange6 lineSolid +schInstNameColor_qt = #ffb973 qt_solidLine +schPortNameColor = cyan4 lineSolid +schPortNameColor_qt = #01ffff qt_solidLine +schAsmLatchColor = cyan4 lineSolid +schAsmLatchColor_qt = #01ffff qt_solidLine +schAsmRegColor = cyan4 lineSolid +schAsmRegColor_qt = #01ffff qt_solidLine +schAsmTriColor = cyan4 lineSolid +schAsmTriColor_qt = #01ffff qt_solidLine +pre_select = True +ShowPassThroughNet = False +ComputedAnnotColor = ID_PURPLE5 +[schematics_print] +Signature = FALSE +DesignName = PCU +DesignerName = bai +SignatureLocation = LowerRight +MultiPage = TRUE +AutoSliver = FALSE +[sourceColors] +BackgroundActive = gray88 +BackgroundInactive = lightgray +InactiveCode = dimgray +Selection = darkblue +Standard = black +Keyword = blue +Comment = gray25 +Number = black +String = black +Identifier = darkred +Inline = green +colorIdentifier = green +Value = darkgreen +MacroBackground = white +Missing = #400040 +[specColors] +top_plan_linked = #ADFFA6 +top_plan_ignore = #D3D3D3 +top_plan_todo = #EECBAD +sub_plan_ignore = #919191 +sub_plan_todo = #EFAFAF +sub_plan_linked = darkorange +[spec_link_setting] +use_spline = true +goto_section = false +exclude_ignore = true +truncate_abstract = false +abstract_length = 999 +compare_strategy = 2 +auto_apply_margin = FALSE +margin_top = 0.80 +margin_bottom = 0.80 +margin_left = 0.50 +margin_right = 0.50 +margin_unit = inches +[spiceDebug] +ThroughNet = ID_YELLOW5 +InstrumentSig = ID_GREEN5 +InterfaceElement = ID_GREEN5 +Run-timeInterfaceElement = ID_BLUE5 +HighlightThroughNet = TRUE +HighlightInterfaceElement = TRUE +HighlightRuntimeInterfaceElement = TRUE +HighlightSameNet = TRUE +[surefire] +TPLanguage = Verilog +TPName = SureFire +TPPath = verilog +TPOption = +AddImportArgument = TRUE +LineBreakWithScope = TRUE +StopAfterCompileOption = -tcl +[turboSchema_Printer_Options] +Orientation = Landscape +[turbo_library] +bdb_load_scope = +[vdCovFilteringSearchesStrings] +keepLastUsedFiltersMaxNum = 10 +[verisity] +TPLanguage = Verilog +TPName = "Verisity SpeXsim" +TPPath = vlg +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = TRUE +StopAfterCompileOption = -s +[wave.0] +viewPort = 0 27 1920 392 100 65 +[wave.1] +viewPort = 127 219 960 332 100 65 +[wave.2] +viewPort = 38 314 686 205 100 65 +[wave.3] +viewPort = 63 63 700 400 65 41 +[wave.4] +viewPort = 84 84 700 400 65 41 +[wave.5] +viewPort = 92 105 700 400 65 41 +[wave.6] +viewPort = 0 0 700 400 65 41 +[wave.7] +viewPort = 21 21 700 400 65 41 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/novas_dump.log b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/novas_dump.log new file mode 100644 index 0000000..eee133d --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/novas_dump.log @@ -0,0 +1,407 @@ +####################################################################################### +# log primitive debug message of FSDB dumping # +# This is for R&D to analyze when there are issues happening when FSDB dump # +####################################################################################### +ANF: vcsd_get_serial_mode_status('./simv: undefined symbol: vcsd_get_serial_mode_status') +ANF: vcsd_enable_sva_success_callback('./simv: undefined symbol: vcsd_enable_sva_success_callback') +ANF: vcsd_disable_sva_success_callback('./simv: undefined symbol: vcsd_disable_sva_success_callback') +ANF: vcsd_get_power_scope_name('./simv: undefined symbol: vcsd_get_power_scope_name') +ANF: vcsd_begin_no_value_var_info('./simv: undefined symbol: vcsd_begin_no_value_var_info') +ANF: vcsd_end_no_value_var_info('./simv: undefined symbol: vcsd_end_no_value_var_info') +ANF: vcsd_remove_xprop_merge_mode_callback('./simv: undefined symbol: vcsd_remove_xprop_merge_mode_callback') +ANF: vhpi_get_cb_info('./simv: undefined symbol: vhpi_get_cb_info') +ANF: vhpi_free_handle('./simv: undefined symbol: vhpi_free_handle') +ANF: vhpi_fetch_vcsd_handle('./simv: undefined symbol: vhpi_fetch_vcsd_handle') +ANF: vhpi_fetch_vpi_handle('./simv: undefined symbol: vhpi_fetch_vpi_handle') +ANF: vhpi_has_verilog_parent('./simv: undefined symbol: vhpi_has_verilog_parent') +ANF: vhpi_is_verilog_scope('./simv: undefined symbol: vhpi_is_verilog_scope') +ANF: scsd_xprop_is_enabled('./simv: undefined symbol: scsd_xprop_is_enabled') +ANF: scsd_xprop_sig_is_promoted('./simv: undefined symbol: scsd_xprop_sig_is_promoted') +ANF: scsd_xprop_int_xvalue('./simv: undefined symbol: scsd_xprop_int_xvalue') +ANF: scsd_xprop_bool_xvalue('./simv: undefined symbol: scsd_xprop_bool_xvalue') +ANF: scsd_xprop_enum_xvalue('./simv: undefined symbol: scsd_xprop_enum_xvalue') +ANF: scsd_xprop_register_merge_mode_cb('./simv: undefined symbol: scsd_xprop_register_merge_mode_cb') +ANF: scsd_xprop_delete_merge_mode_cb('./simv: undefined symbol: scsd_xprop_delete_merge_mode_cb') +ANF: scsd_xprop_get_merge_mode('./simv: undefined symbol: scsd_xprop_get_merge_mode') +ANF: scsd_thread_get_info('./simv: undefined symbol: scsd_thread_get_info') +ANF: scsd_thread_vc_init('./simv: undefined symbol: scsd_thread_vc_init') +ANF: scsd_master_set_delta_sync_cbk('./simv: undefined symbol: scsd_master_set_delta_sync_cbk') +ANF: scsd_fgp_get_fsdb_cores('./simv: undefined symbol: scsd_fgp_get_fsdb_cores') +ANF: msvEnableDumpingMode('./simv: undefined symbol: msvEnableDumpingMode') +ANF: msvGetVersion('./simv: undefined symbol: msvGetVersion') +ANF: msvGetInstProp('./simv: undefined symbol: msvGetInstProp') +ANF: msvIsSpiceEngineReady('./simv: undefined symbol: msvIsSpiceEngineReady') +ANF: msvSetAddProbeCallback('./simv: undefined symbol: msvSetAddProbeCallback') +ANF: msvGetInstHandle('./simv: undefined symbol: msvGetInstHandle') +ANF: msvGetProbeByInst('./simv: undefined symbol: msvGetProbeByInst') +ANF: msvGetSigHandle('./simv: undefined symbol: msvGetSigHandle') +ANF: msvGetProbeBySig('./simv: undefined symbol: msvGetProbeBySig') +ANF: msvGetProbeInfo('./simv: undefined symbol: msvGetProbeInfo') +ANF: msvRelease('./simv: undefined symbol: msvRelease') +ANF: msvSetVcCallbackFunc('./simv: undefined symbol: msvSetVcCallbackFunc') +ANF: msvCheckVcCallback('./simv: undefined symbol: msvCheckVcCallback') +ANF: msvAddVcCallback('./simv: undefined symbol: msvAddVcCallback') +ANF: msvRemoveVcCallback('./simv: undefined symbol: msvRemoveVcCallback') +ANF: msvGetLatestValue('./simv: undefined symbol: msvGetLatestValue') +ANF: msvSetEndofSimCallback('./simv: undefined symbol: msvSetEndofSimCallback') +ANF: msvIgnoredProbe('./simv: undefined symbol: msvIgnoredProbe') +ANF: msvGetThruNetInfo('./simv: undefined symbol: msvGetThruNetInfo') +ANF: msvFreeThruNetInfo('./simv: undefined symbol: msvFreeThruNetInfo') +ANF: PI_ace_get_output_time_unit('./simv: undefined symbol: PI_ace_get_output_time_unit') +ANF: PI_ace_sim_sync('./simv: undefined symbol: PI_ace_sim_sync') +ANF: msvGetRereadInitFile('./simv: undefined symbol: msvGetRereadInitFile') +ANF: msvSetBeforeRereadCallback('./simv: undefined symbol: msvSetBeforeRereadCallback') +ANF: msvSetAfterRereadCallback('./simv: undefined symbol: msvSetAfterRereadCallback') +ANF: msvSetForceCallback('./simv: undefined symbol: msvSetForceCallback') +ANF: msvSetReleaseCallback('./simv: undefined symbol: msvSetReleaseCallback') +ANF: msvGetForceStatus('./simv: undefined symbol: msvGetForceStatus') +ANF: vhdi_dt_get_type('./simv: undefined symbol: vhdi_dt_get_type') +ANF: vhdi_dt_get_key('./simv: undefined symbol: vhdi_dt_get_key') +ANF: vhdi_dt_get_vhdl_enum_info('./simv: undefined symbol: vhdi_dt_get_vhdl_enum_info') +ANF: vhdi_dt_get_vhdl_physical_info('./simv: undefined symbol: vhdi_dt_get_vhdl_physical_info') +ANF: vhdi_dt_get_vhdl_array_info('./simv: undefined symbol: vhdi_dt_get_vhdl_array_info') +ANF: vhdi_dt_get_vhdl_record_info('./simv: undefined symbol: vhdi_dt_get_vhdl_record_info') +ANF: vhdi_def_traverse_module('./simv: undefined symbol: vhdi_def_traverse_module') +ANF: vhdi_def_traverse_scope('./simv: undefined symbol: vhdi_def_traverse_scope') +ANF: vhdi_def_traverse_variable('./simv: undefined symbol: vhdi_def_traverse_variable') +ANF: vhdi_def_get_module_id_by_vhpi('./simv: undefined symbol: vhdi_def_get_module_id_by_vhpi') +ANF: vhdi_def_get_handle_by_module_id('./simv: undefined symbol: vhdi_def_get_handle_by_module_id') +ANF: vhdi_def_get_variable_info_by_vhpi('./simv: undefined symbol: vhdi_def_get_variable_info_by_vhpi') +ANF: vhdi_def_free('./simv: undefined symbol: vhdi_def_free') +ANF: vhdi_ist_traverse_scope('./simv: undefined symbol: vhdi_ist_traverse_scope') +ANF: vhdi_ist_traverse_variable('./simv: undefined symbol: vhdi_ist_traverse_variable') +ANF: vhdi_ist_convert_by_vhpi('./simv: undefined symbol: vhdi_ist_convert_by_vhpi') +ANF: vhdi_ist_clone('./simv: undefined symbol: vhdi_ist_clone') +ANF: vhdi_ist_free('./simv: undefined symbol: vhdi_ist_free') +ANF: vhdi_ist_hash_key('./simv: undefined symbol: vhdi_ist_hash_key') +ANF: vhdi_ist_compare('./simv: undefined symbol: vhdi_ist_compare') +ANF: vhdi_ist_get_value_addr('./simv: undefined symbol: vhdi_ist_get_value_addr') +ANF: vhdi_set_scsd_callback('./simv: undefined symbol: vhdi_set_scsd_callback') +ANF: vhdi_cbk_set_force_callback('./simv: undefined symbol: vhdi_cbk_set_force_callback') +ANF: vhdi_trigger_init_force('./simv: undefined symbol: vhdi_trigger_init_force') +ANF: vhdi_ist_check_scsd_callback('./simv: undefined symbol: vhdi_ist_check_scsd_callback') +ANF: vhdi_ist_add_scsd_callback('./simv: undefined symbol: vhdi_ist_add_scsd_callback') +ANF: vhdi_ist_remove_scsd_callback('./simv: undefined symbol: vhdi_ist_remove_scsd_callback') +ANF: vhdi_ist_get_scsd_user_data('./simv: undefined symbol: vhdi_ist_get_scsd_user_data') +ANF: vhdi_add_time_change_callback('./simv: undefined symbol: vhdi_add_time_change_callback') +ANF: vhdi_get_real_value_by_value_addr('./simv: undefined symbol: vhdi_get_real_value_by_value_addr') +ANF: vhdi_get_64_value_by_value_addr('./simv: undefined symbol: vhdi_get_64_value_by_value_addr') +ANF: vhdi_xprop_inst_is_promoted('./simv: undefined symbol: vhdi_xprop_inst_is_promoted') +ANF: vdi_ist_convert_by_vhdi('./simv: undefined symbol: vdi_ist_convert_by_vhdi') +ANF: vhdi_ist_get_module_id('./simv: undefined symbol: vhdi_ist_get_module_id') +ANF: vhdi_refine_foreign_scope_type('./simv: undefined symbol: vhdi_refine_foreign_scope_type') +ANF: vhdi_flush_callback('./simv: undefined symbol: vhdi_flush_callback') +ANF: vhdi_set_orig_name('./simv: undefined symbol: vhdi_set_orig_name') +ANF: vhdi_set_dump_pt('./simv: undefined symbol: vhdi_set_dump_pt') +ANF: vhdi_get_fsdb_option('./simv: undefined symbol: vhdi_get_fsdb_option') +ANF: vhdi_fgp_get_mode('./simv: undefined symbol: vhdi_fgp_get_mode') +ANF: vhdi_node_register_composite_var('./simv: undefined symbol: vhdi_node_register_composite_var') +ANF: vhdi_node_analysis('./simv: undefined symbol: vhdi_node_analysis') +ANF: vhdi_node_id('./simv: undefined symbol: vhdi_node_id') +ANF: vhdi_node_ist_check_scsd_callback('./simv: undefined symbol: vhdi_node_ist_check_scsd_callback') +ANF: vhdi_node_ist_add_scsd_callback('./simv: undefined symbol: vhdi_node_ist_add_scsd_callback') +ANF: vhdi_node_ist_get_value_addr('./simv: undefined symbol: vhdi_node_ist_get_value_addr') +VCS compile option: + option[0]: ./simv + option[1]: -l + option[2]: sim.log + option[3]: -cm + option[4]: line+cond+fsm+tgl+branch + option[5]: -cm_dir + option[6]: ../../coverage/try/ + option[7]: -cm_name + option[8]: flattop + option[9]: +ENABLE_FSDB=1 + option[10]: /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/vcs1 + option[11]: -Mcc=gcc + option[12]: -Mcplusplus=g++ + option[13]: -Masflags= + option[14]: -Mcfl= -pipe -fPIC -O -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include + option[15]: -Mxcflags= -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include + option[16]: -Mldflags= -rdynamic + option[17]: -Mout=simv + option[18]: -Mamsrun= + option[19]: -Mvcsaceobjs= + option[20]: -Mobjects= /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvirsim.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/liberrorinf.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a + option[21]: -Mexternalobj= + option[22]: -Msaverestoreobj=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o + option[23]: -Mcrt0= + option[24]: -Mcrtn= + option[25]: -Mcsrc= + option[26]: -Msyslibs=/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lm + option[27]: -l + option[28]: compile.log + option[29]: -full64 + option[30]: -j8 + option[31]: +lint=TFIPC-L + option[32]: +v2k + option[33]: -debug_access+all + option[34]: +vpi + option[35]: +vcsd1 + option[36]: +itf+/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab + option[37]: -debug_region+cell+encrypt + option[38]: -P + option[39]: /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab + option[40]: +define+DUMP_FSDB + option[41]: -lca + option[42]: -q + option[43]: -timescale=1ns/1ps + option[44]: +nospecify + option[45]: -cm + option[46]: line+cond+fsm+tgl+branch + option[47]: -cm_dir + option[48]: ./coverage/simv.vdb + option[49]: -picarchive + option[50]: -P + option[51]: /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab + option[52]: -fsdb + option[53]: -sverilog + option[54]: -gen_obj + option[55]: -f + option[56]: filelist_vlg.f + option[57]: +incdir+./../../rtl/define + option[58]: +incdir+./../../rtl/qubitmcu + option[59]: +incdir+./../../model + option[60]: -load + option[61]: /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/libnovas.so:FSDBDumpCmd + option[62]: timescale=1ns/1ps +Chronologic Simulation VCS Release O-2018.09-SP2_Full64 +Linux 3.10.0-1160.92.1.el7.x86_64 #1 SMP Tue Jun 20 11:48:01 UTC 2023 x86_64 +CPU cores: 96 +Limit information: +====================================== +cputime unlimited +filesize unlimited +datasize unlimited +stacksize 8194 kbytes +coredumpsize 0 kbytes +memoryuse unlimited +vmemoryuse unlimited +descriptors 4096 +memorylocked 64 kbytes +maxproc 4096 +====================================== +(Special)Runtime environment variables: + +Runtime environment variables: +XMODIFIERS=@im=ibus +SPECTRE_DEFAULTS=-E +SHELL=/bin/bash +VTE_VERSION=5204 +AMS_ENABLE_NOISE=YES +_=/bin/csh +OA_UNSUPPORTED_PLAT=linux_rhel50_gcc44x +SPECMAN_DIR=/opt/cadence/INCISIVE152/components/sn +HISTCONTROL=ignoredups +SNPSLMD_LICENSE_FILE=27050@cryo1 +MENTOR_HOME=/opt/mentor +XDG_DATA_DIRS=/home/shbyang/.local/share/flatpak/exports/share:/var/lib/flatpak/exports/share:/usr/local/share:/usr/share +DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-pbYbSoHCDo,guid=6bec37f851a0ec63831138606819dc51 +MACHTYPE=x86_64 +LESSOPEN=||/usr/bin/lesspipe.sh %s +CDSROOT=/opt/cadence/IC618 +FM_HOME=/opt/synopsys/fm/L-2016.03-SP1 +CDS_LIC_ONLY=1 +CDSDIR=/opt/cadence/IC618 +PATH=/opt/compiler/V0P100:/opt/synopsys/fpga/K-2015.09/bin:/opt/synopsys/vc_stat/vc_static/V-2023.12/bin:/opt/synopsys/wv/N-2017.12-SP2/bin:/opt/synopsys/hspice/N-2017.12-SP2/hspice/bin:/opt/synopsys/idq/O-2018.06-SP1/linux64/iddq/bin:/opt/synopsys/txs/O-2018.06-SP1/bin:/opt/synopsys/lc/O-2018.06-SP1/bin:/opt/synopsys/starrc/O-2018.06-SP1/bin:/opt/synopsys/fm/L-2016.03-SP1/bin:/opt/synopsys/pwr/O-2018.06-SP3/bin:/opt/synopsys/pts/O-2018.06-SP1/bin:/opt/synopsys/syn/O-2018.06-SP1/bin:/opt/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/opt/synopsys/vcs-mx/O-2018.09-SP2/gui/dve/bin:/opt/synopsys/vcs-mx/O-2018.09-SP2/bin:/opt/synopsys/scl/2018.06/linux64/bin:/opt/compiler/V0P100:/opt/synopsys/fpga/K-2015.09/bin:/opt/synopsys/vc_stat/vc_static/V-2023.12/bin:/opt/synopsys/wv/N-2017.12-SP2/bin:/opt/synopsys/hspice/N-2017.12-SP2/hspice/bin:/opt/synopsys/idq/O-2018.06-SP1/linux64/iddq/bin:/opt/synopsys/txs/O-2018.06-SP1/bin:/opt/synopsys/lc/O-2018.06-SP1/bin:/opt/synopsys/starrc/O-2018.06-SP1/bin:/opt/synopsys/fm/L-2016.03-SP1/bin:/opt/synopsys/pwr/O-2018.06-SP3/bin:/opt/synopsys/pts/O-2018.06-SP1/bin:/opt/synopsys/syn/O-2018.06-SP1/bin:/opt/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/opt/synopsys/vcs-mx/O-2018.09-SP2/gui/dve/bin:/opt/synopsys/vcs-mx/O-2018.09-SP2/bin:/opt/synopsys/scl/2018.06/linux64/bin:/opt/xilinx/Vivado/2019.2/bin:/opt/xilinx/DocNav:/usr/local/git/bin:/usr/lib64/qt-3.3/bin:/usr/local/bin:/bin:/usr/bin:/usr/local/sbin:/usr/sbin:/home/shbyang/.local/bin:/home/shbyang/bin:/opt/cadence/IC618/tools/bin:/opt/cadence/IC618/tools/dfII/bin:/opt/cadence/IC618/tools/plot/bin:/opt/cadence/SPECTRE181/bin:/opt/cadence/SPECTRE181/tools/bin:/opt/cadence/INNOVUS181/bin:/opt/cadence/INNOVUS181/tools/bin:/opt/cadence/GENUS152/bin:/opt/cadence/GENUS152/tools/bin:/opt/cadence/INCISIVE152/bin:/opt/cadence/INCISIVE152/tools/bin:/opt/cadence/INCISIVE152/tools.lnx86/bin:/opt/cadence/INCISIVE152/tools/dfII/bin:/opt/cadence/INCISIVE152/tools.lnx86/dfII/bin:/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/bin:/opt/xilinx/Vivado/2019.2//bin:/opt/xilinx/Vivado/2019.2//bin/unwrapped/lnx64.o/:/opt/cadence/IC618/tools/bin:/opt/cadence/IC618/tools/dfII/bin:/opt/cadence/IC618/tools/plot/bin:/opt/cadence/SPECTRE181/bin:/opt/cadence/SPECTRE181/tools/bin:/opt/cadence/INNOVUS181/bin:/opt/cadence/INNOVUS181/tools/bin:/opt/cadence/GENUS152/bin:/opt/cadence/GENUS152/tools/bin:/opt/cadence/INCISIVE152/bin:/opt/cadence/INCISIVE152/tools/bin:/opt/cadence/INCISIVE152/tools.lnx86/bin:/opt/cadence/INCISIVE152/tools/dfII/bin:/opt/cadence/INCISIVE152/tools.lnx86/dfII/bin:/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/bin:/opt/xilinx/Vivado/2019.2//bin:/opt/xilinx/Vivado/2019.2//bin/unwrapped/lnx64.o/ +MGC_PDF_REDER=evince +XILINX_VIVADO=/opt/xilinx/Vivado/2019.2 +CDS_ROOT=/opt/cadence/IC618 +QT_GRAPHICSSYSTEM_CHECKED=1 +SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/24088,unix/unix:/tmp/.ICE-unix/24088 +SPECTRE_HOME=/opt/cadence/SPECTRE181 +XDG_RUNTIME_DIR=/run/user/1019 +VENDOR=unknown +CDS_AUTO_64BIT=ALL +XDG_MENU_PREFIX=gnome- +LS_COLORS=rs=0:di=38;5;27:ln=38;5;51:mh=44;38;5;15:pi=40;38;5;11:so=38;5;13:do=38;5;5:bd=48;5;232;38;5;11:cd=48;5;232;38;5;3:or=48;5;232;38;5;9:mi=05;48;5;232;38;5;15:su=48;5;196;38;5;15:sg=48;5;11;38;5;16:ca=48;5;196;38;5;226:tw=48;5;10;38;5;16:ow=48;5;10;38;5;21:st=48;5;21;38;5;15:ex=38;5;34:*.tar=38;5;9:*.tgz=38;5;9:*.arc=38;5;9:*.arj=38;5;9:*.taz=38;5;9:*.lha=38;5;9:*.lz4=38;5;9:*.lzh=38;5;9:*.lzma=38;5;9:*.tlz=38;5;9:*.txz=38;5;9:*.tzo=38;5;9:*.t7z=38;5;9:*.zip=38;5;9:*.z=38;5;9:*.Z=38;5;9:*.dz=38;5;9:*.gz=38;5;9:*.lrz=38;5;9:*.lz=38;5;9:*.lzo=38;5;9:*.xz=38;5;9:*.bz2=38;5;9:*.bz=38;5;9:*.tbz=38;5;9:*.tbz2=38;5;9:*.tz=38;5;9:*.deb=38;5;9:*.rpm=38;5;9:*.jar=38;5;9:*.war=38;5;9:*.ear=38;5;9:*.sar=38;5;9:*.rar=38;5;9:*.alz=38;5;9:*.ace=38;5;9:*.zoo=38;5;9:*.cpio=38;5;9:*.7z=38;5;9:*.rz=38;5;9:*.cab=38;5;9:*.jpg=38;5;13:*.jpeg=38;5;13:*.gif=38;5;13:*.bmp=38;5;13:*.pbm=38;5;13:*.pgm=38;5;13:*.ppm=38;5;13:*.tga=38;5;13:*.xbm=38;5;13:*.xpm=38;5;13:*.tif=38;5;13:*.tiff=38;5;13:*.png=38;5;13:*.svg=38;5;13:*.svgz=38;5;13:*.mng=38;5;13:*.pcx=38;5;13:*.mov=38;5;13:*.mpg=38;5;13:*.mpeg=38;5;13:*.m2v=38;5;13:*.mkv=38;5;13:*.webm=38;5;13:*.ogm=38;5;13:*.mp4=38;5;13:*.m4v=38;5;13:*.mp4v=38;5;13:*.vob=38;5;13:*.qt=38;5;13:*.nuv=38;5;13:*.wmv=38;5;13:*.asf=38;5;13:*.rm=38;5;13:*.rmvb=38;5;13:*.flc=38;5;13:*.avi=38;5;13:*.fli=38;5;13:*.flv=38;5;13:*.gl=38;5;13:*.dl=38;5;13:*.xcf=38;5;13:*.xwd=38;5;13:*.yuv=38;5;13:*.cgm=38;5;13:*.emf=38;5;13:*.axv=38;5;13:*.anx=38;5;13:*.ogv=38;5;13:*.ogx=38;5;13:*.aac=38;5;45:*.au=38;5;45:*.flac=38;5;45:*.mid=38;5;45:*.midi=38;5;45:*.mka=38;5;45:*.mp3=38;5;45:*.mpc=38;5;45:*.ogg=38;5;45:*.ra=38;5;45:*.wav=38;5;45:*.axa=38;5;45:*.oga=38;5;45:*.spx=38;5;45:*.xspf=38;5;45: +MOZILLA_HOME=/usr/bin/firefox +SSH_AUTH_SOCK=/run/user/1019/keyring/ssh +DISPLAY=unix:17 +MGC_HOME=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11 +IMSETTINGS_INTEGRATE_DESKTOP=yes +HOME=/home/shbyang +VCS_HOME=/opt/synopsys/vcs-mx/O-2018.09-SP2 +PWD=/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/flattop +FPGA_HOME=/opt/synopsys/fpga/K-2015.09 +SSH_AGENT_PID=24257 +CALIBRE_HOME=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11 +MGC_CALIBRE_REALTIME_VIRTUOSO_ENABLED=1 +VERDI_HOME=/opt/synopsys/verdi/Verdi_O-2018.09-SP2 +MGLS_LICENSE_FILE=/opt/mentor/license/license.dat +PT_HOME=/opt/synopsys/pts/O-2018.06-SP1 +SYNOPSYS=/opt/synopsys +LD_LIBRARY_PATH=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/shared/pkgs/icv/tools/calibre_client/lib/64 +SPECMAN_HOME=/opt/cadence/INCISIVE152/components/sn +VRST_HOME=/opt/cadence/INCISIVE152 +CDS_SPECTRE_FBENABLE=1 +LOGNAME=shbyang +TERM=xterm-256color +INNOVUS_HOME=/opt/cadence/INNOVUS181 +CDS_LIC_FILE=/opt/cadence/license/license.dat +HSPICE_HOME=/opt/synopsys/hspice/N-2017.12-SP2 +GNOME_DESKTOP_SESSION_ID=this-is-deprecated +HOSTNAME=cryo1 +GENUS_HOME=/opt/cadence/GENUS152 +MGC_CALIBRE_REALTIME_VIRTUOSO_SAVE_MESSENGER_CELL=1 +COLORTERM=truecolor +PWR_HOME=/opt/synopsys/pwr/O-2018.06-SP3 +QT_IM_MODULE=ibus +OSTYPE=linux +SHLVL=6 +GNOME_SHELL_SESSION_MODE=classic +XDG_SESSION_ID=c34 +USER=shbyang +QTLIB=/usr/lib64/qt-3.3/lib +XDG_CURRENT_DESKTOP=GNOME +VNCDESKTOP=cryo1:17 (shbyang) +INCISIVE_HOME=/opt/cadence/INCISIVE152 +CDS=/opt/cadence/IC618 +WV_HOME=/opt/synopsys/wv/N-2017.12-SP2 +CDS_LOAD_ENV=CWD +VC_STATIC_HOME=/opt/synopsys/vc_stat/vc_static/V-2023.12 +IMSETTINGS_MODULE=none +starRC_HOME=/opt/synopsys/starrc/O-2018.06-SP1 +MAKEFLAGS= +MFLAGS= +SYN_HOME=/opt/synopsys/syn/O-2018.06-SP1 +MAIL=/var/spool/mail/shbyang +CADHOME=/opt/cadence +MGC_LIB_PATH=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/lib +CDSHOME=/opt/cadence/IC618 +LC_HOME=/opt/synopsys/lc/O-2018.06-SP1 +CADENCE_DIR=/opt/cadence/IC618 +CDS_INST_DIR=/opt/cadence/IC618 +NOVAS_HOME=/opt/synopsys/verdi/Verdi_O-2018.09-SP2 +XILINX_HOME=/opt/xilinx +DBUS_STARTER_BUS_TYPE=session +W3264_NO_HOST_CHECK=1 +SCL_HOME=/opt/synopsys/scl/2018.06 +HOSTTYPE=x86_64-linux +GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/300489a5_6011_46a1_a329_83b2a6d46428 +CDS_SPECTRERF_FBENABLE=1 +GNOME_TERMINAL_SERVICE=:1.1458 +HISTSIZE=1000 +GROUP=cryo +TXS_HOME=/opt/synopsys/txs/O-2018.06-SP1 +CDS_Netlisting_Mode=Analog +IDQ_HOME=/opt/synopsys/idq/O-2018.06-SP1 +QTINC=/usr/lib64/qt-3.3/include +QTDIR=/usr/lib64/qt-3.3 +VIVADO_HOME=/opt/xilinx/Vivado/2019.2/ +CDS_ENABLE_VMS=1 +LANG=C +MGC_CALIBRE_SAVE_ALL_RUNSET_VALUES=1 +CALIBRE_ENABLE_SKILL_PEXBA_MODE=1 +DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-pbYbSoHCDo,guid=6bec37f851a0ec63831138606819dc51 +HOST=cryo1 +MAKELEVEL=1 +VCS_HEAP_EXEC=true +VCS_PATHMAP_PRELOAD_DONE=1 +VCS_STACK_EXEC=true +VCS_EXEC_DONE=1 +LC_ALL=C +DVE=/opt/synopsys/vcs-mx/O-2018.09-SP2/gui/dve +SPECMAN_OUTPUT_TO_TTY=1 +Runtime command line arguments: +argv[0]=./simv +argv[1]=-l +argv[2]=sim.log +argv[3]=-cm +argv[4]=line+cond+fsm+tgl+branch +argv[5]=-cm_dir +argv[6]=../../coverage/try/ +argv[7]=-cm_name +argv[8]=flattop +argv[9]=+ENABLE_FSDB=1 +316 profile - 100 + CPU/Mem usage: 0.080 sys, 0.350 user, 316.72M mem +317 Fri Mar 13 16:24:00 2026 +318 pliAppInit +319 FSDB_GATE is set. +320 FSDB_RTL is set. +321 Enable Parallel Dumping. +322 pliAppMiscSet: New Sim Round +323 pliEntryInit +324 LIBSSCORE=found /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUXAMD64/libsscore_vcs201809.so through $NOVAS_HOME setting. +325 FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019 +326 (C) 1996 - 2019 by Synopsys, Inc. +327 FSDB_VCS_ENABLE_FAST_VC is enable +328 sps_call_fsdbAutoSwitchDumpfile_main_vd at 0 : ../../sim/chip_top/TB.sv(57) +329 sps_call_fsdbAutoSwitchDumpfile at 0 : ../../sim/chip_top/TB.sv(57) +330 argv[0]: (500) +331 argv[1]: (./verdplus.fsdb) +332 argv[2]: (1000000) +333 *Verdi* FSDB: The switch FSDB file size might not match the input size (500MB) because of performance concerns. +334 *Verdi* FSDB: To have the FSDB file size match the input size (500MB), set the FSDB_ENV_PRECISE_AUTOSWITCH environment, though the dumping performance might decrease. +335 *Verdi* : Enable automatic switching of the FSDB file. +336 *Verdi* : (Filename='./verdplus', Limit Size=500MB, File Amount=1000000). +337 *Verdi* : Create FSDB file './verdplus_000.fsdb' +338 compile option from '/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcs_rebuild'. +339 "vcs '-full64' '-j8' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+all' '-debug_region+cell+encrypt' '-P' '/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab' '/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a' '+define+DUMP_FSDB' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-cm' 'line+cond+fsm+tgl+branch' '-cm_dir' './coverage/simv.vdb' '-f' 'filelist_vlg.f' '+incdir+./../../rtl/define' '+incdir+./../../rtl/qubitmcu' '+incdir+./../../model' 2>&1" +340 *Verdi* : Create the file './verdplus.log' to log the time range of each FSDB file. +341 *Verdi* : Create virtual FSDB file './verdplus.vf' to log each FSDB file. +342 sps_call_fsdbDumpvars_vd_main at 0 : ../../sim/chip_top/TB.sv(58) +343 [spi_vcs_vd_ppi_create_root]: no upf option +344 FSDB dumper cannot dump UPF related power signal ($power_tree): no ppiPowerNetwork. +345 *Verdi* : Begin traversing the scopes, layer (0). +346 *Verdi* : End of traversing. +347 pliAppHDL_DumpVarComplete traverse var: profile - + CPU/Mem usage: 0.090 sys, 0.420 user, 413.95M mem + incr: 0.010 sys, 0.070 user, 9.70M mem + accu: 0.010 sys, 0.070 user, 9.70M mem + accu incr: 0.010 sys, 0.070 user, 9.70M mem + + Count usage: 12707 var, 14739 idcode, 7320 callback + incr: 12707 var, 14739 idcode, 7320 callback + accu: 12707 var, 14739 idcode, 7320 callback + accu incr: 12707 var, 14739 idcode, 7320 callback +348 Fri Mar 13 16:24:00 2026 +349 pliAppHDL_DumpVarComplete: profile - + CPU/Mem usage: 0.090 sys, 0.420 user, 414.99M mem + incr: 0.000 sys, 0.000 user, 1.05M mem + accu: 0.010 sys, 0.070 user, 10.75M mem + accu incr: 0.000 sys, 0.000 user, 1.05M mem + + Count usage: 12707 var, 14739 idcode, 7320 callback + incr: 0 var, 0 idcode, 0 callback + accu: 12707 var, 14739 idcode, 7320 callback + accu incr: 0 var, 0 idcode, 0 callback +350 Fri Mar 13 16:24:00 2026 +351 sps_call_fsdbDumpMDA_vd_main at 0 : ../../sim/chip_top/TB.sv(59) +352 *Verdi* : Begin traversing the MDAs, layer (0). +353 *Verdi* : Enable +mda and +packedmda dumping. +354 *Verdi* : End of traversing the MDAs. +355 pliAppHDL_DumpVarComplete traverse var: profile - + CPU/Mem usage: 0.100 sys, 0.440 user, 418.82M mem + incr: 0.010 sys, 0.020 user, 3.83M mem + accu: 0.010 sys, 0.020 user, 3.83M mem + accu incr: 0.010 sys, 0.020 user, 3.83M mem + + Count usage: 80429 var, 81757 idcode, 7372 callback + incr: 67722 var, 67018 idcode, 52 callback + accu: 67722 var, 67018 idcode, 52 callback + accu incr: 67722 var, 67018 idcode, 52 callback +356 Fri Mar 13 16:24:00 2026 +357 pliAppHDL_DumpVarComplete: profile - + CPU/Mem usage: 0.100 sys, 0.440 user, 426.29M mem + incr: 0.000 sys, 0.000 user, 7.47M mem + accu: 0.010 sys, 0.020 user, 11.30M mem + accu incr: 0.000 sys, 0.000 user, 7.47M mem + + Count usage: 80429 var, 81757 idcode, 7372 callback + incr: 0 var, 0 idcode, 0 callback + accu: 67722 var, 67018 idcode, 52 callback + accu incr: 0 var, 0 idcode, 0 callback +358 Fri Mar 13 16:24:00 2026 +359 End of simulation at 198910080 +360 Fri Mar 13 16:24:05 2026 +361 Begin FSDB profile info: +362 FSDB Writer : bc1(19254673) bcn(1920554) mtf/stf(0/0) +FSDB Writer elapsed time : flush(0.212152) io wait(0.000000) theadpool wait(0.000000) target functin(0.000000) +FSDB Writer cpu time : MT Compression : 0 +363 End FSDB profile info +364 Parallel profile - Flush:4 Expand:0 ProduceWait:0 ConsumerWait:244 BlockUsed:244 +365 ProduceTime:5.741575592 ConsumerTime:2.877569778 Buffer:64MB +366 SimExit +367 Sim process exit diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/sim.log b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/sim.log new file mode 100644 index 0000000..d03ae49 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/sim.log @@ -0,0 +1,260 @@ +Command: /home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/flattop/./simv -l sim.log -cm line+cond+fsm+tgl+branch -cm_dir ../../coverage/try/ -cm_name flattop +ENABLE_FSDB=1 +Chronologic VCS simulator copyright 1991-2018 +Contains Synopsys proprietary information. +Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64; Mar 13 16:24 2026 +Information: *** Instance TB.U_da4008_chip_top.digital_top.u_dw_stream_sync is the DW_stream_sync Clock Domain Crossing Module *** +../../../../case/config/try//flattop.txt +../../data_RTL/try/flattop.txt +*Verdi* Loading libsscore_vcs201809.so +FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019 +(C) 1996 - 2019 by Synopsys, Inc. +*Verdi* FSDB: The switch FSDB file size might not match the input size (500MB) because of performance concerns. +*Verdi* FSDB: To have the FSDB file size match the input size (500MB), set the FSDB_ENV_PRECISE_AUTOSWITCH environment, though the dumping performance might decrease. +*Verdi* : Enable automatic switching of the FSDB file. +*Verdi* : (Filename='./verdplus', Limit Size=500MB, File Amount=1000000). +*Verdi* : Create FSDB file './verdplus_000.fsdb' +*Verdi* : Create the file './verdplus.log' to log the time range of each FSDB file. +*Verdi* : Create virtual FSDB file './verdplus.vf' to log each FSDB file. +*Verdi* : Begin traversing the scopes, layer (0). +*Verdi* : End of traversing. +*Verdi* : Begin traversing the MDAs, layer (0). +*Verdi* : Enable +mda and +packedmda dumping. +*Verdi* : End of traversing the MDAs. +Frame check passed: Frame check passed +----------ONE-PKT-DRIVING---------- +cmd: 0 +addr: 0100000 +cfgid: 00 +data[ 0]='h04000002 +data[ 1]='h800003e8 +data[ 2]='h04004002 +----------------------------------- +----------ONE-PKT-DRIVING---------- +cmd: 0 +addr: 0200000 +cfgid: 00 +data[ 0]='h04030100 +data[ 1]='h0b090706 +data[ 2]='h110f0e0c +data[ 3]='h17161412 +data[ 4]='h1d1c1a19 +data[ 5]='h2422211f +data[ 6]='h2a282725 +data[ 7]='h302f2d2c +data[ 8]='h37353332 +data[ 9]='h3d3b3a38 +data[10]='h4342403e +data[11]='h4a484645 +data[12]='h504e4d4b +data[13]='h56555351 +data[14]='h5c5b5958 +data[15]='h6361605e +data[16]='h69676664 +data[17]='h6f6e6c6b +data[18]='h76747271 +data[19]='h7c7a7977 +data[20]='h82817f7d +data[21]='h89878584 +data[22]='h8f8d8c8a +data[23]='h95949290 +data[24]='h9b9a9897 +data[25]='ha2a09f9d +data[26]='ha8a6a5a3 +data[27]='haeadabaa +data[28]='hb5b3b1b0 +data[29]='hbbb9b8b6 +data[30]='hc1c0bebc +data[31]='hc8c6c4c3 +data[32]='hc3c4c6c8 +data[33]='hbcbec0c1 +data[34]='hb6b8b9bb +data[35]='hb0b1b3b5 +data[36]='haaabadae +data[37]='ha3a5a6a8 +data[38]='h9d9fa0a2 +data[39]='h97989a9b +data[40]='h90929495 +data[41]='h8a8c8d8f +data[42]='h84858789 +data[43]='h7d7f8182 +data[44]='h77797a7c +data[45]='h71727476 +data[46]='h6b6c6e6f +data[47]='h64666769 +data[48]='h5e606163 +data[49]='h58595b5c +data[50]='h51535556 +data[51]='h4b4d4e50 +data[52]='h4546484a +data[53]='h3e404243 +data[54]='h383a3b3d +data[55]='h32333537 +data[56]='h2c2d2f30 +data[57]='h2527282a +data[58]='h1f212224 +data[59]='h191a1c1d +data[60]='h12141617 +data[61]='h0c0e0f11 +data[62]='h0607090b +data[63]='h00010304 +----------------------------------- +----------ONE-PKT-DRIVING---------- +cmd: 0 +addr: 0100000 +cfgid: 00 +data[ 0]='h04000002 +data[ 1]='h800003e8 +data[ 2]='h04004002 +----------------------------------- +----------ONE-PKT-DRIVING---------- +cmd: 0 +addr: 0200000 +cfgid: 00 +data[ 0]='h04030100 +data[ 1]='h0b090706 +data[ 2]='h110f0e0c +data[ 3]='h17161412 +data[ 4]='h1d1c1a19 +data[ 5]='h2422211f +data[ 6]='h2a282725 +data[ 7]='h302f2d2c +data[ 8]='h37353332 +data[ 9]='h3d3b3a38 +data[10]='h4342403e +data[11]='h4a484645 +data[12]='h504e4d4b +data[13]='h56555351 +data[14]='h5c5b5958 +data[15]='h6361605e +data[16]='h69676664 +data[17]='h6f6e6c6b +data[18]='h76747271 +data[19]='h7c7a7977 +data[20]='h82817f7d +data[21]='h89878584 +data[22]='h8f8d8c8a +data[23]='h95949290 +data[24]='h9b9a9897 +data[25]='ha2a09f9d +data[26]='ha8a6a5a3 +data[27]='haeadabaa +data[28]='hb5b3b1b0 +data[29]='hbbb9b8b6 +data[30]='hc1c0bebc +data[31]='hc8c6c4c3 +data[32]='hc3c4c6c8 +data[33]='hbcbec0c1 +data[34]='hb6b8b9bb +data[35]='hb0b1b3b5 +data[36]='haaabadae +data[37]='ha3a5a6a8 +data[38]='h9d9fa0a2 +data[39]='h97989a9b +data[40]='h90929495 +data[41]='h8a8c8d8f +data[42]='h84858789 +data[43]='h7d7f8182 +data[44]='h77797a7c +data[45]='h71727476 +data[46]='h6b6c6e6f +data[47]='h64666769 +data[48]='h5e606163 +data[49]='h58595b5c +data[50]='h51535556 +data[51]='h4b4d4e50 +data[52]='h4546484a +data[53]='h3e404243 +data[54]='h383a3b3d +data[55]='h32333537 +data[56]='h2c2d2f30 +data[57]='h2527282a +data[58]='h1f212224 +data[59]='h191a1c1d +data[60]='h12141617 +data[61]='h0c0e0f11 +data[62]='h0607090b +data[63]='h00010304 +----------------------------------- +----------ONE-PKT-DRIVING---------- +cmd: 0 +addr: 0100000 +cfgid: 00 +data[ 0]='h04000002 +data[ 1]='h800003e8 +data[ 2]='h04004002 +----------------------------------- +----------ONE-PKT-DRIVING---------- +cmd: 0 +addr: 0200000 +cfgid: 00 +data[ 0]='h04030100 +data[ 1]='h0b090706 +data[ 2]='h110f0e0c +data[ 3]='h17161412 +data[ 4]='h1d1c1a19 +data[ 5]='h2422211f +data[ 6]='h2a282725 +data[ 7]='h302f2d2c +data[ 8]='h37353332 +data[ 9]='h3d3b3a38 +data[10]='h4342403e +data[11]='h4a484645 +data[12]='h504e4d4b +data[13]='h56555351 +data[14]='h5c5b5958 +data[15]='h6361605e +data[16]='h69676664 +data[17]='h6f6e6c6b +data[18]='h76747271 +data[19]='h7c7a7977 +data[20]='h82817f7d +data[21]='h89878584 +data[22]='h8f8d8c8a +data[23]='h95949290 +data[24]='h9b9a9897 +data[25]='ha2a09f9d +data[26]='ha8a6a5a3 +data[27]='haeadabaa +data[28]='hb5b3b1b0 +data[29]='hbbb9b8b6 +data[30]='hc1c0bebc +data[31]='hc8c6c4c3 +data[32]='hc3c4c6c8 +data[33]='hbcbec0c1 +data[34]='hb6b8b9bb +data[35]='hb0b1b3b5 +data[36]='haaabadae +data[37]='ha3a5a6a8 +data[38]='h9d9fa0a2 +data[39]='h97989a9b +data[40]='h90929495 +data[41]='h8a8c8d8f +data[42]='h84858789 +data[43]='h7d7f8182 +data[44]='h77797a7c +data[45]='h71727476 +data[46]='h6b6c6e6f +data[47]='h64666769 +data[48]='h5e606163 +data[49]='h58595b5c +data[50]='h51535556 +data[51]='h4b4d4e50 +data[52]='h4546484a +data[53]='h3e404243 +data[54]='h383a3b3d +data[55]='h32333537 +data[56]='h2c2d2f30 +data[57]='h2527282a +data[58]='h1f212224 +data[59]='h191a1c1d +data[60]='h12141617 +data[61]='h0c0e0f11 +data[62]='h0607090b +data[63]='h00010304 +----------------------------------- + +--------------------------------------------------------------------------- +VCS Coverage Metrics: during simulation line, cond, FSM, branch, tgl was monitored +--------------------------------------------------------------------------- + V C S S i m u l a t i o n R e p o r t +Time: 198910080 ps diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv new file mode 100755 index 0000000..0036aa9 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/.daidir_complete b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/.daidir_complete new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/.normal_done b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/.normal_done new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/.vcs.timestamp b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/.vcs.timestamp new file mode 100644 index 0000000..0d4e6bb --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/.vcs.timestamp @@ -0,0 +1,230 @@ +4 +0 ../define/chip_define.v +0 /opt/synopsys/vcs-mx/O-2018.09-SP2/etc/systemverilog/../define/chip_define.v +0 ../define/chip_undefine.v +0 /opt/synopsys/vcs-mx/O-2018.09-SP2/etc/systemverilog/../define/chip_undefine.v +48 ++define+DUMP_FSDB ++incdir+./../../model ++incdir+./../../rtl/define ++incdir+./../../rtl/qubitmcu ++itf+/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab ++lint=TFIPC-L ++nospecify ++v2k ++vcsd1 ++vpi +-Mamsrun= +-Masflags= +-Mcc=gcc +-Mcfl= -pipe -fPIC -O -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include +-Mcplusplus=g++ +-Mcrt0= +-Mcrtn= +-Mcsrc= +-Mexternalobj= +-Mldflags= -rdynamic +-Mobjects= /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvirsim.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/liberrorinf.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a +-Mout=simv +-Msaverestoreobj=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o +-Msyslibs=/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lm +-Mvcsaceobjs= +-Mxcflags= -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include +-P +-P +-cm +-cm_dir +-debug_access+all +-debug_region+cell+encrypt +-f filelist_vlg.f +-fsdb +-full64 +-gen_obj +-l +-lca +-picarchive +-q +-sverilog +-timescale=1ns/1ps +./coverage/simv.vdb +/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/vcs1 +/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +compile.log +line+cond+fsm+tgl+branch +110 +sysc_uni_pwd=/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top +starRC_HOME=/opt/synopsys/starrc/O-2018.06-SP1 +XMODIFIERS=@im=ibus +XILINX_VIVADO=/opt/xilinx/Vivado/2019.2 +XILINX_HOME=/opt/xilinx +XDG_SESSION_ID=c34 +XDG_RUNTIME_DIR=/run/user/1019 +XDG_MENU_PREFIX=gnome- +XDG_DATA_DIRS=/home/shbyang/.local/share/flatpak/exports/share:/var/lib/flatpak/exports/share:/usr/local/share:/usr/share +XDG_CURRENT_DESKTOP=GNOME +WV_HOME=/opt/synopsys/wv/N-2017.12-SP2 +WAVE=1 +W3264_NO_HOST_CHECK=1 +VTE_VERSION=5204 +VRST_HOME=/opt/cadence/INCISIVE152 +VNCDESKTOP=cryo1:17 (shbyang) +VMR_MODE_FLAG=64 +VIVADO_HOME=/opt/xilinx/Vivado/2019.2/ +VERDI_HOME=/opt/synopsys/verdi/Verdi_O-2018.09-SP2 +VENDOR=unknown +VC_STATIC_HOME=/opt/synopsys/vc_stat/vc_static/V-2023.12 +VCS_MX_HOME_INTERNAL=1 +VCS_MODE_FLAG=64 +VCS_LOG_FILE=compile.log +VCS_LCAMSG_PRINT_OFF=1 +VCS_HOME=/opt/synopsys/vcs-mx/O-2018.09-SP2 +VCS_DEPTH=0 +VCS_ARG_ADDED_FOR_TMP=1 +VCS_ARCH=linux64 +UNAME=/bin/uname +TXS_HOME=/opt/synopsys/txs/O-2018.06-SP1 +TOOL_HOME=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64 +SYN_HOME=/opt/synopsys/syn/O-2018.06-SP1 +SYNOPSYS=/opt/synopsys +SSH_AUTH_SOCK=/run/user/1019/keyring/ssh +SSH_AGENT_PID=24257 +SPECTRE_HOME=/opt/cadence/SPECTRE181 +SPECTRE_DEFAULTS=-E +SPECMAN_HOME=/opt/cadence/INCISIVE152/components/sn +SPECMAN_DIR=/opt/cadence/INCISIVE152/components/sn +SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/24088,unix/unix:/tmp/.ICE-unix/24088 +SCRNAME=vcs +SCRIPT_NAME=vcs +SCL_HOME=/opt/synopsys/scl/2018.06 +QT_IM_MODULE=ibus +QT_GRAPHICSSYSTEM_CHECKED=1 +QTLIB=/usr/lib64/qt-3.3/lib +QTINC=/usr/lib64/qt-3.3/include +QTDIR=/usr/lib64/qt-3.3 +PWR_HOME=/opt/synopsys/pwr/O-2018.06-SP3 +PT_HOME=/opt/synopsys/pts/O-2018.06-SP1 +OVA_UUM=0 +OSTYPE=linux +OA_UNSUPPORTED_PLAT=linux_rhel50_gcc44x +NOVAS_HOME=/opt/synopsys/verdi/Verdi_O-2018.09-SP2 +MOZILLA_HOME=/usr/bin/firefox +MGLS_LICENSE_FILE=/opt/mentor/license/license.dat +MGC_PDF_REDER=evince +MGC_LIB_PATH=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/lib +MGC_HOME=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11 +MGC_CALIBRE_SAVE_ALL_RUNSET_VALUES=1 +MGC_CALIBRE_REALTIME_VIRTUOSO_SAVE_MESSENGER_CELL=1 +MGC_CALIBRE_REALTIME_VIRTUOSO_ENABLED=1 +MFLAGS=-s +MENTOR_HOME=/opt/mentor +MAKEOVERRIDES=${-*-command-variables-*-} +MAKELEVEL=2 +MAKEFLAGS=s -- WAVE=1 +LESSOPEN=||/usr/bin/lesspipe.sh %s +LC_HOME=/opt/synopsys/lc/O-2018.06-SP1 +LC_ALL=C +INNOVUS_HOME=/opt/cadence/INNOVUS181 +INCISIVE_HOME=/opt/cadence/INCISIVE152 +IMSETTINGS_MODULE=none +IMSETTINGS_INTEGRATE_DESKTOP=yes +IDQ_HOME=/opt/synopsys/idq/O-2018.06-SP1 +HSPICE_HOME=/opt/synopsys/hspice/N-2017.12-SP2 +HOSTTYPE=x86_64-linux +HISTCONTROL=ignoredups +GROUP=cryo +GNOME_TERMINAL_SERVICE=:1.1458 +GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/300489a5_6011_46a1_a329_83b2a6d46428 +GNOME_SHELL_SESSION_MODE=classic +GNOME_DESKTOP_SESSION_ID=this-is-deprecated +GENUS_HOME=/opt/cadence/GENUS152 +FPGA_HOME=/opt/synopsys/fpga/K-2015.09 +FM_HOME=/opt/synopsys/fm/L-2016.03-SP1 +DBUS_STARTER_BUS_TYPE=session +DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-pbYbSoHCDo,guid=6bec37f851a0ec63831138606819dc51 +DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-pbYbSoHCDo,guid=6bec37f851a0ec63831138606819dc51 +COLORTERM=truecolor +CDS_SPECTRE_FBENABLE=1 +CDS_SPECTRERF_FBENABLE=1 +CDS_ROOT=/opt/cadence/IC618 +CDS_Netlisting_Mode=Analog +CDS_LOAD_ENV=CWD +CDS_LIC_ONLY=1 +CDS_LIC_FILE=/opt/cadence/license/license.dat +CDS_INST_DIR=/opt/cadence/IC618 +CDS_ENABLE_VMS=1 +CDS_AUTO_64BIT=ALL +CDSROOT=/opt/cadence/IC618 +CDSHOME=/opt/cadence/IC618 +CDSDIR=/opt/cadence/IC618 +CDS=/opt/cadence/IC618 +CALIBRE_HOME=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11 +CALIBRE_ENABLE_SKILL_PEXBA_MODE=1 +CADHOME=/opt/cadence +CADENCE_DIR=/opt/cadence/IC618 +AMS_ENABLE_NOISE=YES +0 +55 +1773384753 ../../model/LVDS_DRIVER.sv +1773384753 ../../model/SPI_DRIVER.sv +1773384753 ./../../rtl/define/../define/chip_undefine.v +1773384753 ./../../rtl/define/../define/chip_define.v +1773384753 ../../rtl/define/chip_undefine.v +1773384753 ../../sim/chip_top/TB.sv +1773384753 ../../model/DW_pulse_sync.v +1773384753 ../../model/DW_sync.v +1773384753 ../../model/DW_reset_sync.v +1773384753 ../../model/DW_stream_sync.v +1773384753 ../../model/reset_tb.v +1773384753 ../../model/DEM_Reverse.v +1773384753 ../../model/DEM_Reverse_64CH.v +1773384753 ../../model/clk_gen.v +1773384753 ../../model/spi_if.sv +1773384753 ../../model/clock_tb.v +1773384753 ../../rtl/spi/spi_sys.v +1773384753 ../../rtl/spi/spi_pll.v +1773384753 ../../rtl/spi/spi_slave.v +1773384753 ../../rtl/spi/spi_bus_decoder.sv +1773384753 ../../rtl/top/digital_top.sv +1773384753 ../../rtl/top/da4008_chip_top.sv +1773384753 ../../rtl/dem/DA4008_DEM_Parallel_PRBS_64CH.v +1773384753 ../../rtl/dem/DA4008_DEM_Parallel_PRBS_1CH.v +1773384753 ../../rtl/dem/DEM_PhaseSync_4008.sv +1773384753 ../../rtl/awg/awg_ctrl.v +1773384753 ../../rtl/awg/awg_top.sv +1773384753 ../../rtl/clk/clk_regfile.v +1773384753 ../../rtl/memory/spram.v +1773384753 ../../rtl/memory/bhv_spram.v +1773384753 ../../rtl/memory/dpram.v +1773384753 ../../rtl/memory/sram_dmux.sv +1773384753 ../../rtl/memory/sram_if.sv +1773384753 ../../rtl/memory/tsmc_dpram.v +1773384753 ../../rtl/comm/ramp_gen.v +1773384753 ../../rtl/comm/syncer.v +1773384753 ../../rtl/comm/sirv_gnrl_dffs.v +1773384753 ../../rtl/comm/pulse_generator.sv +1773384753 ../../rtl/comm/sirv_gnrl_xchecker.v +1773384753 ../../rtl/rstgen/rst_sync.v +1773384753 ../../rtl/rstgen/rst_gen_unit.v +1773384753 ../../rtl/lvds/ulink_rx.sv +1773384753 ../../rtl/dac_regfile/dac_regfile.v +1773384753 ../../rtl/fifo/syn_fwft_fifo.v +1773384753 ../../rtl/dacif/dacif.v +1773384753 ../../rtl/systemregfile/systemregfile.v +1773384753 ../../rtl/io/iopad.v +1773384753 ../../lib/tsdn28hpcpuhdb4096x128m4mw_170a_ffg0p99v0c.v +1773384753 ../../lib/tphn28hpcpgv18.v +1773384753 ../../rtl/define/chip_define.v +1551421444 /opt/synopsys/vcs-mx/O-2018.09-SP2/include/cm_vcsd.tab +1773384753 filelist_vlg.f +1550753332 /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +1550753332 /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +1551421246 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab +5 +1551422344 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvirsim.so +1551421792 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/liberrorinf.so +1551421768 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so +1551421789 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so +1550752033 /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a +1773384887 simv.daidir +-1 partitionlib diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/_32553_archive_1.so b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/_32553_archive_1.so new file mode 100755 index 0000000..fd59063 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is automatically generated by VCS. Any changes you make +# to it will be overwritten the next time VCS is run. +vcs '-full64' '-j8' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+all' '-debug_region+cell+encrypt' '-P' '/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab' '/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a' '+define+DUMP_FSDB' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-cm' 'line+cond+fsm+tgl+branch' '-cm_dir' './coverage/simv.vdb' '-f' 'filelist_vlg.f' '+incdir+./../../rtl/define' '+incdir+./../../rtl/qubitmcu' '+incdir+./../../model' -static_dbgen_only -daidir=$1 2>&1 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/cc/cc_bcode.db b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/cc/cc_bcode.db new file mode 100644 index 0000000..757c06d --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/cc/cc_bcode.db @@ -0,0 +1,561 @@ +sid sirv_gnrl_xchecker +bcid 0 0 WIDTH,32 CALL_ARG_VAL,2,0 WIDTH,1 XOR_REDUCE OPT_CONST_4ST,1,1 NEQU RET +sid clk_gen +bcid 1 0 WIDTH,4 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU RET +sid spi_sys_0000 +bcid 2 0 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 3 1 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 4 2 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 M_EQU AND CALL_ARG_VAL,4,0 OR RET +bcid 5 3 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 6 4 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,26 WIDTH,1 M_EQU AND RET +bcid 7 5 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,30 WIDTH,1 M_EQU AND AND RET +bcid 8 6 WIDTH,5 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_EQU RET +bcid 9 7 WIDTH,5 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_NEQU RET +bcid 10 8 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 AND AND RET +bcid 11 9 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 AND AND RET +bcid 12 10 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 NOT CALL_ARG_VAL,5,0 AND AND AND RET +bcid 13 11 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 AND AND AND RET +bcid 14 12 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND RET +bcid 15 13 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND RET +bcid 16 14 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND WIDTH,2 OPT_CONST,1 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,4,0 AND WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,5,0 AND WIDTH,2 OPT_CONST,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,6,0 AND WIDTH,2 OPT_CONST,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,7,0 AND WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,8,0 AND WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 17 15 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND OR CALL_ARG_VAL,4,0 WIDTH,5 CALL_ARG_VAL,5,0 OPT_CONST,27 WIDTH,1 M_EQU AND AND RET +bcid 18 16 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,25 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,25 CALL_ARG_VAL,4,0 WIDTH,1 CALL_ARG_VAL,5,0 WIDTH,25 CALL_ARG_VAL,6,0 OPT_CONST,4 ADD CALL_ARG_VAL,6,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 19 17 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,31 WIDTH,1 M_EQU AND AND RET +bcid 20 18 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND CALL_ARG_VAL,4,0 WIDTH,5 CALL_ARG_VAL,5,0 OPT_CONST,28 WIDTH,1 M_EQU AND AND RET +bcid 21 19 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,30 WIDTH,1 M_EQU AND AND RET +bcid 22 20 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,31 WIDTH,1 M_EQU AND AND RET +bcid 23 21 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 WIDTH,2 CALL_ARG_VAL,4,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,5,0 AND WIDTH,32 CALL_ARG_VAL,6,0 OPT_CONST,0 WIDTH,31 SLICE,1 WIDTH,1 OPT_CONST,0 WIDTH,32 CONCATENATE,2 CALL_ARG_VAL,6,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 24 22 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_NEQU RET +sid spi_slave +bcid 25 0 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 26 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 M_EQU AND RET +bcid 27 2 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 28 3 WIDTH,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,26 WIDTH,1 M_EQU AND AND RET +bcid 29 4 WIDTH,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,30 WIDTH,1 M_EQU AND AND RET +bcid 30 5 WIDTH,5 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 M_EQU WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 NOT WIDTH,5 CALL_ARG_VAL,4,0 WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,5 SLICE,1 WIDTH,1 M_EQU AND AND RET +bcid 31 6 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,30 WIDTH,1 M_EQU CALL_ARG_VAL,4,0 AND AND RET +bcid 32 7 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND CALL_ARG_VAL,4,0 OR CALL_ARG_VAL,5,0 WIDTH,5 CALL_ARG_VAL,6,0 OPT_CONST,29 WIDTH,1 M_EQU AND AND RET +bcid 33 8 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,8 CALL_ARG_VAL,4,0 OPT_CONST,4 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 CALL_ARG_VAL,5,0 MITECONDNOINSTR,4 RET +bcid 34 9 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 RET +bcid 35 10 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,30 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 36 11 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,29 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 37 12 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,28 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,2 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 38 13 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,27 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,3 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 39 14 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,26 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,4 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 40 15 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,25 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,5 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 41 16 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,24 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,6 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 42 17 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,23 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,7 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 43 18 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,22 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,8 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 44 19 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,21 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,9 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 45 20 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,20 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,10 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 46 21 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,19 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,11 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 47 22 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,13 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,18 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,12 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 48 23 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,17 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,13 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 49 24 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,14 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 50 25 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,15 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 51 26 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,17 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,16 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 52 27 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,18 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,13 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,17 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 53 28 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,19 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,12 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,18 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 54 29 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,19 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 55 30 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,21 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,20 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 56 31 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,22 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,9 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,21 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 57 32 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,23 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,8 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,22 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 58 33 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,24 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,7 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,23 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 59 34 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,6 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,24 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 60 35 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,26 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,25 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 61 36 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,27 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,26 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 62 37 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,28 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,27 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 63 38 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,29 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,28 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 64 39 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,30 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,29 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 65 40 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,30 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +sid spi_bus_decoder_0000 +bcid 66 0 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,20 MULTI_CONCATENATE,1,20 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 AND RET +bcid 67 1 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,20 MULTI_CONCATENATE,1,20 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 AND RET +bcid 68 2 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,20 MULTI_CONCATENATE,1,20 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 AND RET +bcid 69 3 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,20 MULTI_CONCATENATE,1,20 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 AND RET +bcid 70 4 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 71 5 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 72 6 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 73 7 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 74 8 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,4 MULTI_CONCATENATE,1,4 AND RET +sid systemregfile +bcid 75 0 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,8 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,19,0 OPT_CONST,1 EQU WIDTH,8 OPT_CONST,32 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,8 OPT_CONST,88 WIDTH,1 CALL_ARG_VAL,21,0 OPT_CONST,1 EQU WIDTH,8 OPT_CONST,218 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 76 1 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,4 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,21,0 OPT_CONST,1 EQU WIDTH,4 OPT_CONST,2 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,4 OPT_CONST,4 WIDTH,1 CALL_ARG_VAL,23,0 OPT_CONST,1 EQU WIDTH,4 OPT_CONST,4 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 77 2 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU OPT_CONST,0 CALL_ARG_VAL,23,0 OPT_CONST,1 EQU OPT_CONST,0 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU OPT_CONST,0 CALL_ARG_VAL,25,0 OPT_CONST,1 EQU OPT_CONST,0 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 78 3 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,19 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,11 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,25,0 OPT_CONST,1 EQU WIDTH,11 OPT_CONST,1541 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,11 OPT_CONST,1109 WIDTH,1 CALL_ARG_VAL,27,0 OPT_CONST,1 EQU WIDTH,11 OPT_CONST,8 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 79 4 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,19 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,27,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,29,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 80 5 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,19 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,31,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,2 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,33,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,0 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 81 6 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,19 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,35,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,37,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 82 7 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU CALL_ARG_VAL,11,0 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU CALL_ARG_VAL,13,0 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU CALL_ARG_VAL,27,0 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU CALL_ARG_VAL,29,0 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU CALL_ARG_VAL,31,0 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,19 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 EQU OPT_CONST,1 CALL_ARG_VAL,45,0 OPT_CONST,1 EQU OPT_CONST,0 CALL_ARG_VAL,46,0 OPT_CONST,1 EQU OPT_CONST,0 CALL_ARG_VAL,47,0 OPT_CONST,1 EQU OPT_CONST,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 83 8 WIDTH,6 CALL_ARG_VAL,2,0 WIDTH,32 PAD RET +bcid 84 9 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 85 10 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 86 11 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 87 12 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 88 13 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 M_EQU RET +bcid 89 14 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 M_EQU RET +bcid 90 15 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 M_EQU RET +bcid 91 16 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 M_EQU RET +bcid 92 17 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU RET +bcid 93 18 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 M_EQU RET +bcid 94 19 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,10 WIDTH,1 M_EQU RET +bcid 95 20 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,11 WIDTH,1 M_EQU RET +bcid 96 21 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,1 M_EQU RET +bcid 97 22 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,13 WIDTH,1 M_EQU RET +bcid 98 23 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,14 WIDTH,1 M_EQU RET +bcid 99 24 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,1 M_EQU RET +bcid 100 25 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,19 WIDTH,1 M_EQU RET +bcid 101 26 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 M_EQU RET +bcid 102 27 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,21 WIDTH,1 M_EQU RET +bcid 103 28 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 M_EQU RET +bcid 104 29 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,17 WIDTH,1 M_EQU RET +bcid 105 30 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,18 WIDTH,1 M_EQU RET +bcid 106 31 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,22 WIDTH,1 M_EQU RET +bcid 107 32 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,23 WIDTH,1 M_EQU RET +bcid 108 33 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,24 WIDTH,1 M_EQU RET +bcid 109 34 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,1 M_EQU RET +bcid 110 35 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU AND RET +bcid 111 36 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 112 37 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_NEQU RET +sid DW_sync_0000 +bcid 113 0 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +sid DW_pulse_sync_0000 +bcid 114 0 WIDTH,32 PARAMETER,2 OPT_CONST,0 WIDTH,1 EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 XOR WIDTH,32 PARAMETER,2 OPT_CONST,1 WIDTH,1 EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,5,0 NOT AND CALL_ARG_VAL,4,0 XOR WIDTH,32 PARAMETER,2 OPT_CONST,2 WIDTH,1 EQU CALL_ARG_VAL,3,0 NOT CALL_ARG_VAL,5,0 AND CALL_ARG_VAL,4,0 XOR WIDTH,32 PARAMETER,2 OPT_CONST,3 WIDTH,1 EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,5,0 CALL_ARG_VAL,4,0 XOR XOR OPT_CONST_4ST,1,1 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 115 1 WIDTH,32 PARAMETER,2 OPT_CONST,0 WIDTH,1 M_NEQU WIDTH,2 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,2 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 XOR MITECONDNOINSTR,4 RET +sid ulink_descrambler_32 +bcid 116 0 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND WIDTH,32 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 XOR CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +sid syn_fwft_fifo +bcid 117 0 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,62 WIDTH,1 M_GT RET +bcid 118 1 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,59 WIDTH,1 M_GT RET +bcid 119 2 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,510 WIDTH,1 M_GT RET +bcid 120 3 WIDTH,7 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 121 4 WIDTH,7 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_LT RET +bcid 122 5 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,17 WIDTH,1 M_LT RET +bcid 123 6 WIDTH,6 CALL_ARG_VAL,2,0 WIDTH,4 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 LNOT AND WIDTH,5 CONCATENATE,2 WIDTH,6 PAD ADD RET +bcid 124 7 WIDTH,6 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_NEQU RET +bcid 125 8 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,128 CONST,0,0 CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +sid ulink_frame_receiver_0000 +bcid 126 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,16 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,16 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 127 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,4 MULTI_CONCATENATE,1,4 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,4 MULTI_CONCATENATE,1,4 NOT OR RET +bcid 128 2 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 WIDTH,1 M_NEQU AND RET +sid ulink_rx +bcid 129 0 WIDTH,20 CALL_ARG_VAL,2,0 OPT_CONST,10000 WIDTH,1 M_NEQU RET +bcid 130 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,20 CALL_ARG_VAL,3,0 OPT_CONST,9999 WIDTH,1 M_EQU AND RET +bcid 131 2 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,20 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,20 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 132 3 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 133 4 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 M_EQU AND RET +bcid 134 5 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 135 6 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,1751543404 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1751543404 WIDTH,1 M_EQU AND WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1751543404 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,1751543404 WIDTH,1 M_EQU AND AND RET +bcid 136 7 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,1702390132 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1702390132 WIDTH,1 M_EQU AND WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1702390132 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,1702390132 WIDTH,1 M_EQU AND AND RET +bcid 137 8 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,20 CALL_ARG_VAL,3,0 WIDTH,32 PAD WIDTH,20 CALL_ARG_VAL,4,0 WIDTH,32 PAD OPT_CONST,2 SUBTRACT WIDTH,1 M_EQU AND RET +bcid 138 9 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,3 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 CALL_ARG_VAL,3,0 ADD MITECONDNOINSTR,4 RET +bcid 139 10 WIDTH,128 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 SLICE,1 OPT_CONST,-1128481604 WIDTH,1 M_EQU RET +bcid 140 11 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND OPT_CONST,1 CALL_ARG_VAL,4,0 OPT_CONST,0 CALL_ARG_VAL,5,0 OPT_CONST,0 CALL_ARG_VAL,6,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 141 12 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 M_EQU AND CALL_ARG_VAL,4,0 OR RET +bcid 142 13 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,3 MULTI_CONCATENATE,1,3 RET +sid pulse_generator +bcid 143 0 WIDTH,16 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_EQU RET +sid tsdn28hpcpuhdb4096x128m4mw_170a +bcid 144 0 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 145 1 WIDTH,1 OPT_CONST,0 RET +bcid 146 2 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 147 3 WIDTH,1 OPT_CONST,0 RET +bcid 148 4 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 149 5 WIDTH,1 OPT_CONST,0 RET +bcid 150 6 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 151 7 WIDTH,1 OPT_CONST,0 RET +bcid 152 8 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 153 9 WIDTH,1 OPT_CONST,0 RET +bcid 154 10 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 155 11 WIDTH,1 OPT_CONST,0 RET +bcid 156 12 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 157 13 WIDTH,1 OPT_CONST,0 RET +bcid 158 14 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 159 15 WIDTH,1 OPT_CONST,0 RET +bcid 160 16 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 161 17 WIDTH,1 OPT_CONST,0 RET +bcid 162 18 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 163 19 WIDTH,1 OPT_CONST,0 RET +bcid 164 20 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 165 21 WIDTH,1 OPT_CONST,0 RET +bcid 166 22 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 167 23 WIDTH,1 OPT_CONST,0 RET +bcid 168 24 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 169 25 WIDTH,1 OPT_CONST,0 RET +bcid 170 26 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 171 27 WIDTH,1 OPT_CONST,0 RET +bcid 172 28 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 173 29 WIDTH,1 OPT_CONST,0 RET +bcid 174 30 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 175 31 WIDTH,1 OPT_CONST,0 RET +bcid 176 32 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 177 33 WIDTH,1 OPT_CONST,0 RET +bcid 178 34 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 179 35 WIDTH,1 OPT_CONST,0 RET +bcid 180 36 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 181 37 WIDTH,1 OPT_CONST,0 RET +bcid 182 38 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 183 39 WIDTH,1 OPT_CONST,0 RET +bcid 184 40 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 185 41 WIDTH,1 OPT_CONST,0 RET +bcid 186 42 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 187 43 WIDTH,1 OPT_CONST,0 RET +bcid 188 44 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 189 45 WIDTH,1 OPT_CONST,0 RET +bcid 190 46 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 191 47 WIDTH,1 OPT_CONST,0 RET +bcid 192 48 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 193 49 WIDTH,1 OPT_CONST,0 RET +bcid 194 50 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 195 51 WIDTH,1 OPT_CONST,0 RET +bcid 196 52 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 197 53 WIDTH,1 OPT_CONST,0 RET +bcid 198 54 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 199 55 WIDTH,1 OPT_CONST,0 RET +bcid 200 56 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 201 57 WIDTH,1 OPT_CONST,0 RET +bcid 202 58 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 203 59 WIDTH,1 OPT_CONST,0 RET +bcid 204 60 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 205 61 WIDTH,1 OPT_CONST,0 RET +bcid 206 62 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 207 63 WIDTH,1 OPT_CONST,0 RET +bcid 208 64 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 209 65 WIDTH,1 OPT_CONST,0 RET +bcid 210 66 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 211 67 WIDTH,1 OPT_CONST,0 RET +bcid 212 68 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 213 69 WIDTH,1 OPT_CONST,0 RET +bcid 214 70 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 215 71 WIDTH,1 OPT_CONST,0 RET +bcid 216 72 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 217 73 WIDTH,1 OPT_CONST,0 RET +bcid 218 74 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 219 75 WIDTH,1 OPT_CONST,0 RET +bcid 220 76 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 221 77 WIDTH,1 OPT_CONST,0 RET +bcid 222 78 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 223 79 WIDTH,1 OPT_CONST,0 RET +bcid 224 80 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 225 81 WIDTH,1 OPT_CONST,0 RET +bcid 226 82 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 227 83 WIDTH,1 OPT_CONST,0 RET +bcid 228 84 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 229 85 WIDTH,1 OPT_CONST,0 RET +bcid 230 86 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 231 87 WIDTH,1 OPT_CONST,0 RET +bcid 232 88 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 233 89 WIDTH,1 OPT_CONST,0 RET +bcid 234 90 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 235 91 WIDTH,1 OPT_CONST,0 RET +bcid 236 92 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 237 93 WIDTH,1 OPT_CONST,0 RET +bcid 238 94 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 239 95 WIDTH,1 OPT_CONST,0 RET +bcid 240 96 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 241 97 WIDTH,1 OPT_CONST,0 RET +bcid 242 98 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 243 99 WIDTH,1 OPT_CONST,0 RET +bcid 244 100 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 245 101 WIDTH,1 OPT_CONST,0 RET +bcid 246 102 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 247 103 WIDTH,1 OPT_CONST,0 RET +bcid 248 104 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 249 105 WIDTH,1 OPT_CONST,0 RET +bcid 250 106 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 251 107 WIDTH,1 OPT_CONST,0 RET +bcid 252 108 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 253 109 WIDTH,1 OPT_CONST,0 RET +bcid 254 110 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 255 111 WIDTH,1 OPT_CONST,0 RET +bcid 256 112 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 257 113 WIDTH,1 OPT_CONST,0 RET +bcid 258 114 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 259 115 WIDTH,1 OPT_CONST,0 RET +bcid 260 116 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 261 117 WIDTH,1 OPT_CONST,0 RET +bcid 262 118 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 263 119 WIDTH,1 OPT_CONST,0 RET +bcid 264 120 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 265 121 WIDTH,1 OPT_CONST,0 RET +bcid 266 122 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 267 123 WIDTH,1 OPT_CONST,0 RET +bcid 268 124 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 269 125 WIDTH,1 OPT_CONST,0 RET +bcid 270 126 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 271 127 WIDTH,1 OPT_CONST,0 RET +bcid 272 128 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 273 129 WIDTH,1 OPT_CONST,0 RET +bcid 274 130 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 275 131 WIDTH,1 OPT_CONST,0 RET +bcid 276 132 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 277 133 WIDTH,1 OPT_CONST,0 RET +bcid 278 134 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 279 135 WIDTH,1 OPT_CONST,0 RET +bcid 280 136 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 281 137 WIDTH,1 OPT_CONST,0 RET +bcid 282 138 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 283 139 WIDTH,1 OPT_CONST,0 RET +bcid 284 140 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 285 141 WIDTH,1 OPT_CONST,0 RET +bcid 286 142 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 287 143 WIDTH,1 OPT_CONST,0 RET +bcid 288 144 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 289 145 WIDTH,1 OPT_CONST,0 RET +bcid 290 146 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 291 147 WIDTH,1 OPT_CONST,0 RET +bcid 292 148 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 293 149 WIDTH,1 OPT_CONST,0 RET +bcid 294 150 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 295 151 WIDTH,1 OPT_CONST,0 RET +bcid 296 152 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 297 153 WIDTH,1 OPT_CONST,0 RET +bcid 298 154 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 299 155 WIDTH,1 OPT_CONST,0 RET +bcid 300 156 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 301 157 WIDTH,1 OPT_CONST,0 RET +bcid 302 158 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 303 159 WIDTH,1 OPT_CONST,0 RET +bcid 304 160 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 305 161 WIDTH,1 OPT_CONST,0 RET +bcid 306 162 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 307 163 WIDTH,1 OPT_CONST,0 RET +bcid 308 164 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 309 165 WIDTH,1 OPT_CONST,0 RET +bcid 310 166 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 311 167 WIDTH,1 OPT_CONST,0 RET +bcid 312 168 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 313 169 WIDTH,1 OPT_CONST,0 RET +bcid 314 170 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 315 171 WIDTH,1 OPT_CONST,0 RET +bcid 316 172 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 317 173 WIDTH,1 OPT_CONST,0 RET +bcid 318 174 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 319 175 WIDTH,1 OPT_CONST,0 RET +bcid 320 176 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 321 177 WIDTH,1 OPT_CONST,0 RET +bcid 322 178 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 323 179 WIDTH,1 OPT_CONST,0 RET +bcid 324 180 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 325 181 WIDTH,1 OPT_CONST,0 RET +bcid 326 182 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 327 183 WIDTH,1 OPT_CONST,0 RET +bcid 328 184 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 329 185 WIDTH,1 OPT_CONST,0 RET +bcid 330 186 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 331 187 WIDTH,1 OPT_CONST,0 RET +bcid 332 188 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 333 189 WIDTH,1 OPT_CONST,0 RET +bcid 334 190 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 335 191 WIDTH,1 OPT_CONST,0 RET +bcid 336 192 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 337 193 WIDTH,1 OPT_CONST,0 RET +bcid 338 194 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 339 195 WIDTH,1 OPT_CONST,0 RET +bcid 340 196 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 341 197 WIDTH,1 OPT_CONST,0 RET +bcid 342 198 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 343 199 WIDTH,1 OPT_CONST,0 RET +bcid 344 200 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 345 201 WIDTH,1 OPT_CONST,0 RET +bcid 346 202 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 347 203 WIDTH,1 OPT_CONST,0 RET +bcid 348 204 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 349 205 WIDTH,1 OPT_CONST,0 RET +bcid 350 206 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 351 207 WIDTH,1 OPT_CONST,0 RET +bcid 352 208 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 353 209 WIDTH,1 OPT_CONST,0 RET +bcid 354 210 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 355 211 WIDTH,1 OPT_CONST,0 RET +bcid 356 212 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 357 213 WIDTH,1 OPT_CONST,0 RET +bcid 358 214 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 359 215 WIDTH,1 OPT_CONST,0 RET +bcid 360 216 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 361 217 WIDTH,1 OPT_CONST,0 RET +bcid 362 218 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 363 219 WIDTH,1 OPT_CONST,0 RET +bcid 364 220 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 365 221 WIDTH,1 OPT_CONST,0 RET +bcid 366 222 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 367 223 WIDTH,1 OPT_CONST,0 RET +bcid 368 224 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 369 225 WIDTH,1 OPT_CONST,0 RET +bcid 370 226 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 371 227 WIDTH,1 OPT_CONST,0 RET +bcid 372 228 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 373 229 WIDTH,1 OPT_CONST,0 RET +bcid 374 230 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 375 231 WIDTH,1 OPT_CONST,0 RET +bcid 376 232 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 377 233 WIDTH,1 OPT_CONST,0 RET +bcid 378 234 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 379 235 WIDTH,1 OPT_CONST,0 RET +bcid 380 236 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 381 237 WIDTH,1 OPT_CONST,0 RET +bcid 382 238 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 383 239 WIDTH,1 OPT_CONST,0 RET +bcid 384 240 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 385 241 WIDTH,1 OPT_CONST,0 RET +bcid 386 242 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 387 243 WIDTH,1 OPT_CONST,0 RET +bcid 388 244 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 389 245 WIDTH,1 OPT_CONST,0 RET +bcid 390 246 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 391 247 WIDTH,1 OPT_CONST,0 RET +bcid 392 248 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 393 249 WIDTH,1 OPT_CONST,0 RET +bcid 394 250 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 395 251 WIDTH,1 OPT_CONST,0 RET +bcid 396 252 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 397 253 WIDTH,1 OPT_CONST,0 RET +bcid 398 254 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 399 255 WIDTH,1 OPT_CONST,0 RET +sid dpram +bcid 400 0 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU WIDTH,512 MULTI_CONCATENATE,1,512 CALL_ARG_VAL,3,0 AND WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU WIDTH,512 MULTI_CONCATENATE,1,512 CALL_ARG_VAL,4,0 AND OR RET +bcid 401 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 MULTI_CONCATENATE,1,8 RET +sid awg_top +bcid 402 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,13 CALL_ARG_VAL,3,0 WIDTH,6 OPT_CONST,0 WIDTH,19 CONCATENATE,2 WIDTH,13 CALL_ARG_VAL,4,0 WIDTH,6 OPT_CONST,0 WIDTH,19 CONCATENATE,2 MITECONDNOINSTR,4 RET +bcid 403 1 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,62 WIDTH,1 M_GT RET +bcid 404 2 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,59 WIDTH,1 M_GT RET +bcid 405 3 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,30 WIDTH,1 M_GT RET +bcid 406 4 WIDTH,7 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 407 5 WIDTH,7 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_LT RET +bcid 408 6 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,17 WIDTH,1 M_LT RET +bcid 409 7 WIDTH,6 CALL_ARG_VAL,2,0 WIDTH,4 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 LNOT AND WIDTH,5 CONCATENATE,2 WIDTH,6 PAD ADD RET +bcid 410 8 WIDTH,6 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_NEQU RET +bcid 411 9 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 412 10 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND RET +bcid 413 11 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 SLICE,1 NOT AND RET +bcid 414 12 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 SLICE,1 AND RET +bcid 415 13 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,31 WIDTH,1 SLICE,1 CALL_ARG_VAL,5,0 NOT AND AND RET +bcid 416 14 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 AND AND RET +bcid 417 15 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,31 WIDTH,1 SLICE,1 CALL_ARG_VAL,5,0 OR NOT AND RET +bcid 418 16 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 AND AND RET +bcid 419 17 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND WIDTH,3 OPT_CONST,1 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,4,0 AND WIDTH,3 OPT_CONST,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,5,0 AND WIDTH,3 OPT_CONST,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,6,0 AND WIDTH,3 OPT_CONST,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,7,0 AND WIDTH,3 OPT_CONST,0 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,8,0 AND WIDTH,3 OPT_CONST,2 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,9,0 AND WIDTH,3 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 420 18 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 OR OR CALL_ARG_VAL,5,0 NOT AND RET +bcid 421 19 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 422 20 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,13 CALL_ARG_VAL,3,0 WIDTH,32 PAD WIDTH,13 CALL_ARG_VAL,4,0 WIDTH,32 PAD OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU AND RET +bcid 423 21 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,13 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,13 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 424 22 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 WIDTH,32 PAD WIDTH,5 CALL_ARG_VAL,4,0 WIDTH,32 PAD OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 M_NEQU AND AND RET +bcid 425 23 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 426 24 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 427 25 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,31 CALL_ARG_VAL,3,0 WIDTH,32 PAD WIDTH,31 CALL_ARG_VAL,4,0 WIDTH,32 PAD OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU AND RET +bcid 428 26 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,31 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,31 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 429 27 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,512 CALL_ARG_VAL,3,0 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,8 CALL_ARG_VAL,5,0 WIDTH,512 MULTI_CONCATENATE,1,64 CONST,0,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 430 28 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU OR RET +bcid 431 29 WIDTH,13 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 ADD RET +sid ramp_gen_0000 +bcid 432 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU AND RET +bcid 433 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 434 2 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,8 SHIFT_L RET +bcid 435 3 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,8 SHIFT_L RET +bcid 436 4 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,8 SHIFT_L RET +bcid 437 5 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,4 WIDTH,8 SHIFT_L RET +bcid 438 6 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,5 WIDTH,8 SHIFT_L RET +bcid 439 7 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,6 WIDTH,8 SHIFT_L RET +sid dac_regfile +bcid 440 0 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,46,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,48,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU CALL_ARG_VAL,49,0 CALL_ARG_VAL,50,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,51,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 441 1 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,46,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,48,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,50,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,51,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 442 2 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,44,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,46,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,48,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,50,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,51,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 443 3 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,44,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,46,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,48,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,50,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,51,0 OPT_CONST,10 WIDTH,22 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 444 4 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,44,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,46,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,48,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,50,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,51,0 OPT_CONST,4 WIDTH,6 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 445 5 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 OPT_CONST,539362576 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,3,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,5,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,6,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,7,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,8,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,9,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,10,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,11,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,12,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,13,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,14,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,15,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,16,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,17,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,18,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,19,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,20,0 OPT_CONST,10 WIDTH,22 SLICE,1 CALL_ARG_VAL,21,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 446 6 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 OPT_CONST,539362576 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,3,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,5,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,6,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,7,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,10 CALL_ARG_VAL,8,0 WIDTH,32 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,9,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,10,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,11,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,12,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,13,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,14,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,15,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,16,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,17,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,18,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,19,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,20,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,21,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,22,0 OPT_CONST,4 WIDTH,6 SLICE,1 CALL_ARG_VAL,23,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 447 7 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 OPT_CONST,539362576 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,3,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,5,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,6,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,7,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,8,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,9,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,10,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,11,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,10 CALL_ARG_VAL,12,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,13,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,14,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,15,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,16,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,17,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,18,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,19,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,20,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,21,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,22,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,23,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,24,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,25,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,26,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,27,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,28,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,29,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 448 8 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 OPT_CONST,539362576 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,3,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,5,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,6,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,7,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,8,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,9,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,10,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,11,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,10 CALL_ARG_VAL,12,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,13,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,14,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,15,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,16,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,17,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,18,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,19,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,20,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,21,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,22,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,23,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,24,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,25,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,26,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,27,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,28,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,29,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,30,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,31,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,32,0 OPT_CONST,1 WIDTH,2 SLICE,1 CALL_ARG_VAL,33,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 449 9 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 OPT_CONST,539362576 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,3,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,5,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,6,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,7,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,8,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,9,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,10,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,11,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,10 CALL_ARG_VAL,12,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,13,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,14,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,15,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,16,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,17,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,18,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,19,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,20,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,21,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,22,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,23,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,24,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,25,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,26,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,27,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,28,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,29,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,30,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,31,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,32,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,33,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,34,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,35,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 450 10 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 451 11 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 452 12 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 453 13 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 454 14 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 M_EQU RET +bcid 455 15 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 M_EQU RET +bcid 456 16 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 M_EQU RET +bcid 457 17 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 M_EQU RET +bcid 458 18 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU RET +bcid 459 19 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 M_EQU RET +bcid 460 20 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,10 WIDTH,1 M_EQU RET +bcid 461 21 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,11 WIDTH,1 M_EQU RET +bcid 462 22 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,1 M_EQU RET +bcid 463 23 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,13 WIDTH,1 M_EQU RET +bcid 464 24 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,14 WIDTH,1 M_EQU RET +bcid 465 25 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,1 M_EQU RET +bcid 466 26 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 M_EQU RET +bcid 467 27 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,17 WIDTH,1 M_EQU RET +bcid 468 28 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,18 WIDTH,1 M_EQU RET +bcid 469 29 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,19 WIDTH,1 M_EQU RET +bcid 470 30 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 M_EQU RET +bcid 471 31 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,21 WIDTH,1 M_EQU RET +bcid 472 32 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,22 WIDTH,1 M_EQU RET +bcid 473 33 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,23 WIDTH,1 M_EQU RET +bcid 474 34 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,24 WIDTH,1 M_EQU RET +bcid 475 35 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,1 M_EQU RET +bcid 476 36 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,26 WIDTH,1 M_EQU RET +bcid 477 37 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,27 WIDTH,1 M_EQU RET +bcid 478 38 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,28 WIDTH,1 M_EQU RET +bcid 479 39 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,29 WIDTH,1 M_EQU RET +bcid 480 40 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,30 WIDTH,1 M_EQU RET +bcid 481 41 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 M_EQU RET +bcid 482 42 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,32 WIDTH,1 M_EQU RET +bcid 483 43 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,33 WIDTH,1 M_EQU RET +bcid 484 44 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,34 WIDTH,1 M_EQU RET +bcid 485 45 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,35 WIDTH,1 M_EQU RET +bcid 486 46 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,36 WIDTH,1 M_EQU RET +bcid 487 47 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,37 WIDTH,1 M_EQU RET +bcid 488 48 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,38 WIDTH,1 M_EQU RET +bcid 489 49 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,39 WIDTH,1 M_EQU RET +bcid 490 50 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,40 WIDTH,1 M_EQU RET +bcid 491 51 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,41 WIDTH,1 M_EQU RET +sid clk_regfile +bcid 492 0 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,24 WIDTH,8 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 493 1 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,20 WIDTH,4 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 494 2 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,16 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,16 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,16 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,16 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,16 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,16 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,16 WIDTH,4 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 495 3 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 496 4 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 497 5 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 498 6 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 499 7 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,39,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 500 8 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,39,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,41,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 501 9 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,39,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU CALL_ARG_VAL,41,0 CALL_ARG_VAL,42,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,43,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 EQU CALL_ARG_VAL,45,0 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 502 10 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 503 11 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 504 12 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 505 13 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 506 14 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 M_EQU RET +bcid 507 15 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 M_EQU RET +bcid 508 16 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 M_EQU RET +bcid 509 17 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 M_EQU RET +bcid 510 18 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU RET +bcid 511 19 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 M_EQU RET +bcid 512 20 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,10 WIDTH,1 M_EQU RET +bcid 513 21 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,11 WIDTH,1 M_EQU RET +bcid 514 22 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,1 M_EQU RET +bcid 515 23 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,13 WIDTH,1 M_EQU RET +bcid 516 24 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,14 WIDTH,1 M_EQU RET +bcid 517 25 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,1 M_EQU RET +bcid 518 26 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 M_EQU RET +bcid 519 27 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,17 WIDTH,1 M_EQU RET +bcid 520 28 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,18 WIDTH,1 M_EQU RET +bcid 521 29 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,19 WIDTH,1 M_EQU RET +bcid 522 30 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 M_EQU RET +bcid 523 31 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,21 WIDTH,1 M_EQU RET +sid da4008_chip_top +bcid 524 0 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 NOT AND OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,2 WIDTH,1 EQU OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD MITECONDNOINSTR,4 WIDTH,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 AND OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 EQU OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 OPT_CONST,1 SUBTRACT MITECONDNOINSTR,4 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 525 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 526 2 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 527 3 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 WIDTH,32 PAD OPT_CONST,31 WIDTH,1 NEQU WIDTH,5 MULTI_CONCATENATE,1,5 CALL_ARG_VAL,3,0 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,5 SLICE,1 ADD AND CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 528 4 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,31 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 SLICE,1 NOT WIDTH,32 CONCATENATE,2 CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 529 5 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 EQU AND CALL_ARG_VAL,4,0 NOT CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 530 6 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST_4ST,1,1 EQU CALL_ARG_VAL,3,0 OPT_CONST_4ST,1,1 EQU OR OPT_CONST_4ST,1,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 OPT_CONST,16 WIDTH,5 CALL_ARG_VAL,4,0 WIDTH,32 PAD WIDTH,1 M_GT AND OPT_CONST,1 WIDTH,5 CALL_ARG_VAL,4,0 WIDTH,32 PAD OPT_CONST,15 WIDTH,1 M_GT OPT_CONST,0 CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 531 7 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST_4ST,1,1 EQU WIDTH,4 OPT_CONST_4ST,15,15 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG,3 CALL_ARG_VAL,5,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 532 8 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 533 9 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 M_EQU AND RET +bcid 534 10 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1 WIDTH,1 M_EQU AND RET +bcid 535 11 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 NOT AND OPT_CONST,1 CALL_ARG_VAL,3,0 OPT_CONST,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 536 12 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND OPT_CONST,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 NOT CALL_ARG_VAL,4,0 AND AND OPT_CONST,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 537 13 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 SM_GT RET +bcid 538 14 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1 WIDTH,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 EQU AND AND RET +sid TB +bcid 539 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,6 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,6 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/cc/cc_dummy_file b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/cc/cc_dummy_file new file mode 100644 index 0000000..9ec9235 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/cc/cc_dummy_file @@ -0,0 +1,2 @@ +Dummy_file +Missing line/file info diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/cgname.json b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/cgname.json new file mode 100644 index 0000000..39f08d3 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/cgname.json @@ -0,0 +1,920 @@ +{ + "PDDW04SDGZ_H_G": [ + "PDDW04SDGZ_H_G", + "CQ4ek", + "module", + 12 + ], + "PDB3AC_V_G": [ + "PDB3AC_V_G", + "dviib", + "module", + 9 + ], + "PCLAMP_G": [ + "PCLAMP_G", + "DA1Pu", + "module", + 3 + ], + "PDUW04DGZ_H_G": [ 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"PRUW16DGZ_H_G", + "AVYgt", + "module", + 68 + ], + "PRUW16DGZ_V_G": [ + "PRUW16DGZ_V_G", + "ErxQ3", + "module", + 69 + ], + "PVDD1A_H_G": [ + "PVDD1A_H_G", + "zNPu5", + "module", + 72 + ], + "PVDD1A_V_G": [ + "PVDD1A_V_G", + "CNBi6", + "module", + 73 + ], + "sirv_gnrl_ltch": [ + "sirv_gnrl_ltch", + "UTi0b", + "module", + 128 + ], + "PVDD1AC_H_G": [ + "PVDD1AC_H_G", + "W9VnM", + "module", + 74 + ], + "PVDD1AC_V_G": [ + "PVDD1AC_V_G", + "qn6Yx", + "module", + 75 + ], + "PVDD1ANA_H_G": [ + "PVDD1ANA_H_G", + "fEWTj", + "module", + 76 + ], + "awg_top": [ + "awg_top", + "J5zQK", + "module", + 137 + ], + "PVDD1DGZ_H_G": [ + "PVDD1DGZ_H_G", + "Eie6s", + "module", + 78 + ], + "PVSS2AC_V_G": [ + "PVSS2AC_V_G", + "YBQ1m", + "module", + 101 + ], + "PVSS3AC_V_G": [ + "PVSS3AC_V_G", + "i0k2A", + "module", + 109 + ], + "PVDD3AC_V_G": [ + "PVDD3AC_V_G", + "rZC3e", + "module", + 89 + ], + "PVDD2DGZ_V_G": [ + "PVDD2DGZ_V_G", + "LSxxn", + "module", + 83 + ], + "PVDD2POC_V_G": [ + "PVDD2POC_V_G", + "urn8Q", + "module", + 85 + ], + "PVDD3AC_H_G": [ + "PVDD3AC_H_G", + "U0PST", + "module", + 88 + ], + "tsdn28hpcpuhdb4096x128m4mw_170a_Int_Array": [ + "tsdn28hpcpuhdb4096x128m4mw_170a_Int_Array", + "bghMB", + "module", + 113 + ], + "PVSS1A_V_G": [ + "PVSS1A_V_G", + "ZmPik", + "module", + 91 + ], + "PVSS1AC_V_G": [ + "PVSS1AC_V_G", + "I7RzE", + "module", + 93 + ], + "PVSS1ANA_H_G": [ + "PVSS1ANA_H_G", + "HtwuV", + "module", + 94 + ], + "PVSS1DGZ_V_G": [ + "PVSS1DGZ_V_G", + "jHcbf", + "module", + 97 + ], + "PVSS2A_H_G": [ + "PVSS2A_H_G", + "usz4x", + "module", + 98 + ], + "PVSS2A_V_G": [ + "PVSS2A_V_G", + "fMI2k", + "module", + 99 + ], + "PVSS2AC_H_G": [ + "PVSS2AC_H_G", + "TqmdJ", + "module", + 100 + ], + "PVSS2ANA_V_G": [ + "PVSS2ANA_V_G", + "Md441", + "module", + 103 + ], + "PVSS2DGZ_H_G": [ + "PVSS2DGZ_H_G", + "ke5cH", + "module", + 104 + ], + "PVSS2DGZ_V_G": [ + "PVSS2DGZ_V_G", + "S5Dr6", + "module", + 105 + ], + "PVSS3A_V_G": [ + "PVSS3A_V_G", + "VSdee", + "module", + 107 + ], + "tsdn28hpcpuhdb4096x128m4mw_170a": [ + "tsdn28hpcpuhdb4096x128m4mw_170a", + "UJ4u7", + "module", + 112 + ], + "PVSS3AC_H_G": [ + "PVSS3AC_H_G", + "B0f3F", + "module", + 108 + ], + "PVSS3DGZ_H_G": [ + "PVSS3DGZ_H_G", + "rq1J0", + "module", + 110 + ], + "PVSS3DGZ_V_G": [ + "PVSS3DGZ_V_G", + "IZu3i", + "module", + 111 + ], + "DEM_PhaseSync_4008": [ + "DEM_PhaseSync_4008", + "sIRhK", + "module", + 138 + ], + "dacif_0000": [ + "dacif_0000", + "yeRHW", + "module", + 116 + ], + "dac_regfile": [ + "dac_regfile", + "LR0zI", + "module", + 118 + ], + "ulink_rx": [ + "ulink_rx", + "dteMU", + "module", + 119 + ], + "ulink_descrambler_128": [ + "ulink_descrambler_128", + "qxEhc", + "module", + 121 + ], + "sram_if": [ + "sram_if", + "NABmh", + "module", + 130 + ], + "sram_if_0000": [ + "sram_if_0000", + "nJgqZ", + "module", + 131 + ], + "sram_if_0001": [ + "sram_if_0001", + "z4wk8", + "module", + 132 + ], + "sram_if_0002": [ + "sram_if_0002", + "bEAZ8", + "module", + 133 + ], + "sram_dmux_w_0000": [ + "sram_dmux_w_0000", + "dc6nH", + "module", + 134 + ], + "clk_regfile": [ + "clk_regfile", + "jAdLC", + "module", + 136 + ], + "DA4008_DEM_Parallel_PRBS_1CH": [ + "DA4008_DEM_Parallel_PRBS_1CH", + "cQW1k", + "module", + 139 + ], + "DA4008_DEM_Parallel_PRBS_64CH": [ + "DA4008_DEM_Parallel_PRBS_64CH", + "q09PC", + "module", + 140 + ], + "spi_slave": [ + "spi_slave", + "eAsJz", + "module", + 143 + ], + "spi_if": [ + "spi_if", + "IHYdB", + "module", + 145 + ], + "clk_gen": [ + "clk_gen", + "MEIvW", + "module", + 146 + ], + "DEM_Reverse_64CH_0000": [ + "DEM_Reverse_64CH_0000", + "YnCHV", + "module", + 147 + ], + "DW_sync_0000": [ + "DW_sync_0000", + "zVfcK", + "module", + 149 + ], + "DW_pulse_sync_0000": [ + "DW_pulse_sync_0000", + "Ss3zK", + "module", + 150 + ], + "lvds_if": [ + "lvds_if", + "nS0i0", + "module", + 151 + ], + "TB": [ + "TB", + "sH4Fc", + "module", + 152 + ], + "...MASTER...": [ + "SIM", + "amcQw", + "module", + 153 + ] +} \ No newline at end of file diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/constraint.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/constraint.sdb new file mode 100644 index 0000000..82e87e8 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/constraint.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/covg_defs b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/covg_defs new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/.version b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/.version new file mode 100644 index 0000000..ed555f5 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/.version @@ -0,0 +1,4 @@ +O-2018.09-SP2_Full64 +Build Date = Feb 28 2019 22:34:30 +RedHat +Compile Location: /home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/AllModulesSkeletons.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/AllModulesSkeletons.sdb new file mode 100644 index 0000000..645927b Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/AllModulesSkeletons.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/HsimSigOptDb.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/HsimSigOptDb.sdb new file mode 100644 index 0000000..a582302 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/HsimSigOptDb.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/dumpcheck.db b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/dumpcheck.db new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/dve_debug.db.gz b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/dve_debug.db.gz new file mode 100644 index 0000000..a58895a Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/dve_debug.db.gz differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/fsearch/.create_fsearch_db b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/fsearch/.create_fsearch_db new file mode 100755 index 0000000..0efe198 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/fsearch/.create_fsearch_db @@ -0,0 +1,9 @@ +#!/bin/sh -h +PYTHONHOME=/opt/synopsys/vcs-mx/O-2018.09-SP2/etc/search/pyh +export PYTHONHOME +PYTHONPATH=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/pylib27 +export PYTHONPATH +LD_LIBRARY_PATH=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib:/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/pylib27 +export LD_LIBRARY_PATH +/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/vcsfind_create_index.exe -z "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/./idents_X4vtNx.xml.gz" "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" +\mv "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.db" diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/fsearch/check_fsearch_db b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/fsearch/check_fsearch_db new file mode 100755 index 0000000..1c1ff54 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/fsearch/check_fsearch_db @@ -0,0 +1,57 @@ +#!/bin/sh -h + +FILE_PATH="/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch" +lockfile="${FILE_PATH}"/lock + +FSearch_lock_release() { + echo "" > /dev/null +} +create_fsearch_db_ctrl() { + if [ -s "${FILE_PATH}"/fsearch.stat ]; then + if [ -s "${FILE_PATH}"/fsearch.log ]; then + echo "ERROR building identifier database failed. Check ${FILE_PATH}/fsearch.log" + else + cat "${FILE_PATH}"/fsearch.stat + fi + return + fi + nohup "$1" > "${FILE_PATH}"/fsearch.log 2>&1 193>/dev/null & + MY_PID=`echo $!` + BUILDER="pid ${MY_PID} ${USER}@${hostname}" + echo "INFO Started building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." + echo "INFO Still building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." > "${FILE_PATH}"/fsearch.stat + return +} + +dir_name=`/bin/dirname "$0"` +if [ "${dir_name}" = "." ]; then + cd $dir_name + dir_name=`/bin/pwd` +fi +if [ -d "$dir_name"/../../../../../../../../../../.. ]; then + cd "$dir_name"/../../../../../../../../../../.. +fi + +if [ -f "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db" ]; then + if [ ! -f "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.db" ]; then + if [ "$#" -eq 1 ] && [ "x$1" == "x-background" ]; then + trap FSearch_lock_release EXIT + ( + flock 193 + create_fsearch_db_ctrl "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db" + exit 193 + ) 193> "$lockfile" + rstat=$? + if [ "${rstat}"x != "193x" ]; then + exit $rstat + fi + else + "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db" + if [ -f "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then + rm -f "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" + fi + fi + elif [ -f "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then + rm -f "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" + fi +fi diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/fsearch/fsearch.stat b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/fsearch/fsearch.stat new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/fsearch/idents_X4vtNx.xml.gz b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/fsearch/idents_X4vtNx.xml.gz new file mode 100644 index 0000000..56532b3 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/fsearch/idents_X4vtNx.xml.gz differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz new file mode 100644 index 0000000..f24a0fd Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/src_files_verilog b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/src_files_verilog new file mode 100644 index 0000000..376b419 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/src_files_verilog @@ -0,0 +1,48 @@ +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/lib/tphn28hpcpgv18.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/lib/tsdn28hpcpuhdb4096x128m4mw_170a_ffg0p99v0c.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/DEM_Reverse.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/DEM_Reverse_64CH.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/DW_pulse_sync.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/DW_reset_sync.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/DW_stream_sync.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/DW_sync.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/LVDS_DRIVER.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/SPI_DRIVER.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/clk_gen.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/clock_tb.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/reset_tb.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/spi_if.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/awg/awg_ctrl.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/awg/awg_top.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/clk/clk_regfile.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/comm/pulse_generator.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/comm/ramp_gen.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/comm/sirv_gnrl_dffs.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/comm/sirv_gnrl_xchecker.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/comm/syncer.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/dac_regfile/dac_regfile.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/dacif/dacif.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/define/chip_define.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/define/chip_undefine.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/dem/DA4008_DEM_Parallel_PRBS_1CH.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/dem/DA4008_DEM_Parallel_PRBS_64CH.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/dem/DEM_PhaseSync_4008.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/fifo/syn_fwft_fifo.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/io/iopad.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/lvds/ulink_rx.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/memory/bhv_spram.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/memory/dpram.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/memory/spram.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/memory/sram_dmux.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/memory/sram_if.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/memory/tsmc_dpram.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/rstgen/rst_gen_unit.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/rstgen/rst_sync.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/spi/spi_bus_decoder.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/spi/spi_pll.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/spi/spi_slave.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/spi/spi_sys.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/systemregfile/systemregfile.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/top/da4008_chip_top.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/top/digital_top.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/TB.sv diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/topmodules b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/topmodules new file mode 100644 index 0000000..5dce012 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/topmodules @@ -0,0 +1 @@ +r’LžD•B’–\ƒ$…c–Cšs°1´S¤ ¦%ºg¿)!©t¬x"µ.º<8¦Y©S9Iƒ:“>­B°;“?»¹¨5¨7¥2›AŸ*')°.´Q)*¤ ¦$*+Ÿs£xB“Iµ,º8D“O¦X©PE“P‰6Ž›tŸn§ª7¯\³2¤[¦e¬Z¯>$ m‹Ž=¤¦:†2ˆB ;¤§Rªe¯i´ †F‰)¤B¦L¤m¦w¬l¯O†LŠ"¦V©I¨n¬Aµ»l ¥¶O \ No newline at end of file diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/vir.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/vir.sdb new file mode 100644 index 0000000..9b4dea7 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/debug_dump/vir.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/eblklvl.db b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/eblklvl.db new file mode 100644 index 0000000..2870040 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/eblklvl.db differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/elabmoddb.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/elabmoddb.sdb new file mode 100644 index 0000000..4d03f67 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/elabmoddb.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/external_functions b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/external_functions new file mode 100644 index 0000000..394a9dd --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/external_functions @@ -0,0 +1,129 @@ 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novas_call_fsdbDumpoff - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbSwitchDumpfile novas_call_fsdbSwitchDumpfile - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpfile novas_call_fsdbDumpfile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbAutoSwitchDumpfile novas_call_fsdbAutoSwitchDumpfile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpFinish novas_call_fsdbDumpFinish - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpflush novas_call_fsdbDumpflush - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbLog novas_call_fsdbLog - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbAddRuntimeSignal novas_call_fsdbAddRuntimeSignal - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpSC novas_call_fsdbDumpSC - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpvarsToFile novas_call_fsdbDumpvarsToFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_create_transaction_stream novas_call_sps_create_transaction_stream - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_begin_transaction novas_call_sps_begin_transaction - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_end_transaction novas_call_sps_end_transaction - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_free_transaction novas_call_sps_free_transaction - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_add_attribute novas_call_sps_add_attribute - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_update_label novas_call_sps_update_label - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_add_relation novas_call_sps_add_relation - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbWhatif novas_call_fsdbWhatif - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $paa_init novas_call_paa_init - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $paa_sync novas_call_paa_sync - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpClassMethod novas_call_fsdbDumpClassMethod - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbSuppressClassMethod novas_call_fsdbSuppressClassMethod - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbSuppressClassProp novas_call_fsdbSuppressClassProp - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpMDAByFile novas_call_fsdbDumpMDAByFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_create_stream_begin novas_call_fsdbEvent_create_stream_begin - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_define_attribute novas_call_fsdbEvent_add_stream_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_create_stream_end novas_call_fsdbEvent_create_stream_end - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_begin novas_call_fsdbEvent_begin - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_set_label novas_call_fsdbEvent_set_label - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_attribute novas_call_fsdbEvent_add_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_tag novas_call_fsdbEvent_add_tag - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_end novas_call_fsdbEvent_end - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_relation novas_call_fsdbEvent_add_relation - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_get_error_code novas_call_fsdbEvent_get_error_code - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_stream_attribute novas_call_fsdbTrans_add_stream_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_scope_attribute novas_call_fsdbTrans_add_scope_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_interactive novas_call_sps_interactive - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_test novas_call_sps_test - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpClassObject novas_call_fsdbDumpClassObject - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpClassObjectByFile novas_call_fsdbDumpClassObjectByFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $ridbDump novas_call_ridbDump - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_flush_file novas_call_sps_flush_file - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpPSL novas_call_fsdbDumpPSL - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumplimit novas_call_fsdbDumplimit - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpvars novas_call_fsdbDumpvars - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsES novas_call_fsdbDumpvarsES - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDA novas_call_fsdbDumpMDA - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVA novas_call_fsdbDumpSVA - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsByFile novas_call_fsdbDumpvarsByFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppress novas_call_fsdbSuppress - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpon novas_call_fsdbDumpon - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpoff novas_call_fsdbDumpoff - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSwitchDumpfile novas_call_fsdbSwitchDumpfile - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpfile novas_call_fsdbDumpfile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbAutoSwitchDumpfile novas_call_fsdbAutoSwitchDumpfile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpFinish novas_call_fsdbDumpFinish - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpflush novas_call_fsdbDumpflush - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbLog novas_call_fsdbLog - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbAddRuntimeSignal novas_call_fsdbAddRuntimeSignal - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSC novas_call_fsdbDumpSC - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsToFile novas_call_fsdbDumpvarsToFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_create_transaction_stream novas_call_sps_create_transaction_stream - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_begin_transaction novas_call_sps_begin_transaction - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_end_transaction novas_call_sps_end_transaction - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_free_transaction novas_call_sps_free_transaction - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_add_attribute novas_call_sps_add_attribute - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_update_label novas_call_sps_update_label - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_add_relation novas_call_sps_add_relation - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbWhatif novas_call_fsdbWhatif - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $paa_init novas_call_paa_init - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $paa_sync novas_call_paa_sync - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassMethod novas_call_fsdbDumpClassMethod - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppressClassMethod novas_call_fsdbSuppressClassMethod - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppressClassProp novas_call_fsdbSuppressClassProp - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAByFile novas_call_fsdbDumpMDAByFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_create_stream_begin novas_call_fsdbEvent_create_stream_begin - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_define_attribute novas_call_fsdbEvent_add_stream_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_create_stream_end novas_call_fsdbEvent_create_stream_end - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_begin novas_call_fsdbEvent_begin - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_set_label novas_call_fsdbEvent_set_label - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_attribute novas_call_fsdbEvent_add_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_tag novas_call_fsdbEvent_add_tag - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_end novas_call_fsdbEvent_end - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_relation novas_call_fsdbEvent_add_relation - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_get_error_code novas_call_fsdbEvent_get_error_code - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_stream_attribute novas_call_fsdbTrans_add_stream_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_scope_attribute novas_call_fsdbTrans_add_scope_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_interactive novas_call_sps_interactive - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_test novas_call_sps_test - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassObject novas_call_fsdbDumpClassObject - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassObjectByFile novas_call_fsdbDumpClassObjectByFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $ridbDump novas_call_ridbDump - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_flush_file novas_call_sps_flush_file - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSL novas_call_fsdbDumpPSL - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDisplay novas_call_fsdbDisplay - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumplimit novas_call_fsdbDumplimit - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMem novas_call_fsdbDumpMem - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemNow novas_call_fsdbDumpMemNow - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemInScope novas_call_fsdbDumpMemInScope - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDANow novas_call_fsdbDumpMDANow - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAOnChange novas_call_fsdbDumpMDAOnChange - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAInScope novas_call_fsdbDumpMDAInScope - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemInFile novas_call_fsdbDumpMemInFile - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSLon novas_call_fsdbDumpPSLon - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSLoff novas_call_fsdbDumpPSLoff - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVAon novas_call_fsdbDumpSVAon - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVAoff novas_call_fsdbDumpSVAoff - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpStrength novas_call_fsdbDumpStrength - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSingle novas_call_fsdbDumpSingle - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpIO novas_call_fsdbDumpIO - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPattern novas_call_fsdbDumpPattern - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSubstituteHier novas_call_fsdbSubstituteHier - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $dumpports DumpPortsIeeeCALL - DumpPortsMISC +pli $lsi_dumpports DumpPortsLsiCALL - DumpPortsMISC +pli $dumpportson DumpPortsOnCALL - DumpPortsMISC +pli $dumpportsoff DumpPortsOffCALL - DumpPortsMISC +pli $dumpportsflush DumpPortsFlushCALL - DumpPortsMISC +pli $simlearn simLearnCall simLearnCheck simLearnMisc +pli $dumpportsall DumpPortsAllCALL - DumpPortsMISC +pli $dumpportslimit DumpPortsLimitCALL - DumpPortsMISC +pli $countdrivers CountDriversCALL - - +pli $vcsmemprof DMMemProfCALL DMMemProfCheck DMMemProfMISC diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/hslevel_callgraph.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/hslevel_callgraph.sdb new file mode 100644 index 0000000..a00346b Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/hslevel_callgraph.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/hslevel_level.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/hslevel_level.sdb new file mode 100644 index 0000000..4cd2f62 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/hslevel_level.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/hslevel_rtime_level.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/hslevel_rtime_level.sdb new file mode 100644 index 0000000..8153356 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/hslevel_rtime_level.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/hsscan_cfg.dat b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/hsscan_cfg.dat new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/indcall.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/indcall.sdb new file mode 100644 index 0000000..c8ddf48 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/indcall.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/indcall_32553.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/indcall_32553.sdb new file mode 100644 index 0000000..50736b6 Binary files /dev/null and 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a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/pcxpxmr.dat b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/pcxpxmr.dat new file mode 100644 index 0000000..ee5778d Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/pcxpxmr.dat differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/prof.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/prof.sdb new file mode 100644 index 0000000..76179fc Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/prof.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/rmapats.dat b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/rmapats.dat new file mode 100644 index 0000000..cc1f304 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/rmapats.dat differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/rmapats.so b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/rmapats.so new file mode 100755 index 0000000..6df9faa Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/rmapats.so differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/saifNetInfo.db b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/saifNetInfo.db new file mode 100644 index 0000000..a69d3f9 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/saifNetInfo.db @@ -0,0 +1,22 @@ +7 +TB.U_da4008_chip_top.U_iopad.PDDW08SDGZ_V_G_sync_out +C +Scal +TB.U_da4008_chip_top.U_iopad.PDUW08SDGZ_V_G_irq +C +Scal +TB.U_da4008_chip_top.U_iopad.PDUW08SDGZ_V_G_miso +C +Scal +tsmc_dpram +spram_512X8192_generation®BWEBA +All +tsmc_dpram +spram_512X8192_generation®BWEBB +All +tsmc_dpram +spram_512X8192_generation®U_CEBA +All +tsmc_dpram +spram_512X8192_generation®U_CEBB +All diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/simv.kdb b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/simv.kdb new file mode 100644 index 0000000..68eacf4 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/simv.kdb @@ -0,0 +1,16 @@ +rc file Version 1.0 + +[Design] +COMPILE_PATH=/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top +SystemC=FALSE +UUM=FALSE +KDB=FALSE +USE_NOVAS_HOME=FALSE +COSIM=FALSE +TOP=PCLAMP_G PCLAMPC_H_G PCLAMPC_V_G PDB3A_H_G PDB3A_V_G PDB3AC_H_G PDB3AC_V_G PDDW04DGZ_H_G PDDW04DGZ_V_G PDDW04SDGZ_H_G PDDW08DGZ_H_G PDDW08DGZ_V_G PDDW08SDGZ_H_G PDDW08SDGZ_V_G PDDW12DGZ_H_G PDDW12DGZ_V_G PDDW12SDGZ_H_G PDDW12SDGZ_V_G PDDW16DGZ_H_G PDDW16DGZ_V_G PDDW16SDGZ_H_G PDDW16SDGZ_V_G PDUW04DGZ_H_G PDUW04DGZ_V_G PDUW04SDGZ_H_G PDUW08DGZ_H_G PDUW08DGZ_V_G PDUW08SDGZ_H_G PDUW12DGZ_H_G PDUW12DGZ_V_G PDUW12SDGZ_H_G PDUW12SDGZ_V_G PDUW16DGZ_H_G PDUW16DGZ_V_G PDUW16SDGZ_H_G PDUW16SDGZ_V_G PDXOEDG_H_G PDXOEDG_V_G PENDCAP_G PENDCAPA_G PRCUT_G PRCUTA_G PRDW08DGZ_H_G PRDW08DGZ_V_G PRDW08SDGZ_H_G PRDW08SDGZ_V_G PRDW12DGZ_H_G PRDW12DGZ_V_G PRDW12SDGZ_H_G PRDW12SDGZ_V_G PRDW16DGZ_H_G PRDW16DGZ_V_G PRDW16SDGZ_H_G PRDW16SDGZ_V_G PRUW08DGZ_H_G PRUW08DGZ_V_G PRUW08SDGZ_H_G PRUW08SDGZ_V_G PRUW12DGZ_H_G PRUW12DGZ_V_G PRUW12SDGZ_H_G PRUW12SDGZ_V_G PRUW16DGZ_H_G PRUW16DGZ_V_G PRUW16SDGZ_H_G PRUW16SDGZ_V_G PVDD1A_H_G PVDD1A_V_G PVDD1AC_H_G PVDD1AC_V_G PVDD1ANA_H_G PVDD1ANA_V_G PVDD1DGZ_H_G PVDD1DGZ_V_G PVDD2ANA_H_G PVDD2ANA_V_G PVDD2DGZ_H_G PVDD2DGZ_V_G PVDD2POC_H_G PVDD2POC_V_G PVDD3A_H_G PVDD3A_V_G PVDD3AC_H_G PVDD3AC_V_G PVSS1A_H_G PVSS1A_V_G PVSS1AC_H_G PVSS1AC_V_G PVSS1ANA_H_G PVSS1ANA_V_G PVSS1DGZ_H_G PVSS1DGZ_V_G PVSS2A_H_G PVSS2A_V_G PVSS2AC_H_G PVSS2AC_V_G PVSS2ANA_H_G PVSS2ANA_V_G PVSS2DGZ_H_G PVSS2DGZ_V_G PVSS3A_H_G PVSS3A_V_G PVSS3AC_H_G PVSS3AC_V_G PVSS3DGZ_H_G PVSS3DGZ_V_G sirv_gnrl_xchecker sirv_gnrl_dffl sirv_gnrl_ltch clk_gen reset_tb TB +OPTION=-ssz -ssv -ssy +ELAB_OPTION=-ssz -ssv -ssy + +[Value] +WREALX=ffff534e50535f58 +WREALZ=ffff534e50535f5a diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/stitch_nsparam.dat b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/stitch_nsparam.dat new file mode 100644 index 0000000..0357d47 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/stitch_nsparam.dat differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/tt.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/tt.sdb new file mode 100644 index 0000000..f118f49 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/tt.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/ttIncr_32553.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/ttIncr_32553.sdb new file mode 100644 index 0000000..698630c Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/ttIncr_32553.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/ttIncr_32573.sdb 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b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/ttIncr_32579.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcs_rebuild b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcs_rebuild new file mode 100755 index 0000000..403c9c0 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcs_rebuild @@ -0,0 +1,4 @@ +#!/bin/sh -e +# This file is automatically generated by VCS. Any changes you make +# to it will be overwritten the next time VCS is run. +vcs '-full64' '-j8' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+all' '-debug_region+cell+encrypt' '-P' '/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab' '/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a' '+define+DUMP_FSDB' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-cm' 'line+cond+fsm+tgl+branch' '-cm_dir' './coverage/simv.vdb' '-f' 'filelist_vlg.f' '+incdir+./../../rtl/define' '+incdir+./../../rtl/qubitmcu' '+incdir+./../../model' 2>&1 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_master_hsim_elabout.db b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_master_hsim_elabout.db new file mode 100644 index 0000000..d941a4e --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_master_hsim_elabout.db @@ -0,0 +1,691 @@ +hsDirType 1 +fHsimDesignHasDebugNodes 63 +fNSParam 1024 +fLargeSizeSdfTest 0 +fHsimDelayGateMbme 0 +fNoMergeDelays 0 +fHsimAllMtmPat 0 +fHsimCertRaptMode 0 +fSharedMasterElab 0 +hsimLevelizeDone 1 +fHsimCompressDiag 1 +fHsimPowerOpt 0 +fLoopReportElab 0 +fHsimRtl 0 +fHsimCbkOptVec 1 +fHsimDynamicCcnHeur 1 +fHsimPvcs 0 +fHsimPvcsCcn 0 +fHsimOldLdr 0 +fHsimSingleDB 1 +uVfsGcLimit 50 +fHsimCompatSched 0 +fHsimCompatOrder 0 +fHsimTransUsingdoMpd32 0 +fHsimDynamicElabForGates 1 +fHsimDynamicElabForVectors 0 +fHsimDynamicElabForVectorsAlways 0 +fHsimDynamicElabForVectorsMinputs 0 +fHsimDeferForceSelTillReElab 0 +fHsimModByModElab 1 +fSvNettRealResType 0 +fHsimExprID 1 +fHsimSequdpon 0 +fHsimDatapinOpt 0 +fHsimExprPrune 0 +fHsimMimoGate 0 +fHsimNewChangeCheckFrankch 1 +fHsimNoSched0Front 0 +fHsimNoSched0FrontForMd 1 +fHsimScalReg 0 +fHsimNtbVl 0 +fHsimICTimeStamp 0 +fHsimICDiag 0 +fHsimNewCSDF 1 +vcselabIncrMode 2 +fHsimMPPackDelay 0 +fHsimMultDriver 0 +fHsimPart 0 +fHsimPrlComp 0 +fHsimPartTest 0 +fHsimTestChangeCheck 0 +fHsimTestFlatNodeOrder 0 +fHsimTestNState 0 +fHsimPartDebug 0 +fHsimPartFlags 0 +fHsimOdeSched0 0 +fHsimNewRootSig 1 +fHsimDisableRootSigModeOpt 0 +fHsimTestRootSigModeOpt 0 +fHsimIncrWriteOnce 0 +fHsimUnifInterfaceFlow 1 +fHsimUnifInterfaceFlowDiag 0 +fHsimUnifInterfaceFlowXmrDiag 0 +fHsimUnifInterfaceMultiDrvChk 1 +fHsimXVirForGenerateScope 0 +fHsimCongruencyIntTestI 0 +fHsimCongruencySVA 0 +fHsimCongruencySVADbg 0 +fHsimCongruencyLatchEdgeFix 0 +fHsimCongruencyFlopEdgeFix 0 +fHsimCongruencyXprop 0 +fHsimCongruencyXpropFix 0 +fHsimCongruencyXpropDbsEdge 0 +fHsimCongruencyResetRecoveryDbs 0 +fHsimCongruencyClockControlDiag 0 +fHsimCongruencySampleUpdate 0 +fHsimCongruencyFFDbsFix 0 +fHsimCongruency 0 +fHsimCongruencySlave 0 +fHsimCongruencyCombinedLoads 0 +fHsimCongruencyFGP 0 +fHsimDeraceClockDataUdp 0 +fHsimDeraceClockDataLERUpdate 0 +fHsimCongruencyPC 0 +fHsimCongruencyPCInl 0 +fHsimCongruencyPCDbg 0 +fHsimCongruencyPCNoReuse 0 +fHsimCongruencyDumpHier 0 +fHsimCongruencyResolution 0 +fHsimCongruencyEveBus 0 +fHsimHcExpr 0 +fHsCgOptModOpt 0 +fHsCgOptSlowProp 0 +fHsimCcnOpt 1 +fHsimCcnOpt2 1 +fHsimCcnOpt3 0 +fHsimSmdMap 0 +fHsimSmdDiag 0 +fHsimSmdSimProf 0 +fHsimSgdDiag 0 +fHsimRtDiagLite 0 +fHsimRtDiagLiteCevent 100 +fHsimRtDiag 0 +fHsimSkRtDiag 0 +fHsimDDBSRtdiag 0 +fHsimDbg 0 +fHsimCompWithGates 0 +fHsimMdbDebugOpt 0 +fHsimMdbDebugOptP1 0 +fHsimMdbDebugOptP2 0 +fHsimMdbPruneOpt 1 +fHsimMdbMemOpt 0 +hsimRandValue 0 +fHsimSimMemProfile 0 +fHsimSimTimeProfile 0 +fHsimElabMemProfile 0 +fHsimElabTimeProfile 0 +fHsimElabMemNodesProfile 0 +fHsimElabMemAllNodesProfile 0 +fHsimDisableVpdGatesProfile 0 +fHsimFileProfile 0 +fHsimCountProfile 0 +fHsimXmrDefault 1 +fHsimFuseWireAndReg 0 +fHsimFuseSelfDrvLogic 0 +fHsimFuseProcess 0 +fHsimNoStitchDump 0 +fHsimAllExtXmrs 0 +fHsimAllXmrs 1 +fHsimMvsimDb 0 +fHsimTaskFuncXmrs 0 +fHsimTaskFuncXmrsDbg 0 +fHsimAllTaskFuncXmrs 0 +fHsimPageArray 16383 +fHsimPageControls 16383 +hsDfsNodePageElems 0 +hsNodePageElems 0 +hsFlatNodePageElems 0 +hsGateMapPageElems 0 +hsGateOffsetPageElems 0 +hsGateInputOffsetPageElems 0 +hsDbsOffsetPageElems 0 +hsMinPulseWidthPageElems 0 +hsNodeUpPatternPageElems 0 +hsNodeDownPatternPageElems 0 +hsNodeUpOffsetPageElems 0 +hsNodeEblkOffsetPageElems 0 +hsNodeDownOffsetPageElems 0 +hsNodeUpdateOffsetPageElems 0 +hsSdfOffsetPageElems 0 +fHsimPageAllLevelData 0 +fHsimAggrCg 0 +fHsimViWire 1 +fHsimPcCbOpt 1 +fHsimAmsTunneling 0 +fHsimAmsTunnelingDiag 0 +fHsimScUpwardXmrNoSplit 1 +fHsimOrigNdbViewOnly 0 +fHsimVcsInterface 1 +fHsimVcsInterfaceAlias 1 +fHsimSVTypesIntf 1 +fUnifiedAssertCtrlDiag 0 +fHsimEnable2StateScal 0 +fHsimDisable2StateScalIbn 0 +fHsimVcsInterfaceAliasDbg 0 +fHsimVcsInterfaceDbg 0 +fHsimVcsVirtIntfDbg 0 +fHsimVcsAllIntfVarMem 0 +fHsimCheckVIDynLoadOffsets 0 +fHsimModInline 1 +fHsimModInlineDbg 0 +fHsimPCDrvLoadDbg 0 +fHsimDrvChk 1 +fHsimRtlProcessingNeeded 0 +fHsimGrpByGrpElab 0 +fHsimGrpByGrpElabMaster 0 +fHsimNoParentSplitPC 0 +fHsimNusymMode 0 +fHsimOneIntfPart 0 +fHsimCompressInSingleDb 2 +fHsimCompressFlatDb 0 +fHsimNoTime0Sched 1 +fHsimMdbVectorizeInstances 0 +fHsimMdbSplitGates 0 +fHsimDeleteInstances 0 +fHsimUserDeleteInstances 0 +fHsimDeleteGdb 0 +fHsimDeleteInstancesMdb 0 +fHsimShortInstMap 0 +fHsimMdbVectorizationDump 0 +fHsimScanVectorize 0 +fHsimParallelScanVectorize 0 +noInstsInVectorization 0 +cHsimNonReplicatedInstances 0 +fHsimScanRaptor 0 +fHsimConfigFileCount 0 +fHsimVectorConstProp 0 +fHsimPromoteParam 0 +fHsimNoVecInRaptor 0 +fRaptorDumpVal 0 +fRaptorVecNodes 0 +fRaptorVecNodes2 0 +fRaptorNonVecNodes 0 +fRaptorBdrNodes 0 +fRaptorVecGates 0 +fRaptorNonVecGates 0 +fRaptorTotalNodesBeforeVect 0 +fRaptorTotalGatesBeforeVect 0 +fHsimCountRaptorBits 0 +fHsimNewEvcd 1 +fHsimNewEvcdMX 0 +fHsimNewEvcdVecRoot 1 +fHsimNewEvcdForce 1 +fHsimNewEvcdTest 0 +fHsimNewEvcdObnDrv 1 +fHsimNewEvcdW 1 +fHsimNewEvcdWTest 0 +fHsimEvcdDbgFlags 0 +fHsimNewEvcdMultiDrvFmt 1 +fHsimDumpOffsetData 1 +fFlopGlitchDetect 0 +fHsimClkGlitch 0 +fHsimGlitchDumpOnce 0 +fHsimDynamicElab 1 +fHsimCgVectors2Debug 0 +fHsimOdeDynElab 0 +fHsimOdeDynElabDiag 0 +fHsimOdeSeqUdp 0 +fHsimOdeSeqUdpXEdge 0 +fHsimOdeSeqUdpDbg 0 +fHsimOdeRmvSched0 0 +fHsimAllLevelSame 0 +fHsimRtlDbsList 0 +fHsimPePort 0 +fHsimPeXmr 0 +fHsimPePortDiag 0 +fHsimUdpDbs 0 +fHsimRemoveDbgCaps 0 +fFsdbGateOnepassTraverse 0 +fHsimAllowVecGateInVpd 1 +fHsimAllowAllVecGateInVpd 0 +fHsimAllowUdpInVpd 1 +fHsimAllowAlwaysCombInVpd 1 +fHsimAllowAlwaysCombCmpDvcSimv 0 +fHsimAllowAlwaysCombDbg 0 +fHsimMakeAllP2SPrimary 0 +fHsimMakeAllSeqPrimary 0 +fHsimNoCcnDump 0 +fHsimFsdbProfDiag 0 +fVpdSeqGate 0 +fVpdUseMaxBCode 0 +fVpdHsIntVecGate 0 +fVpdHsCmplxVecGate 0 +fVpdHsVecGateDiags 0 +fSeqGateCodePatch 0 +fVpdLongFaninOpt 0 +fVpdSeqLongFaninOpt 0 +fVpdNoLoopDetect 0 +fVpdNoSeqLoopDetect 0 +fVpdOptAllowConstDriver 0 +fVpdAllowCellReconstruction 0 +fVpdRtlForSharedLib 0 +fHsimVpdOptGate 1 +fHsimVpdOptDelay 0 +fHsimVpdOptMPDelay 0 +fHsimCbkOptDiag 0 +fHsimSK 0 +fHsimSharedKernel 1 +fHsimOnepass 0 +fHsimStitchNew 0 +fHsimParallelLevelize 0 +fHsimParallelLevelizeDbg 0 +fHsimSeqUdpDbsByteArray 0 +fHsimCoLocate 0 +fHsimSeqUdpEblkOpt 0 +fHsimSeqUdpEblkOptDiag 0 +fHsimGateInputAndDbsOffsetsOpt 1 +fHsimUdpDynElab 0 +fHsimCompressData 4 +fHsimIgnoreZForDfuse 1 +fHsimIgnoreDifferentCaps 0 +fHandleGlitchQC 1 +fGlitchDetectForAllRtlLoads 0 +fHsimFuseConstDriversOpt 1 +fHsimMdSchedTr 0 +fHsimIgnoreReElab 0 +fHsimFuseMultiDrivers 0 +fHsimNoSched0Reg 0 +fHsimAmsFusionEnabled 0 +fHsimRtlDbs 0 +fHsimWakeupId 0 +fHsimPassiveIbn 0 +fHsimBcOpt 1 +fHsimCertitude 0 +fHsimCertRapAutoTest 0 +fHsimRaceDetect 0 +fCheckTcCond 0 +fHsimScanOptRelaxDbg 0 +fHsimScanOptRelaxDbgDynamic 0 +fHsimScanOptRelaxDbgDynamicPli 0 +fHsimScanOptRelaxDbgDiag 0 +fHsimScanOptRelaxDbgDiagHi 0 +fHsimScanOptNoErrorOnPliAccess 0 +fHsimScanOptTiming 0 +fRelaxIbnSchedCheck 0 +fHsimScanOptNoDumpCombo 0 +fHsimScanOptPrintSwitchState 0 +fHsimScanOptSelectiveSwitchOn 0 +fHsimScanOptSingleSEPliOpt 1 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+fHsCgOptNoClockFusing 0 +fHsClkWheelLimit 50000 +fHsFgpSchedCgUcLoads 1 +fHsimAdvanceUdpInfer 0 +fFgpIbnSchedIntf 0 +fHsCgOptNewSelCheck 1 +fFgpReportUnsafeFuncs 0 +fHsCgOptUncPrlThreshold 4 +fHsimCosimGatesProp 0 +fHsSVNettypePerfOpt 0 +fHsCgOptHashFixMap 1 +fHsimLowPowerRetAnalysisInChild 0 +fRetainWithDelayedSig 0 +fHsimChargeDecay 0 +fHsimCongruencyConfigFile 0 +fHsimCongruencyLogFile 0 +fHsimCoverageEnabled 1 +fHsimCoverageOptions 279 +fHsimCoverageDir ./coverage/simv.vdb diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_hsim_fegate.db b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_hsim_fegate.db new file mode 100644 index 0000000..8be0045 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_hsim_fegate.db differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_hsim_lvl.db b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_hsim_lvl.db new file mode 100644 index 0000000..861898a Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_hsim_lvl.db differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_hsim_merge.db b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_hsim_merge.db new file mode 100644 index 0000000..3e9e254 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_hsim_merge.db differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_hsim_name.db b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_hsim_name.db new file mode 100644 index 0000000..2c3116f Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_hsim_name.db differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_hsim_uds.db b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_hsim_uds.db new file mode 100644 index 0000000..12a2348 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_hsim_uds.db @@ -0,0 +1,5 @@ +vcselab_misc_midd.db 57445 +vcselab_misc_mnmn.db 2715 +vcselab_misc_hsim_name.db 18117 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1349204 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_midd.db b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_midd.db new file mode 100644 index 0000000..3b682e9 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_midd.db differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_mnmn.db b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_mnmn.db new file mode 100644 index 0000000..d30eaa6 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_mnmn.db differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_partition.db b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_partition.db new file mode 100644 index 0000000..45c0dfb Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_partition.db differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_partitionDbg.db b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_partitionDbg.db new file mode 100644 index 0000000..410c022 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_partitionDbg.db differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_vcselabref.db b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_vcselabref.db new file mode 100644 index 0000000..f76dd23 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_vcselabref.db differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_vpdnodenums b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_vpdnodenums new file mode 100644 index 0000000..c7400e4 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/simv.daidir/vcselab_misc_vpdnodenums differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/ucli.key b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/ucli.key new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/.diagnose.oneSearch b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/.diagnose.oneSearch new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/ToNetlist.log b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/ToNetlist.log new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/compiler.log b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/compiler.log new file mode 100644 index 0000000..c9b958d --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/compiler.log @@ -0,0 +1,262 @@ +*design* DebussyLib (btIdent Verdi_O-2018.09-SP2) +Command arguments: + +define+verilog + -sverilog + -f filelist_vlg.f + ../../../../rtl/define/chip_define.v + ../../../../lib/tphn28hpcpgv18.v + ../../../../lib/tsdn28hpcpuhdb4096x128m4mw_170a_ffg0p99v0c.v + ../../../../rtl/io/iopad.v + ../../../../rtl/systemregfile/systemregfile.v + ../../../../rtl/dacif/dacif.v + ../../../../rtl/fifo/syn_fwft_fifo.v + ../../../../rtl/dac_regfile/dac_regfile.v + ../../../../rtl/lvds/ulink_rx.sv + ../../../../rtl/rstgen/rst_gen_unit.v + ../../../../rtl/rstgen/rst_sync.v + ../../../../rtl/comm/sirv_gnrl_xchecker.v + ../../../../rtl/comm/pulse_generator.sv + ../../../../rtl/comm/sirv_gnrl_dffs.v + ../../../../rtl/comm/syncer.v + ../../../../rtl/comm/ramp_gen.v + ../../../../rtl/memory/tsmc_dpram.v + ../../../../rtl/memory/sram_if.sv + ../../../../rtl/memory/sram_dmux.sv + ../../../../rtl/memory/dpram.v + ../../../../rtl/memory/bhv_spram.v + ../../../../rtl/memory/spram.v + ../../../../rtl/clk/clk_regfile.v + ../../../../rtl/awg/awg_top.sv + ../../../../rtl/awg/awg_ctrl.v + ../../../../rtl/dem/DEM_PhaseSync_4008.sv + ../../../../rtl/dem/DA4008_DEM_Parallel_PRBS_1CH.v + ../../../../rtl/dem/DA4008_DEM_Parallel_PRBS_64CH.v + ../../../../rtl/top/da4008_chip_top.sv + ../../../../rtl/top/digital_top.sv + ../../../../rtl/spi/spi_bus_decoder.sv + ../../../../rtl/spi/spi_slave.v + ../../../../rtl/spi/spi_pll.v + ../../../../rtl/spi/spi_sys.v + ../../../../model/clock_tb.v + ../../../../model/spi_if.sv + ../../../../model/clk_gen.v + ../../../../model/DEM_Reverse_64CH.v + ../../../../model/DEM_Reverse.v + ../../../../model/reset_tb.v + ../../../../model/DW_stream_sync.v + ../../../../model/DW_reset_sync.v + ../../../../model/DW_sync.v + ../../../../model/DW_pulse_sync.v + ../../../../sim/chip_top/TB.sv + ../../../../rtl/define/chip_undefine.v + -top + TB + + +*Error* `include file "../define/chip_define.v" cannot be read +"../../../../rtl/io/iopad.v", 35: + +*Error* `include file "../define/chip_undefine.v" cannot be read +"../../../../rtl/io/iopad.v", 187: + +*Error* `include file "../define/chip_define.v" cannot be read +"../../../../rtl/memory/dpram.v", 2: + +*Error* `include file "../define/chip_undefine.v" cannot be read +"../../../../rtl/memory/dpram.v", 90: + +*Error* `include file "../define/chip_define.v" cannot be read +"../../../../rtl/top/da4008_chip_top.sv", 3: + +*Error* `include file "../define/chip_undefine.v" cannot be read +"../../../../rtl/top/da4008_chip_top.sv", 212: + +*Error* `include file "../define/chip_define.v" cannot be read +"../../../../rtl/top/digital_top.sv", 34: + +*Error* `include file "../define/chip_undefine.v" cannot be read +"../../../../rtl/top/digital_top.sv", 528: + +*Error* `include file "../../rtl/define/chip_define.v" cannot be read +"../../../../sim/chip_top/TB.sv", 1: + +*Error* `include file "../../model/SPI_DRIVER.sv" cannot be read +"../../../../sim/chip_top/TB.sv", 3: + +*Error* `include file "../../model/LVDS_DRIVER.sv" cannot be read +"../../../../sim/chip_top/TB.sv", 5: + +*Error* failed to find symbol 'my_drv' +"../../../../sim/chip_top/TB.sv", 81: + +*Error* failed to find symbol 'lvds_drv' +"../../../../sim/chip_top/TB.sv", 82: +Highest level modules: +PCLAMP_G +PCLAMPC_H_G +PCLAMPC_V_G +PDB3A_H_G +PDB3A_V_G +PDB3AC_H_G +PDB3AC_V_G +PDDW04DGZ_H_G +PDDW04DGZ_V_G +PDDW04SDGZ_H_G +PDDW08DGZ_H_G +PDDW08DGZ_V_G +PDDW08SDGZ_H_G +PDDW08SDGZ_V_G +PDDW12DGZ_H_G +PDDW12DGZ_V_G +PDDW12SDGZ_H_G +PDDW12SDGZ_V_G +PDDW16DGZ_H_G +PDDW16DGZ_V_G +PDDW16SDGZ_H_G +PDDW16SDGZ_V_G +PDUW04DGZ_H_G +PDUW04DGZ_V_G +PDUW04SDGZ_H_G +PDUW08DGZ_H_G +PDUW08DGZ_V_G +PDUW08SDGZ_H_G +PDUW12DGZ_H_G +PDUW12DGZ_V_G +PDUW12SDGZ_H_G +PDUW12SDGZ_V_G +PDUW16DGZ_H_G +PDUW16DGZ_V_G +PDUW16SDGZ_H_G +PDUW16SDGZ_V_G +PDXOEDG_H_G +PDXOEDG_V_G +PENDCAP_G +PENDCAPA_G +PRCUT_G +PRCUTA_G +PRDW08DGZ_H_G +PRDW08DGZ_V_G +PRDW08SDGZ_H_G +PRDW08SDGZ_V_G +PRDW12DGZ_H_G +PRDW12DGZ_V_G +PRDW12SDGZ_H_G +PRDW12SDGZ_V_G +PRDW16DGZ_H_G +PRDW16DGZ_V_G +PRDW16SDGZ_H_G +PRDW16SDGZ_V_G +PRUW08DGZ_H_G +PRUW08DGZ_V_G +PRUW08SDGZ_H_G +PRUW08SDGZ_V_G +PRUW12DGZ_H_G +PRUW12DGZ_V_G +PRUW12SDGZ_H_G +PRUW12SDGZ_V_G +PRUW16DGZ_H_G +PRUW16DGZ_V_G +PRUW16SDGZ_H_G +PRUW16SDGZ_V_G +PVDD1A_H_G +PVDD1A_V_G +PVDD1AC_H_G +PVDD1AC_V_G +PVDD1ANA_H_G +PVDD1ANA_V_G +PVDD1DGZ_H_G +PVDD1DGZ_V_G +PVDD2ANA_H_G +PVDD2ANA_V_G +PVDD2DGZ_H_G +PVDD2DGZ_V_G +PVDD2POC_H_G +PVDD2POC_V_G +PVDD3A_H_G +PVDD3A_V_G +PVDD3AC_H_G +PVDD3AC_V_G +PVSS1A_H_G +PVSS1A_V_G +PVSS1AC_H_G +PVSS1AC_V_G +PVSS1ANA_H_G +PVSS1ANA_V_G +PVSS1DGZ_H_G +PVSS1DGZ_V_G +PVSS2A_H_G +PVSS2A_V_G +PVSS2AC_H_G +PVSS2AC_V_G +PVSS2ANA_H_G +PVSS2ANA_V_G +PVSS2DGZ_H_G +PVSS2DGZ_V_G +PVSS3A_H_G +PVSS3A_V_G +PVSS3AC_H_G +PVSS3AC_V_G +PVSS3DGZ_H_G +PVSS3DGZ_V_G +sirv_gnrl_xchecker +sirv_gnrl_dffl +sirv_gnrl_ltch +clk_gen +reset_tb +TB + + +*Error* failed to find identifier lvds_drv +"../../../../sim/chip_top/TB.sv", 89: + +*Error* failed to find identifier lvds_drv.new +"../../../../sim/chip_top/TB.sv", 89: + +*Error* failed to find identifier lvds_drv.drv_if +"../../../../sim/chip_top/TB.sv", 91: + +*Error* failed to find identifier my_drv +"../../../../sim/chip_top/TB.sv", 94: + +*Error* failed to find identifier my_drv.new +"../../../../sim/chip_top/TB.sv", 94: + +*Error* failed to find identifier my_drv.file_path +"../../../../sim/chip_top/TB.sv", 95: + +*Error* failed to find identifier my_drv.itf +"../../../../sim/chip_top/TB.sv", 96: + +*Error* failed to find identifier lvds_drv.train_count +"../../../../sim/chip_top/TB.sv", 102: + +*Error* failed to find identifier lvds_drv.send_training +"../../../../sim/chip_top/TB.sv", 103: + +*Error* failed to find identifier lvds_drv.scrambler_en +"../../../../sim/chip_top/TB.sv", 104: + +*Error* failed to find identifier lvds_drv.send_frame_from_file +"../../../../sim/chip_top/TB.sv", 105: + +*Error* failed to find identifier my_drv.do_drive +"../../../../sim/chip_top/TB.sv", 108: + +*Error* failed to find identifier my_drv.do_drive +"../../../../sim/chip_top/TB.sv", 120: + +*Error* failed to find identifier my_drv.do_drive +"../../../../sim/chip_top/TB.sv", 131: + +*Error* failed to find identifier lvds_bus.data +"../../../../sim/chip_top/TB.sv", 218: + +*Error* failed to find identifier lvds_bus.valid +"../../../../sim/chip_top/TB.sv", 219: + +*Error* failed to find identifier lvds_bus.clk +"../../../../sim/chip_top/TB.sv", 220: + +*Error* view lvds_if is not defined for instance lvds_bus +"../../../../sim/chip_top/TB.sv", 69: +Total 31 error(s), 0 warning(s) diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/exe.log b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/exe.log new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/novas.log b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/novas.log new file mode 100644 index 0000000..157ce72 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/novas.log @@ -0,0 +1,10 @@ +Verdi (R) + +Release Verdi_O-2018.09-SP2 for (RH Linux x86_64/64bit) -- Thu Feb 21 04:40:56 PDT 2019 + +Copyright (c) 1999 - 2019 Synopsys, Inc. +This software and the associated documentation are proprietary to Synopsys, Inc. +This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. +All other use, reproduction, or distribution of this software is strictly prohibited. + + diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/novas.rc b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/novas.rc new file mode 100644 index 0000000..e4560f4 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/novas.rc @@ -0,0 +1,1302 @@ +@verdi rc file Version 1.0 +[Library] +work = ./work +[Annotation] +3D_Active_Annotation = FALSE +[CommandSyntax.finsim] +InvokeCommand = +FullFileName = TRUE +Separator = . +SimPromptSign = ">" +HierNameLevel = 1 +RunContinue = "continue" +Finish = "quit" +UseAbsTime = FALSE +NextTime = "run 1" +NextNTime = "run ${SimBPTime}" +NextEvent = "run 1" +Reset = +ObjPosBreak = "break posedge ${SimBPObj}" +ObjNegBreak = "break negedge ${SimBPObj}" +ObjAnyBreak = "break change ${SimBPObj}" +ObjLevelBreak = +LineBreak = "breakline ${SimBPFile} ${SimBPLine}" +AbsTimeBreak = "break abstimeaf ${SimBPTime}" +RelTimeBreak = "break reltimeaf ${SimBPTime}" +EnableBP = "breakon ${SimBPId}" +DisableBP = "breakoff ${SimBPId}" +DeleteBP = "breakclr ${SimBPId}" +DeleteAllBP = "breakclr" +SimSetScope = "cd ${SimDmpObj}" +[CommandSyntax.ikos] +InvokeCommand = "setvar debussy true;elaborate -p ${SimTop} -s ${SimArch}; run until 0;fsdbInteractive; " +FullFileName = TRUE +NeedTimeUnit = TRUE +NormalizeTimeUnit = TRUE +Separator = / +HierNameLevel = 2 +RunContinue = "run" +Finish = "exit" +NextTime = "run ${SimBPTime} ${SimTimeUnit}" +NextNTime = "run for ${SimBPTime} ${SimTimeUnit}" +NextEvent = "step 1" +Reset = "reset" +ObjPosBreak = "stop if ${SimBPObj} = \"'1'\"" +ObjNegBreak = "stop if ${SimBPObj} = \"'0'\"" +ObjAnyBreak = +ObjLevelBreak = "stop if ${SimBPObj} = ${SimBPValue}" +LineBreak = "stop at ${SimBPFile}:${SimBPLine}" +AbsTimeBreak = +RelTimeBreak = +EnableBP = "enable ${SimBPId}" +DisableBP = "disable ${SimBPId}" +DeleteBP = "delete ${SimBPId}" +DeleteAllBP = "delete *" +[CommandSyntax.verisity] +InvokeCommand = +FullFileName = FALSE +Separator = . +SimPromptSign = "> " +HierNameLevel = 1 +RunContinue = "." +Finish = "$finish;" +NextTime = "$db_steptime(1);" +NextNTime = "$db_steptime(${SimBPTime});" +NextEvent = "$db_step;" +SimSetScope = "$scope(${SimDmpObj});" +Reset = "$reset;" +ObjPosBreak = "$db_breakonposedge(${SimBPObj});" +ObjNegBreak = "$db_breakonnegedge(${SimBPObj});" +ObjAnyBreak = "$db_breakwhen(${SimBPObj});" +ObjLevelBreak = "$db_breakwhen(${SimBPObj}, ${SimBPValue});" +LineBreak = "$db_breakatline(${SimBPLine}, ${SimBPScope}, \"${SimBPFile}\");" +AbsTimeBreak = "$db_breakbeforetime(${SimBPTime});" +RelTimeBreak = "$db_breakbeforetime(${SimBPTime});" +EnableBP = "$db_enablebreak(${SimBPId});" +DisableBP = "$db_disablebreak(${SimBPId});" +DeleteBP = "$db_deletebreak(${SimBPId});" +DeleteAllBP = "$db_deletebreak;" +FSDBInit = "$novasInteractive;" +FSDBDumpvars = "$novasDumpvars(0, ${SimDmpObj});" +FSDBDumpsingle = "$novasDumpsingle(${SimDmpObj});" +FSDBDumpvarsInFile = "$novasDumpvarsToFile(\"${SimDmpFile}\");" +FSDBDumpMem = "$novasDumpMemNow(${SimDmpObj}, ${SimDmpBegin}, ${SimDmpSize});" +[CoverageDetail] +cross_filter_limit = 1000 +branch_limit_vector_display = 50 +showgrid = TRUE +reuseFirst = TRUE +justify = TRUE +scrollbar_mode = per pane +test_combo_left_truncate = TRUE +instance_combo_left_truncate = TRUE +loop_navigation = TRUE +condSubExpr = 20 +tglMda = 1000 +linecoverable = 100000 +lineuncovered = 50000 +tglcoverable = 30000 +tgluncovered = 30000 +pendingMax = 1000 +show_full_more = FALSE +[CoverageHier] +showgrid = FALSE +[CoverageWeight] +Assert = 1 +Covergroup = 1 +Line = 1 +Condition = 1 +Toggle = 1 +FSM = 1 +Branch = 1 +[DesignTree] +IfShowModule = {TRUE, FALSE} +[DisabledMessages] +version = Verdi_O-2018.09-SP2 +[Editor] +editorName = TurboEditor +[Emacs] +EmacsFont = "Clean 14" +EmacsBG = white +EmacsFG = black +[Exclusion] +enableAsDefault = TRUE +saveAsDefault = TRUE +saveManually = TRUE +illegalBehavior = FALSE +DisplayExcludedItem = FALSE +adaptiveExclusion = TRUE +warningExcludeInstance = TRUE +favorite_exclude_annotation = "" +[FSM] +viewport = 65 336 387 479 +WndBk-FillColor = Gray3 +Background-FillColor = gray5 +prefKey_Link-FillColor = yellow4 +prefKey_Link-TextColor = black +Trap = red3 +Hilight = blue4 +Window = Gray3 +Selected = white +Trans. = green2 +State = black +Init. = black +SmartTips = TRUE +VectorFont = FALSE +StopAskBkgndColor = FALSE +ShowStateAction = FALSE +ShowTransAction = FALSE +ShowTransCond = FALSE +StateLable = NAME +StateValueRadix = ORIG +State-LineColor = ID_BLACK +State-LineWidth = 1 +State-FillColor = ID_BLUE2 +State-TextColor = ID_WHITE +Init_State-LineColor = ID_BLACK +Init_State-LineWidth = 2 +Init_State-FillColor = ID_YELLOW2 +Init_State-TextColor = ID_BLACK +Reset_State-LineColor = ID_BLACK +Reset_State-LineWidth = 2 +Reset_State-FillColor = ID_YELLOW7 +Reset_State-TextColor = ID_BLACK +Trap_State-LineColor = ID_RED2 +Trap_State-LineWidth = 2 +Trap_State-FillColor = ID_CYAN5 +Trap_State-TextColor = ID_RED2 +State_Action-LineColor = ID_BLACK +State_Action-LineWidth = 1 +State_Action-FillColor = ID_WHITE +State_Action-TextColor = ID_BLACK +Junction-LineColor = ID_BLACK +Junction-LineWidth = 1 +Junction-FillColor = ID_GREEN2 +Junction-TextColor = ID_BLACK +Connection-LineColor = ID_BLACK +Connection-LineWidth = 1 +Connection-FillColor = ID_GRAY5 +Connection-TextColor = ID_BLACK +prefKey_Port-LineColor = ID_BLACK +prefKey_Port-LineWidth = 1 +prefKey_Port-FillColor = ID_ORANGE6 +prefKey_Port-TextColor = ID_YELLOW2 +Transition-LineColor = ID_BLACK +Transition-LineWidth = 1 +Transition-FillColor = ID_WHITE +Transition-TextColor = ID_BLACK +Trans_Condition-LineColor = ID_BLACK +Trans_Condition-LineWidth = 1 +Trans_Condition-FillColor = ID_WHITE +Trans_Condition-TextColor = ID_ORANGE2 +Trans_Action-LineColor = ID_BLACK +Trans_Action-LineWidth = 1 +Trans_Action-FillColor = ID_WHITE +Trans_Action-TextColor = ID_GREEN2 +SelectedSet-LineColor = ID_RED2 +SelectedSet-LineWidth = 1 +SelectedSet-FillColor = ID_RED2 +SelectedSet-TextColor = ID_WHITE +StickSet-LineColor = ID_ORANGE5 +StickSet-LineWidth = 1 +StickSet-FillColor = ID_PURPLE6 +StickSet-TextColor = ID_BLACK +HilightSet-LineColor = ID_RED5 +HilightSet-LineWidth = 1 +HilightSet-FillColor = ID_RED7 +HilightSet-TextColor = ID_BLUE5 +ControlPoint-LineColor = ID_BLACK +ControlPoint-LineWidth = 1 +ControlPoint-FillColor = ID_WHITE +Bundle-LineColor = ID_BLACK +Bundle-LineWidth = 1 +Bundle-FillColor = ID_WHITE +Bundle-TextColor = ID_BLUE4 +QtBackground-FillColor = ID_GRAY6 +prefKey_Link-LineColor = ID_ORANGE2 +prefKey_Link-LineWidth = 1 +Selection-LineColor = ID_BLUE2 +Selection-LineWidth = 1 +[FSM_Dlg-Print] +Orientation = Landscape +[Form] +version = Verdi_O-2018.09-SP2 +[General] +autoSaveSession = FALSE +TclAutoSource = +cmd_enter_form = FALSE +SyncBrowserDir = TRUE +version = Verdi_O-2018.09-SP2 +SignalCaseInSensitive = FALSE +ShowWndCtntDuringResizing = FALSE +[GlobalProp] +ErrWindow_Font = Helvetica_M_R_12 +[Globals] +app_default_font = Bitstream Vera Sans,10,-1,5,50,0,0,0,0,0 +app_fixed_width_font = Courier,10,-1,5,50,0,0,0,0,0 +text_encoding = Unicode(utf8) +smart_resize = TRUE +smart_resize_child_limit = 2000 +tooltip_max_width = 200 +tooltip_max_height = 20 +tooltip_viewer_key = F3 +tooltip_display_time = 1000 +bookmark_name_length_limit = 12 +disable_tooltip = FALSE +auto_load_source = TRUE +max_array_size = 4096 +filter_when_typing = TRUE +filter_keep_children = TRUE +filter_syntax = Wildcards +filter_keystroke_interval = 800 +filter_case_sensitive = FALSE +filter_full_path = FALSE +load_detail_for_funcov = FALSE +sort_limit = 100000 +ignoreDBVersionChecking = FALSE +[HB] +ViewSchematic = FALSE +windowLayout = 0 0 804 500 182 214 804 148 +import_filter = *.v; *.vc; *.f +designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +import_filter_vhdl = *.vhd; *.vhdl; *.f +import_default_language = Verilog +import_filter_verilog = *.v; *.vc; *.f +simulation_file_type = *.fsdb;*.fsdb.gz;*.fsdb.bz2;*.ff;*.dump +PrefetchViewableAnnot = TRUE +[Hier] +filterTimeout = 1500 +[ImportLiberty] +SearchPriority = .lib++ +bSkipStateCell = False +bImportPowerInfo = False +bSkipFFCell = False +bScpecifyCellNameCase = False +bSpecifyPinNameCase = False +CellNameToCase = +PinNameToCase = +[Language] +EditWindow_Font = COURIER12 +Background = ID_WHITE +Comment = ID_GRAY4 +Keyword = ID_BLUE5 +UserKeyword = ID_GREEN2 +Text = ID_BLACK +SelText = ID_WHITE +SelBackground = ID_BLUE2 +[Library.Ikos] +pack = ./work.lib++ +vital = ./work.lib++ +work = ./work.lib++ +std = ${dls_std}.lib++ +ieee = ${dls_ieee}.lib++ +synopsys = ${dls_synopsys}.lib++ +silc = ${dls_silc}.lib++ +ikos = ${dls_ikos}.lib++ +novas = ${VOYAGER_LIB_VHDL}/${VOYAGER_MACHINE}/novas.lib++ +[MDT] +ART_RF_SP = spr[0-9]*bx[0-9]* +ART_RF_2P = dpr[0-9]*bx[0-9]* +ART_SRAM_SP = spm[0-9]*bx[0-9]* +ART_SRAM_DP = dpm[0-9]*bx[0-9]* +VIR_SRAM_SP = hdsd1_[0-9]*x[0-9]*cm4sw1 +VIR_SRAM_DP = hdsd2_[0-9]*x[0-9]*cm4sw1 +VIR_RF_SP = rfsd1_[0-9]*x[0-9]*cm2sw0 +VIR_RF_DP = rfsd2_[0-9]*x[0-9]*cm2sw1 +VIR_STAR_SRAM_SP = shsd1_[0-9]*x[0-9]*cm4sw0 +[NPExpanding] +functiongroups = FALSE +modules = FALSE +[NPFilter] +showAssertion = TRUE +showCoverGroup = TRUE +showProperty = TRUE +showSequence = TRUE +showDollarUnit = TRUE +[OldFontRC] +Wave_legend_window_font = -f COURIER12 -c ID_CYAN5 +Wave_value_window_font = -f COURIER12 -c ID_CYAN5 +Wave_curve_window_font = -f COURIER12 -c ID_CYAN5 +Wave_group_name_font = -f COURIER12 -c ID_GREEN5 +Wave_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_comment_string_font = -f COURIER12 -c ID_RED5 +HB_designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +Text_font = COURIER12 +nMemory_font = Fixed 14 +[OtherEditor] +cmd1 = "xterm -font 9x15 -fg black -bg gray -e" +name = "vi" +options = "+${CurLine} ${CurFullFileName}" +[Power] +PowerDownInstance = ID_GRAY1 +RetentionSignal = ID_YELLOW2 +IsolationSignal = ID_RED6 +LevelShiftedSignal = ID_GREEN6 +PowerSwitchObject = ID_ORANGE5 +AlwaysOnObject = ID_GREEN5 +PowerNet = ID_RED2 +GroundNet = ID_RED2 +SimulationOnly = ID_CYAN3 +SRSN/SPA = ID_CYAN3 +CNSSignal = ID_CYAN3 +RPTRSignal = ID_CYAN3 +AcknowledgeSignal = ID_CYAN3 +BoundaryPort = ID_CYAN3 +DisplayInstrumentedCell = TRUE +ShowCmdByFile = FALSE +ShowPstAnnot = FALSE +ShowIsoSymbol = TRUE +ExtractIsoSameNets = FALSE +AnnotateSignal = TRUE +HighlightPowerObject = TRUE +HighlightPowerDomain = TRUE +TraceThroughInstruLowPower = FALSE +BrightenPowerColorInSchematicWindow = FALSE +ShowAlias = FALSE +ShowVoltage = TRUE +MatchTreeNodesCaseInsensitive = FALSE +SearchHBNodeDynamically = FALSE +ContinueTracingSupplyOrLogicNet = FALSE +[Print] +PrinterName = lp +FileName = test.ps +PaperSize = A4 - 210x297 (mm) +ColorPrint = FALSE +[PropertyTools] +saveWaveformStat = TRUE +savePropStat = FALSE +savePropDtl = TRUE +[QtDialog] +QwUserAskDlg = 953,517,324,130 +[Relationship] +hideRecursiceNode = FALSE +[Session Cache] +2 = string (session file name) +3 = string (session file name) +4 = string (session file name) +5 = string (session file name) +1 = /home/shbyang/verdiLog/novas_autosave.ses +[Simulation] +scsPath = scsim +scsOption = +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +osciPath = gdb +osciOption = +vcsPath = simv +vcsOption = +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +speedsimPath = +speedsimOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +interactiveDebugging = {True, False} +KeepBreakPoints = False +ScsDebugAll = False +simType = {vcssv, xl, nc, vcs, mti, mti_vlog, vhnc, scs, mixnc} +thirdpartyIdx = -1 +iscCmdSep = FALSE +NoAppendOption = False +[SimulationPlus] +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +vcsPath = simv +vcsOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +speedsimPath = verilog +speedsimOption = +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +scsPath = scsim +scsOption = +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +vcs_svPath = simv +vcs_svOption = +simType = vcssv +thirdpartyIdx = -1 +interactiveDebugging = FALSE +KeepBreakPoints = FALSE +iscCmdSep = FALSE +ScsDebugAll = FALSE +NoAppendOption = FALSE +invokeSimPath = work +[SimulationPlus2] +eventDumpUnfinish = FALSE +[Source] +wordWrapOn = TRUE +viewReuse = TRUE +lineNumberOn = TRUE +warnOutdatedDlg = TRUE +showEncrypt = FALSE +loadInclude = FALSE +showColorForActive = FALSE +tabWidth = 8 +editor = vi +reload = Never +sync_active_to_source = TRUE +navigateAsColored = FALSE +navigateCovered = FALSE +navigateUncovered = TRUE +navigateExcluded = FALSE +not_ask_for_source_path = FALSE +expandMacroOn = TRUE +expandMacroInstancesThreshold = 10000 +[SourceVHDL] +vhSimType = ModelSim +ohSimType = VerilogXL +[TclShell] +nLineSize = 1024 +[Test] +verbose_progress = FALSE +[Text] +hdlTypeName = blue4 +hdlLibrary = blue4 +viewport = 396 392 445 487 +hdlOther = ID_BLACK +hdlComment = ID_GRAY1 +hdlKeyword = ID_BLUE5 +hdlEntity = ID_BLACK +hdlEntityInst = ID_BLACK +hdlSignal = ID_RED2 +hdlInSignal = ID_RED2 +hdlOutSignal = ID_RED2 +hdlInOutSignal = ID_RED2 +hdlOperator = ID_BLACK +hdlMinus = ID_BLACK +hdlSymbol = ID_BLACK +hdlString = ID_BLACK +hdlNumberBase = ID_BLACK +hdlNumber = ID_BLACK +hdlLiteral = ID_BLACK +hdlIdentifier = ID_BLACK +hdlSystemTask = ID_BLACK +hdlParameter = ID_BLACK +hdlIncFile = ID_BLACK +hdlDataFile = ID_BLACK +hdlCDSkipIf = ID_GRAY1 +hdlMacro = ID_BLACK +hdlMacroValue = ID_BLACK +hdlPlainText = ID_BLACK +hdlOvaId = ID_PURPLE2 +hdlPslId = ID_PURPLE2 +HvlEId = ID_BLACK +HvlVERAId = ID_BLACK +hdlEscSignal = ID_BLACK +hdlEscInSignal = ID_BLACK +hdlEscOutSignal = ID_BLACK +hdlEscInOutSignal = ID_BLACK +textBackgroundColor = ID_GRAY6 +textHiliteBK = ID_BLUE5 +textHiliteText = ID_WHITE +textTracedMark = ID_GREEN2 +textLineNo = ID_BLACK +textFoldedLineNo = ID_RED5 +textUserKeyword = ID_GREEN2 +textParaAnnotText = ID_BLACK +textFuncAnnotText = ID_BLUE2 +textAnnotText = ID_BLACK +textUserDefAnnotText = ID_BLACK +ComputedSignal = ID_PURPLE5 +textAnnotTextShadow = ID_WHITE +parenthesisBGColor = ID_YELLOW5 +codeInParenthesis = ID_CYAN5 +text3DLight = ID_WHITE +text3DShadow = ID_BLACK +textHvlDriver = ID_GREEN3 +textHvlLoad = ID_YELLOW3 +textHvlDriverLoad = ID_BLUE3 +irOutline = ID_RED2 +irDriver = ID_YELLOW5 +irLoad = ID_BLACK +irBookMark = ID_YELLOW2 +irIndicator = ID_WHITE +irBreakpoint = ID_GREEN5 +irCurLine = ID_BLUE5 +hdlVhEntity = ID_BLACK +hdlArchitecture = ID_BLACK +hdlPackage = ID_BLUE5 +hdlRefPackage = ID_BLUE5 +hdlAlias = ID_BLACK +hdlGeneric = ID_BLUE5 +specialAnnotShadow = ID_BLUE1 +hdlZeroInHead = ID_GREEN2 +hdlZeroInComment = ID_GREEN2 +hdlPslHead = ID_GRAY1 +hdlPslComment = ID_GRAY1 +hdlSynopsysHead = ID_GREEN2 +hdlSynopsysComment = ID_GREEN2 +pdmlIdentifier = ID_BLACK +pdmlCommand = ID_BLACK +pdmlMacro = ID_BLACK +font = COURIER12 +annotFont = Helvetica_M_R_10 +[Text.1] +viewport = 597 184 1017 706 45 +[TextPrinter] +Orientation = Landscape +Indicator = FALSE +LineNum = TRUE +FontSize = 7 +Column = 2 +Annotation = TRUE +[Texteditor] +TexteditorFont = "Clean 14" +TexteditorBG = white +TexteditorFG = black +[ThirdParty] +ThirdPartySimTool = verisity surefire ikos finsim +[TurboEditor] +autoBackup = TRUE +[UserButton.mixnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +Button8 = "FSDB Ver" "call fsdbVersion" +Button9 = "Dump On" "call fsdbDumpon" +Button10 = "Dump Off" "call fsdbDumpoff" +Button11 = "All Tasks" "call" +Button12 = "Dump Selected Instance" "call fsdbDumpvars 1 ${SelInst}" +[UserButton.mti] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.mti_vlog] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.nc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.scs] +Button1 = "Dump All Signals" "call fsdbDumpvars(0, \"${TopScope}\");\n" +Button2 = "Next 1000 Time" "run 1000 \n" +Button3 = "Next ? Time" "run ${Arg:Next Time} \n" +Button4 = "Run Step" "step\n" +Button5 = "Show Variables" "ls -v {${SelVars}}\n" +[UserButton.vhnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.xl] +Button13 = "Dump Off" "$fsdbDumpoff;\n" +Button12 = "Dump On" "$fsdbDumpon;\n" +Button11 = "Delete Focus" "$db_deletefocus(${treeSelScope});\n" +Button10 = "Set Focus" "$db_setfocus(${treeSelScope});\n" +Button9 = "Deposit Variable" "$deposit(${SelVar},${Arg:New Value});\n" +Button8 = "Release Variable" "release ${SelVar};\n" +Button7 = "Force Variable" "force ${SelVar} = ${Arg:New Value};\n" +Button6 = "Show Variables" "$showvars(${SelVars});\n" +Button5 = "Next ? Event" "$db_step(${Arg:Next Event});\n" +Button4 = "Next Event" "$db_step(1);\n" +Button3 = "Next ? Time" "#${Arg:Next Time} $stop;.\n" +Button2 = "Next 1000 Time" "#1000 $stop;.\n" +Button1 = "Dump All Signals" "$fsdbDumpvars;\n" +[VIA] +viaLogViewerDefaultRuleOneSearchForm = "share/VIA/Apps/PredefinedRules/Misc/Onesearch_rule.rc" +[VIA.oneSearch.preference] +DefaultDisplayTimeUnit = "1.000000ns" +DefaultLogTimeUnit = "1.000000ns" +[VIA.oneSearch.preference.vgifColumnSettingRC] +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0] +parRuleSets = "" +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column0] +name = Severity +width = 60 +visualIndex = 1 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column1] +name = Code +width = 60 +visualIndex = 2 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column2] +name = Type +width = 60 +visualIndex = 3 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column3] +name = Time +width = 60 +visualIndex = 0 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column4] +name = Message +width = 2000 +visualIndex = 4 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[Vi] +ViFont = "Clean 14" +ViBG = white +ViFG = black +[Wave] +ovaEventSuccessColor = -c ID_CYAN5 +ovaEventFailureColor = -c ID_RED5 +ovaBooleanSuccessColor = -c ID_CYAN5 +ovaBooleanFailureColor = -c ID_RED5 +ovaAssertSuccessColor = -c ID_GREEN5 +ovaAssertFailureColor = -c ID_RED5 +ovaForbidSuccessColor = -c ID_GREEN5 +SigGroupRuleFile = +DisplayFileName = FALSE +waveform_vertical_scroll_bar = TRUE +viewPort = 54 237 960 332 100 65 +signalSpacing = 5 +digitalSignalHeight = 15 +analogSignalHeight = 98 +commentSignalHeight = 98 +transactionSignalHeight = 98 +messageSignalHeight = 98 +minCompErrWidth = 4 +DragZoomTolerance = 4 +maxTransExpandedLayer = 10 +WaveMaxPoint = 512 +legendBackground = -c ID_BLACK +valueBackground = -c ID_BLACK +curveBackground = -c ID_BLACK +getSignalSignalList_BackgroundColor = -c ID_GRAY6 +glitchColor = -c ID_RED5 +cursor = -c ID_YELLOW5 -lw 1 -ls long_dashed +marker = -c ID_WHITE -lw 1 -ls dash_dot_l +usermarker = -c ID_GREEN5 -lw 1 -ls long_dashed +trace = -c ID_GRAY5 -lw 1 -ls long_dashed +grid = -c ID_WHITE -lw 1 -ls short_dashed +rulerBackground = -c ID_GRAY3 +rulerForeground = -c ID_YELLOW5 +busTextColor = -c ID_ORANGE8 +legendForeground = -c ID_CYAN5 +valueForeground = -c ID_CYAN5 +curveForeground = -c ID_CYAN5 +groupNameColor = -c ID_GREEN5 +commentStringColor = -c ID_RED5 +region(Active)Background = -c ID_YELLOW1 +region(NBA)Background = -c ID_RED1 +region(Re-Active)Background = -c ID_YELLOW3 +region(Re-NBA)Background = -c ID_RED3 +region(VHDL-Delta)Background = -c ID_ORANGE3 +region(Dump-Off)Background = -c ID_GRAY4 +High_Light = -c ID_GRAY2 +Input_Signal = -c ID_RED5 +Output_Signal = -c ID_GREEN5 +InOut_Signal = -c ID_BLUE5 +Net_Signal = -c ID_YELLOW5 +Register_Signal = -c ID_PURPLE5 +Verilog_Signal = -c ID_CYAN5 +VHDL_Signal = -c ID_ORANGE5 +SystemC_Signal = -c ID_BLUE7 +Dump_Off_Color = -c ID_BLUE2 +Compress_Bar_Color = -c ID_YELLOW4 +Vector_Dense_Block_Color = -c ID_ORANGE8 +Scalar_Dense_Block_Color = -c ID_GREEN6 +Analog_Dense_Block_Color = -c ID_PURPLE2 +Composite_Dense_Block_Color = -c ID_ORANGE5 +RPTR_Power_Off_Layer = -c ID_CYAN3 -stipple dots +DB_Power_Off_Layer = -c ID_BLUE4 -stipple dots +SPA_Driver_Power_Off_Layer = -c ID_ORANGE4 -stipple dots +SPA_Receiver_Power_Off_Layer = -c ID_GREEN5 -stipple dots +SRSN_Power_Off_Layer = -c ID_GREEN4 -stipple dots +Isolation_Power_Off_Layer = -c ID_RED4 -stipple dots +PD_Power_Off_Layer = -c ID_GRAY4 -stipple dots +Isolation_Layer = -c ID_RED4 -stipple vLine +Retention_Level_Trigger_Layer = -c ID_ORANGE1 -stipple fill_solid +Retention_Edge_Trigger_Layer = -c ID_YELLOW6 -stipple fill_solid +Driving_Power_Off_Layer = -c ID_YELLOW2 -stipple x +Toggle_Layer = -c ID_YELLOW4 -stipple slash +analogRealStyle = pwl +analogVoltageStyle = pwl +analogCurrentStyle = pwl +analogOthersStyle = pwl +busSignalLayer = -c ID_ORANGE8 +busZLayer = -c ID_ORANGE6 +busMixedLayer = -c ID_GREEN5 +busNotComputedLayer = -c ID_GRAY1 +busNoValueLayer = -c ID_BLUE2 +signalGridLayer = -c ID_WHITE +analogGridLayer = -c ID_GRAY6 +analogRulerLayer = -c ID_GRAY6 +keywordLayer = -c ID_RED5 +loadedLayer = -c ID_BLUE5 +loadingLayer = -c ID_BLACK +qdsCurMarkerLayer = -c ID_BLUE5 +qdsBrkMarkerLayer = -c ID_GREEN5 +qdsTrgMarkerLayer = -c ID_RED5 +arrowDefaultColor = -c ID_ORANGE6 +startNodeArrowColor = -c ID_WHITE +endNodeArrowColor = -c ID_YELLOW5 +propertyEventMatchColor = -c ID_GREEN5 +propertyEventNoMatchColor = -c ID_RED5 +propertyVacuousSuccessMatchColor = -c ID_YELLOW2 +propertyStatusBoundaryColor = -c ID_WHITE +propertyBooleanSuccessColor = -c ID_CYAN5 +propertyBooleanFailureColor = -c ID_RED5 +propertyAssertSuccessColor = -c ID_GREEN5 +propertyAssertFailureColor = -c ID_RED5 +propertyForbidSuccessColor = -c ID_GREEN5 +transactionForegroundColor = -c ID_YELLOW8 +transactionBackgroundColor = -c ID_BLACK +transactionHighLightColor = -c ID_CYAN6 +transactionRelationshipColor = -c ID_PURPLE6 +transactionErrorTypeColor = -c ID_RED5 +coverageFullyCoveredColor = -c ID_GREEN5 +coverageNoCoverageColor = -c ID_RED5 +coveragePartialCoverageColor = -c ID_YELLOW5 +coverageReferenceLineColor = -c ID_GRAY4 +messageForegroundColor = -c ID_YELLOW4 +messageBackgroundColor = -c ID_PURPLE1 +messageHighLightColor = -c ID_CYAN6 +messageInformationColor = -c ID_RED5 +ComputedAnnotColor = -c ID_PURPLE5 +fsvSecurityDataColor = -c ID_PURPLE3 +qdsAutoBusGroup = TRUE +qdsTimeStampMode = FALSE +qdsVbfBusOrderAscending = FALSE +openDumpFilter = *.fsdb;*.vf;*.jf +DumpFileFilter = *.vcd +RestoreSignalFilter = *.rc +SaveSignalFilter = *.rc +AddAliasFilter = *.alias;*.adb +CompareSignalFilter = *.err +ConvertFFFilter = *.vcd;*.out;*.tr0;*.xp;*.raw;*.wfm +Scroll_Ratio = 100 +Zoom_Ratio = 10 +EventSequence_SyncCursorTime = TRUE +EventSequence_Sorting = FALSE +EventSequence_RemoveGrid = FALSE +EventSequence_IsGridMode = FALSE +SetDefaultRadix_global = FALSE +DefaultRadix = Hex +SigSearchSignalMatchCase = FALSE +SigSearchSignalScopeOption = FALSE +SigSearchSignalSamenetInterface = FALSE +SigSearchSignalFullScope = FALSE +SigSearchSignalWithRegExp = FALSE +SigSearchDynamically = FALSE +SigDisplayBySelectionOrder = FALSE +SigDisplayRowMajor = FALSE +SigDragSelFollowColumn = FALSE +SigDisplayHierarchyBox = TRUE +SigDisplaySubscopeBox = TRUE +SigDisplayEmptyScope = TRUE +SigDisplaySignalNavigationBox = FALSE +SigDisplayFormBus = TRUE +SigShowSubProgram = TRUE +SigSearchScopeDynamically = TRUE +SigCollapseSubtreeNodes = FALSE +activeFileApplyToAnnotation = FALSE +GrpSelMode = TRUE +dispGridCount = FALSE +hierarchyName = FALSE +partial_level_name = FALSE +partial_level_head = 1 +partial_level_tail = 1 +displayMessageLabelOnly = TRUE +autoInsertDumpoffs = TRUE +displayMessageCallStack = FALSE +displayCallStackWithFullSections = TRUE +displayCallStackWithLastSection = FALSE +limitMessageMaxWidth = FALSE +messageMaxWidth = 50 +displayTransBySpecificColor = FALSE +fittedTransHeight = FALSE +snap = TRUE +gravitySnap = FALSE +displayLeadingZero = FALSE +displayGlitchs = FALSE +allfileTimeRange = FALSE +fixDelta = FALSE +displayCursorMarker = FALSE +autoUpdate = FALSE +restoreFromActiveFile = TRUE +restoreToEnd = FALSE +dispCompErr = TRUE +showMsgDes = TRUE +anaAutoFit = FALSE +anaAutoPattn = FALSE +anaAuto100VertFit = FALSE +displayDeltaY = FALSE +centerCursor = FALSE +denseBlockDrawing = TRUE +relativeFreqPrecision = 3 +showMarkerAbsolute = FALSE +showMarkerAdjacent = FALSE +showMarkerRelative = FALSE +showMarkerFrequency = FALSE +stickCursorMarkerOnWaveform = TRUE +keepMarkerAtEndTimeOfTransaction = FALSE +doubleClickToExpandTransaction = TRUE +expandTransactionAssociatedSignals = TRUE +expandTransactionAttributeSignals = FALSE +WaveExtendLastTick = TRUE +InOutSignal = FALSE +NetRegisterSignal = FALSE +VerilogVHDLSignal = FALSE +LabelMarker = TRUE +ResolveSymbolicLink = TRUE +signal_rc_abspath = TRUE +signal_rc_no_natural_bus_range = FALSE +save_scope_with_macro = FALSE +scope_to_save_with_macro +TipInSignalWin = FALSE +DisplayPackedSiganlInBitwiseManner = FALSE +DisplaySignalTypeAheadOfSignalName = TRUE ICON +TipInCurveWin = FALSE +MouseGesturesInCurveWin = TRUE +DisplayLSBsFirst = FALSE +PaintSpecificColorPattern = TRUE +ModuleName = TRUE +form_all_memory_signal = FALSE +formBusSignalFromPartSelects = FALSE +read_value_change_on_demand_for_drawing = FALSE +load_scopes_on_demand = on 5 +TransitionMode = TRUE +DisplayRadix = FALSE +SchemaX = FALSE +Hilight = TRUE +UseBeforeValue = FALSE +DisplayFileNameAheadOfSignalName = FALSE +DisplayFileNumberAheadOfSignalName = FALSE +DisplayValueSpace = TRUE +FitAnaByBusSize = FALSE +displayTransactionAttributeName = FALSE +expandOverlappedTrans = FALSE +dispSamplePointForAttrSig = TRUE +dispClassName = TRUE +ReloadActiveFileOnly = FALSE +NormalizeEVCD = FALSE +OverwriteAliasWithRC = TRUE +overlay_added_analog_signals = FALSE +case_insensitive = FALSE +vhdlVariableCalculate = TRUE +showError = TRUE +signal_vertical_scroll_bar = TRUE +showPortNameForDroppedInstance = FALSE +truncateFilePathInTitleBar = TRUE +filterPropVacuousSuccess = FALSE +includeLocalSignals = FALSE +encloseSignalsByGroup = TRUE +resaveSignals = TRUE +adjustBusPrefix = adjustBus_ +adjustBusBits = 1 +adjustBusSettings = 69889 +maskPowerOff = TRUE +maskIsolation = TRUE +maskRetention = TRUE +maskDrivingPowerOff = TRUE +maskToggle = TRUE +autoBackupSignals = off 5 "\"/home/shbyang/verdiLog\"" "\"novas_autosave_sig\"" +signal_rc_attribute = 65535 +signal_rc_alias_attribute = 0 +ConvertAttr1 = -inc FALSE +ConvertAttr2 = -hier FALSE +ConvertAttr3 = -ucase FALSE +ConvertAttr4 = -lcase FALSE +ConvertAttr5 = -org FALSE +ConvertAttr6 = -mem 24 +ConvertAttr7 = -deli . +ConvertAttr8 = -hier_scope FALSE +ConvertAttr9 = -inst_array FALSE +ConvertAttr10 = -vhdlnaming FALSE +ConvertAttr11 = -orgScope FALSE +analogFmtPrecision = Automatic 2 +confirmOverwrite = TRUE +confirmExit = TRUE +confirmGetAll = TRUE +printTimeRange = TRUE 0.000000 0.000000 0.000000 +printPageRange = TRUE 1 1 +printOption = 0 +printBasic = 1 0 0 FALSE FALSE +printDest = -printer {} +printSignature = {%f %h %t} {} +curveWindow_Drag&Drop_Mode = TRUE +hspiceIncOpenMode = TRUE +pcSelectMode = TRUE +hierarchyDelimiter = / +open_file_time_range = FALSE +open_file_dir +open_rc_file_dir +value_window_aligment = Right +signal_window_alignment = Auto +ShowDeltaTime = TRUE +legend_window_font = -f COURIER12 -c ID_CYAN5 +value_window_font = -f COURIER12 -c ID_CYAN5 +curve_window_font = -f COURIER12 -c ID_CYAN5 +group_name_font = -f COURIER12 -c ID_GREEN5 +ruler_value_font = -f COURIER12 -c ID_CYAN5 +analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +comment_string_font = -f COURIER12 -c ID_RED5 +getsignal_form_font = -f COURIER12 +SigsCheckNum = on 1000 +filter_synthesized_net = off n +filterOutNet = on +filter_synthesized_instance = off +filterOutInstance = on +showGroupTree = TRUE +hierGroupDelim = / +MsgSeverityColor = {y \"Severity\"==\"1\" ID_RED5} {y \"Severity\"==\"2\" ID_RED6} {y \"Severity\"==\"3\" ID_RED7} {y \"Severity\"==\"4\" ID_RED8} {y \"Severity\"==\"5\" ID_ORANGE5} {y \"Severity\"==\"6\" ID_ORANGE6} {y \"Severity\"==\"7\" ID_ORANGE7} {y \"Severity\"==\"8\" \ +ID_GREEN7} {y \"Severity\"==\"9\" ID_GREEN6} {y \"Severity\"==\"10\" ID_GREEN5} +AutoApplySeverityColor = TRUE +AutoAdjustMsgWidthByLabel = off +verilogStrengthDispType = type1 +waveDblClkActiveTrace = on +autoConnectTBrowser = FALSE +connectTBrowserInContainer = TRUE +SEQShowComparisonIcon = TRUE +SEQAddDriverLoadInSameGroup = TRUE +autoSyncCursorMarker = FALSE +autoSyncHorizontalRange = FALSE +autoSyncVerticalScroll = FALSE +[cov_hier_name_column] +justify = TRUE +[coverageColors] +sou_uncov = TRUE +sou_pc = TRUE +sou_cov = TRUE +sou_exuncov = TRUE +sou_excov = TRUE +sou_unreach = TRUE +sou_unreachcon = TRUE +sou_fillColor_uncov = red +sou_fillColor_pc = yellow +sou_fillColor_cov = green3 +sou_fillColor_exuncov = grey +sou_fillColor_excov = #3C9371 +sou_fillColor_unreach = grey +sou_fillColor_unreachcon = orange +numberOfBins = 6 +rangeMin_0 = 0 +rangeMax_0 = 20 +fillColor_0 = #FF6464 +rangeMin_1 = 20 +rangeMax_1 = 40 +fillColor_1 = #FF9999 +rangeMin_2 = 40 +rangeMax_2 = 60 +fillColor_2 = #FF8040 +rangeMin_3 = 60 +rangeMax_3 = 80 +fillColor_3 = #FFFF99 +rangeMin_4 = 80 +rangeMax_4 = 100 +fillColor_4 = #99FF99 +rangeMin_5 = 100 +rangeMax_5 = 100 +fillColor_5 = #64FF64 +[coveragesetting] +assertTopoMode = FALSE +urgAppendOptions = +group_instance_new_format_name = TRUE +showvalue = FALSE +computeGroupsScoreByRatio = FALSE +computeGroupsScoreByInst = FALSE +showConditionId = FALSE +showfullhier = FALSE +nameLeftAlignment = TRUE +showAllInfoInTooltips = FALSE +copyItemHvpName = TRUE +ignoreGroupWeight = FALSE +absTestName = FALSE +HvpMergeTool = +ShowMergeMenuItem = FALSE +fsmScoreMode = transition +[eco] +IsFreezeSilicon = FALSE +cellQuantityManagement = FALSE +ManageMode = INSTANCE_NAME +SpareCellsPinsManagement = TRUE +LogCommitReport = FALSE +InputPinStatus = 1 +OutputPinStatus = 2 +NameRule = +RevisedComponentColor = ID_BLUE5 +SpareCellColor = ID_RED5 +UserName = shbyang +CommentFormat = Novas ECO updated by ${UserName} ${Date} ${Time} +PrefixN = eco_n +PrefixP = eco_p +PrefixI = eco_i +DefaultTieUpNet = 1'b1 +DefaultTieDownNet = 1'b0 +MultipleInstantiations = TRUE +KeepClockPinConnection = FALSE +KeepAsyncResetPinConnection = FALSE +ScriptFileModeType = 1 +MagmaScriptPower = VDD +MagmaScriptGround = GND +ShowModeMsg = TRUE +AstroScriptPower = VDD +AstroScriptGround = VSS +ClearFloatingPorts = FALSE +[eco_connection] +Port/NetIsUnique = TRUE +SerialNet = 0 +SerialPort = 0 +SerialInst = 0 +[finsim] +TPLanguage = Verilog +TPName = Super-FinSim +TPPath = TOP.sim +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[hvpsetting] +importExcelXMLOptions = +use_test_loca_as_source = FALSE +autoTurnOffHideMeetGoalInit = FALSE +autoTurnOffHideMeetGoal = TRUE +autoTurnOffModifierInit = FALSE +autoTurnOffModifier = TRUE +enableNumbering = TRUE +autoSaveCheck = TRUE +autoSaveTime = 5 +ShowMissingScore = TRUE +enableFeatureId = FALSE +enable_HVP_FEAT_ID = FALSE +enableMeasureConcealment = FALSE +HvpCloneHierShowMsgAgain = 1 +HvpCloneHierType = tree +HvpCloneHierMetrics = Line,Cond,FSM,Toggle,Branch,Assert +autoRecalPlanAfterLoadingCovDBUserDataPlan = false +warnMeAutoRecalPlanAfterLoadingCovDBUserDataPlan = true +autoRecalExclWithPlan = false +warnMeAutoRecalExclWithPlan = true +autoRecalPlanWithExcl = false +warnMeAutoRecalPlanWithExcl = true +warnPopupWarnWhenMultiFilters = true +warnPopupWarnIfHvpReadOnly = true +unmappedObjsReportLevel = def_var_inst +unmappedObjsReportInst = true +unmappedObjsNumOfObjs = High +[ikos] +TPLanguage = VHDL +TPName = Voyager +TPPath = vsh +TPOption = -X +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[imp] +options = NULL +libPath = NULL +libDir = NULL +[nCompare] +ErrorViewport = 80 180 800 550 +EditorViewport = 409 287 676 475 +EditorHeightWidth = 802 380 +WaveCommand = "novas" +WaveArgs = "-nWave" +[nCompare.Wnd0] +ViewByHier = FALSE +[nMemory] +dispMode = ADDR_HINT +addrColWidth = 120 +valueColWidth = 100 +showCellBitRangeWithAddr = TRUE +wordsShownInOneRow = 8 +syncCursorTime = FALSE +fixCellColumnWidth = FALSE +font = Courier 12 +[planColors] +plan_fillColor_inactive = lightGray +plan_fillColor_warning = orange +plan_fillColor_error = red +plan_fillColor_invalid = #F0DCDB +plan_fillColor_subplan = lightGray +[schematics] +viewport = 178 262 638 516 +schBackgroundColor = black lineSolid +schBackgroundColor_qt = #000000 qt_solidLine 1 +schBodyColor = orange6 lineSolid +schBodyColor_qt = #ffb973 qt_solidLine 1 +schAsmBodyColor = blue7 lineSolid +schAsmBodyColor_qt = #a5a5ff qt_solidLine 1 +schPortColor = orange6 lineSolid +schPortColor_qt = #ffb973 qt_solidLine 1 +schCellNameColor = Gray6 lineSolid +schCellNameColor_qt = #e0e0e0 qt_solidLine 1 +schCLKNetColor = red6 lineSolid +schCLKNetColor_qt = #ff7373 qt_solidLine 1 +schPWRNetColor = red4 lineSolid +schPWRNetColor_qt = #ff0101 qt_solidLine 1 +schGNDNetColor = cyan4 lineSolid +schGNDNetColor_qt = #01ffff qt_solidLine 1 +schSIGNetColor = green8 lineSolid +schSIGNetColor_qt = #cdffcd qt_solidLine 1 +schTraceColor = yellow4 lineSolid +schTraceColor_qt = #ffff01 qt_solidLine 2 +schBackAnnotateColor = white lineSolid +schBackAnnotateColor_qt = #ffffff qt_solidLine 1 +schValue0 = yellow4 lineSolid +schValue0_qt = #ffff01 qt_solidLine 1 +schValue1 = green3 lineSolid +schValue1_qt = #008000 qt_solidLine 1 +schValueX = red4 lineSolid +schValueX_qt = #ff0101 qt_solidLine 1 +schValueZ = purple7 lineSolid +schValueZ_qt = #ffcdff qt_solidLine 1 +dimColor = cyan2 lineSolid +dimColor_qt = #008080 qt_solidLine 1 +schPreSelColor = green4 lineDash +schPreSelColor_qt = #01ff01 qt_dashLine 2 +schSIGBusNetColor = green8 lineSolid +schSIGBusNetColor_qt = #cdffcd qt_solidLine +schGNDBusNetColor = cyan4 lineSolid +schGNDBusNetColor_qt = #01ffff qt_solidLine +schPWRBusNetColor = red4 lineSolid +schPWRBusNetColor_qt = #ff0101 qt_solidLine +schCLKBusNetColor = red6 lineSolid +schCLKBusNetColor_qt = #ff7373 qt_solidLine +schEdgeSensitiveColor = orange6 lineSolid +schEdgeSensitiveColor_qt = #ffb973 qt_solidLine +schAnnotColor = cyan4 lineSolid +schAnnotColor_qt = #01ffff qt_solidLine +schInstNameColor = orange6 lineSolid +schInstNameColor_qt = #ffb973 qt_solidLine +schPortNameColor = cyan4 lineSolid +schPortNameColor_qt = #01ffff qt_solidLine +schAsmLatchColor = cyan4 lineSolid +schAsmLatchColor_qt = #01ffff qt_solidLine +schAsmRegColor = cyan4 lineSolid +schAsmRegColor_qt = #01ffff qt_solidLine +schAsmTriColor = cyan4 lineSolid +schAsmTriColor_qt = #01ffff qt_solidLine +pre_select = True +ShowPassThroughNet = False +ComputedAnnotColor = ID_PURPLE5 +[schematics_print] +Signature = FALSE +DesignName = PCU +DesignerName = bai +SignatureLocation = LowerRight +MultiPage = TRUE +AutoSliver = FALSE +[sourceColors] +BackgroundActive = gray88 +BackgroundInactive = lightgray +InactiveCode = dimgray +Selection = darkblue +Standard = black +Keyword = blue +Comment = gray25 +Number = black +String = black +Identifier = darkred +Inline = green +colorIdentifier = green +Value = darkgreen +MacroBackground = white +Missing = #400040 +[specColors] +top_plan_linked = #ADFFA6 +top_plan_ignore = #D3D3D3 +top_plan_todo = #EECBAD +sub_plan_ignore = #919191 +sub_plan_todo = #EFAFAF +sub_plan_linked = darkorange +[spec_link_setting] +use_spline = true +goto_section = false +exclude_ignore = true +truncate_abstract = false +abstract_length = 999 +compare_strategy = 2 +auto_apply_margin = FALSE +margin_top = 0.80 +margin_bottom = 0.80 +margin_left = 0.50 +margin_right = 0.50 +margin_unit = inches +[spiceDebug] +ThroughNet = ID_YELLOW5 +InstrumentSig = ID_GREEN5 +InterfaceElement = ID_GREEN5 +Run-timeInterfaceElement = ID_BLUE5 +HighlightThroughNet = TRUE +HighlightInterfaceElement = TRUE +HighlightRuntimeInterfaceElement = TRUE +HighlightSameNet = TRUE +[surefire] +TPLanguage = Verilog +TPName = SureFire +TPPath = verilog +TPOption = +AddImportArgument = TRUE +LineBreakWithScope = TRUE +StopAfterCompileOption = -tcl +[turboSchema_Printer_Options] +Orientation = Landscape +[turbo_library] +bdb_load_scope = +[vdCovFilteringSearchesStrings] +keepLastUsedFiltersMaxNum = 10 +[verisity] +TPLanguage = Verilog +TPName = "Verisity SpeXsim" +TPPath = vlg +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = TRUE +StopAfterCompileOption = -s +[wave.0] +viewPort = 50 214 960 332 100 65 +[wave.1] +viewPort = 127 219 960 332 100 65 +[wave.2] +viewPort = 38 314 686 205 100 65 +[wave.3] +viewPort = 63 63 700 400 65 41 +[wave.4] +viewPort = 84 84 700 400 65 41 +[wave.5] +viewPort = 92 105 700 400 65 41 +[wave.6] +viewPort = 0 0 700 400 65 41 +[wave.7] +viewPort = 21 21 700 400 65 41 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/novas_autosave.ses b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/novas_autosave.ses new file mode 100644 index 0000000..490ab1a --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/novas_autosave.ses @@ -0,0 +1,82 @@ +@verdi rc file Version 1.0 +[General] +saveDB = TRUE +relativePath = FALSE +saveSingleView = FALSE +saveNWaveWinId = +VerdiVersion = Verdi_O-2018.09-SP2 +[KeyNote] +Line1 = Automatic Backup 0 +Line2 = Save Open Database Information: Yes +Line3 = Path Option: Absolute Paths +Line4 = Windows Option: All Windows +[TestBench] +ConstrViewShow = 0 +InherViewShow = 0 +FSDBMsgShow = 0 +AnnotationShow = 0 +Console = FALSE +powerDumped = 0 +[hb] +postSimFile = /home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdplus_000.fsdb +syncTime = 41008932 +viewport = 0 27 1920 977 0 0 256 1015 +activeNode = "TB" +activeScope = "TB" +activeFile = "../../../../sim/chip_top/TB.sv" +interactiveMode = False +viewType = Source +simulatorMode = False +sourceBeginLine = 312 +baMode = False +srcLineNum = True +AutoWrap = True +IdentifyFalseLogic = False +syncSignal = False +traceMode = Hierarchical +showTraceInSchema = True +paMode = False +funcMode = False +powerAwareAnnot = True +amsAnnot = True +traceCrossHier = True +DnDtraceCrossHierOnly = True +traceIncTopPort = False +leadingZero = False +signalPane = False +Scope1 = "TB" +multipleSelection = 1 316 6 0 0 +sdfCheckUndef = FALSE +simFlow = FALSE +[hb.design] +importCmd = "-sverilog" "-f" "filelist_vlg.f" "-top" "TB" +invokeDir = /home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/flattop +[hb.sourceTab.1] +scope = TB +File = /home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/TB.sv +Line = 313 +[nMemoryManager] +WaveformFile = /home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdplus_000.fsdb +UserActionNum = 0 +nMemWindowNum = 0 +[wave.0] +viewPort = 0 27 1920 392 100 65 +primaryWindow = TRUE +SessionFile = /home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/novas_autosave.ses.wave.0 +displayGrid = FALSE +hierarchicalName = FALSE +snap = TRUE +displayLeadingZeros = FALSE +fixDelta = FALSE +displayCursorMarker = FALSE +autoUpdate = FALSE +highlightGlitchs = FALSE +waveformSyncCursorMarker = FALSE +waveformSyncHorizontalRange = FALSE +waveformSyncVerticalscroll = FALSE +displayErrors = TRUE +displayMsgSymbols = TRUE +showMsgDescriptions = TRUE +autoFit = FALSE +displayDeltaY = FALSE +centerCursor = FALSE diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/novas_autosave.ses.config b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/novas_autosave.ses.config new file mode 100644 index 0000000..e9c08bf --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/novas_autosave.ses.config @@ -0,0 +1,55 @@ +[qBaseWindowStateGroup] +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\Verdi=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\nWave=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\hdlHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\hdlSrc=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\messageWindow=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\svtbHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\OneSearch=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1=7 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_0=widgetDock_hdlHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_1=widgetDock_messageWindow_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_2=widgetDock_hdlSrc_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_3=widgetDock_signalList_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_4=widgetDock_svtbHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_5=windowDock_OneSearch_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_6=windowDock_nWave_1 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_encode_to_relative_window_id_name=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlHier_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlHier_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlHier_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlHier_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_messageWindow_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_messageWindow_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_messageWindow_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_messageWindow_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_signalList_1\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_svtbHier_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_svtbHier_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_svtbHier_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_svtbHier_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_OneSearch_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_OneSearch_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_OneSearch_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_OneSearch_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_OneSearch_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\ProductVersion=201809 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+Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\size=@Size(1920 977) +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_width=1920 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_height=977 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/novas_autosave.ses.png b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/novas_autosave.ses.png new file mode 100644 index 0000000..f857478 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/novas_autosave.ses.png differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/novas_autosave.ses.wave.0 b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/novas_autosave.ses.wave.0 new file mode 100644 index 0000000..4d06552 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/novas_autosave.ses.wave.0 @@ -0,0 +1,56 @@ +Magic 271485 +Revision Verdi_O-2018.09-SP2 + +; Window Layout +viewPort 0 27 1920 392 100 65 + +; File list: +; openDirFile [-d delimiter] [-s time_offset] [-rf auto_bus_rule_file] path_name file_name +openDirFile -d / "" "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdplus_000.fsdb" + +; file time scale: +; fileTimeScale ### s|ms|us|ns|ps + +; signal spacing: +signalSpacing 5 + +; windowTimeUnit is used for zoom, cursor & marker +; waveform viewport range +zoom 36647693.257720 45370269.704986 +cursor 41008932.000000 +marker 41008956.000000 + +; user define markers +; userMarker time_pos marker_name color linestyle +; visible top row signal index +top 0 +; marker line index +markerPos 2 + +; event list +; addEvent event_name event_expression +; curEvent event_name + + + +COMPLEX_EVENT_BEGIN + + +COMPLEX_EVENT_END + + + +; toolbar current search type +; curSTATUS search_type +curSTATUS ByChange + + +addGroup "G1" +activeDirFile "" "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdplus_000.fsdb" +addSignal -h 15 -UNSIGNED -HEX /TB/cs_wave[7:0] +addSignal -h 15 -holdScope clk_40g +addGroup "G2" + +; getSignalForm Scope Hierarchy Status +; active file of getSignalForm + diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/pes.bat b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/pes.bat new file mode 100644 index 0000000..7c6e4ac --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/pes.bat @@ -0,0 +1,3 @@ +where +detach +quit diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/turbo.log b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/turbo.log new file mode 100644 index 0000000..d116551 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/turbo.log @@ -0,0 +1,3 @@ +Command Line: /opt/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/bin/Novas -sverilog -f filelist_vlg.f -top TB -ssf verdplus_000.fsdb -nologo +uname(Linux cryo1 3.10.0-1160.92.1.el7.x86_64 #1 SMP Tue Jun 20 11:48:01 UTC 2023 x86_64) +au time 579.359709 17.293455 7.676470 delta 411447296 411447296 total 836534272 836534272 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/verdi.cmd b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/verdi.cmd new file mode 100644 index 0000000..9ffe241 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/verdi.cmd @@ -0,0 +1,319 @@ +sidCmdLineBehaviorAnalysisOpt -incr -clockSkew 0 -loopUnroll 0 -bboxEmptyModule 0 -cellModel 0 -bboxIgnoreProtected 0 +debImport "-sverilog" "-f" "filelist_vlg.f" "-top" "TB" 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a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/verdi_perf_err.log b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdiLog/verdi_perf_err.log new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdplus.log b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdplus.log new file mode 100644 index 0000000..dbf7adf --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdplus.log @@ -0,0 +1,2 @@ +File Name Time +./verdplus_000.fsdb 0 to 198,910,080 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdplus.vf b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdplus.vf new file mode 100644 index 0000000..1ef6a51 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdplus.vf @@ -0,0 +1,7 @@ +@FSDB rc file Version 1.0 +[VRTL_FILE_HEADER] +# !! DON'T EDIT [VRTL_FILE_HEADER] SESSION !! +Version = 1 +[VRTL_FILE_SOURCE] +FileType = switch +File1 = ./verdplus_000.fsdb diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdplus_000.fsdb b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdplus_000.fsdb new file mode 100644 index 0000000..8d52e1d Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/flattop/verdplus_000.fsdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/Makefile b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/Makefile new file mode 100644 index 0000000..b1f80ac --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/Makefile @@ -0,0 +1,72 @@ + +WAVE ?= 0 + +SIM = RTL + +folder = simv + +ifeq ($(WAVE),1) + WAVE_OPTS = -debug_access+all -debug_region+cell+encrypt -P $(NOVAS_HOME)/share/PLI/VCS/linux64/novas_new_dumper.tab $(NOVAS_HOME)/share/PLI/VCS/linux64/pli.a +define+DUMP_FSDB + WAVE_SIM_OPTS = -fsdbDumpfile=sim.fsdb + else + WAVE_OPTS = -debug_access+pp +endif + +ifeq ($(SIM),PostPr) +VCS = vcs -full64 -sverilog -Mupdate +lint=TFIPC-L +v2k +warn=noSDFCOM_IWSBA,noNTCDNC -notice +mindelays +tchk+edge+warn +neg_tchk -negdelay +overlap +sdfverbose -sdfretain +optconfigfile+notimingcheck.cfg -override_timescale=1ns/1ps -debug_access+all $(WAVE_OPTS) -lca -q -l compile.log -cm line+cond+fsm+tgl+branch -cm_dir ./coverage/simv.vdb |tee +else +VCS = vcs -full64 -j8 -sverilog +lint=TFIPC-L +v2k $(WAVE_OPTS) -lca -q -timescale=1ns/1ps +nospecify -l compile.log -cm line+cond+fsm+tgl+branch -cm_dir ./coverage/simv.vdb +endif + +ifeq ($(SIM),PostPr) + post_dir = ./data_PostPr +else + post_dir = ./data_PostSyn +endif + + +ifeq ($(SIM),PostSyn) +FileList = filelist_syn.f +else + ifeq ($(SIM),PostPr) + FileList = filelist_pr.f + else + FileList = filelist_vlg.f + endif +endif + +SIMV = ./simv sync:busywait -Xdprof=timeline $(WAVE_SIM_OPTS) -l |tee sim.log + +all:comp run + +comp: + ${VCS} -f $(FileList) +incdir+./../../rtl/define +incdir+./../../rtl/qubitmcu +incdir+./../../model + +run: + ${SIMV} + +dbg: + verdi -sverilog -f $(FileList) -top TB -ssf *.fsdb -nologo & + +clean: + rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *fsdb* *.dat *.daidir *.vdb *~ + +compare: + ./compare_files.csh ${post_dir} ./data_RTL ./compare.txt + +regress: + ./regress.csh $(SIM) + +rmwork: + rm -rf ./work* + +rmdata: + rm -rf ./data* +cov: + verdi -cov -covdir coverage/merged.vdb & +cov_d: + dve -full64 -covdir coverage/*.vdb & +merge: + urg -full64 -dbname coverage/merged.vdb -flex_merge union -dir coverage/simv.vdb -parallel -maxjobs 64& +merge_i: + urg -full64 -flex_merge union -dir coverage/merged.vdb -dir coverage/$(folder) -dbname coverage/merged.vdb -parallel -maxjobs 64& diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/cm.log b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/cm.log new file mode 100644 index 0000000..1afd018 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/cm.log @@ -0,0 +1,1428 @@ +: // Synopsys, Inc. +: // + +: // Generated by: VCS Coverage Metrics O-2018.09-SP2_Full64 +: // User: shbyang +: // Date: Fri Mar 13 16:24:06 2026 + +: Disabling fsm sequence coverage for module \$unit::../../lib/tphn28hpcpgv18.v::../../lib/tsdn28hpcpuhdb4096x128m4mw_170a_ffg0p99v0c.v...@348857874 ... +: Disabling fsm sequence coverage for module PCLAMP_G ... +: Disabling fsm sequence coverage for module PCLAMPC_H_G ... +: Disabling fsm sequence coverage for module PCLAMPC_V_G ... +: Disabling fsm sequence coverage for module PDB3A_H_G ... +: Disabling fsm sequence coverage for module PDB3A_V_G ... +: Disabling fsm sequence coverage for module PDB3AC_H_G ... +: Disabling fsm sequence coverage for module PDB3AC_V_G ... +: Disabling fsm sequence coverage for module PDDW04DGZ_H_G ... +: Disabling fsm sequence coverage for module PDDW04DGZ_V_G ... +: Disabling fsm sequence coverage for module PDDW04SDGZ_H_G ... +: Disabling fsm sequence coverage for module PDDW08DGZ_H_G ... +: Disabling fsm sequence coverage for module PDDW08DGZ_V_G ... +: Disabling fsm sequence coverage for module PDDW08SDGZ_H_G ... +: Disabling fsm sequence coverage for module PDDW08SDGZ_V_G ... +: Disabling fsm sequence coverage for module PDDW12DGZ_H_G ... +: Disabling fsm sequence coverage for module PDDW12DGZ_V_G ... +: Disabling fsm sequence coverage for module PDDW12SDGZ_H_G ... +: Disabling fsm sequence coverage for module PDDW12SDGZ_V_G ... +: Disabling fsm sequence coverage for module PDDW16DGZ_H_G ... +: Disabling fsm sequence coverage for module PDDW16DGZ_V_G ... +: Disabling fsm sequence coverage for module PDDW16SDGZ_H_G ... +: Disabling fsm sequence coverage for module PDDW16SDGZ_V_G ... +: Disabling fsm sequence coverage for module PDUW04DGZ_H_G ... +: Disabling fsm sequence coverage for module PDUW04DGZ_V_G ... +: Disabling fsm sequence coverage for module PDUW04SDGZ_H_G ... +: Disabling fsm sequence coverage for module PDUW08DGZ_H_G ... +: Disabling fsm sequence coverage for module PDUW08DGZ_V_G ... +: Disabling fsm sequence coverage for module PDUW08SDGZ_H_G ... +: Disabling fsm sequence coverage for module PDUW12DGZ_H_G ... +: Disabling fsm sequence coverage for module PDUW12DGZ_V_G ... +: Disabling fsm sequence coverage for module PDUW12SDGZ_H_G ... +: Disabling fsm sequence coverage for module PDUW12SDGZ_V_G ... +: Disabling fsm sequence coverage for module PDUW16DGZ_H_G ... +: Disabling fsm sequence coverage for module PDUW16DGZ_V_G ... +: Disabling fsm sequence coverage for module PDUW16SDGZ_H_G ... +: Disabling fsm sequence coverage for module PDUW16SDGZ_V_G ... +: Disabling fsm sequence coverage for module PDXOEDG_H_G ... +: Disabling fsm sequence coverage for module PDXOEDG_V_G ... +: Disabling fsm sequence coverage for module PENDCAP_G ... +: Disabling fsm sequence coverage for module PENDCAPA_G ... +: Disabling fsm sequence coverage for module PRCUT_G ... +: Disabling fsm sequence coverage for module PRCUTA_G ... +: Disabling fsm sequence coverage for module PRDW08DGZ_H_G ... +: Disabling fsm sequence coverage for module PRDW08DGZ_V_G ... +: Disabling fsm sequence coverage for module PRDW08SDGZ_H_G ... +: Disabling fsm sequence coverage for module PRDW08SDGZ_V_G ... +: Disabling fsm sequence coverage for module PRDW12DGZ_H_G ... +: Disabling fsm sequence coverage for module PRDW12DGZ_V_G ... +: Disabling fsm sequence coverage for module PRDW12SDGZ_H_G ... +: Disabling fsm sequence coverage for module PRDW12SDGZ_V_G ... +: Disabling fsm sequence coverage for module PRDW16DGZ_H_G ... +: Disabling fsm sequence coverage for module PRDW16DGZ_V_G ... +: Disabling fsm sequence coverage for module PRDW16SDGZ_H_G ... +: Disabling fsm sequence coverage for module PRDW16SDGZ_V_G ... +: Disabling fsm sequence coverage for module PRUW08DGZ_H_G ... +: Disabling fsm sequence coverage for module PRUW08DGZ_V_G ... +: Disabling fsm sequence coverage for module PRUW08SDGZ_H_G ... +: Disabling fsm sequence coverage for module PRUW08SDGZ_V_G ... +: Disabling fsm sequence coverage for module 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coverage for module PVDD2ANA_H_G ... +: Disabling fsm sequence coverage for module PVDD2ANA_V_G ... +: Disabling fsm sequence coverage for module PVDD2DGZ_H_G ... +: Disabling fsm sequence coverage for module PVDD2DGZ_V_G ... +: Disabling fsm sequence coverage for module PVDD2POC_H_G ... +: Disabling fsm sequence coverage for module PVDD2POC_V_G ... +: Disabling fsm sequence coverage for module PVDD3A_H_G ... +: Disabling fsm sequence coverage for module PVDD3A_V_G ... +: Disabling fsm sequence coverage for module PVDD3AC_H_G ... +: Disabling fsm sequence coverage for module PVDD3AC_V_G ... +: Disabling fsm sequence coverage for module PVSS1A_H_G ... +: Disabling fsm sequence coverage for module PVSS1A_V_G ... +: Disabling fsm sequence coverage for module PVSS1AC_H_G ... +: Disabling fsm sequence coverage for module PVSS1AC_V_G ... +: Disabling fsm sequence coverage for module PVSS1ANA_H_G ... +: Disabling fsm sequence coverage for module PVSS1ANA_V_G ... +: Disabling fsm sequence coverage for module PVSS1DGZ_H_G ... +: Disabling fsm sequence coverage for module PVSS1DGZ_V_G ... +: Disabling fsm sequence coverage for module PVSS2A_H_G ... +: Disabling fsm sequence coverage for module PVSS2A_V_G ... +: Disabling fsm sequence coverage for module PVSS2AC_H_G ... +: Disabling fsm sequence coverage for module PVSS2AC_V_G ... +: Disabling fsm sequence coverage for module PVSS2ANA_H_G ... +: Disabling fsm sequence coverage for module PVSS2ANA_V_G ... +: Disabling fsm sequence coverage for module PVSS2DGZ_H_G ... +: Disabling fsm sequence coverage for module PVSS2DGZ_V_G ... +: Disabling fsm sequence coverage for module PVSS3A_H_G ... +: Disabling fsm sequence coverage for module PVSS3A_V_G ... +: Disabling fsm sequence coverage for module PVSS3AC_H_G ... +: Disabling fsm sequence coverage for module PVSS3AC_V_G ... +: Disabling fsm sequence coverage for module PVSS3DGZ_H_G ... +: Disabling fsm sequence coverage for module PVSS3DGZ_V_G ... +: Disabling fsm sequence coverage for module sirv_gnrl_xchecker ... +: Disabling fsm sequence coverage for module sirv_gnrl_dffl ... +: Disabling fsm sequence coverage for module sirv_gnrl_ltch ... +: Disabling fsm sequence coverage for module clk_gen ... +: Disabling fsm sequence coverage for module reset_tb ... +: Disabling fsm sequence coverage for module TB ... +: Disabling fsm sequence coverage for module TB.clk_inst ... +: Disabling fsm sequence coverage for module TB.clk_40g_inst ... +: Disabling fsm sequence coverage for module TB.spi_bus ... +: Disabling fsm sequence coverage for module TB.lvds_bus ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_iopad ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_iopad.PDUW08SDGZ_V_G_async_rstn ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_iopad.PDDW04SDGZ_V_G_sync_in ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_iopad.PDDW08SDGZ_V_G_sync_out ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_iopad.PDUW04SDGZ_V_G_sclk ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_iopad.PDUW04SDGZ_V_G_csn ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_iopad.PDUW08SDGZ_V_G_mosi ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_iopad.PDUW08SDGZ_V_G_miso ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_iopad.PDUW08SDGZ_V_G_irq ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.mst ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.bit_cnt_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.bit_cnt_r_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.cmd_or_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.second_falling_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.wnr_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.addr_m5b_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.addr_l8b_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.chipid_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.rddata_update_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.addr_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.oen_dffrs ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.miso_reg_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[0].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[1].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[2].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[3].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[4].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[5].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[6].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[7].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[8].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[9].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[10].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[11].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[12].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[13].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[14].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[15].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[16].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[17].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[18].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[19].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[20].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[21].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[22].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[23].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[24].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[25].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[26].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[27].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[28].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[29].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[30].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[31].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.sclk_reg_dffrs ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.csn_reg_dffrs ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.mosi_reg_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.cnt_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.initaddr_vld_r_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.initaddr_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.cmd_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.chipid_vld_r_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.chipid_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.state_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.second_falling_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.addr_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.wrdata_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.wren_r_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.wren_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.rden_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.rddata_reg_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_dout_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.oen_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[0].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[1].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[2].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[3].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[4].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[5].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[6].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[7].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[8].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[9].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[10].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[11].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[12].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[13].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[14].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[15].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[16].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[17].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[18].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[19].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[20].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[21].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[22].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[23].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[24].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[25].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[26].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[27].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[28].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[29].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[30].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[31].spi_din_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[0].CMD_REG.rwaddr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[0].CMD_REG.wrdata_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[0].CMD_REG.wren_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[0].CMD_REG.reen_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[1].CMD_REG.rwaddr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[1].CMD_REG.wrdata_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[1].CMD_REG.wren_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[1].CMD_REG.reen_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[2].CMD_REG.rwaddr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[2].CMD_REG.wrdata_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[2].CMD_REG.wren_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[2].CMD_REG.reen_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[3].CMD_REG.rwaddr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[3].CMD_REG.wrdata_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[3].CMD_REG.wren_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[3].CMD_REG.reen_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.testr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.sfrtr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.syncr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.syncr16_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.syncr16_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.sync_oen_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.rampctr_dfflrs ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.ramp_ifs_dfflrs ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.doselr_dfflrs ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdsftr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdstfr_dfflrs ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdstsr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdsthr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdstamr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdsdser_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdstaor_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.llvdssr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdsfcsr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdscecr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdsfstr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdststr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.imr_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.cnt_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.sys_soft_rstn_r_dffls ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.rddata_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.train_ready_r_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.crc_error_r_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.cphase_adj_req_r_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.link_down_r_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.cmd_fifo_full_r_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.cmd_fifo_empty_r_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.isr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.misr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.irq_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_rst_gen_unit ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_rst_gen_unit.ch0_rstn_sync ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_rst_gen_unit.ch1_rstn_sync ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_rst_gen_unit.ch2_rstn_sync ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_rst_gen_unit.ch3_rstn_sync ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_SRC_INIT ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_SRC_INIT.SIM ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_SYNC_CLR_S ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_DEST_INIT ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_DEST_INIT.SIM ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_FB_DEST ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_FB_DEST.SIM ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_ACK ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_ACK.SIM ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_SYNC ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.U_prefill ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.U_prefill.delay_counter_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.U_prefill.prefill_start_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.U_prefill.prefilling_r_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.U_prefill.prefill_done_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.lane0_reg_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.lane1_reg_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.lane2_reg_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.lane3_reg_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.bit_counter_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.match_counter_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.state_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.delay_tap_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.tap_adj_req_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.link_down_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.train_ready_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.data_buf_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.match_head_start_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.data_counter_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.valid_int_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.descram_valid_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.data_in_reg_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.train_status_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_descrambler ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_descrambler.u0 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_descrambler.u1 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_descrambler.u2 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_descrambler.u3 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.u_fifo ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.u_fifo.spram ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.u_fifo.spram.bhv_spram ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.word_state_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.current_fifo_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.current_word_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.word_valid_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.data_len_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.data_cnt_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.state_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.cur_block_offset_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.block_done_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.base_addr_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.cur_block_addr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.cur_block_addr_r_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.wr_addr_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.wr_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.byte_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.wr_en_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.frame_done_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.u_crc32 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.crc_clear_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.crc_error_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.frame_status_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[0].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[1].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[2].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[3].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[4].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[5].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[6].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[7].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[8].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[9].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[10].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[11].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[12].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[13].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[14].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[15].cur_block_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[0].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[1].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[2].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[3].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[4].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[5].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[6].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[7].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[8].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[9].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[10].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[11].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[12].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[13].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[14].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[15].cur_block_mask_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.sync_in_syncer ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.sync_in_syncer.data_temp0_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.sync_in_syncer.SYNCER[1].data_tempn0_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.sync_out_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.pulse_inst_sync ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.start_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.sync_start_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.state_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.cycle_num_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.base_addr_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.wave_leng_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.hold_leng_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.addr_cnt_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.wave_cnt_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.hold_cnt_c_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.sram_rd_en_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.sram_rd_addr_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.last_sram_rd_en_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.last_wave_data_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.last_rddata_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.wave_vld_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.hold_vld_n_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.hold_vld_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.wave_valid_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.wave_data_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.cmd_fifo_inst ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.cmd_fifo_inst.spram ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.cmd_fifo_inst.spram.bhv_spram ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_sram_muxin ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_sram_muxout ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.U_sram_dmux_w ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U0_tsdn28hpcpuhdb4096x128m4mw_170a ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U0_tsdn28hpcpuhdb4096x128m4mw_170a.MX ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U1_tsdn28hpcpuhdb4096x128m4mw_170a ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U1_tsdn28hpcpuhdb4096x128m4mw_170a.MX ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U2_tsdn28hpcpuhdb4096x128m4mw_170a ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U2_tsdn28hpcpuhdb4096x128m4mw_170a.MX ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U3_tsdn28hpcpuhdb4096x128m4mw_170a ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U3_tsdn28hpcpuhdb4096x128m4mw_170a.MX ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U0_tsdn28hpcpuhdb4096x128m4mw_170a ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U0_tsdn28hpcpuhdb4096x128m4mw_170a.MX ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U1_tsdn28hpcpuhdb4096x128m4mw_170a ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U1_tsdn28hpcpuhdb4096x128m4mw_170a.MX ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U2_tsdn28hpcpuhdb4096x128m4mw_170a ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U2_tsdn28hpcpuhdb4096x128m4mw_170a.MX ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U3_tsdn28hpcpuhdb4096x128m4mw_170a ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U3_tsdn28hpcpuhdb4096x128m4mw_170a.MX ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_ramp_gen ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.dacif_vld_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[0].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[1].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[2].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[3].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[4].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[5].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[6].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[7].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[8].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[9].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[10].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[11].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[12].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[13].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[14].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[15].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[16].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[17].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[18].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[19].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[20].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[21].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[22].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[23].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[24].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[25].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[26].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[27].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[28].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[29].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[30].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[31].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[32].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[33].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[34].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[35].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[36].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[37].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[38].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[39].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[40].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[41].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[42].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[43].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[44].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[45].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[46].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[47].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[48].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[49].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[50].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[51].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[52].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[53].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[54].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[55].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[56].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[57].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[58].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[59].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[60].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[61].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[62].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[63].mux_dfflr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[0].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[1].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[2].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[3].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[4].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[5].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[6].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[7].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[8].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[9].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[10].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[11].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[12].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[13].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[14].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[15].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[16].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[17].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[18].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[19].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[20].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[21].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[22].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[23].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[24].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[25].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[26].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[27].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[28].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[29].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[30].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[31].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[32].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[33].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[34].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[35].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[36].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[37].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[38].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[39].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[40].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[41].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[42].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[43].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[44].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[45].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[46].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[47].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[48].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[49].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[50].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[51].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[52].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[53].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[54].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[55].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[56].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[57].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[58].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[59].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[60].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[61].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[62].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[63].dout_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.rtermr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.prbsr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set0r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set1r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set2r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set3r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set4r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set5r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set6r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set7r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set8r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set9r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set10r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set11r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set12r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set13r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set14r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set15r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set16r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set17r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set18r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set19r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set20r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set21r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set22r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set23r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set24r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set25r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set26r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set27r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set28r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set29r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set30r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set31r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.casaddrr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.casdwr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.imctr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.ibleedctr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.iclkcmlr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.currsvr0_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.currsvr1_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.rddata_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalrstnr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.cclkdccenr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.casclkctr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccaldccqecpir_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalqecctr1_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.biasct3r_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalpictr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalcrossctr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalrsvr0_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalrsvr1_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.selck10gdr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.selck2p5gdr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.selck625mdr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.p2sdataenr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.enallpr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.enpipr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.clkdivrstnr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.p2srsvr0_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.p2srsvr1_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ckrxswr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.rstckr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ctrzinr_dfflrd ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.rddata_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.slv[0] ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.slv[1] ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.slv[2] ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.digital_top.slv[3] ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.DEM_VLD_dffr ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_0 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_1 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_2 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_3 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_4 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_5 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_6 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_7 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_8 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_9 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_10 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_11 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_12 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_13 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_14 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_15 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_16 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_17 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_18 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_19 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_20 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_21 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_22 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_23 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_24 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_25 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_26 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_27 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_28 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_29 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_30 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_31 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_32 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_33 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_34 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_35 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_36 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_37 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_38 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_39 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_40 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_41 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_42 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_43 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_44 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_45 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_46 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_47 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_48 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_49 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_50 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_51 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_52 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_53 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_54 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_55 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_56 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_57 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_58 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_59 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_60 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_61 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_62 ... +: Disabling fsm sequence coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_63 ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[0].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[1].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[2].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[3].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[4].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[5].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[6].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[7].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[8].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[9].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[10].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[11].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[12].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[13].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[14].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[15].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[16].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[17].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[18].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[19].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[20].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[21].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[22].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[23].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[24].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[25].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[26].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[27].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[28].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[29].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[30].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk1[31].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[32].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[33].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[34].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[35].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[36].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[37].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[38].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[39].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[40].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[41].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[42].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[43].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[44].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[45].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[46].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[47].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[48].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[49].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[50].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[51].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[52].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[53].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[54].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[55].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[56].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[57].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[58].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[59].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[60].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[61].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[62].U_DEM_Reverse ... +: Disabling fsm sequence coverage for module TB.U_DEM_Reverse_64CH.genblk2[63].U_DEM_Reverse ... +: Starting toggle coverage for module sirv_gnrl_xchecker +: Starting toggle coverage for module sirv_gnrl_dffl +: Starting toggle coverage for module sirv_gnrl_ltch +: Starting toggle coverage for module clk_gen +: Starting toggle coverage for module reset_tb +: Starting toggle coverage for module TB +: Starting toggle coverage for module TB.clk_inst +: Starting toggle coverage for module TB.clk_40g_inst +: Starting toggle coverage for module TB.spi_bus +: Starting toggle coverage for module TB.lvds_bus +: Starting toggle coverage for module TB.U_da4008_chip_top +: Starting toggle coverage for module TB.U_da4008_chip_top.U_iopad +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.mst +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.bit_cnt_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.bit_cnt_r_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.cmd_or_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.second_falling_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.wnr_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.addr_m5b_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.addr_l8b_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.chipid_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.rddata_update_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.addr_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.oen_dffrs +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.miso_reg_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[0].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[1].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[2].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[3].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[4].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[5].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[6].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[7].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[8].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[9].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[10].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[11].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[12].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[13].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[14].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[15].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[16].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[17].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[18].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[19].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[20].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[21].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[22].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[23].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[24].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[25].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[26].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[27].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[28].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[29].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[30].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_pll.spi_pll_recv[31].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.sclk_reg_dffrs +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.csn_reg_dffrs +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.mosi_reg_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.cnt_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.initaddr_vld_r_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.initaddr_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.cmd_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.chipid_vld_r_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.chipid_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.state_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.second_falling_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.addr_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.wrdata_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.wren_r_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.wren_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.rden_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.rddata_reg_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_dout_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.oen_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[0].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[1].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[2].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[3].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[4].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[5].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[6].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[7].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[8].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[9].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[10].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[11].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[12].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[13].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[14].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[15].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[16].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[17].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[18].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[19].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[20].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[21].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[22].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[23].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[24].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[25].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[26].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[27].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[28].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[29].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[30].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_slave.U_spi_sys.spi_sys_recv[31].spi_din_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[0].CMD_REG.rwaddr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[0].CMD_REG.wrdata_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[0].CMD_REG.wren_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[0].CMD_REG.reen_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[1].CMD_REG.rwaddr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[1].CMD_REG.wrdata_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[1].CMD_REG.wren_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[1].CMD_REG.reen_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[2].CMD_REG.rwaddr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[2].CMD_REG.wrdata_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[2].CMD_REG.wren_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[2].CMD_REG.reen_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[3].CMD_REG.rwaddr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[3].CMD_REG.wrdata_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[3].CMD_REG.wren_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_spi_bus_decoder.MAIN[3].CMD_REG.reen_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.testr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.sfrtr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.syncr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.syncr16_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.syncr16_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.sync_oen_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.rampctr_dfflrs +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.ramp_ifs_dfflrs +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.doselr_dfflrs +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdsftr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdstfr_dfflrs +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdstsr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdsthr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdstamr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdsdser_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdstaor_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.llvdssr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdsfcsr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdscecr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdsfstr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.lvdststr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.imr_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.cnt_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.sys_soft_rstn_r_dffls +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.rddata_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.train_ready_r_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.crc_error_r_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.cphase_adj_req_r_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.link_down_r_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.cmd_fifo_full_r_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.cmd_fifo_empty_r_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.isr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.misr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_systemregfile.irq_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_rst_gen_unit +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_rst_gen_unit.ch0_rstn_sync +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_rst_gen_unit.ch1_rstn_sync +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_rst_gen_unit.ch2_rstn_sync +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_rst_gen_unit.ch3_rstn_sync +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_SRC_INIT +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_SRC_INIT.SIM +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_SYNC_CLR_S +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_DEST_INIT +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_DEST_INIT.SIM +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_FB_DEST +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_FB_DEST.SIM +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_ACK +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_RST_SYNC.U_PS_ACK.SIM +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.u_dw_stream_sync.U_SYNC +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.U_prefill +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.U_prefill.delay_counter_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.U_prefill.prefill_start_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.U_prefill.prefilling_r_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.U_prefill.prefill_done_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.lane0_reg_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.lane1_reg_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.lane2_reg_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.lane3_reg_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.bit_counter_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.match_counter_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.state_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.delay_tap_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.tap_adj_req_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.link_down_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.train_ready_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.data_buf_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.match_head_start_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.data_counter_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.valid_int_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.descram_valid_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.data_in_reg_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_train.train_status_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_descrambler +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_descrambler.u0 +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_descrambler.u1 +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_descrambler.u2 +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_descrambler.u3 +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.u_fifo +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.u_fifo.spram +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.u_fifo.spram.bhv_spram +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.word_state_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.current_fifo_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.current_word_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.word_valid_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.data_len_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.data_cnt_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.state_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.cur_block_offset_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.block_done_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.base_addr_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.cur_block_addr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.cur_block_addr_r_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.wr_addr_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.wr_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.byte_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.wr_en_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.frame_done_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.u_crc32 +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.crc_clear_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.crc_error_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.frame_status_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[0].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[1].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[2].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[3].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[4].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[5].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[6].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[7].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[8].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[9].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[10].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[11].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[12].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[13].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[14].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_block_data[15].cur_block_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[0].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[1].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[2].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[3].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[4].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[5].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[6].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[7].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[8].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[9].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[10].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[11].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[12].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[13].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[14].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dut.u_frame.gen_mask[15].cur_block_mask_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.sync_in_syncer +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.sync_in_syncer.data_temp0_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.sync_in_syncer.SYNCER[1].data_tempn0_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.sync_out_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.pulse_inst_sync +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.start_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.sync_start_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.state_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.cycle_num_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.base_addr_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.wave_leng_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.hold_leng_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.addr_cnt_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.wave_cnt_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.hold_cnt_c_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.sram_rd_en_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.sram_rd_addr_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.last_sram_rd_en_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.last_wave_data_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.last_rddata_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.wave_vld_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.hold_vld_n_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.hold_vld_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.wave_valid_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst.wave_data_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.cmd_fifo_inst +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.cmd_fifo_inst.spram +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.cmd_fifo_inst.spram.bhv_spram +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_sram_muxin +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_sram_muxout +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.U_sram_dmux_w +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U0_tsdn28hpcpuhdb4096x128m4mw_170a.MX +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U1_tsdn28hpcpuhdb4096x128m4mw_170a.MX +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U2_tsdn28hpcpuhdb4096x128m4mw_170a.MX +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[0].U3_tsdn28hpcpuhdb4096x128m4mw_170a.MX +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U0_tsdn28hpcpuhdb4096x128m4mw_170a.MX +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U1_tsdn28hpcpuhdb4096x128m4mw_170a.MX +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U2_tsdn28hpcpuhdb4096x128m4mw_170a.MX +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_awg_top.wave_dpram.U_tsmc_dpram.spram_512X8192_generation.genblk2[1].U3_tsdn28hpcpuhdb4096x128m4mw_170a.MX +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_ramp_gen +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.dacif_vld_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[0].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[1].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[2].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[3].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[4].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[5].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[6].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[7].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[8].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[9].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[10].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[11].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[12].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[13].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[14].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[15].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[16].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[17].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[18].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[19].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[20].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[21].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[22].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[23].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[24].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[25].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[26].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[27].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[28].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[29].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[30].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[31].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[32].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[33].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[34].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[35].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[36].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[37].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[38].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[39].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[40].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[41].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[42].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[43].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[44].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[45].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[46].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[47].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[48].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[49].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[50].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[51].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[52].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[53].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[54].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[55].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[56].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[57].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[58].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[59].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[60].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[61].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[62].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk1[63].mux_dfflr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[0].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[1].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[2].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[3].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[4].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[5].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[6].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[7].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[8].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[9].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[10].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[11].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[12].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[13].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[14].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[15].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[16].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[17].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[18].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[19].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[20].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[21].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[22].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[23].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[24].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[25].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[26].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[27].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[28].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[29].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[30].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[31].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[32].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[33].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[34].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[35].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[36].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[37].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[38].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[39].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[40].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[41].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[42].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[43].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[44].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[45].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[46].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[47].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[48].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[49].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[50].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[51].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[52].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[53].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[54].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[55].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[56].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[57].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[58].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[59].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[60].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[61].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[62].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.dacif_inst.genblk2[63].dout_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.rtermr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.prbsr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set0r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set1r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set2r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set3r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set4r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set5r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set6r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set7r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set8r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set9r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set10r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set11r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set12r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set13r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set14r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set15r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set16r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set17r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set18r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set19r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set20r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set21r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set22r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set23r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set24r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set25r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set26r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set27r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set28r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set29r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set30r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.set31r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.casaddrr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.casdwr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.imctr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.ibleedctr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.iclkcmlr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.currsvr0_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.currsvr1_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_dac_regfile.rddata_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalrstnr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.cclkdccenr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.casclkctr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccaldccqecpir_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalqecctr1_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.biasct3r_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalpictr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalcrossctr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalrsvr0_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ccalrsvr1_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.selck10gdr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.selck2p5gdr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.selck625mdr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.p2sdataenr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.enallpr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.enpipr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.clkdivrstnr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.p2srsvr0_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.p2srsvr1_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ckrxswr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.rstckr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.ctrzinr_dfflrd +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.U_clk_regfile.rddata_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.slv[0] +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.slv[1] +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.slv[2] +: Starting toggle coverage for module TB.U_da4008_chip_top.digital_top.slv[3] +: Starting toggle coverage for module TB.U_da4008_chip_top.DEM_VLD_dffr +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_0 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_1 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_2 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_3 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_4 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_5 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_6 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_7 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_8 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_9 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_10 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_11 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_12 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_13 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_14 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_15 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_16 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_17 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_18 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_19 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_20 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_21 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_22 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_23 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_24 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_25 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_26 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_27 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_28 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_29 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_30 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_31 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_32 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_33 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_34 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_35 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_36 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_37 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_38 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_39 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_40 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_41 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_42 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_43 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_44 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_45 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_46 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_47 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_48 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_49 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_50 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_51 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_52 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_53 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_54 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_55 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_56 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_57 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_58 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_59 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_60 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_61 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_62 +: Starting toggle coverage for module TB.U_da4008_chip_top.U_DEM_PhaseSync_4008.inst_dem_64ch.inst_dem_63 +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[0].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[1].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[2].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[3].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[4].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[5].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[6].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[7].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[8].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[9].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[10].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[11].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[12].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[13].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[14].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[15].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[16].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[17].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[18].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[19].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[20].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[21].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[22].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[23].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[24].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[25].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[26].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[27].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[28].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[29].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[30].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk1[31].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[32].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[33].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[34].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[35].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[36].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[37].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[38].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[39].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[40].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[41].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[42].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[43].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[44].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[45].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[46].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[47].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[48].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[49].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[50].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[51].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[52].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[53].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[54].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[55].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[56].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[57].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[58].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[59].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[60].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[61].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[62].U_DEM_Reverse +: Starting toggle coverage for module TB.U_DEM_Reverse_64CH.genblk2[63].U_DEM_Reverse +: Reporting line coverage at the end of simulation ... +: End of Line Coverage ... +: Reporting condition coverage at the end of simulation ... +: End of Condition Coverage ... +: Reporting branch coverage at the end of simulation ... +: End of Branch Coverage ... +: Coverage status: End of All Coverages ... + diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/filelist_syn.f b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/filelist_syn.f new file mode 100644 index 0000000..59d68ec --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/filelist_syn.f @@ -0,0 +1,23 @@ +../../../../rtl/define/chip_define.v +../../../../sim/chip_top/TB.sv +../../../../model/spi_if.sv +../../../../model/DW01_addsub.v +../../../../model/DW02_mult.v +../../../../model/DW_mult_pipe.v +../../../../model/clk_gen.v +../../../../model/clock_tb.v +../../../../model/reset_tb.v +../../../../model/thermo2binary_top.v +../../../../model/thermo7_binary3.v +../../../../model/thermo15_binary4.v +../../../../model/glbl.v +../../../../rtl/memory/tsdn28hpcpuhdb128x128m4mw_170a_ffg0p99v0c.v +../../../../rtl/memory/tsdn28hpcpuhdb4096x32m4mw_170a_ffg0p99v0c.v +../../../../rtl/memory/tsdn28hpcpuhdb64x32m4mw_170a_ffg0p99v0c.v +../../../../rtl/memory/tsdn28hpcpuhdb512x128m4mwr_170a_ffg0p99v0c.v +../../../../rtl/memory/tsdn28hpcpuhdb4096x128m4mw_170a_ffg0p99v0c.v +../../../../rtl/dem/DEM_31MSB_decoder_1ch.v +../../../../rtl/dem/DEM_31MSB_decoder_16ch_XY.v +/data/pdk/TSMCHOME/digital/Front_End/verilog/tphn28hpcpgv18_110a/tphn28hpcpgv18.v +../../../../lib/tcbn28hpcplusbwp7t35p140.v +../../../../syn/current/outputs/xyz_chip_top.syn.v diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/filelist_vlg.f b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/filelist_vlg.f new file mode 100644 index 0000000..c92f7d1 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/filelist_vlg.f @@ -0,0 +1,46 @@ +../../../../rtl/define/chip_define.v +../../../../lib/tphn28hpcpgv18.v +../../../../lib/tsdn28hpcpuhdb4096x128m4mw_170a_ffg0p99v0c.v +../../../../rtl/io/iopad.v +../../../../rtl/systemregfile/systemregfile.v +../../../../rtl/dacif/dacif.v +../../../../rtl/fifo/syn_fwft_fifo.v +../../../../rtl/dac_regfile/dac_regfile.v +../../../../rtl/lvds/ulink_rx.sv +../../../../rtl/rstgen/rst_gen_unit.v +../../../../rtl/rstgen/rst_sync.v +../../../../rtl/comm/sirv_gnrl_xchecker.v +../../../../rtl/comm/pulse_generator.sv +../../../../rtl/comm/sirv_gnrl_dffs.v +../../../../rtl/comm/syncer.v +../../../../rtl/comm/ramp_gen.v +../../../../rtl/memory/tsmc_dpram.v +../../../../rtl/memory/sram_if.sv +../../../../rtl/memory/sram_dmux.sv +../../../../rtl/memory/dpram.v +../../../../rtl/memory/bhv_spram.v +../../../../rtl/memory/spram.v +../../../../rtl/clk/clk_regfile.v +../../../../rtl/awg/awg_top.sv +../../../../rtl/awg/awg_ctrl.v +../../../../rtl/dem/DEM_PhaseSync_4008.sv +../../../../rtl/dem/DA4008_DEM_Parallel_PRBS_1CH.v +../../../../rtl/dem/DA4008_DEM_Parallel_PRBS_64CH.v +../../../../rtl/top/da4008_chip_top.sv +../../../../rtl/top/digital_top.sv +../../../../rtl/spi/spi_bus_decoder.sv +../../../../rtl/spi/spi_slave.v +../../../../rtl/spi/spi_pll.v +../../../../rtl/spi/spi_sys.v +../../../../model/clock_tb.v +../../../../model/spi_if.sv +../../../../model/clk_gen.v +../../../../model/DEM_Reverse_64CH.v +../../../../model/DEM_Reverse.v +../../../../model/reset_tb.v +../../../../model/DW_stream_sync.v +../../../../model/DW_reset_sync.v +../../../../model/DW_sync.v +../../../../model/DW_pulse_sync.v +../../../../sim/chip_top/TB.sv +../../../../rtl/define/chip_undefine.v diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/novas.conf b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/novas.conf new file mode 100644 index 0000000..1ff985d --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/novas.conf @@ -0,0 +1,359 @@ +[qBaseWindowStateGroup] +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true 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+10=/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/novas_autosave.ses + +[qDockerWindow_C] +Verdi_1\position.x=-1 +Verdi_1\position.y=27 +Verdi_1\width=1920 +Verdi_1\height=977 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/novas.rc b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/novas.rc new file mode 100644 index 0000000..e7e2b6b --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/novas.rc @@ -0,0 +1,1313 @@ +@verdi rc file Version 1.0 +[Library] +work = ./work +[Annotation] +3D_Active_Annotation = FALSE +[CommandSyntax.finsim] +InvokeCommand = +FullFileName = TRUE +Separator = . +SimPromptSign = ">" +HierNameLevel = 1 +RunContinue = "continue" +Finish = "quit" +UseAbsTime = FALSE +NextTime = "run 1" +NextNTime = "run ${SimBPTime}" +NextEvent = "run 1" +Reset = +ObjPosBreak = "break posedge ${SimBPObj}" +ObjNegBreak = "break negedge ${SimBPObj}" +ObjAnyBreak = "break change ${SimBPObj}" +ObjLevelBreak = +LineBreak = "breakline ${SimBPFile} ${SimBPLine}" +AbsTimeBreak = "break abstimeaf ${SimBPTime}" +RelTimeBreak = "break reltimeaf ${SimBPTime}" +EnableBP = "breakon ${SimBPId}" +DisableBP = "breakoff ${SimBPId}" +DeleteBP = "breakclr ${SimBPId}" +DeleteAllBP = "breakclr" +SimSetScope = "cd ${SimDmpObj}" +[CommandSyntax.ikos] +InvokeCommand = "setvar debussy true;elaborate -p ${SimTop} -s ${SimArch}; run until 0;fsdbInteractive; " +FullFileName = TRUE +NeedTimeUnit = TRUE +NormalizeTimeUnit = TRUE +Separator = / +HierNameLevel = 2 +RunContinue = "run" +Finish = "exit" +NextTime = "run ${SimBPTime} ${SimTimeUnit}" +NextNTime = "run for ${SimBPTime} ${SimTimeUnit}" +NextEvent = "step 1" +Reset = "reset" +ObjPosBreak = "stop if ${SimBPObj} = \"'1'\"" +ObjNegBreak = "stop if ${SimBPObj} = \"'0'\"" +ObjAnyBreak = +ObjLevelBreak = "stop if ${SimBPObj} = ${SimBPValue}" +LineBreak = "stop at ${SimBPFile}:${SimBPLine}" +AbsTimeBreak = +RelTimeBreak = +EnableBP = "enable ${SimBPId}" +DisableBP = "disable ${SimBPId}" +DeleteBP = "delete ${SimBPId}" +DeleteAllBP = "delete *" +[CommandSyntax.verisity] +InvokeCommand = +FullFileName = FALSE +Separator = . +SimPromptSign = "> " +HierNameLevel = 1 +RunContinue = "." +Finish = "$finish;" +NextTime = "$db_steptime(1);" +NextNTime = "$db_steptime(${SimBPTime});" +NextEvent = "$db_step;" +SimSetScope = "$scope(${SimDmpObj});" +Reset = "$reset;" +ObjPosBreak = "$db_breakonposedge(${SimBPObj});" +ObjNegBreak = "$db_breakonnegedge(${SimBPObj});" +ObjAnyBreak = "$db_breakwhen(${SimBPObj});" +ObjLevelBreak = "$db_breakwhen(${SimBPObj}, ${SimBPValue});" +LineBreak = "$db_breakatline(${SimBPLine}, ${SimBPScope}, \"${SimBPFile}\");" +AbsTimeBreak = "$db_breakbeforetime(${SimBPTime});" +RelTimeBreak = "$db_breakbeforetime(${SimBPTime});" +EnableBP = "$db_enablebreak(${SimBPId});" +DisableBP = "$db_disablebreak(${SimBPId});" +DeleteBP = "$db_deletebreak(${SimBPId});" +DeleteAllBP = "$db_deletebreak;" +FSDBInit = "$novasInteractive;" +FSDBDumpvars = "$novasDumpvars(0, ${SimDmpObj});" +FSDBDumpsingle = "$novasDumpsingle(${SimDmpObj});" +FSDBDumpvarsInFile = "$novasDumpvarsToFile(\"${SimDmpFile}\");" +FSDBDumpMem = "$novasDumpMemNow(${SimDmpObj}, ${SimDmpBegin}, ${SimDmpSize});" +[CoverageDetail] +cross_filter_limit = 1000 +branch_limit_vector_display = 50 +showgrid = TRUE +reuseFirst = TRUE +justify = TRUE +scrollbar_mode = per pane +test_combo_left_truncate = TRUE +instance_combo_left_truncate = TRUE +loop_navigation = TRUE +condSubExpr = 20 +tglMda = 1000 +linecoverable = 100000 +lineuncovered = 50000 +tglcoverable = 30000 +tgluncovered = 30000 +pendingMax = 1000 +show_full_more = FALSE +[CoverageHier] +showgrid = FALSE +[CoverageWeight] +Assert = 1 +Covergroup = 1 +Line = 1 +Condition = 1 +Toggle = 1 +FSM = 1 +Branch = 1 +[DesignTree] +IfShowModule = {TRUE, FALSE} +[DisabledMessages] +version = Verdi_O-2018.09-SP2 +[Editor] +editorName = TurboEditor +[Emacs] +EmacsFont = "Clean 14" +EmacsBG = white +EmacsFG = black +[Exclusion] +enableAsDefault = TRUE +saveAsDefault = TRUE +saveManually = TRUE +illegalBehavior = FALSE +DisplayExcludedItem = FALSE +adaptiveExclusion = TRUE +warningExcludeInstance = TRUE +favorite_exclude_annotation = "" +[FSM] +viewport = 65 336 387 479 +WndBk-FillColor = Gray3 +Background-FillColor = gray5 +prefKey_Link-FillColor = yellow4 +prefKey_Link-TextColor = black +Trap = red3 +Hilight = blue4 +Window = Gray3 +Selected = white +Trans. = green2 +State = black +Init. = black +SmartTips = TRUE +VectorFont = FALSE +StopAskBkgndColor = FALSE +ShowStateAction = FALSE +ShowTransAction = FALSE +ShowTransCond = FALSE +StateLable = NAME +StateValueRadix = ORIG +State-LineColor = ID_BLACK +State-LineWidth = 1 +State-FillColor = ID_BLUE2 +State-TextColor = ID_WHITE +Init_State-LineColor = ID_BLACK +Init_State-LineWidth = 2 +Init_State-FillColor = ID_YELLOW2 +Init_State-TextColor = ID_BLACK +Reset_State-LineColor = ID_BLACK +Reset_State-LineWidth = 2 +Reset_State-FillColor = ID_YELLOW7 +Reset_State-TextColor = ID_BLACK +Trap_State-LineColor = ID_RED2 +Trap_State-LineWidth = 2 +Trap_State-FillColor = ID_CYAN5 +Trap_State-TextColor = ID_RED2 +State_Action-LineColor = ID_BLACK +State_Action-LineWidth = 1 +State_Action-FillColor = ID_WHITE +State_Action-TextColor = ID_BLACK +Junction-LineColor = ID_BLACK +Junction-LineWidth = 1 +Junction-FillColor = ID_GREEN2 +Junction-TextColor = ID_BLACK +Connection-LineColor = ID_BLACK +Connection-LineWidth = 1 +Connection-FillColor = ID_GRAY5 +Connection-TextColor = ID_BLACK +prefKey_Port-LineColor = ID_BLACK +prefKey_Port-LineWidth = 1 +prefKey_Port-FillColor = ID_ORANGE6 +prefKey_Port-TextColor = ID_YELLOW2 +Transition-LineColor = ID_BLACK +Transition-LineWidth = 1 +Transition-FillColor = ID_WHITE +Transition-TextColor = ID_BLACK +Trans_Condition-LineColor = ID_BLACK +Trans_Condition-LineWidth = 1 +Trans_Condition-FillColor = ID_WHITE +Trans_Condition-TextColor = ID_ORANGE2 +Trans_Action-LineColor = ID_BLACK +Trans_Action-LineWidth = 1 +Trans_Action-FillColor = ID_WHITE +Trans_Action-TextColor = ID_GREEN2 +SelectedSet-LineColor = ID_RED2 +SelectedSet-LineWidth = 1 +SelectedSet-FillColor = ID_RED2 +SelectedSet-TextColor = ID_WHITE +StickSet-LineColor = ID_ORANGE5 +StickSet-LineWidth = 1 +StickSet-FillColor = ID_PURPLE6 +StickSet-TextColor = ID_BLACK +HilightSet-LineColor = ID_RED5 +HilightSet-LineWidth = 1 +HilightSet-FillColor = ID_RED7 +HilightSet-TextColor = ID_BLUE5 +ControlPoint-LineColor = ID_BLACK +ControlPoint-LineWidth = 1 +ControlPoint-FillColor = ID_WHITE +Bundle-LineColor = ID_BLACK +Bundle-LineWidth = 1 +Bundle-FillColor = ID_WHITE +Bundle-TextColor = ID_BLUE4 +QtBackground-FillColor = ID_GRAY6 +prefKey_Link-LineColor = ID_ORANGE2 +prefKey_Link-LineWidth = 1 +Selection-LineColor = ID_BLUE2 +Selection-LineWidth = 1 +[FSM_Dlg-Print] +Orientation = Landscape +[Form] +version = Verdi_O-2018.09-SP2 +wave/sigCPL.fm = 100,100,243,333 +[General] +autoSaveSession = FALSE +TclAutoSource = +cmd_enter_form = FALSE +SyncBrowserDir = TRUE +version = Verdi_O-2018.09-SP2 +SignalCaseInSensitive = FALSE +ShowWndCtntDuringResizing = FALSE +[GlobalProp] +ErrWindow_Font = Helvetica_M_R_12 +[Globals] +app_default_font = Bitstream Vera Sans,10,-1,5,50,0,0,0,0,0 +app_fixed_width_font = Courier,10,-1,5,50,0,0,0,0,0 +text_encoding = Unicode(utf8) +smart_resize = TRUE +smart_resize_child_limit = 2000 +tooltip_max_width = 200 +tooltip_max_height = 20 +tooltip_viewer_key = F3 +tooltip_display_time = 1000 +bookmark_name_length_limit = 12 +disable_tooltip = FALSE +auto_load_source = TRUE +max_array_size = 4096 +filter_when_typing = TRUE +filter_keep_children = TRUE +filter_syntax = Wildcards +filter_keystroke_interval = 800 +filter_case_sensitive = FALSE +filter_full_path = FALSE +load_detail_for_funcov = FALSE +sort_limit = 100000 +ignoreDBVersionChecking = FALSE +[HB] +ViewSchematic = FALSE +windowLayout = 0 0 804 500 182 214 804 148 +import_filter = *.v; *.vc; *.f +designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +import_filter_vhdl = *.vhd; *.vhdl; *.f +import_default_language = Verilog +import_filter_verilog = *.v; *.vc; *.f +simulation_file_type = *.fsdb;*.fsdb.gz;*.fsdb.bz2;*.ff;*.dump +PrefetchViewableAnnot = TRUE +[Hier] +filterTimeout = 1500 +[ImportLiberty] +SearchPriority = .lib++ +bSkipStateCell = False +bImportPowerInfo = False +bSkipFFCell = False +bScpecifyCellNameCase = False +bSpecifyPinNameCase = False +CellNameToCase = +PinNameToCase = +[Language] +EditWindow_Font = COURIER12 +Background = ID_WHITE +Comment = ID_GRAY4 +Keyword = ID_BLUE5 +UserKeyword = ID_GREEN2 +Text = ID_BLACK +SelText = ID_WHITE +SelBackground = ID_BLUE2 +[Library.Ikos] +pack = ./work.lib++ +vital = ./work.lib++ +work = ./work.lib++ +std = ${dls_std}.lib++ +ieee = ${dls_ieee}.lib++ +synopsys = ${dls_synopsys}.lib++ +silc = ${dls_silc}.lib++ +ikos = ${dls_ikos}.lib++ +novas = ${VOYAGER_LIB_VHDL}/${VOYAGER_MACHINE}/novas.lib++ +[MDT] +ART_RF_SP = spr[0-9]*bx[0-9]* +ART_RF_2P = dpr[0-9]*bx[0-9]* +ART_SRAM_SP = spm[0-9]*bx[0-9]* +ART_SRAM_DP = dpm[0-9]*bx[0-9]* +VIR_SRAM_SP = hdsd1_[0-9]*x[0-9]*cm4sw1 +VIR_SRAM_DP = hdsd2_[0-9]*x[0-9]*cm4sw1 +VIR_RF_SP = rfsd1_[0-9]*x[0-9]*cm2sw0 +VIR_RF_DP = rfsd2_[0-9]*x[0-9]*cm2sw1 +VIR_STAR_SRAM_SP = shsd1_[0-9]*x[0-9]*cm4sw0 +[NPExpanding] +functiongroups = FALSE +modules = FALSE +[NPFilter] +showAssertion = TRUE +showCoverGroup = TRUE +showProperty = TRUE +showSequence = TRUE +showDollarUnit = TRUE +[OldFontRC] +Wave_legend_window_font = -f COURIER12 -c ID_CYAN5 +Wave_value_window_font = -f COURIER12 -c ID_CYAN5 +Wave_curve_window_font = -f COURIER12 -c ID_CYAN5 +Wave_group_name_font = -f COURIER12 -c ID_GREEN5 +Wave_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_comment_string_font = -f COURIER12 -c ID_RED5 +HB_designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +Text_font = COURIER12 +nMemory_font = Fixed 14 +Wave_getsignal_form_font = -f COURIER12 +Text_annotFont = Helvetica_M_R_10 +[OtherEditor] +cmd1 = "xterm -font 9x15 -fg black -bg gray -e" +name = "vi" +options = "+${CurLine} ${CurFullFileName}" +[Power] +PowerDownInstance = ID_GRAY1 +RetentionSignal = ID_YELLOW2 +IsolationSignal = ID_RED6 +LevelShiftedSignal = ID_GREEN6 +PowerSwitchObject = ID_ORANGE5 +AlwaysOnObject = ID_GREEN5 +PowerNet = ID_RED2 +GroundNet = ID_RED2 +SimulationOnly = ID_CYAN3 +SRSN/SPA = ID_CYAN3 +CNSSignal = ID_CYAN3 +RPTRSignal = ID_CYAN3 +AcknowledgeSignal = ID_CYAN3 +BoundaryPort = ID_CYAN3 +DisplayInstrumentedCell = TRUE +ShowCmdByFile = FALSE +ShowPstAnnot = FALSE +ShowIsoSymbol = TRUE +ExtractIsoSameNets = FALSE +AnnotateSignal = TRUE +HighlightPowerObject = TRUE +HighlightPowerDomain = TRUE +TraceThroughInstruLowPower = FALSE +BrightenPowerColorInSchematicWindow = FALSE +ShowAlias = FALSE +ShowVoltage = TRUE +MatchTreeNodesCaseInsensitive = FALSE +SearchHBNodeDynamically = FALSE +ContinueTracingSupplyOrLogicNet = FALSE +[Print] +PrinterName = lp +FileName = test.ps +PaperSize = A4 - 210x297 (mm) +ColorPrint = FALSE +[PropertyTools] +saveWaveformStat = TRUE +savePropStat = FALSE +savePropDtl = TRUE +[QtDialog] +qWaveSignalDialog = 559,313,800,479 +QwWarnMsgDlg = 659,446,600,250 +EventReportDialog = 599,412,720,280 +QwUserAskDlg = 798,487,324,134 +[Relationship] +hideRecursiceNode = FALSE +[Session Cache] +3 = string (session file name) +4 = string (session file name) +5 = string (session file name) +1 = /home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/novas_autosave.ses +2 = /home/shbyang/verdiLog/novas_autosave.ses +[Simulation] +scsPath = scsim +scsOption = +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +osciPath = gdb +osciOption = +vcsPath = simv +vcsOption = +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +speedsimPath = +speedsimOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +interactiveDebugging = {True, False} +KeepBreakPoints = False +ScsDebugAll = False +simType = {vcssv, xl, nc, vcs, mti, mti_vlog, vhnc, scs, mixnc} +thirdpartyIdx = -1 +iscCmdSep = FALSE +NoAppendOption = False +[SimulationPlus] +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +vcsPath = simv +vcsOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +speedsimPath = verilog +speedsimOption = +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +scsPath = scsim +scsOption = +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +vcs_svPath = simv +vcs_svOption = +simType = vcssv +thirdpartyIdx = -1 +interactiveDebugging = FALSE +KeepBreakPoints = FALSE +iscCmdSep = FALSE +ScsDebugAll = FALSE +NoAppendOption = FALSE +invokeSimPath = work +[SimulationPlus2] +eventDumpUnfinish = FALSE +[Source] +wordWrapOn = TRUE +viewReuse = TRUE +lineNumberOn = TRUE +warnOutdatedDlg = TRUE +showEncrypt = FALSE +loadInclude = FALSE +showColorForActive = FALSE +tabWidth = 8 +editor = vi +reload = Never +sync_active_to_source = TRUE +navigateAsColored = FALSE +navigateCovered = FALSE +navigateUncovered = TRUE +navigateExcluded = FALSE +not_ask_for_source_path = FALSE +expandMacroOn = TRUE +expandMacroInstancesThreshold = 10000 +[SourceVHDL] +vhSimType = ModelSim +ohSimType = VCS +[TclShell] +nLineSize = 1024 +[Test] +verbose_progress = FALSE +[TestBenchBrowser] +-showUVMDynamicHierTreeWin = FALSE +[Text] +hdlTypeName = blue4 +hdlLibrary = blue4 +viewport = 396 392 445 487 +hdlOther = ID_BLACK +hdlComment = ID_GRAY1 +hdlKeyword = ID_BLUE5 +hdlEntity = ID_BLACK +hdlEntityInst = ID_BLACK +hdlSignal = ID_RED2 +hdlInSignal = ID_RED2 +hdlOutSignal = ID_RED2 +hdlInOutSignal = ID_RED2 +hdlOperator = ID_BLACK +hdlMinus = ID_BLACK +hdlSymbol = ID_BLACK +hdlString = ID_BLACK +hdlNumberBase = ID_BLACK +hdlNumber = ID_BLACK +hdlLiteral = ID_BLACK +hdlIdentifier = ID_BLACK +hdlSystemTask = ID_BLACK +hdlParameter = ID_BLACK +hdlIncFile = ID_BLACK +hdlDataFile = ID_BLACK +hdlCDSkipIf = ID_GRAY1 +hdlMacro = ID_BLACK +hdlMacroValue = ID_BLACK +hdlPlainText = ID_BLACK +hdlOvaId = ID_PURPLE2 +hdlPslId = ID_PURPLE2 +HvlEId = ID_BLACK +HvlVERAId = ID_BLACK +hdlEscSignal = ID_BLACK +hdlEscInSignal = ID_BLACK +hdlEscOutSignal = ID_BLACK +hdlEscInOutSignal = ID_BLACK +textBackgroundColor = ID_GRAY6 +textHiliteBK = ID_BLUE5 +textHiliteText = ID_WHITE +textTracedMark = ID_GREEN2 +textLineNo = ID_BLACK +textFoldedLineNo = ID_RED5 +textUserKeyword = ID_GREEN2 +textParaAnnotText = ID_BLACK +textFuncAnnotText = ID_BLUE2 +textAnnotText = ID_BLACK +textUserDefAnnotText = ID_BLACK +ComputedSignal = ID_PURPLE5 +textAnnotTextShadow = ID_WHITE +parenthesisBGColor = ID_YELLOW5 +codeInParenthesis = ID_CYAN5 +text3DLight = ID_WHITE +text3DShadow = ID_BLACK +textHvlDriver = ID_GREEN3 +textHvlLoad = ID_YELLOW3 +textHvlDriverLoad = ID_BLUE3 +irOutline = ID_RED2 +irDriver = ID_YELLOW5 +irLoad = ID_BLACK +irBookMark = ID_YELLOW2 +irIndicator = ID_WHITE +irBreakpoint = ID_GREEN5 +irCurLine = ID_BLUE5 +hdlVhEntity = ID_BLACK +hdlArchitecture = ID_BLACK +hdlPackage = ID_BLUE5 +hdlRefPackage = ID_BLUE5 +hdlAlias = ID_BLACK +hdlGeneric = ID_BLUE5 +specialAnnotShadow = ID_BLUE1 +hdlZeroInHead = ID_GREEN2 +hdlZeroInComment = ID_GREEN2 +hdlPslHead = ID_BLACK +hdlPslComment = ID_BLACK +hdlSynopsysHead = ID_GREEN2 +hdlSynopsysComment = ID_GREEN2 +pdmlIdentifier = ID_BLACK +pdmlCommand = ID_BLACK +pdmlMacro = ID_BLACK +font = COURIER12 +annotFont = Helvetica_M_R_10 +[Text.1] +viewport = -1 27 1920 977 45 +[TextPrinter] +Orientation = Landscape +Indicator = FALSE +LineNum = TRUE +FontSize = 7 +Column = 2 +Annotation = TRUE +[Texteditor] +TexteditorFont = "Clean 14" +TexteditorBG = white +TexteditorFG = black +[ThirdParty] +ThirdPartySimTool = verisity surefire ikos finsim +[TurboEditor] +autoBackup = TRUE +[UserButton.mixnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +Button8 = "FSDB Ver" "call fsdbVersion" +Button9 = "Dump On" "call fsdbDumpon" +Button10 = "Dump Off" "call fsdbDumpoff" +Button11 = "All Tasks" "call" +Button12 = "Dump Selected Instance" "call fsdbDumpvars 1 ${SelInst}" +[UserButton.mti] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.mti_vlog] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.nc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.scs] +Button1 = "Dump All Signals" "call fsdbDumpvars(0, \"${TopScope}\");\n" +Button2 = "Next 1000 Time" "run 1000 \n" +Button3 = "Next ? Time" "run ${Arg:Next Time} \n" +Button4 = "Run Step" "step\n" +Button5 = "Show Variables" "ls -v {${SelVars}}\n" +[UserButton.vhnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.xl] +Button13 = "Dump Off" "$fsdbDumpoff;\n" +Button12 = "Dump On" "$fsdbDumpon;\n" +Button11 = "Delete Focus" "$db_deletefocus(${treeSelScope});\n" +Button10 = "Set Focus" "$db_setfocus(${treeSelScope});\n" +Button9 = "Deposit Variable" "$deposit(${SelVar},${Arg:New Value});\n" +Button8 = "Release Variable" "release ${SelVar};\n" +Button7 = "Force Variable" "force ${SelVar} = ${Arg:New Value};\n" +Button6 = "Show Variables" "$showvars(${SelVars});\n" +Button5 = "Next ? Event" "$db_step(${Arg:Next Event});\n" +Button4 = "Next Event" "$db_step(1);\n" +Button3 = "Next ? Time" "#${Arg:Next Time} $stop;.\n" +Button2 = "Next 1000 Time" "#1000 $stop;.\n" +Button1 = "Dump All Signals" "$fsdbDumpvars;\n" +[VIA] +viaLogViewerDefaultRuleOneSearchForm = "share/VIA/Apps/PredefinedRules/Misc/Onesearch_rule.rc" +[VIA.oneSearch.preference] +DefaultDisplayTimeUnit = "1.000000ns" +DefaultLogTimeUnit = "1.000000ns" +[VIA.oneSearch.preference.vgifColumnSettingRC] +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0] +parRuleSets = "" +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column0] +name = Severity +width = 60 +visualIndex = 1 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column1] +name = Time +width = 60 +visualIndex = 0 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column2] +name = Message +width = 2000 +visualIndex = 4 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column3] +name = Code +width = 60 +visualIndex = 2 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column4] +name = Type +width = 60 +visualIndex = 3 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[Vi] +ViFont = "Clean 14" +ViBG = white +ViFG = black +[Wave] +ovaEventSuccessColor = -c ID_CYAN5 +ovaEventFailureColor = -c ID_RED5 +ovaBooleanSuccessColor = -c ID_CYAN5 +ovaBooleanFailureColor = -c ID_RED5 +ovaAssertSuccessColor = -c ID_GREEN5 +ovaAssertFailureColor = -c ID_RED5 +ovaForbidSuccessColor = -c ID_GREEN5 +SigGroupRuleFile = +DisplayFileName = FALSE +waveform_vertical_scroll_bar = TRUE +scope_to_save_with_macro +open_file_dir +open_rc_file_dir +getSignalForm = 559 276 800 479 245 381 505 183 +viewPort = 0 27 1920 309 152 65 +signalSpacing = 5 +digitalSignalHeight = 15 +analogSignalHeight = 98 +commentSignalHeight = 98 +transactionSignalHeight = 98 +messageSignalHeight = 98 +minCompErrWidth = 4 +DragZoomTolerance = 4 +maxTransExpandedLayer = 10 +WaveMaxPoint = 512 +legendBackground = -c ID_BLACK +valueBackground = -c ID_BLACK +curveBackground = -c ID_BLACK +getSignalSignalList_BackgroundColor = -c ID_GRAY6 +glitchColor = -c ID_RED5 +cursor = -c ID_YELLOW5 -lw 1 -ls long_dashed +marker = -c ID_WHITE -lw 1 -ls dash_dot_l +usermarker = -c ID_GREEN5 -lw 1 -ls long_dashed +trace = -c ID_GRAY5 -lw 1 -ls long_dashed +grid = -c ID_WHITE -lw 1 -ls short_dashed +rulerBackground = -c ID_GRAY3 +rulerForeground = -c ID_YELLOW5 +busTextColor = -c ID_ORANGE8 +legendForeground = -c ID_CYAN5 +valueForeground = -c ID_CYAN5 +curveForeground = -c ID_CYAN5 +groupNameColor = -c ID_GREEN5 +commentStringColor = -c ID_RED5 +region(Active)Background = -c ID_YELLOW1 +region(NBA)Background = -c ID_RED1 +region(Re-Active)Background = -c ID_YELLOW3 +region(Re-NBA)Background = -c ID_RED3 +region(VHDL-Delta)Background = -c ID_ORANGE3 +region(Dump-Off)Background = -c ID_GRAY4 +High_Light = -c ID_GRAY2 +Input_Signal = -c ID_RED5 +Output_Signal = -c ID_GREEN5 +InOut_Signal = -c ID_BLUE5 +Net_Signal = -c ID_YELLOW5 +Register_Signal = -c ID_PURPLE5 +Verilog_Signal = -c ID_CYAN5 +VHDL_Signal = -c ID_ORANGE5 +SystemC_Signal = -c ID_BLUE7 +Dump_Off_Color = -c ID_BLUE2 +Compress_Bar_Color = -c ID_YELLOW4 +Vector_Dense_Block_Color = -c ID_ORANGE8 +Scalar_Dense_Block_Color = -c ID_GREEN6 +Analog_Dense_Block_Color = -c ID_PURPLE2 +Composite_Dense_Block_Color = -c ID_ORANGE5 +RPTR_Power_Off_Layer = -c ID_CYAN3 -stipple dots +DB_Power_Off_Layer = -c ID_BLUE4 -stipple dots +SPA_Driver_Power_Off_Layer = -c ID_ORANGE4 -stipple dots +SPA_Receiver_Power_Off_Layer = -c ID_GREEN5 -stipple dots +SRSN_Power_Off_Layer = -c ID_GREEN4 -stipple dots +Isolation_Power_Off_Layer = -c ID_RED4 -stipple dots +PD_Power_Off_Layer = -c ID_GRAY4 -stipple dots +Isolation_Layer = -c ID_RED4 -stipple vLine +Retention_Level_Trigger_Layer = -c ID_ORANGE1 -stipple fill_solid +Retention_Edge_Trigger_Layer = -c ID_YELLOW6 -stipple fill_solid +Driving_Power_Off_Layer = -c ID_YELLOW2 -stipple x +Toggle_Layer = -c ID_YELLOW4 -stipple slash +analogRealStyle = pwl +analogVoltageStyle = pwl +analogCurrentStyle = pwl +analogOthersStyle = pwl +busSignalLayer = -c ID_ORANGE8 +busXLayer = -c ID_RED5 +busZLayer = -c ID_ORANGE6 +busMixedLayer = -c ID_GREEN5 +busNotComputedLayer = -c ID_GRAY1 +busNoValueLayer = -c ID_BLUE2 +signalGridLayer = -c ID_WHITE +analogGridLayer = -c ID_GRAY6 +analogRulerLayer = -c ID_GRAY6 +keywordLayer = -c ID_RED5 +loadedLayer = -c ID_BLUE5 +loadingLayer = -c ID_BLACK +qdsCurMarkerLayer = -c ID_BLUE5 +qdsBrkMarkerLayer = -c ID_GREEN5 +qdsTrgMarkerLayer = -c ID_RED5 +arrowDefaultColor = -c ID_ORANGE6 +startNodeArrowColor = -c ID_WHITE +endNodeArrowColor = -c ID_YELLOW5 +propertyEventMatchColor = -c ID_GREEN5 +propertyEventNoMatchColor = -c ID_RED5 +propertyVacuousSuccessMatchColor = -c ID_YELLOW2 +propertyStatusBoundaryColor = -c ID_WHITE +propertyBooleanSuccessColor = -c ID_CYAN5 +propertyBooleanFailureColor = -c ID_RED5 +propertyAssertSuccessColor = -c ID_GREEN5 +propertyAssertFailureColor = -c ID_RED5 +propertyForbidSuccessColor = -c ID_GREEN5 +transactionForegroundColor = -c ID_YELLOW8 +transactionBackgroundColor = -c ID_BLACK +transactionHighLightColor = -c ID_CYAN6 +transactionRelationshipColor = -c ID_PURPLE6 +transactionErrorTypeColor = -c ID_RED5 +coverageFullyCoveredColor = -c ID_GREEN5 +coverageNoCoverageColor = -c ID_RED5 +coveragePartialCoverageColor = -c ID_YELLOW5 +coverageReferenceLineColor = -c ID_GRAY4 +messageForegroundColor = -c ID_YELLOW4 +messageBackgroundColor = -c ID_PURPLE1 +messageHighLightColor = -c ID_CYAN6 +messageInformationColor = -c ID_RED5 +ComputedAnnotColor = -c ID_PURPLE5 +fsvSecurityDataColor = -c ID_PURPLE3 +qdsAutoBusGroup = TRUE +qdsTimeStampMode = FALSE +qdsVbfBusOrderAscending = FALSE +openDumpFilter = *.fsdb;*.vf;*.jf +DumpFileFilter = *.vcd +RestoreSignalFilter = *.rc +SaveSignalFilter = *.rc +AddAliasFilter = *.alias;*.adb +CompareSignalFilter = *.err +ConvertFFFilter = *.vcd;*.out;*.tr0;*.xp;*.raw;*.wfm +Scroll_Ratio = 100 +Zoom_Ratio = 10 +EventSequence_SyncCursorTime = TRUE +EventSequence_Sorting = FALSE +EventSequence_RemoveGrid = FALSE +EventSequence_IsGridMode = FALSE +SetDefaultRadix_global = FALSE +DefaultRadix = Hex +SigSearchSignalMatchCase = FALSE +SigSearchSignalScopeOption = FALSE +SigSearchSignalSamenetInterface = FALSE +SigSearchSignalFullScope = FALSE +SigSearchSignalWithRegExp = FALSE +SigSearchDynamically = FALSE +SigDisplayBySelectionOrder = FALSE +SigDisplayRowMajor = FALSE +SigDragSelFollowColumn = FALSE +SigDisplayHierarchyBox = TRUE +SigDisplaySubscopeBox = TRUE +SigDisplayEmptyScope = TRUE +SigDisplaySignalNavigationBox = FALSE +SigDisplayFormBus = TRUE +SigShowSubProgram = TRUE +SigSearchScopeDynamically = TRUE +SigCollapseSubtreeNodes = FALSE +activeFileApplyToAnnotation = FALSE +GrpSelMode = TRUE +dispGridCount = FALSE +hierarchyName = FALSE +partial_level_name = FALSE +partial_level_head = 1 +partial_level_tail = 1 +displayMessageLabelOnly = TRUE +autoInsertDumpoffs = TRUE +displayMessageCallStack = FALSE +displayCallStackWithFullSections = TRUE +displayCallStackWithLastSection = FALSE +limitMessageMaxWidth = FALSE +messageMaxWidth = 50 +displayTransBySpecificColor = FALSE +fittedTransHeight = FALSE +snap = TRUE +gravitySnap = FALSE +displayLeadingZero = FALSE +displayGlitchs = FALSE +allfileTimeRange = FALSE +fixDelta = FALSE +displayCursorMarker = FALSE +autoUpdate = FALSE +restoreFromActiveFile = TRUE +restoreToEnd = FALSE +dispCompErr = TRUE +showMsgDes = TRUE +anaAutoFit = FALSE +anaAutoPattn = FALSE +anaAuto100VertFit = FALSE +displayDeltaY = FALSE +centerCursor = FALSE +denseBlockDrawing = TRUE +relativeFreqPrecision = 3 +showMarkerAbsolute = FALSE +showMarkerAdjacent = FALSE +showMarkerRelative = FALSE +showMarkerFrequency = FALSE +stickCursorMarkerOnWaveform = TRUE +keepMarkerAtEndTimeOfTransaction = FALSE +doubleClickToExpandTransaction = TRUE +expandTransactionAssociatedSignals = TRUE +expandTransactionAttributeSignals = FALSE +WaveExtendLastTick = TRUE +InOutSignal = FALSE +NetRegisterSignal = FALSE +VerilogVHDLSignal = FALSE +LabelMarker = TRUE +ResolveSymbolicLink = TRUE +signal_rc_abspath = TRUE +signal_rc_no_natural_bus_range = FALSE +save_scope_with_macro = FALSE +TipInSignalWin = FALSE +DisplayPackedSiganlInBitwiseManner = FALSE +DisplaySignalTypeAheadOfSignalName = TRUE ICON +TipInCurveWin = FALSE +MouseGesturesInCurveWin = TRUE +DisplayLSBsFirst = FALSE +PaintSpecificColorPattern = TRUE +ModuleName = TRUE +form_all_memory_signal = FALSE +formBusSignalFromPartSelects = FALSE +read_value_change_on_demand_for_drawing = FALSE +load_scopes_on_demand = on 5 +TransitionMode = TRUE +DisplayRadix = FALSE +SchemaX = FALSE +Hilight = TRUE +UseBeforeValue = FALSE +DisplayFileNameAheadOfSignalName = FALSE +DisplayFileNumberAheadOfSignalName = FALSE +DisplayValueSpace = TRUE +FitAnaByBusSize = FALSE +displayTransactionAttributeName = FALSE +expandOverlappedTrans = FALSE +dispSamplePointForAttrSig = TRUE +dispClassName = TRUE +ReloadActiveFileOnly = FALSE +NormalizeEVCD = FALSE +OverwriteAliasWithRC = TRUE +overlay_added_analog_signals = FALSE +case_insensitive = FALSE +vhdlVariableCalculate = TRUE +showError = TRUE +signal_vertical_scroll_bar = TRUE +showPortNameForDroppedInstance = FALSE +truncateFilePathInTitleBar = TRUE +filterPropVacuousSuccess = FALSE +includeLocalSignals = FALSE +encloseSignalsByGroup = TRUE +resaveSignals = TRUE +adjustBusPrefix = adjustBus_ +adjustBusBits = 1 +adjustBusSettings = 69889 +maskPowerOff = TRUE +maskIsolation = TRUE +maskRetention = TRUE +maskDrivingPowerOff = TRUE +maskToggle = TRUE +autoBackupSignals = off 5 "\"/home/shbyang/verdiLog\"" "\"novas_autosave_sig\"" +signal_rc_attribute = 65535 +signal_rc_alias_attribute = 0 +ConvertAttr1 = -inc FALSE +ConvertAttr2 = -hier FALSE +ConvertAttr3 = -ucase FALSE +ConvertAttr4 = -lcase FALSE +ConvertAttr5 = -org FALSE +ConvertAttr6 = -mem 24 +ConvertAttr7 = -deli . +ConvertAttr8 = -hier_scope FALSE +ConvertAttr9 = -inst_array FALSE +ConvertAttr10 = -vhdlnaming FALSE +ConvertAttr11 = -orgScope FALSE +analogFmtPrecision = Automatic 2 +confirmOverwrite = TRUE +confirmExit = TRUE +confirmGetAll = TRUE +printTimeRange = TRUE 0.000000 0.000000 0.000000 +printPageRange = TRUE 1 1 +printOption = 0 +printBasic = 1 0 0 FALSE FALSE +printDest = -printer {} +printSignature = {%f %h %t} {} +curveWindow_Drag&Drop_Mode = TRUE +hspiceIncOpenMode = TRUE +pcSelectMode = TRUE +hierarchyDelimiter = / +RecentFile1 = "\"/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdplus_000.fsdb\"" +open_file_time_range = FALSE +value_window_aligment = Right +signal_window_alignment = Auto +ShowDeltaTime = TRUE +legend_window_font = -f COURIER12 -c ID_CYAN5 +value_window_font = -f COURIER12 -c ID_CYAN5 +curve_window_font = -f COURIER12 -c ID_CYAN5 +group_name_font = -f COURIER12 -c ID_GREEN5 +ruler_value_font = -f COURIER12 -c ID_CYAN5 +analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +comment_string_font = -f COURIER12 -c ID_RED5 +getsignal_form_font = -f COURIER12 +SigsCheckNum = on 1000 +filter_synthesized_net = off n +filterOutNet = on +filter_synthesized_instance = off +filterOutInstance = on +showGroupTree = TRUE +hierGroupDelim = / +MsgSeverityColor = {y \"Severity\"==\"1\" ID_RED5} {y \"Severity\"==\"2\" ID_RED6} {y \"Severity\"==\"3\" ID_RED7} {y \"Severity\"==\"4\" ID_RED8} {y \"Severity\"==\"5\" ID_ORANGE5} {y \"Severity\"==\"6\" ID_ORANGE6} {y \"Severity\"==\"7\" ID_ORANGE7} {y \"Severity\"==\"8\" \ +ID_GREEN7} {y \"Severity\"==\"9\" ID_GREEN6} {y \"Severity\"==\"10\" ID_GREEN5} +AutoApplySeverityColor = TRUE +AutoAdjustMsgWidthByLabel = off +verilogStrengthDispType = type1 +waveDblClkActiveTrace = on +autoConnectTBrowser = FALSE +connectTBrowserInContainer = TRUE +SEQShowComparisonIcon = TRUE +SEQAddDriverLoadInSameGroup = TRUE +autoSyncCursorMarker = FALSE +autoSyncHorizontalRange = FALSE +autoSyncVerticalScroll = FALSE +[cov_hier_name_column] +justify = TRUE +[coverageColors] +sou_uncov = TRUE +sou_pc = TRUE +sou_cov = TRUE +sou_exuncov = TRUE +sou_excov = TRUE +sou_unreach = TRUE +sou_unreachcon = TRUE +sou_fillColor_uncov = red +sou_fillColor_pc = yellow +sou_fillColor_cov = green3 +sou_fillColor_exuncov = grey +sou_fillColor_excov = #3C9371 +sou_fillColor_unreach = grey +sou_fillColor_unreachcon = orange +numberOfBins = 6 +rangeMin_0 = 0 +rangeMax_0 = 20 +fillColor_0 = #FF6464 +rangeMin_1 = 20 +rangeMax_1 = 40 +fillColor_1 = #FF9999 +rangeMin_2 = 40 +rangeMax_2 = 60 +fillColor_2 = #FF8040 +rangeMin_3 = 60 +rangeMax_3 = 80 +fillColor_3 = #FFFF99 +rangeMin_4 = 80 +rangeMax_4 = 100 +fillColor_4 = #99FF99 +rangeMin_5 = 100 +rangeMax_5 = 100 +fillColor_5 = #64FF64 +[coveragesetting] +assertTopoMode = FALSE +urgAppendOptions = +group_instance_new_format_name = TRUE +showvalue = FALSE +computeGroupsScoreByRatio = FALSE +computeGroupsScoreByInst = FALSE +showConditionId = FALSE +showfullhier = FALSE +nameLeftAlignment = TRUE +showAllInfoInTooltips = FALSE +copyItemHvpName = TRUE +ignoreGroupWeight = FALSE +absTestName = FALSE +HvpMergeTool = +ShowMergeMenuItem = FALSE +fsmScoreMode = transition +[eco] +NameRule = +IsFreezeSilicon = FALSE +cellQuantityManagement = FALSE +ManageMode = INSTANCE_NAME +SpareCellsPinsManagement = TRUE +LogCommitReport = FALSE +InputPinStatus = 1 +OutputPinStatus = 2 +RevisedComponentColor = ID_BLUE5 +SpareCellColor = ID_RED5 +UserName = shbyang +CommentFormat = Novas ECO updated by ${UserName} ${Date} ${Time} +PrefixN = eco_n +PrefixP = eco_p +PrefixI = eco_i +DefaultTieUpNet = 1'b1 +DefaultTieDownNet = 1'b0 +MultipleInstantiations = TRUE +KeepClockPinConnection = FALSE +KeepAsyncResetPinConnection = FALSE +ScriptFileModeType = 1 +MagmaScriptPower = VDD +MagmaScriptGround = GND +ShowModeMsg = TRUE +AstroScriptPower = VDD +AstroScriptGround = VSS +ClearFloatingPorts = FALSE +[eco_connection] +Port/NetIsUnique = TRUE +SerialNet = 0 +SerialPort = 0 +SerialInst = 0 +[finsim] +TPLanguage = Verilog +TPName = Super-FinSim +TPPath = TOP.sim +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[hvpsetting] +importExcelXMLOptions = +use_test_loca_as_source = FALSE +autoTurnOffHideMeetGoalInit = FALSE +autoTurnOffHideMeetGoal = TRUE +autoTurnOffModifierInit = FALSE +autoTurnOffModifier = TRUE +enableNumbering = TRUE +autoSaveCheck = TRUE +autoSaveTime = 5 +ShowMissingScore = TRUE +enableFeatureId = FALSE +enable_HVP_FEAT_ID = FALSE +enableMeasureConcealment = FALSE +HvpCloneHierShowMsgAgain = 1 +HvpCloneHierType = tree +HvpCloneHierMetrics = Line,Cond,FSM,Toggle,Branch,Assert +autoRecalPlanAfterLoadingCovDBUserDataPlan = false +warnMeAutoRecalPlanAfterLoadingCovDBUserDataPlan = true +autoRecalExclWithPlan = false +warnMeAutoRecalExclWithPlan = true +autoRecalPlanWithExcl = false +warnMeAutoRecalPlanWithExcl = true +warnPopupWarnWhenMultiFilters = true +warnPopupWarnIfHvpReadOnly = true +unmappedObjsReportLevel = def_var_inst +unmappedObjsReportInst = true +unmappedObjsNumOfObjs = High +[ikos] +TPLanguage = VHDL +TPName = Voyager +TPPath = vsh +TPOption = -X +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[imp] +options = NULL +libPath = NULL +libDir = NULL +[nCompare] +ErrorViewport = 80 180 800 550 +EditorViewport = 409 287 676 475 +EditorHeightWidth = 802 380 +WaveCommand = "novas" +WaveArgs = "-nWave" +[nCompare.Wnd0] +ViewByHier = FALSE +[nMemory] +dispMode = ADDR_HINT +addrColWidth = 120 +valueColWidth = 100 +showCellBitRangeWithAddr = TRUE +wordsShownInOneRow = 8 +syncCursorTime = FALSE +fixCellColumnWidth = FALSE +font = Courier 12 +[planColors] +plan_fillColor_inactive = lightGray +plan_fillColor_warning = orange +plan_fillColor_error = red +plan_fillColor_invalid = #F0DCDB +plan_fillColor_subplan = lightGray +[schematics] +viewport = 178 262 638 516 +schBackgroundColor = black lineSolid +schBackgroundColor_qt = #000000 qt_solidLine 1 +schBodyColor = orange6 lineSolid +schBodyColor_qt = #ffb973 qt_solidLine 1 +schAsmBodyColor = blue7 lineSolid +schAsmBodyColor_qt = #a5a5ff qt_solidLine 1 +schPortColor = orange6 lineSolid +schPortColor_qt = #ffb973 qt_solidLine 1 +schCellNameColor = Gray6 lineSolid +schCellNameColor_qt = #e0e0e0 qt_solidLine 1 +schCLKNetColor = red6 lineSolid +schCLKNetColor_qt = #ff7373 qt_solidLine 1 +schPWRNetColor = red4 lineSolid +schPWRNetColor_qt = #ff0101 qt_solidLine 1 +schGNDNetColor = cyan4 lineSolid +schGNDNetColor_qt = #01ffff qt_solidLine 1 +schSIGNetColor = green8 lineSolid +schSIGNetColor_qt = #cdffcd qt_solidLine 1 +schTraceColor = yellow4 lineSolid +schTraceColor_qt = #ffff01 qt_solidLine 2 +schBackAnnotateColor = white lineSolid +schBackAnnotateColor_qt = #ffffff qt_solidLine 1 +schValue0 = yellow4 lineSolid +schValue0_qt = #ffff01 qt_solidLine 1 +schValue1 = green3 lineSolid +schValue1_qt = #008000 qt_solidLine 1 +schValueX = red4 lineSolid +schValueX_qt = #ff0101 qt_solidLine 1 +schValueZ = purple7 lineSolid +schValueZ_qt = #ffcdff qt_solidLine 1 +dimColor = cyan2 lineSolid +dimColor_qt = #008080 qt_solidLine 1 +schPreSelColor = green4 lineDash +schPreSelColor_qt = #01ff01 qt_dashLine 2 +schSIGBusNetColor = green8 lineSolid +schSIGBusNetColor_qt = #cdffcd qt_solidLine +schGNDBusNetColor = cyan4 lineSolid +schGNDBusNetColor_qt = #01ffff qt_solidLine +schPWRBusNetColor = red4 lineSolid +schPWRBusNetColor_qt = #ff0101 qt_solidLine +schCLKBusNetColor = red6 lineSolid +schCLKBusNetColor_qt = #ff7373 qt_solidLine +schEdgeSensitiveColor = orange6 lineSolid +schEdgeSensitiveColor_qt = #ffb973 qt_solidLine +schAnnotColor = cyan4 lineSolid +schAnnotColor_qt = #01ffff qt_solidLine +schInstNameColor = orange6 lineSolid +schInstNameColor_qt = #ffb973 qt_solidLine +schPortNameColor = cyan4 lineSolid +schPortNameColor_qt = #01ffff qt_solidLine +schAsmLatchColor = cyan4 lineSolid +schAsmLatchColor_qt = #01ffff qt_solidLine +schAsmRegColor = cyan4 lineSolid +schAsmRegColor_qt = #01ffff qt_solidLine +schAsmTriColor = cyan4 lineSolid +schAsmTriColor_qt = #01ffff qt_solidLine +pre_select = True +ShowPassThroughNet = False +ComputedAnnotColor = ID_PURPLE5 +[schematics_print] +Signature = FALSE +DesignName = PCU +DesignerName = bai +SignatureLocation = LowerRight +MultiPage = TRUE +AutoSliver = FALSE +[sourceColors] +BackgroundActive = gray88 +BackgroundInactive = lightgray +InactiveCode = dimgray +Selection = darkblue +Standard = black +Keyword = blue +Comment = gray25 +Number = black +String = black +Identifier = darkred +Inline = green +colorIdentifier = green +Value = darkgreen +MacroBackground = white +Missing = #400040 +[specColors] +top_plan_linked = #ADFFA6 +top_plan_ignore = #D3D3D3 +top_plan_todo = #EECBAD +sub_plan_ignore = #919191 +sub_plan_todo = #EFAFAF +sub_plan_linked = darkorange +[spec_link_setting] +use_spline = true +goto_section = false +exclude_ignore = true +truncate_abstract = false +abstract_length = 999 +compare_strategy = 2 +auto_apply_margin = FALSE +margin_top = 0.80 +margin_bottom = 0.80 +margin_left = 0.50 +margin_right = 0.50 +margin_unit = inches +[spiceDebug] +ThroughNet = ID_YELLOW5 +InstrumentSig = ID_GREEN5 +InterfaceElement = ID_GREEN5 +Run-timeInterfaceElement = ID_BLUE5 +HighlightThroughNet = TRUE +HighlightInterfaceElement = TRUE +HighlightRuntimeInterfaceElement = TRUE +HighlightSameNet = TRUE +[surefire] +TPLanguage = Verilog +TPName = SureFire +TPPath = verilog +TPOption = +AddImportArgument = TRUE +LineBreakWithScope = TRUE +StopAfterCompileOption = -tcl +[turboSchema_Printer_Options] +Orientation = Landscape +[turbo_library] +bdb_load_scope = +[vdCovFilteringSearchesStrings] +keepLastUsedFiltersMaxNum = 10 +[verisity] +TPLanguage = Verilog +TPName = "Verisity SpeXsim" +TPPath = vlg +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = TRUE +StopAfterCompileOption = -s +[wave.0] +viewPort = 0 27 1920 309 152 65 +[wave.1] +viewPort = 127 219 960 332 100 65 +[wave.2] +viewPort = 38 314 686 205 100 65 +[wave.3] +viewPort = 63 63 700 400 65 41 +[wave.4] +viewPort = 84 84 700 400 65 41 +[wave.5] +viewPort = 92 105 700 400 65 41 +[wave.6] +viewPort = 0 0 700 400 65 41 +[wave.7] +viewPort = 21 21 700 400 65 41 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/novas_dump.log b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/novas_dump.log new file mode 100644 index 0000000..78fdfed --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/novas_dump.log @@ -0,0 +1,408 @@ +####################################################################################### +# log primitive debug message of FSDB dumping # +# This is for R&D to analyze when there are issues happening when FSDB dump # +####################################################################################### +ANF: vcsd_get_serial_mode_status('./simv: undefined symbol: vcsd_get_serial_mode_status') +ANF: vcsd_enable_sva_success_callback('./simv: undefined symbol: vcsd_enable_sva_success_callback') +ANF: vcsd_disable_sva_success_callback('./simv: undefined symbol: vcsd_disable_sva_success_callback') +ANF: vcsd_get_power_scope_name('./simv: undefined symbol: vcsd_get_power_scope_name') +ANF: vcsd_begin_no_value_var_info('./simv: undefined symbol: vcsd_begin_no_value_var_info') +ANF: vcsd_end_no_value_var_info('./simv: undefined symbol: vcsd_end_no_value_var_info') +ANF: vcsd_remove_xprop_merge_mode_callback('./simv: undefined symbol: vcsd_remove_xprop_merge_mode_callback') +ANF: vhpi_get_cb_info('./simv: undefined symbol: vhpi_get_cb_info') +ANF: vhpi_free_handle('./simv: undefined symbol: vhpi_free_handle') +ANF: vhpi_fetch_vcsd_handle('./simv: undefined symbol: vhpi_fetch_vcsd_handle') +ANF: vhpi_fetch_vpi_handle('./simv: undefined symbol: vhpi_fetch_vpi_handle') +ANF: vhpi_has_verilog_parent('./simv: undefined symbol: vhpi_has_verilog_parent') +ANF: vhpi_is_verilog_scope('./simv: undefined symbol: vhpi_is_verilog_scope') +ANF: scsd_xprop_is_enabled('./simv: undefined symbol: scsd_xprop_is_enabled') +ANF: scsd_xprop_sig_is_promoted('./simv: undefined symbol: scsd_xprop_sig_is_promoted') +ANF: scsd_xprop_int_xvalue('./simv: undefined symbol: scsd_xprop_int_xvalue') +ANF: scsd_xprop_bool_xvalue('./simv: undefined symbol: scsd_xprop_bool_xvalue') +ANF: scsd_xprop_enum_xvalue('./simv: undefined symbol: scsd_xprop_enum_xvalue') +ANF: scsd_xprop_register_merge_mode_cb('./simv: undefined symbol: scsd_xprop_register_merge_mode_cb') +ANF: scsd_xprop_delete_merge_mode_cb('./simv: undefined symbol: scsd_xprop_delete_merge_mode_cb') +ANF: scsd_xprop_get_merge_mode('./simv: undefined symbol: scsd_xprop_get_merge_mode') +ANF: scsd_thread_get_info('./simv: undefined symbol: scsd_thread_get_info') +ANF: scsd_thread_vc_init('./simv: undefined symbol: scsd_thread_vc_init') +ANF: scsd_master_set_delta_sync_cbk('./simv: undefined symbol: scsd_master_set_delta_sync_cbk') +ANF: scsd_fgp_get_fsdb_cores('./simv: undefined symbol: scsd_fgp_get_fsdb_cores') +ANF: msvEnableDumpingMode('./simv: undefined symbol: msvEnableDumpingMode') +ANF: msvGetVersion('./simv: undefined symbol: msvGetVersion') +ANF: msvGetInstProp('./simv: undefined symbol: msvGetInstProp') +ANF: msvIsSpiceEngineReady('./simv: undefined symbol: msvIsSpiceEngineReady') +ANF: msvSetAddProbeCallback('./simv: undefined symbol: msvSetAddProbeCallback') +ANF: msvGetInstHandle('./simv: undefined symbol: msvGetInstHandle') +ANF: msvGetProbeByInst('./simv: undefined symbol: msvGetProbeByInst') +ANF: msvGetSigHandle('./simv: undefined symbol: msvGetSigHandle') +ANF: msvGetProbeBySig('./simv: undefined symbol: msvGetProbeBySig') +ANF: msvGetProbeInfo('./simv: undefined symbol: msvGetProbeInfo') +ANF: msvRelease('./simv: undefined symbol: msvRelease') +ANF: msvSetVcCallbackFunc('./simv: undefined symbol: msvSetVcCallbackFunc') +ANF: msvCheckVcCallback('./simv: undefined symbol: msvCheckVcCallback') +ANF: msvAddVcCallback('./simv: undefined symbol: msvAddVcCallback') +ANF: msvRemoveVcCallback('./simv: undefined symbol: msvRemoveVcCallback') +ANF: msvGetLatestValue('./simv: undefined symbol: msvGetLatestValue') +ANF: msvSetEndofSimCallback('./simv: undefined symbol: msvSetEndofSimCallback') +ANF: msvIgnoredProbe('./simv: undefined symbol: msvIgnoredProbe') +ANF: msvGetThruNetInfo('./simv: undefined symbol: msvGetThruNetInfo') +ANF: msvFreeThruNetInfo('./simv: undefined symbol: msvFreeThruNetInfo') +ANF: PI_ace_get_output_time_unit('./simv: undefined symbol: PI_ace_get_output_time_unit') +ANF: PI_ace_sim_sync('./simv: undefined symbol: PI_ace_sim_sync') +ANF: msvGetRereadInitFile('./simv: undefined symbol: msvGetRereadInitFile') +ANF: msvSetBeforeRereadCallback('./simv: undefined symbol: msvSetBeforeRereadCallback') +ANF: msvSetAfterRereadCallback('./simv: undefined symbol: msvSetAfterRereadCallback') +ANF: msvSetForceCallback('./simv: undefined symbol: msvSetForceCallback') +ANF: msvSetReleaseCallback('./simv: undefined symbol: msvSetReleaseCallback') +ANF: msvGetForceStatus('./simv: undefined symbol: msvGetForceStatus') +ANF: vhdi_dt_get_type('./simv: undefined symbol: vhdi_dt_get_type') +ANF: vhdi_dt_get_key('./simv: undefined symbol: vhdi_dt_get_key') +ANF: vhdi_dt_get_vhdl_enum_info('./simv: undefined symbol: vhdi_dt_get_vhdl_enum_info') +ANF: vhdi_dt_get_vhdl_physical_info('./simv: undefined symbol: vhdi_dt_get_vhdl_physical_info') +ANF: vhdi_dt_get_vhdl_array_info('./simv: undefined symbol: vhdi_dt_get_vhdl_array_info') +ANF: vhdi_dt_get_vhdl_record_info('./simv: undefined symbol: vhdi_dt_get_vhdl_record_info') +ANF: vhdi_def_traverse_module('./simv: undefined symbol: vhdi_def_traverse_module') +ANF: vhdi_def_traverse_scope('./simv: undefined symbol: vhdi_def_traverse_scope') +ANF: vhdi_def_traverse_variable('./simv: undefined symbol: vhdi_def_traverse_variable') +ANF: vhdi_def_get_module_id_by_vhpi('./simv: undefined symbol: vhdi_def_get_module_id_by_vhpi') +ANF: vhdi_def_get_handle_by_module_id('./simv: undefined symbol: vhdi_def_get_handle_by_module_id') +ANF: vhdi_def_get_variable_info_by_vhpi('./simv: undefined symbol: vhdi_def_get_variable_info_by_vhpi') +ANF: vhdi_def_free('./simv: undefined symbol: vhdi_def_free') +ANF: vhdi_ist_traverse_scope('./simv: undefined symbol: vhdi_ist_traverse_scope') +ANF: vhdi_ist_traverse_variable('./simv: undefined symbol: vhdi_ist_traverse_variable') +ANF: vhdi_ist_convert_by_vhpi('./simv: undefined symbol: vhdi_ist_convert_by_vhpi') +ANF: vhdi_ist_clone('./simv: undefined symbol: vhdi_ist_clone') +ANF: vhdi_ist_free('./simv: undefined symbol: vhdi_ist_free') +ANF: vhdi_ist_hash_key('./simv: undefined symbol: vhdi_ist_hash_key') +ANF: vhdi_ist_compare('./simv: undefined symbol: vhdi_ist_compare') +ANF: vhdi_ist_get_value_addr('./simv: undefined symbol: vhdi_ist_get_value_addr') +ANF: vhdi_set_scsd_callback('./simv: undefined symbol: vhdi_set_scsd_callback') +ANF: vhdi_cbk_set_force_callback('./simv: undefined symbol: vhdi_cbk_set_force_callback') +ANF: vhdi_trigger_init_force('./simv: undefined symbol: vhdi_trigger_init_force') +ANF: vhdi_ist_check_scsd_callback('./simv: undefined symbol: vhdi_ist_check_scsd_callback') +ANF: vhdi_ist_add_scsd_callback('./simv: undefined symbol: vhdi_ist_add_scsd_callback') +ANF: vhdi_ist_remove_scsd_callback('./simv: undefined symbol: vhdi_ist_remove_scsd_callback') +ANF: vhdi_ist_get_scsd_user_data('./simv: undefined symbol: vhdi_ist_get_scsd_user_data') +ANF: vhdi_add_time_change_callback('./simv: undefined symbol: vhdi_add_time_change_callback') +ANF: vhdi_get_real_value_by_value_addr('./simv: undefined symbol: vhdi_get_real_value_by_value_addr') +ANF: vhdi_get_64_value_by_value_addr('./simv: undefined symbol: vhdi_get_64_value_by_value_addr') +ANF: vhdi_xprop_inst_is_promoted('./simv: undefined symbol: vhdi_xprop_inst_is_promoted') +ANF: vdi_ist_convert_by_vhdi('./simv: undefined symbol: vdi_ist_convert_by_vhdi') +ANF: vhdi_ist_get_module_id('./simv: undefined symbol: vhdi_ist_get_module_id') +ANF: vhdi_refine_foreign_scope_type('./simv: undefined symbol: vhdi_refine_foreign_scope_type') +ANF: vhdi_flush_callback('./simv: undefined symbol: vhdi_flush_callback') +ANF: vhdi_set_orig_name('./simv: undefined symbol: vhdi_set_orig_name') +ANF: vhdi_set_dump_pt('./simv: undefined symbol: vhdi_set_dump_pt') +ANF: vhdi_get_fsdb_option('./simv: undefined symbol: vhdi_get_fsdb_option') +ANF: vhdi_fgp_get_mode('./simv: undefined symbol: vhdi_fgp_get_mode') +ANF: vhdi_node_register_composite_var('./simv: undefined symbol: vhdi_node_register_composite_var') +ANF: vhdi_node_analysis('./simv: undefined symbol: vhdi_node_analysis') +ANF: vhdi_node_id('./simv: undefined symbol: vhdi_node_id') +ANF: vhdi_node_ist_check_scsd_callback('./simv: undefined symbol: vhdi_node_ist_check_scsd_callback') +ANF: vhdi_node_ist_add_scsd_callback('./simv: undefined symbol: vhdi_node_ist_add_scsd_callback') +ANF: vhdi_node_ist_get_value_addr('./simv: undefined symbol: vhdi_node_ist_get_value_addr') +VCS compile option: + option[0]: ./simv + option[1]: -l + option[2]: sim.log + option[3]: -cm + option[4]: line+cond+fsm+tgl+branch + option[5]: -cm_dir + option[6]: ../../coverage/try/ + option[7]: -cm_name + option[8]: sine_1g + option[9]: +ENABLE_FSDB=1 + option[10]: /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/vcs1 + option[11]: -Mcc=gcc + option[12]: -Mcplusplus=g++ + option[13]: -Masflags= + option[14]: -Mcfl= -pipe -fPIC -O -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include + option[15]: -Mxcflags= -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include + option[16]: -Mldflags= -rdynamic + option[17]: -Mout=simv + option[18]: -Mamsrun= + option[19]: -Mvcsaceobjs= + option[20]: -Mobjects= /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvirsim.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/liberrorinf.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a + option[21]: -Mexternalobj= + option[22]: -Msaverestoreobj=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o + option[23]: -Mcrt0= + option[24]: -Mcrtn= + option[25]: -Mcsrc= + option[26]: -Msyslibs=/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lm + option[27]: -l + option[28]: compile.log + option[29]: -full64 + option[30]: -j8 + option[31]: +lint=TFIPC-L + option[32]: +v2k + option[33]: -debug_access+all + option[34]: +vpi + option[35]: +vcsd1 + option[36]: +itf+/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab + option[37]: -debug_region+cell+encrypt + option[38]: -P + option[39]: /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab + option[40]: +define+DUMP_FSDB + option[41]: -lca + option[42]: -q + option[43]: -timescale=1ns/1ps + option[44]: +nospecify + option[45]: -cm + option[46]: line+cond+fsm+tgl+branch + option[47]: -cm_dir + option[48]: ./coverage/simv.vdb + option[49]: -picarchive + option[50]: -P + option[51]: /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab + option[52]: -fsdb + option[53]: -sverilog + option[54]: -gen_obj + option[55]: -f + option[56]: filelist_vlg.f + option[57]: +incdir+./../../rtl/define + option[58]: +incdir+./../../rtl/qubitmcu + option[59]: +incdir+./../../model + option[60]: -load + option[61]: /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/libnovas.so:FSDBDumpCmd + option[62]: timescale=1ns/1ps +Chronologic Simulation VCS Release O-2018.09-SP2_Full64 +Linux 3.10.0-1160.92.1.el7.x86_64 #1 SMP Tue Jun 20 11:48:01 UTC 2023 x86_64 +CPU cores: 96 +Limit information: +====================================== +cputime unlimited +filesize unlimited +datasize unlimited +stacksize 8194 kbytes +coredumpsize 0 kbytes +memoryuse unlimited +vmemoryuse unlimited +descriptors 4096 +memorylocked 64 kbytes +maxproc 4096 +====================================== +(Special)Runtime environment variables: + +Runtime environment variables: +XMODIFIERS=@im=ibus +SPECTRE_DEFAULTS=-E +SHELL=/bin/bash +VTE_VERSION=5204 +AMS_ENABLE_NOISE=YES +_=/bin/csh +OA_UNSUPPORTED_PLAT=linux_rhel50_gcc44x +SPECMAN_DIR=/opt/cadence/INCISIVE152/components/sn +HISTCONTROL=ignoredups +SNPSLMD_LICENSE_FILE=27050@cryo1 +MENTOR_HOME=/opt/mentor +XDG_DATA_DIRS=/home/shbyang/.local/share/flatpak/exports/share:/var/lib/flatpak/exports/share:/usr/local/share:/usr/share +DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-pbYbSoHCDo,guid=6bec37f851a0ec63831138606819dc51 +MACHTYPE=x86_64 +LESSOPEN=||/usr/bin/lesspipe.sh %s +CDSROOT=/opt/cadence/IC618 +FM_HOME=/opt/synopsys/fm/L-2016.03-SP1 +CDS_LIC_ONLY=1 +CDSDIR=/opt/cadence/IC618 +PATH=/opt/compiler/V0P100:/opt/synopsys/fpga/K-2015.09/bin:/opt/synopsys/vc_stat/vc_static/V-2023.12/bin:/opt/synopsys/wv/N-2017.12-SP2/bin:/opt/synopsys/hspice/N-2017.12-SP2/hspice/bin:/opt/synopsys/idq/O-2018.06-SP1/linux64/iddq/bin:/opt/synopsys/txs/O-2018.06-SP1/bin:/opt/synopsys/lc/O-2018.06-SP1/bin:/opt/synopsys/starrc/O-2018.06-SP1/bin:/opt/synopsys/fm/L-2016.03-SP1/bin:/opt/synopsys/pwr/O-2018.06-SP3/bin:/opt/synopsys/pts/O-2018.06-SP1/bin:/opt/synopsys/syn/O-2018.06-SP1/bin:/opt/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/opt/synopsys/vcs-mx/O-2018.09-SP2/gui/dve/bin:/opt/synopsys/vcs-mx/O-2018.09-SP2/bin:/opt/synopsys/scl/2018.06/linux64/bin:/opt/compiler/V0P100:/opt/synopsys/fpga/K-2015.09/bin:/opt/synopsys/vc_stat/vc_static/V-2023.12/bin:/opt/synopsys/wv/N-2017.12-SP2/bin:/opt/synopsys/hspice/N-2017.12-SP2/hspice/bin:/opt/synopsys/idq/O-2018.06-SP1/linux64/iddq/bin:/opt/synopsys/txs/O-2018.06-SP1/bin:/opt/synopsys/lc/O-2018.06-SP1/bin:/opt/synopsys/starrc/O-2018.06-SP1/bin:/opt/synopsys/fm/L-2016.03-SP1/bin:/opt/synopsys/pwr/O-2018.06-SP3/bin:/opt/synopsys/pts/O-2018.06-SP1/bin:/opt/synopsys/syn/O-2018.06-SP1/bin:/opt/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/opt/synopsys/vcs-mx/O-2018.09-SP2/gui/dve/bin:/opt/synopsys/vcs-mx/O-2018.09-SP2/bin:/opt/synopsys/scl/2018.06/linux64/bin:/opt/xilinx/Vivado/2019.2/bin:/opt/xilinx/DocNav:/usr/local/git/bin:/usr/lib64/qt-3.3/bin:/usr/local/bin:/bin:/usr/bin:/usr/local/sbin:/usr/sbin:/home/shbyang/.local/bin:/home/shbyang/bin:/opt/cadence/IC618/tools/bin:/opt/cadence/IC618/tools/dfII/bin:/opt/cadence/IC618/tools/plot/bin:/opt/cadence/SPECTRE181/bin:/opt/cadence/SPECTRE181/tools/bin:/opt/cadence/INNOVUS181/bin:/opt/cadence/INNOVUS181/tools/bin:/opt/cadence/GENUS152/bin:/opt/cadence/GENUS152/tools/bin:/opt/cadence/INCISIVE152/bin:/opt/cadence/INCISIVE152/tools/bin:/opt/cadence/INCISIVE152/tools.lnx86/bin:/opt/cadence/INCISIVE152/tools/dfII/bin:/opt/cadence/INCISIVE152/tools.lnx86/dfII/bin:/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/bin:/opt/xilinx/Vivado/2019.2//bin:/opt/xilinx/Vivado/2019.2//bin/unwrapped/lnx64.o/:/opt/cadence/IC618/tools/bin:/opt/cadence/IC618/tools/dfII/bin:/opt/cadence/IC618/tools/plot/bin:/opt/cadence/SPECTRE181/bin:/opt/cadence/SPECTRE181/tools/bin:/opt/cadence/INNOVUS181/bin:/opt/cadence/INNOVUS181/tools/bin:/opt/cadence/GENUS152/bin:/opt/cadence/GENUS152/tools/bin:/opt/cadence/INCISIVE152/bin:/opt/cadence/INCISIVE152/tools/bin:/opt/cadence/INCISIVE152/tools.lnx86/bin:/opt/cadence/INCISIVE152/tools/dfII/bin:/opt/cadence/INCISIVE152/tools.lnx86/dfII/bin:/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/bin:/opt/xilinx/Vivado/2019.2//bin:/opt/xilinx/Vivado/2019.2//bin/unwrapped/lnx64.o/ +MGC_PDF_REDER=evince +XILINX_VIVADO=/opt/xilinx/Vivado/2019.2 +CDS_ROOT=/opt/cadence/IC618 +QT_GRAPHICSSYSTEM_CHECKED=1 +SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/24088,unix/unix:/tmp/.ICE-unix/24088 +SPECTRE_HOME=/opt/cadence/SPECTRE181 +XDG_RUNTIME_DIR=/run/user/1019 +VENDOR=unknown +CDS_AUTO_64BIT=ALL +XDG_MENU_PREFIX=gnome- +LS_COLORS=rs=0:di=38;5;27:ln=38;5;51:mh=44;38;5;15:pi=40;38;5;11:so=38;5;13:do=38;5;5:bd=48;5;232;38;5;11:cd=48;5;232;38;5;3:or=48;5;232;38;5;9:mi=05;48;5;232;38;5;15:su=48;5;196;38;5;15:sg=48;5;11;38;5;16:ca=48;5;196;38;5;226:tw=48;5;10;38;5;16:ow=48;5;10;38;5;21:st=48;5;21;38;5;15:ex=38;5;34:*.tar=38;5;9:*.tgz=38;5;9:*.arc=38;5;9:*.arj=38;5;9:*.taz=38;5;9:*.lha=38;5;9:*.lz4=38;5;9:*.lzh=38;5;9:*.lzma=38;5;9:*.tlz=38;5;9:*.txz=38;5;9:*.tzo=38;5;9:*.t7z=38;5;9:*.zip=38;5;9:*.z=38;5;9:*.Z=38;5;9:*.dz=38;5;9:*.gz=38;5;9:*.lrz=38;5;9:*.lz=38;5;9:*.lzo=38;5;9:*.xz=38;5;9:*.bz2=38;5;9:*.bz=38;5;9:*.tbz=38;5;9:*.tbz2=38;5;9:*.tz=38;5;9:*.deb=38;5;9:*.rpm=38;5;9:*.jar=38;5;9:*.war=38;5;9:*.ear=38;5;9:*.sar=38;5;9:*.rar=38;5;9:*.alz=38;5;9:*.ace=38;5;9:*.zoo=38;5;9:*.cpio=38;5;9:*.7z=38;5;9:*.rz=38;5;9:*.cab=38;5;9:*.jpg=38;5;13:*.jpeg=38;5;13:*.gif=38;5;13:*.bmp=38;5;13:*.pbm=38;5;13:*.pgm=38;5;13:*.ppm=38;5;13:*.tga=38;5;13:*.xbm=38;5;13:*.xpm=38;5;13:*.tif=38;5;13:*.tiff=38;5;13:*.png=38;5;13:*.svg=38;5;13:*.svgz=38;5;13:*.mng=38;5;13:*.pcx=38;5;13:*.mov=38;5;13:*.mpg=38;5;13:*.mpeg=38;5;13:*.m2v=38;5;13:*.mkv=38;5;13:*.webm=38;5;13:*.ogm=38;5;13:*.mp4=38;5;13:*.m4v=38;5;13:*.mp4v=38;5;13:*.vob=38;5;13:*.qt=38;5;13:*.nuv=38;5;13:*.wmv=38;5;13:*.asf=38;5;13:*.rm=38;5;13:*.rmvb=38;5;13:*.flc=38;5;13:*.avi=38;5;13:*.fli=38;5;13:*.flv=38;5;13:*.gl=38;5;13:*.dl=38;5;13:*.xcf=38;5;13:*.xwd=38;5;13:*.yuv=38;5;13:*.cgm=38;5;13:*.emf=38;5;13:*.axv=38;5;13:*.anx=38;5;13:*.ogv=38;5;13:*.ogx=38;5;13:*.aac=38;5;45:*.au=38;5;45:*.flac=38;5;45:*.mid=38;5;45:*.midi=38;5;45:*.mka=38;5;45:*.mp3=38;5;45:*.mpc=38;5;45:*.ogg=38;5;45:*.ra=38;5;45:*.wav=38;5;45:*.axa=38;5;45:*.oga=38;5;45:*.spx=38;5;45:*.xspf=38;5;45: +MOZILLA_HOME=/usr/bin/firefox +SSH_AUTH_SOCK=/run/user/1019/keyring/ssh +DISPLAY=unix:17 +MGC_HOME=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11 +IMSETTINGS_INTEGRATE_DESKTOP=yes +HOME=/home/shbyang +VCS_HOME=/opt/synopsys/vcs-mx/O-2018.09-SP2 +PWD=/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g +FPGA_HOME=/opt/synopsys/fpga/K-2015.09 +SSH_AGENT_PID=24257 +CALIBRE_HOME=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11 +MGC_CALIBRE_REALTIME_VIRTUOSO_ENABLED=1 +VERDI_HOME=/opt/synopsys/verdi/Verdi_O-2018.09-SP2 +MGLS_LICENSE_FILE=/opt/mentor/license/license.dat +PT_HOME=/opt/synopsys/pts/O-2018.06-SP1 +SYNOPSYS=/opt/synopsys +LD_LIBRARY_PATH=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/shared/pkgs/icv/tools/calibre_client/lib/64 +SPECMAN_HOME=/opt/cadence/INCISIVE152/components/sn +VRST_HOME=/opt/cadence/INCISIVE152 +CDS_SPECTRE_FBENABLE=1 +LOGNAME=shbyang +TERM=xterm-256color +INNOVUS_HOME=/opt/cadence/INNOVUS181 +CDS_LIC_FILE=/opt/cadence/license/license.dat +HSPICE_HOME=/opt/synopsys/hspice/N-2017.12-SP2 +GNOME_DESKTOP_SESSION_ID=this-is-deprecated +HOSTNAME=cryo1 +GENUS_HOME=/opt/cadence/GENUS152 +MGC_CALIBRE_REALTIME_VIRTUOSO_SAVE_MESSENGER_CELL=1 +COLORTERM=truecolor +PWR_HOME=/opt/synopsys/pwr/O-2018.06-SP3 +QT_IM_MODULE=ibus +OSTYPE=linux +SHLVL=6 +GNOME_SHELL_SESSION_MODE=classic +XDG_SESSION_ID=c34 +USER=shbyang +QTLIB=/usr/lib64/qt-3.3/lib +XDG_CURRENT_DESKTOP=GNOME +VNCDESKTOP=cryo1:17 (shbyang) +INCISIVE_HOME=/opt/cadence/INCISIVE152 +CDS=/opt/cadence/IC618 +WV_HOME=/opt/synopsys/wv/N-2017.12-SP2 +CDS_LOAD_ENV=CWD +VC_STATIC_HOME=/opt/synopsys/vc_stat/vc_static/V-2023.12 +IMSETTINGS_MODULE=none +starRC_HOME=/opt/synopsys/starrc/O-2018.06-SP1 +MAKEFLAGS= +MFLAGS= +SYN_HOME=/opt/synopsys/syn/O-2018.06-SP1 +MAIL=/var/spool/mail/shbyang +CADHOME=/opt/cadence +MGC_LIB_PATH=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/lib +CDSHOME=/opt/cadence/IC618 +LC_HOME=/opt/synopsys/lc/O-2018.06-SP1 +CADENCE_DIR=/opt/cadence/IC618 +CDS_INST_DIR=/opt/cadence/IC618 +NOVAS_HOME=/opt/synopsys/verdi/Verdi_O-2018.09-SP2 +XILINX_HOME=/opt/xilinx +DBUS_STARTER_BUS_TYPE=session +W3264_NO_HOST_CHECK=1 +SCL_HOME=/opt/synopsys/scl/2018.06 +HOSTTYPE=x86_64-linux +GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/300489a5_6011_46a1_a329_83b2a6d46428 +CDS_SPECTRERF_FBENABLE=1 +GNOME_TERMINAL_SERVICE=:1.1458 +HISTSIZE=1000 +GROUP=cryo +TXS_HOME=/opt/synopsys/txs/O-2018.06-SP1 +CDS_Netlisting_Mode=Analog +IDQ_HOME=/opt/synopsys/idq/O-2018.06-SP1 +QTINC=/usr/lib64/qt-3.3/include +QTDIR=/usr/lib64/qt-3.3 +VIVADO_HOME=/opt/xilinx/Vivado/2019.2/ +CDS_ENABLE_VMS=1 +LANG=C +MGC_CALIBRE_SAVE_ALL_RUNSET_VALUES=1 +CALIBRE_ENABLE_SKILL_PEXBA_MODE=1 +DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-pbYbSoHCDo,guid=6bec37f851a0ec63831138606819dc51 +HOST=cryo1 +MAKELEVEL=1 +VCS_HEAP_EXEC=true +VCS_PATHMAP_PRELOAD_DONE=1 +VCS_STACK_EXEC=true +VCS_EXEC_DONE=1 +LC_ALL=C +DVE=/opt/synopsys/vcs-mx/O-2018.09-SP2/gui/dve +SPECMAN_OUTPUT_TO_TTY=1 +Runtime command line arguments: +argv[0]=./simv +argv[1]=-l +argv[2]=sim.log +argv[3]=-cm +argv[4]=line+cond+fsm+tgl+branch +argv[5]=-cm_dir +argv[6]=../../coverage/try/ +argv[7]=-cm_name +argv[8]=sine_1g +argv[9]=+ENABLE_FSDB=1 +316 profile - 100 + CPU/Mem usage: 0.080 sys, 0.350 user, 316.72M mem +317 Fri Mar 13 16:24:06 2026 +318 pliAppInit +319 FSDB_GATE is set. +320 FSDB_RTL is set. +321 Enable Parallel Dumping. +322 pliAppMiscSet: New Sim Round +323 pliEntryInit +324 LIBSSCORE=found /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUXAMD64/libsscore_vcs201809.so through $NOVAS_HOME setting. +325 FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019 +326 (C) 1996 - 2019 by Synopsys, Inc. +327 FSDB_VCS_ENABLE_FAST_VC is enable +328 sps_call_fsdbAutoSwitchDumpfile_main_vd at 0 : ../../sim/chip_top/TB.sv(57) +329 sps_call_fsdbAutoSwitchDumpfile at 0 : ../../sim/chip_top/TB.sv(57) +330 argv[0]: (500) +331 argv[1]: (./verdplus.fsdb) +332 argv[2]: (1000000) +333 *Verdi* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file. +334 *Verdi* FSDB: The switch FSDB file size might not match the input size (500MB) because of performance concerns. +335 *Verdi* FSDB: To have the FSDB file size match the input size (500MB), set the FSDB_ENV_PRECISE_AUTOSWITCH environment, though the dumping performance might decrease. +336 *Verdi* : Enable automatic switching of the FSDB file. +337 *Verdi* : (Filename='./verdplus', Limit Size=500MB, File Amount=1000000). +338 *Verdi* : Create FSDB file './verdplus_000.fsdb' +339 compile option from '/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcs_rebuild'. +340 "vcs '-full64' '-j8' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+all' '-debug_region+cell+encrypt' '-P' '/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab' '/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a' '+define+DUMP_FSDB' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-cm' 'line+cond+fsm+tgl+branch' '-cm_dir' './coverage/simv.vdb' '-f' 'filelist_vlg.f' '+incdir+./../../rtl/define' '+incdir+./../../rtl/qubitmcu' '+incdir+./../../model' 2>&1" +341 *Verdi* : Create the file './verdplus.log' to log the time range of each FSDB file. +342 *Verdi* : Create virtual FSDB file './verdplus.vf' to log each FSDB file. +343 sps_call_fsdbDumpvars_vd_main at 0 : ../../sim/chip_top/TB.sv(58) +344 [spi_vcs_vd_ppi_create_root]: no upf option +345 FSDB dumper cannot dump UPF related power signal ($power_tree): no ppiPowerNetwork. +346 *Verdi* : Begin traversing the scopes, layer (0). +347 *Verdi* : End of traversing. +348 pliAppHDL_DumpVarComplete traverse var: profile - + CPU/Mem usage: 0.090 sys, 0.420 user, 413.95M mem + incr: 0.010 sys, 0.070 user, 9.70M mem + accu: 0.010 sys, 0.070 user, 9.70M mem + accu incr: 0.010 sys, 0.070 user, 9.70M mem + + Count usage: 12707 var, 14739 idcode, 7320 callback + incr: 12707 var, 14739 idcode, 7320 callback + accu: 12707 var, 14739 idcode, 7320 callback + accu incr: 12707 var, 14739 idcode, 7320 callback +349 Fri Mar 13 16:24:07 2026 +350 pliAppHDL_DumpVarComplete: profile - + CPU/Mem usage: 0.100 sys, 0.420 user, 415.00M mem + incr: 0.010 sys, 0.000 user, 1.05M mem + accu: 0.020 sys, 0.070 user, 10.75M mem + accu incr: 0.010 sys, 0.000 user, 1.05M mem + + Count usage: 12707 var, 14739 idcode, 7320 callback + incr: 0 var, 0 idcode, 0 callback + accu: 12707 var, 14739 idcode, 7320 callback + accu incr: 0 var, 0 idcode, 0 callback +351 Fri Mar 13 16:24:07 2026 +352 sps_call_fsdbDumpMDA_vd_main at 0 : ../../sim/chip_top/TB.sv(59) +353 *Verdi* : Begin traversing the MDAs, layer (0). +354 *Verdi* : Enable +mda and +packedmda dumping. +355 *Verdi* : End of traversing the MDAs. +356 pliAppHDL_DumpVarComplete traverse var: profile - + CPU/Mem usage: 0.100 sys, 0.440 user, 418.83M mem + incr: 0.000 sys, 0.020 user, 3.83M mem + accu: 0.000 sys, 0.020 user, 3.83M mem + accu incr: 0.000 sys, 0.020 user, 3.83M mem + + Count usage: 80429 var, 81757 idcode, 7372 callback + incr: 67722 var, 67018 idcode, 52 callback + accu: 67722 var, 67018 idcode, 52 callback + accu incr: 67722 var, 67018 idcode, 52 callback +357 Fri Mar 13 16:24:07 2026 +358 pliAppHDL_DumpVarComplete: profile - + CPU/Mem usage: 0.100 sys, 0.460 user, 426.30M mem + incr: 0.000 sys, 0.020 user, 7.47M mem + accu: 0.000 sys, 0.040 user, 11.30M mem + accu incr: 0.000 sys, 0.020 user, 7.47M mem + + Count usage: 80429 var, 81757 idcode, 7372 callback + incr: 0 var, 0 idcode, 0 callback + accu: 67722 var, 67018 idcode, 52 callback + accu incr: 0 var, 0 idcode, 0 callback +359 Fri Mar 13 16:24:07 2026 +360 End of simulation at 479076480 +361 Fri Mar 13 16:24:18 2026 +362 Begin FSDB profile info: +363 FSDB Writer : bc1(46410999) bcn(4266969) mtf/stf(0/0) +FSDB Writer elapsed time : flush(0.354180) io wait(0.000000) theadpool wait(0.000000) target functin(0.000000) +FSDB Writer cpu time : MT Compression : 0 +364 End FSDB profile info +365 Parallel profile - Flush:4 Expand:0 ProduceWait:0 ConsumerWait:585 BlockUsed:585 +366 ProduceTime:12.620525258 ConsumerTime:6.997658838 Buffer:64MB +367 SimExit +368 Sim process exit diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/sim.log b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/sim.log new file mode 100644 index 0000000..9e3b128 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/sim.log @@ -0,0 +1,831 @@ +Command: /home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/./simv -l sim.log -cm line+cond+fsm+tgl+branch -cm_dir ../../coverage/try/ -cm_name sine_1g +ENABLE_FSDB=1 +Chronologic VCS simulator copyright 1991-2018 +Contains Synopsys proprietary information. +Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64; Mar 13 16:24 2026 +Information: *** Instance TB.U_da4008_chip_top.digital_top.u_dw_stream_sync is the DW_stream_sync Clock Domain Crossing Module *** +../../../../case/config/try//sine_1g.txt +../../data_RTL/try/sine_1g.txt +*Verdi* Loading libsscore_vcs201809.so +FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019 +(C) 1996 - 2019 by Synopsys, Inc. +*Verdi* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file. +*Verdi* FSDB: The switch FSDB file size might not match the input size (500MB) because of performance concerns. +*Verdi* FSDB: To have the FSDB file size match the input size (500MB), set the FSDB_ENV_PRECISE_AUTOSWITCH environment, though the dumping performance might decrease. +*Verdi* : Enable automatic switching of the FSDB file. +*Verdi* : (Filename='./verdplus', Limit Size=500MB, File Amount=1000000). +*Verdi* : Create FSDB file './verdplus_000.fsdb' +*Verdi* : Create the file './verdplus.log' to log the time range of each FSDB file. +*Verdi* : Create virtual FSDB file './verdplus.vf' to log each FSDB file. +*Verdi* : Begin traversing the scopes, layer (0). +*Verdi* : End of traversing. +*Verdi* : Begin traversing the MDAs, layer (0). +*Verdi* : Enable +mda and +packedmda dumping. +*Verdi* : End of traversing the MDAs. +Frame check passed: Frame check passed +----------ONE-PKT-DRIVING---------- +cmd: 0 +addr: 0100000 +cfgid: 00 +data[ 0]='h0c000010 +----------------------------------- +----------ONE-PKT-DRIVING---------- +cmd: 0 +addr: 0200000 +cfgid: 00 +data[ 0]='hb9a79380 +data[ 1]='hf1e6d9ca +data[ 2]='hfdfffdf8 +data[ 3]='hd9e6f1f8 +data[ 4]='h93a7b9ca +data[ 5]='h46586c80 +data[ 6]='h0e192635 +data[ 7]='h02010207 +data[ 8]='h26190e07 +data[ 9]='h6c584635 +data[10]='hb9a7937f +data[11]='hf1e6d9ca +data[12]='hfdfffdf8 +data[13]='hd9e6f1f8 +data[14]='h93a7b9ca +data[15]='h46586c80 +data[16]='h0e192635 +data[17]='h02010207 +data[18]='h26190e07 +data[19]='h6c584635 +data[20]='hb9a7937f +data[21]='hf1e6d9ca +data[22]='hfdfffdf8 +data[23]='hd9e6f1f8 +data[24]='h93a7b9ca +data[25]='h46586c80 +data[26]='h0e192635 +data[27]='h02010207 +data[28]='h26190e07 +data[29]='h6c584635 +data[30]='hb9a7937f +data[31]='hf1e6d9ca +data[32]='hfdfffdf8 +data[33]='hd9e6f1f8 +data[34]='h93a7b9ca +data[35]='h46586c80 +data[36]='h0e192635 +data[37]='h02010207 +data[38]='h26190e07 +data[39]='h6c584635 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+data[223]='hd9e6f1f8 +data[224]='h93a7b9ca +data[225]='h46586c80 +data[226]='h0e192635 +data[227]='h02010207 +data[228]='h26190e07 +data[229]='h6c584635 +data[230]='hb9a79380 +data[231]='hf1e6d9ca +data[232]='hfdfffdf8 +data[233]='hd9e6f1f8 +data[234]='h93a7b9ca +data[235]='h46586c7f +data[236]='h0e192635 +data[237]='h02010207 +data[238]='h26190e07 +data[239]='h6c584635 +data[240]='hb9a7937f +data[241]='hf1e6d9ca +data[242]='hfdfffdf8 +data[243]='hd9e6f1f8 +data[244]='h93a7b9ca +data[245]='h46586c80 +data[246]='h0e192635 +data[247]='h02010207 +data[248]='h26190e07 +data[249]='h6c584635 +data[250]='hb9a7937f +data[251]='hf1e6d9ca +data[252]='hfdfffdf8 +data[253]='hd9e6f1f8 +data[254]='h93a7b9ca +data[255]='h46586c80 +----------------------------------- +----------ONE-PKT-DRIVING---------- +cmd: 0 +addr: 0100000 +cfgid: 00 +data[ 0]='h0c000010 +----------------------------------- +----------ONE-PKT-DRIVING---------- +cmd: 0 +addr: 0200000 +cfgid: 00 +data[ 0]='hb9a79380 +data[ 1]='hf1e6d9ca +data[ 2]='hfdfffdf8 +data[ 3]='hd9e6f1f8 +data[ 4]='h93a7b9ca +data[ 5]='h46586c80 +data[ 6]='h0e192635 +data[ 7]='h02010207 +data[ 8]='h26190e07 +data[ 9]='h6c584635 +data[10]='hb9a7937f +data[11]='hf1e6d9ca +data[12]='hfdfffdf8 +data[13]='hd9e6f1f8 +data[14]='h93a7b9ca +data[15]='h46586c80 +data[16]='h0e192635 +data[17]='h02010207 +data[18]='h26190e07 +data[19]='h6c584635 +data[20]='hb9a7937f +data[21]='hf1e6d9ca +data[22]='hfdfffdf8 +data[23]='hd9e6f1f8 +data[24]='h93a7b9ca +data[25]='h46586c80 +data[26]='h0e192635 +data[27]='h02010207 +data[28]='h26190e07 +data[29]='h6c584635 +data[30]='hb9a7937f +data[31]='hf1e6d9ca +data[32]='hfdfffdf8 +data[33]='hd9e6f1f8 +data[34]='h93a7b9ca +data[35]='h46586c80 +data[36]='h0e192635 +data[37]='h02010207 +data[38]='h26190e07 +data[39]='h6c584635 +data[40]='hb9a7937f +data[41]='hf1e6d9ca +data[42]='hfdfffdf8 +data[43]='hd9e6f1f8 +data[44]='h93a7b9ca +data[45]='h46586c80 +data[46]='h0e192635 +data[47]='h02010207 +data[48]='h26190e07 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+data[231]='hf1e6d9ca +data[232]='hfdfffdf8 +data[233]='hd9e6f1f8 +data[234]='h93a7b9ca +data[235]='h46586c7f +data[236]='h0e192635 +data[237]='h02010207 +data[238]='h26190e07 +data[239]='h6c584635 +data[240]='hb9a7937f +data[241]='hf1e6d9ca +data[242]='hfdfffdf8 +data[243]='hd9e6f1f8 +data[244]='h93a7b9ca +data[245]='h46586c80 +data[246]='h0e192635 +data[247]='h02010207 +data[248]='h26190e07 +data[249]='h6c584635 +data[250]='hb9a7937f +data[251]='hf1e6d9ca +data[252]='hfdfffdf8 +data[253]='hd9e6f1f8 +data[254]='h93a7b9ca +data[255]='h46586c80 +----------------------------------- +----------ONE-PKT-DRIVING---------- +cmd: 0 +addr: 0100000 +cfgid: 00 +data[ 0]='h0c000010 +----------------------------------- +----------ONE-PKT-DRIVING---------- +cmd: 0 +addr: 0200000 +cfgid: 00 +data[ 0]='hb9a79380 +data[ 1]='hf1e6d9ca +data[ 2]='hfdfffdf8 +data[ 3]='hd9e6f1f8 +data[ 4]='h93a7b9ca +data[ 5]='h46586c80 +data[ 6]='h0e192635 +data[ 7]='h02010207 +data[ 8]='h26190e07 +data[ 9]='h6c584635 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a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/.daidir_complete b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/.daidir_complete new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/.normal_done b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/.normal_done new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/.vcs.timestamp b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/.vcs.timestamp new file mode 100644 index 0000000..0d4e6bb --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/.vcs.timestamp @@ -0,0 +1,230 @@ +4 +0 ../define/chip_define.v +0 /opt/synopsys/vcs-mx/O-2018.09-SP2/etc/systemverilog/../define/chip_define.v +0 ../define/chip_undefine.v +0 /opt/synopsys/vcs-mx/O-2018.09-SP2/etc/systemverilog/../define/chip_undefine.v +48 ++define+DUMP_FSDB ++incdir+./../../model ++incdir+./../../rtl/define ++incdir+./../../rtl/qubitmcu ++itf+/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab ++lint=TFIPC-L ++nospecify ++v2k ++vcsd1 ++vpi +-Mamsrun= +-Masflags= +-Mcc=gcc +-Mcfl= -pipe -fPIC -O -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include +-Mcplusplus=g++ +-Mcrt0= +-Mcrtn= +-Mcsrc= +-Mexternalobj= +-Mldflags= -rdynamic +-Mobjects= /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvirsim.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/liberrorinf.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a +-Mout=simv +-Msaverestoreobj=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o +-Msyslibs=/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lm +-Mvcsaceobjs= +-Mxcflags= -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include +-P +-P +-cm +-cm_dir +-debug_access+all +-debug_region+cell+encrypt +-f filelist_vlg.f +-fsdb +-full64 +-gen_obj +-l +-lca +-picarchive +-q +-sverilog +-timescale=1ns/1ps +./coverage/simv.vdb +/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/vcs1 +/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +compile.log +line+cond+fsm+tgl+branch +110 +sysc_uni_pwd=/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top +starRC_HOME=/opt/synopsys/starrc/O-2018.06-SP1 +XMODIFIERS=@im=ibus +XILINX_VIVADO=/opt/xilinx/Vivado/2019.2 +XILINX_HOME=/opt/xilinx +XDG_SESSION_ID=c34 +XDG_RUNTIME_DIR=/run/user/1019 +XDG_MENU_PREFIX=gnome- +XDG_DATA_DIRS=/home/shbyang/.local/share/flatpak/exports/share:/var/lib/flatpak/exports/share:/usr/local/share:/usr/share +XDG_CURRENT_DESKTOP=GNOME +WV_HOME=/opt/synopsys/wv/N-2017.12-SP2 +WAVE=1 +W3264_NO_HOST_CHECK=1 +VTE_VERSION=5204 +VRST_HOME=/opt/cadence/INCISIVE152 +VNCDESKTOP=cryo1:17 (shbyang) +VMR_MODE_FLAG=64 +VIVADO_HOME=/opt/xilinx/Vivado/2019.2/ +VERDI_HOME=/opt/synopsys/verdi/Verdi_O-2018.09-SP2 +VENDOR=unknown +VC_STATIC_HOME=/opt/synopsys/vc_stat/vc_static/V-2023.12 +VCS_MX_HOME_INTERNAL=1 +VCS_MODE_FLAG=64 +VCS_LOG_FILE=compile.log +VCS_LCAMSG_PRINT_OFF=1 +VCS_HOME=/opt/synopsys/vcs-mx/O-2018.09-SP2 +VCS_DEPTH=0 +VCS_ARG_ADDED_FOR_TMP=1 +VCS_ARCH=linux64 +UNAME=/bin/uname +TXS_HOME=/opt/synopsys/txs/O-2018.06-SP1 +TOOL_HOME=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64 +SYN_HOME=/opt/synopsys/syn/O-2018.06-SP1 +SYNOPSYS=/opt/synopsys +SSH_AUTH_SOCK=/run/user/1019/keyring/ssh +SSH_AGENT_PID=24257 +SPECTRE_HOME=/opt/cadence/SPECTRE181 +SPECTRE_DEFAULTS=-E +SPECMAN_HOME=/opt/cadence/INCISIVE152/components/sn +SPECMAN_DIR=/opt/cadence/INCISIVE152/components/sn +SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/24088,unix/unix:/tmp/.ICE-unix/24088 +SCRNAME=vcs +SCRIPT_NAME=vcs +SCL_HOME=/opt/synopsys/scl/2018.06 +QT_IM_MODULE=ibus +QT_GRAPHICSSYSTEM_CHECKED=1 +QTLIB=/usr/lib64/qt-3.3/lib +QTINC=/usr/lib64/qt-3.3/include +QTDIR=/usr/lib64/qt-3.3 +PWR_HOME=/opt/synopsys/pwr/O-2018.06-SP3 +PT_HOME=/opt/synopsys/pts/O-2018.06-SP1 +OVA_UUM=0 +OSTYPE=linux +OA_UNSUPPORTED_PLAT=linux_rhel50_gcc44x +NOVAS_HOME=/opt/synopsys/verdi/Verdi_O-2018.09-SP2 +MOZILLA_HOME=/usr/bin/firefox +MGLS_LICENSE_FILE=/opt/mentor/license/license.dat +MGC_PDF_REDER=evince +MGC_LIB_PATH=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/lib +MGC_HOME=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11 +MGC_CALIBRE_SAVE_ALL_RUNSET_VALUES=1 +MGC_CALIBRE_REALTIME_VIRTUOSO_SAVE_MESSENGER_CELL=1 +MGC_CALIBRE_REALTIME_VIRTUOSO_ENABLED=1 +MFLAGS=-s +MENTOR_HOME=/opt/mentor +MAKEOVERRIDES=${-*-command-variables-*-} +MAKELEVEL=2 +MAKEFLAGS=s -- WAVE=1 +LESSOPEN=||/usr/bin/lesspipe.sh %s +LC_HOME=/opt/synopsys/lc/O-2018.06-SP1 +LC_ALL=C +INNOVUS_HOME=/opt/cadence/INNOVUS181 +INCISIVE_HOME=/opt/cadence/INCISIVE152 +IMSETTINGS_MODULE=none +IMSETTINGS_INTEGRATE_DESKTOP=yes +IDQ_HOME=/opt/synopsys/idq/O-2018.06-SP1 +HSPICE_HOME=/opt/synopsys/hspice/N-2017.12-SP2 +HOSTTYPE=x86_64-linux +HISTCONTROL=ignoredups +GROUP=cryo +GNOME_TERMINAL_SERVICE=:1.1458 +GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/300489a5_6011_46a1_a329_83b2a6d46428 +GNOME_SHELL_SESSION_MODE=classic +GNOME_DESKTOP_SESSION_ID=this-is-deprecated +GENUS_HOME=/opt/cadence/GENUS152 +FPGA_HOME=/opt/synopsys/fpga/K-2015.09 +FM_HOME=/opt/synopsys/fm/L-2016.03-SP1 +DBUS_STARTER_BUS_TYPE=session +DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-pbYbSoHCDo,guid=6bec37f851a0ec63831138606819dc51 +DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-pbYbSoHCDo,guid=6bec37f851a0ec63831138606819dc51 +COLORTERM=truecolor +CDS_SPECTRE_FBENABLE=1 +CDS_SPECTRERF_FBENABLE=1 +CDS_ROOT=/opt/cadence/IC618 +CDS_Netlisting_Mode=Analog +CDS_LOAD_ENV=CWD +CDS_LIC_ONLY=1 +CDS_LIC_FILE=/opt/cadence/license/license.dat +CDS_INST_DIR=/opt/cadence/IC618 +CDS_ENABLE_VMS=1 +CDS_AUTO_64BIT=ALL +CDSROOT=/opt/cadence/IC618 +CDSHOME=/opt/cadence/IC618 +CDSDIR=/opt/cadence/IC618 +CDS=/opt/cadence/IC618 +CALIBRE_HOME=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11 +CALIBRE_ENABLE_SKILL_PEXBA_MODE=1 +CADHOME=/opt/cadence +CADENCE_DIR=/opt/cadence/IC618 +AMS_ENABLE_NOISE=YES +0 +55 +1773384753 ../../model/LVDS_DRIVER.sv +1773384753 ../../model/SPI_DRIVER.sv +1773384753 ./../../rtl/define/../define/chip_undefine.v +1773384753 ./../../rtl/define/../define/chip_define.v +1773384753 ../../rtl/define/chip_undefine.v +1773384753 ../../sim/chip_top/TB.sv +1773384753 ../../model/DW_pulse_sync.v +1773384753 ../../model/DW_sync.v +1773384753 ../../model/DW_reset_sync.v +1773384753 ../../model/DW_stream_sync.v +1773384753 ../../model/reset_tb.v +1773384753 ../../model/DEM_Reverse.v +1773384753 ../../model/DEM_Reverse_64CH.v +1773384753 ../../model/clk_gen.v +1773384753 ../../model/spi_if.sv +1773384753 ../../model/clock_tb.v +1773384753 ../../rtl/spi/spi_sys.v +1773384753 ../../rtl/spi/spi_pll.v +1773384753 ../../rtl/spi/spi_slave.v +1773384753 ../../rtl/spi/spi_bus_decoder.sv +1773384753 ../../rtl/top/digital_top.sv +1773384753 ../../rtl/top/da4008_chip_top.sv +1773384753 ../../rtl/dem/DA4008_DEM_Parallel_PRBS_64CH.v +1773384753 ../../rtl/dem/DA4008_DEM_Parallel_PRBS_1CH.v +1773384753 ../../rtl/dem/DEM_PhaseSync_4008.sv +1773384753 ../../rtl/awg/awg_ctrl.v +1773384753 ../../rtl/awg/awg_top.sv +1773384753 ../../rtl/clk/clk_regfile.v +1773384753 ../../rtl/memory/spram.v +1773384753 ../../rtl/memory/bhv_spram.v +1773384753 ../../rtl/memory/dpram.v +1773384753 ../../rtl/memory/sram_dmux.sv +1773384753 ../../rtl/memory/sram_if.sv +1773384753 ../../rtl/memory/tsmc_dpram.v +1773384753 ../../rtl/comm/ramp_gen.v +1773384753 ../../rtl/comm/syncer.v +1773384753 ../../rtl/comm/sirv_gnrl_dffs.v +1773384753 ../../rtl/comm/pulse_generator.sv +1773384753 ../../rtl/comm/sirv_gnrl_xchecker.v +1773384753 ../../rtl/rstgen/rst_sync.v +1773384753 ../../rtl/rstgen/rst_gen_unit.v +1773384753 ../../rtl/lvds/ulink_rx.sv +1773384753 ../../rtl/dac_regfile/dac_regfile.v +1773384753 ../../rtl/fifo/syn_fwft_fifo.v +1773384753 ../../rtl/dacif/dacif.v +1773384753 ../../rtl/systemregfile/systemregfile.v +1773384753 ../../rtl/io/iopad.v +1773384753 ../../lib/tsdn28hpcpuhdb4096x128m4mw_170a_ffg0p99v0c.v +1773384753 ../../lib/tphn28hpcpgv18.v +1773384753 ../../rtl/define/chip_define.v +1551421444 /opt/synopsys/vcs-mx/O-2018.09-SP2/include/cm_vcsd.tab +1773384753 filelist_vlg.f +1550753332 /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +1550753332 /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +1551421246 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab +5 +1551422344 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvirsim.so +1551421792 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/liberrorinf.so +1551421768 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so +1551421789 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so +1550752033 /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a +1773384887 simv.daidir +-1 partitionlib diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/_32553_archive_1.so b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/_32553_archive_1.so new file mode 100755 index 0000000..fd59063 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/_32553_archive_1.so differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/_32573_archive_1.so b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/_32573_archive_1.so new file mode 100755 index 0000000..a1f01d7 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/_32573_archive_1.so differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/_32574_archive_1.so b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/_32574_archive_1.so new file mode 100755 index 0000000..c3950e9 Binary files /dev/null and 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differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/build_db b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/build_db new file mode 100755 index 0000000..558da36 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/build_db @@ -0,0 +1,4 @@ +#!/bin/sh -e +# This file is automatically generated by VCS. Any changes you make +# to it will be overwritten the next time VCS is run. +vcs '-full64' '-j8' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+all' '-debug_region+cell+encrypt' '-P' '/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab' '/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a' '+define+DUMP_FSDB' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-cm' 'line+cond+fsm+tgl+branch' '-cm_dir' './coverage/simv.vdb' '-f' 'filelist_vlg.f' '+incdir+./../../rtl/define' '+incdir+./../../rtl/qubitmcu' '+incdir+./../../model' -static_dbgen_only -daidir=$1 2>&1 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/cc/cc_bcode.db b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/cc/cc_bcode.db new file mode 100644 index 0000000..757c06d --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/cc/cc_bcode.db @@ -0,0 +1,561 @@ +sid sirv_gnrl_xchecker +bcid 0 0 WIDTH,32 CALL_ARG_VAL,2,0 WIDTH,1 XOR_REDUCE OPT_CONST_4ST,1,1 NEQU RET +sid clk_gen +bcid 1 0 WIDTH,4 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU RET +sid spi_sys_0000 +bcid 2 0 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 3 1 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 4 2 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 M_EQU AND CALL_ARG_VAL,4,0 OR RET +bcid 5 3 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 6 4 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,26 WIDTH,1 M_EQU AND RET +bcid 7 5 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,30 WIDTH,1 M_EQU AND AND RET +bcid 8 6 WIDTH,5 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_EQU RET +bcid 9 7 WIDTH,5 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_NEQU RET +bcid 10 8 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 AND AND RET +bcid 11 9 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 AND AND RET +bcid 12 10 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 NOT CALL_ARG_VAL,5,0 AND AND AND RET +bcid 13 11 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 AND AND AND RET +bcid 14 12 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND RET +bcid 15 13 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND RET +bcid 16 14 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND WIDTH,2 OPT_CONST,1 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,4,0 AND WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,5,0 AND WIDTH,2 OPT_CONST,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,6,0 AND WIDTH,2 OPT_CONST,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,7,0 AND WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,8,0 AND WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 17 15 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND OR CALL_ARG_VAL,4,0 WIDTH,5 CALL_ARG_VAL,5,0 OPT_CONST,27 WIDTH,1 M_EQU AND AND RET +bcid 18 16 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,25 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,25 CALL_ARG_VAL,4,0 WIDTH,1 CALL_ARG_VAL,5,0 WIDTH,25 CALL_ARG_VAL,6,0 OPT_CONST,4 ADD CALL_ARG_VAL,6,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 19 17 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,31 WIDTH,1 M_EQU AND AND RET +bcid 20 18 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND CALL_ARG_VAL,4,0 WIDTH,5 CALL_ARG_VAL,5,0 OPT_CONST,28 WIDTH,1 M_EQU AND AND RET +bcid 21 19 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,30 WIDTH,1 M_EQU AND AND RET +bcid 22 20 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,31 WIDTH,1 M_EQU AND AND RET +bcid 23 21 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 WIDTH,2 CALL_ARG_VAL,4,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,5,0 AND WIDTH,32 CALL_ARG_VAL,6,0 OPT_CONST,0 WIDTH,31 SLICE,1 WIDTH,1 OPT_CONST,0 WIDTH,32 CONCATENATE,2 CALL_ARG_VAL,6,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 24 22 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_NEQU RET +sid spi_slave +bcid 25 0 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 26 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 M_EQU AND RET +bcid 27 2 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 28 3 WIDTH,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,26 WIDTH,1 M_EQU AND AND RET +bcid 29 4 WIDTH,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,30 WIDTH,1 M_EQU AND AND RET +bcid 30 5 WIDTH,5 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 M_EQU WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 NOT WIDTH,5 CALL_ARG_VAL,4,0 WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,5 SLICE,1 WIDTH,1 M_EQU AND AND RET +bcid 31 6 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,30 WIDTH,1 M_EQU CALL_ARG_VAL,4,0 AND AND RET +bcid 32 7 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND CALL_ARG_VAL,4,0 OR CALL_ARG_VAL,5,0 WIDTH,5 CALL_ARG_VAL,6,0 OPT_CONST,29 WIDTH,1 M_EQU AND AND RET +bcid 33 8 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,8 CALL_ARG_VAL,4,0 OPT_CONST,4 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 CALL_ARG_VAL,5,0 MITECONDNOINSTR,4 RET +bcid 34 9 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 RET +bcid 35 10 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,30 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 36 11 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,29 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 37 12 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,28 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,2 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 38 13 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,27 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,3 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 39 14 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,26 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,4 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 40 15 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,25 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,5 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 41 16 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,24 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,6 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 42 17 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,23 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,7 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 43 18 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,22 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,8 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 44 19 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,21 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,9 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 45 20 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,20 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,10 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 46 21 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,19 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,11 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 47 22 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,13 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,18 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,12 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 48 23 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,17 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,13 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 49 24 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,14 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 50 25 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,15 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 51 26 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,17 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,16 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 52 27 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,18 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,13 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,17 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 53 28 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,19 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,12 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,18 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 54 29 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,19 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 55 30 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,21 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,20 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 56 31 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,22 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,9 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,21 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 57 32 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,23 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,8 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,22 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 58 33 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,24 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,7 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,23 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 59 34 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,6 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,24 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 60 35 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,26 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,25 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 61 36 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,27 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,26 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 62 37 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,28 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,27 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 63 38 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,29 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,28 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 64 39 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,30 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,29 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 65 40 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,30 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +sid spi_bus_decoder_0000 +bcid 66 0 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,20 MULTI_CONCATENATE,1,20 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 AND RET +bcid 67 1 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,20 MULTI_CONCATENATE,1,20 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 AND RET +bcid 68 2 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,20 MULTI_CONCATENATE,1,20 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 AND RET +bcid 69 3 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,20 MULTI_CONCATENATE,1,20 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 AND RET +bcid 70 4 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 71 5 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 72 6 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 73 7 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 74 8 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,4 MULTI_CONCATENATE,1,4 AND RET +sid systemregfile +bcid 75 0 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,8 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,19,0 OPT_CONST,1 EQU WIDTH,8 OPT_CONST,32 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,8 OPT_CONST,88 WIDTH,1 CALL_ARG_VAL,21,0 OPT_CONST,1 EQU WIDTH,8 OPT_CONST,218 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 76 1 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,4 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,21,0 OPT_CONST,1 EQU WIDTH,4 OPT_CONST,2 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,4 OPT_CONST,4 WIDTH,1 CALL_ARG_VAL,23,0 OPT_CONST,1 EQU WIDTH,4 OPT_CONST,4 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 77 2 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,19 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU OPT_CONST,0 CALL_ARG_VAL,23,0 OPT_CONST,1 EQU OPT_CONST,0 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU OPT_CONST,0 CALL_ARG_VAL,25,0 OPT_CONST,1 EQU OPT_CONST,0 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 78 3 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,19 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,8 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,11 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,25,0 OPT_CONST,1 EQU WIDTH,11 OPT_CONST,1541 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,11 OPT_CONST,1109 WIDTH,1 CALL_ARG_VAL,27,0 OPT_CONST,1 EQU WIDTH,11 OPT_CONST,8 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 79 4 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,19 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,6 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,27,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,29,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 80 5 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,19 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,3 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,31,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,2 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,33,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,0 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 81 6 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,19 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,35,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,37,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 82 7 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU CALL_ARG_VAL,11,0 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU CALL_ARG_VAL,13,0 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU CALL_ARG_VAL,27,0 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU CALL_ARG_VAL,29,0 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU CALL_ARG_VAL,31,0 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,19 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 EQU OPT_CONST,1 CALL_ARG_VAL,45,0 OPT_CONST,1 EQU OPT_CONST,0 CALL_ARG_VAL,46,0 OPT_CONST,1 EQU OPT_CONST,0 CALL_ARG_VAL,47,0 OPT_CONST,1 EQU OPT_CONST,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 83 8 WIDTH,6 CALL_ARG_VAL,2,0 WIDTH,32 PAD RET +bcid 84 9 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 85 10 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 86 11 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 87 12 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 88 13 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 M_EQU RET +bcid 89 14 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 M_EQU RET +bcid 90 15 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 M_EQU RET +bcid 91 16 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 M_EQU RET +bcid 92 17 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU RET +bcid 93 18 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 M_EQU RET +bcid 94 19 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,10 WIDTH,1 M_EQU RET +bcid 95 20 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,11 WIDTH,1 M_EQU RET +bcid 96 21 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,1 M_EQU RET +bcid 97 22 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,13 WIDTH,1 M_EQU RET +bcid 98 23 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,14 WIDTH,1 M_EQU RET +bcid 99 24 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,1 M_EQU RET +bcid 100 25 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,19 WIDTH,1 M_EQU RET +bcid 101 26 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 M_EQU RET +bcid 102 27 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,21 WIDTH,1 M_EQU RET +bcid 103 28 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 M_EQU RET +bcid 104 29 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,17 WIDTH,1 M_EQU RET +bcid 105 30 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,18 WIDTH,1 M_EQU RET +bcid 106 31 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,22 WIDTH,1 M_EQU RET +bcid 107 32 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,23 WIDTH,1 M_EQU RET +bcid 108 33 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,24 WIDTH,1 M_EQU RET +bcid 109 34 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,1 M_EQU RET +bcid 110 35 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU AND RET +bcid 111 36 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 112 37 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_NEQU RET +sid DW_sync_0000 +bcid 113 0 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +sid DW_pulse_sync_0000 +bcid 114 0 WIDTH,32 PARAMETER,2 OPT_CONST,0 WIDTH,1 EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 XOR WIDTH,32 PARAMETER,2 OPT_CONST,1 WIDTH,1 EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,5,0 NOT AND CALL_ARG_VAL,4,0 XOR WIDTH,32 PARAMETER,2 OPT_CONST,2 WIDTH,1 EQU CALL_ARG_VAL,3,0 NOT CALL_ARG_VAL,5,0 AND CALL_ARG_VAL,4,0 XOR WIDTH,32 PARAMETER,2 OPT_CONST,3 WIDTH,1 EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,5,0 CALL_ARG_VAL,4,0 XOR XOR OPT_CONST_4ST,1,1 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 115 1 WIDTH,32 PARAMETER,2 OPT_CONST,0 WIDTH,1 M_NEQU WIDTH,2 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,2 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 XOR MITECONDNOINSTR,4 RET +sid ulink_descrambler_32 +bcid 116 0 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND WIDTH,32 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 XOR CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +sid syn_fwft_fifo +bcid 117 0 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,62 WIDTH,1 M_GT RET +bcid 118 1 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,59 WIDTH,1 M_GT RET +bcid 119 2 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,510 WIDTH,1 M_GT RET +bcid 120 3 WIDTH,7 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 121 4 WIDTH,7 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_LT RET +bcid 122 5 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,17 WIDTH,1 M_LT RET +bcid 123 6 WIDTH,6 CALL_ARG_VAL,2,0 WIDTH,4 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 LNOT AND WIDTH,5 CONCATENATE,2 WIDTH,6 PAD ADD RET +bcid 124 7 WIDTH,6 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_NEQU RET +bcid 125 8 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,128 CONST,0,0 CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +sid ulink_frame_receiver_0000 +bcid 126 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,16 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,16 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 127 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,4 MULTI_CONCATENATE,1,4 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,4 MULTI_CONCATENATE,1,4 NOT OR RET +bcid 128 2 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 WIDTH,1 M_NEQU AND RET +sid ulink_rx +bcid 129 0 WIDTH,20 CALL_ARG_VAL,2,0 OPT_CONST,10000 WIDTH,1 M_NEQU RET +bcid 130 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,20 CALL_ARG_VAL,3,0 OPT_CONST,9999 WIDTH,1 M_EQU AND RET +bcid 131 2 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,20 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,20 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 132 3 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 133 4 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 M_EQU AND RET +bcid 134 5 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 135 6 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,1751543404 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1751543404 WIDTH,1 M_EQU AND WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1751543404 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,1751543404 WIDTH,1 M_EQU AND AND RET +bcid 136 7 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,1702390132 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1702390132 WIDTH,1 M_EQU AND WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1702390132 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,1702390132 WIDTH,1 M_EQU AND AND RET +bcid 137 8 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,20 CALL_ARG_VAL,3,0 WIDTH,32 PAD WIDTH,20 CALL_ARG_VAL,4,0 WIDTH,32 PAD OPT_CONST,2 SUBTRACT WIDTH,1 M_EQU AND RET +bcid 138 9 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,3 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 CALL_ARG_VAL,3,0 ADD MITECONDNOINSTR,4 RET +bcid 139 10 WIDTH,128 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 SLICE,1 OPT_CONST,-1128481604 WIDTH,1 M_EQU RET +bcid 140 11 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND OPT_CONST,1 CALL_ARG_VAL,4,0 OPT_CONST,0 CALL_ARG_VAL,5,0 OPT_CONST,0 CALL_ARG_VAL,6,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 141 12 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 M_EQU AND CALL_ARG_VAL,4,0 OR RET +bcid 142 13 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,3 MULTI_CONCATENATE,1,3 RET +sid pulse_generator +bcid 143 0 WIDTH,16 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_EQU RET +sid tsdn28hpcpuhdb4096x128m4mw_170a +bcid 144 0 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 145 1 WIDTH,1 OPT_CONST,0 RET +bcid 146 2 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 147 3 WIDTH,1 OPT_CONST,0 RET +bcid 148 4 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 149 5 WIDTH,1 OPT_CONST,0 RET +bcid 150 6 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 151 7 WIDTH,1 OPT_CONST,0 RET +bcid 152 8 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 153 9 WIDTH,1 OPT_CONST,0 RET +bcid 154 10 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 155 11 WIDTH,1 OPT_CONST,0 RET +bcid 156 12 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 157 13 WIDTH,1 OPT_CONST,0 RET +bcid 158 14 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 159 15 WIDTH,1 OPT_CONST,0 RET +bcid 160 16 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 161 17 WIDTH,1 OPT_CONST,0 RET +bcid 162 18 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 163 19 WIDTH,1 OPT_CONST,0 RET +bcid 164 20 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 165 21 WIDTH,1 OPT_CONST,0 RET +bcid 166 22 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 167 23 WIDTH,1 OPT_CONST,0 RET +bcid 168 24 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 169 25 WIDTH,1 OPT_CONST,0 RET +bcid 170 26 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 171 27 WIDTH,1 OPT_CONST,0 RET +bcid 172 28 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 173 29 WIDTH,1 OPT_CONST,0 RET +bcid 174 30 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 175 31 WIDTH,1 OPT_CONST,0 RET +bcid 176 32 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 177 33 WIDTH,1 OPT_CONST,0 RET +bcid 178 34 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 179 35 WIDTH,1 OPT_CONST,0 RET +bcid 180 36 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 181 37 WIDTH,1 OPT_CONST,0 RET +bcid 182 38 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 183 39 WIDTH,1 OPT_CONST,0 RET +bcid 184 40 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 185 41 WIDTH,1 OPT_CONST,0 RET +bcid 186 42 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 187 43 WIDTH,1 OPT_CONST,0 RET +bcid 188 44 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 189 45 WIDTH,1 OPT_CONST,0 RET +bcid 190 46 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 191 47 WIDTH,1 OPT_CONST,0 RET +bcid 192 48 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 193 49 WIDTH,1 OPT_CONST,0 RET +bcid 194 50 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 195 51 WIDTH,1 OPT_CONST,0 RET +bcid 196 52 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 197 53 WIDTH,1 OPT_CONST,0 RET +bcid 198 54 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 199 55 WIDTH,1 OPT_CONST,0 RET +bcid 200 56 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 201 57 WIDTH,1 OPT_CONST,0 RET +bcid 202 58 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 203 59 WIDTH,1 OPT_CONST,0 RET +bcid 204 60 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 205 61 WIDTH,1 OPT_CONST,0 RET +bcid 206 62 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 207 63 WIDTH,1 OPT_CONST,0 RET +bcid 208 64 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 209 65 WIDTH,1 OPT_CONST,0 RET +bcid 210 66 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 211 67 WIDTH,1 OPT_CONST,0 RET +bcid 212 68 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 213 69 WIDTH,1 OPT_CONST,0 RET +bcid 214 70 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 215 71 WIDTH,1 OPT_CONST,0 RET +bcid 216 72 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 217 73 WIDTH,1 OPT_CONST,0 RET +bcid 218 74 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 219 75 WIDTH,1 OPT_CONST,0 RET +bcid 220 76 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 221 77 WIDTH,1 OPT_CONST,0 RET +bcid 222 78 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 223 79 WIDTH,1 OPT_CONST,0 RET +bcid 224 80 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 225 81 WIDTH,1 OPT_CONST,0 RET +bcid 226 82 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 227 83 WIDTH,1 OPT_CONST,0 RET +bcid 228 84 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 229 85 WIDTH,1 OPT_CONST,0 RET +bcid 230 86 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 231 87 WIDTH,1 OPT_CONST,0 RET +bcid 232 88 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 233 89 WIDTH,1 OPT_CONST,0 RET +bcid 234 90 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 235 91 WIDTH,1 OPT_CONST,0 RET +bcid 236 92 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 237 93 WIDTH,1 OPT_CONST,0 RET +bcid 238 94 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 239 95 WIDTH,1 OPT_CONST,0 RET +bcid 240 96 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 241 97 WIDTH,1 OPT_CONST,0 RET +bcid 242 98 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 243 99 WIDTH,1 OPT_CONST,0 RET +bcid 244 100 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 245 101 WIDTH,1 OPT_CONST,0 RET +bcid 246 102 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 247 103 WIDTH,1 OPT_CONST,0 RET +bcid 248 104 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 249 105 WIDTH,1 OPT_CONST,0 RET +bcid 250 106 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 251 107 WIDTH,1 OPT_CONST,0 RET +bcid 252 108 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 253 109 WIDTH,1 OPT_CONST,0 RET +bcid 254 110 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 255 111 WIDTH,1 OPT_CONST,0 RET +bcid 256 112 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 257 113 WIDTH,1 OPT_CONST,0 RET +bcid 258 114 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 259 115 WIDTH,1 OPT_CONST,0 RET +bcid 260 116 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 261 117 WIDTH,1 OPT_CONST,0 RET +bcid 262 118 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 263 119 WIDTH,1 OPT_CONST,0 RET +bcid 264 120 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 265 121 WIDTH,1 OPT_CONST,0 RET +bcid 266 122 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 267 123 WIDTH,1 OPT_CONST,0 RET +bcid 268 124 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 269 125 WIDTH,1 OPT_CONST,0 RET +bcid 270 126 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 271 127 WIDTH,1 OPT_CONST,0 RET +bcid 272 128 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 273 129 WIDTH,1 OPT_CONST,0 RET +bcid 274 130 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 275 131 WIDTH,1 OPT_CONST,0 RET +bcid 276 132 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 277 133 WIDTH,1 OPT_CONST,0 RET +bcid 278 134 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 279 135 WIDTH,1 OPT_CONST,0 RET +bcid 280 136 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 281 137 WIDTH,1 OPT_CONST,0 RET +bcid 282 138 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 283 139 WIDTH,1 OPT_CONST,0 RET +bcid 284 140 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 285 141 WIDTH,1 OPT_CONST,0 RET +bcid 286 142 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 287 143 WIDTH,1 OPT_CONST,0 RET +bcid 288 144 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 289 145 WIDTH,1 OPT_CONST,0 RET +bcid 290 146 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 291 147 WIDTH,1 OPT_CONST,0 RET +bcid 292 148 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 293 149 WIDTH,1 OPT_CONST,0 RET +bcid 294 150 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 295 151 WIDTH,1 OPT_CONST,0 RET +bcid 296 152 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 297 153 WIDTH,1 OPT_CONST,0 RET +bcid 298 154 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 299 155 WIDTH,1 OPT_CONST,0 RET +bcid 300 156 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 301 157 WIDTH,1 OPT_CONST,0 RET +bcid 302 158 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 303 159 WIDTH,1 OPT_CONST,0 RET +bcid 304 160 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 305 161 WIDTH,1 OPT_CONST,0 RET +bcid 306 162 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 307 163 WIDTH,1 OPT_CONST,0 RET +bcid 308 164 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 309 165 WIDTH,1 OPT_CONST,0 RET +bcid 310 166 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 311 167 WIDTH,1 OPT_CONST,0 RET +bcid 312 168 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 313 169 WIDTH,1 OPT_CONST,0 RET +bcid 314 170 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 315 171 WIDTH,1 OPT_CONST,0 RET +bcid 316 172 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 317 173 WIDTH,1 OPT_CONST,0 RET +bcid 318 174 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 319 175 WIDTH,1 OPT_CONST,0 RET +bcid 320 176 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 321 177 WIDTH,1 OPT_CONST,0 RET +bcid 322 178 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 323 179 WIDTH,1 OPT_CONST,0 RET +bcid 324 180 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 325 181 WIDTH,1 OPT_CONST,0 RET +bcid 326 182 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 327 183 WIDTH,1 OPT_CONST,0 RET +bcid 328 184 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 329 185 WIDTH,1 OPT_CONST,0 RET +bcid 330 186 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 331 187 WIDTH,1 OPT_CONST,0 RET +bcid 332 188 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 333 189 WIDTH,1 OPT_CONST,0 RET +bcid 334 190 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 335 191 WIDTH,1 OPT_CONST,0 RET +bcid 336 192 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 337 193 WIDTH,1 OPT_CONST,0 RET +bcid 338 194 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 339 195 WIDTH,1 OPT_CONST,0 RET +bcid 340 196 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 341 197 WIDTH,1 OPT_CONST,0 RET +bcid 342 198 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 343 199 WIDTH,1 OPT_CONST,0 RET +bcid 344 200 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 345 201 WIDTH,1 OPT_CONST,0 RET +bcid 346 202 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 347 203 WIDTH,1 OPT_CONST,0 RET +bcid 348 204 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 349 205 WIDTH,1 OPT_CONST,0 RET +bcid 350 206 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 351 207 WIDTH,1 OPT_CONST,0 RET +bcid 352 208 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 353 209 WIDTH,1 OPT_CONST,0 RET +bcid 354 210 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 355 211 WIDTH,1 OPT_CONST,0 RET +bcid 356 212 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 357 213 WIDTH,1 OPT_CONST,0 RET +bcid 358 214 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 359 215 WIDTH,1 OPT_CONST,0 RET +bcid 360 216 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 361 217 WIDTH,1 OPT_CONST,0 RET +bcid 362 218 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 363 219 WIDTH,1 OPT_CONST,0 RET +bcid 364 220 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 365 221 WIDTH,1 OPT_CONST,0 RET +bcid 366 222 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 367 223 WIDTH,1 OPT_CONST,0 RET +bcid 368 224 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 369 225 WIDTH,1 OPT_CONST,0 RET +bcid 370 226 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 371 227 WIDTH,1 OPT_CONST,0 RET +bcid 372 228 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 373 229 WIDTH,1 OPT_CONST,0 RET +bcid 374 230 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 375 231 WIDTH,1 OPT_CONST,0 RET +bcid 376 232 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 377 233 WIDTH,1 OPT_CONST,0 RET +bcid 378 234 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 379 235 WIDTH,1 OPT_CONST,0 RET +bcid 380 236 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 381 237 WIDTH,1 OPT_CONST,0 RET +bcid 382 238 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 383 239 WIDTH,1 OPT_CONST,0 RET +bcid 384 240 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 385 241 WIDTH,1 OPT_CONST,0 RET +bcid 386 242 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 387 243 WIDTH,1 OPT_CONST,0 RET +bcid 388 244 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 389 245 WIDTH,1 OPT_CONST,0 RET +bcid 390 246 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 391 247 WIDTH,1 OPT_CONST,0 RET +bcid 392 248 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 393 249 WIDTH,1 OPT_CONST,0 RET +bcid 394 250 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 395 251 WIDTH,1 OPT_CONST,0 RET +bcid 396 252 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 397 253 WIDTH,1 OPT_CONST,0 RET +bcid 398 254 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 399 255 WIDTH,1 OPT_CONST,0 RET +sid dpram +bcid 400 0 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU WIDTH,512 MULTI_CONCATENATE,1,512 CALL_ARG_VAL,3,0 AND WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU WIDTH,512 MULTI_CONCATENATE,1,512 CALL_ARG_VAL,4,0 AND OR RET +bcid 401 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 MULTI_CONCATENATE,1,8 RET +sid awg_top +bcid 402 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,13 CALL_ARG_VAL,3,0 WIDTH,6 OPT_CONST,0 WIDTH,19 CONCATENATE,2 WIDTH,13 CALL_ARG_VAL,4,0 WIDTH,6 OPT_CONST,0 WIDTH,19 CONCATENATE,2 MITECONDNOINSTR,4 RET +bcid 403 1 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,62 WIDTH,1 M_GT RET +bcid 404 2 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,59 WIDTH,1 M_GT RET +bcid 405 3 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,30 WIDTH,1 M_GT RET +bcid 406 4 WIDTH,7 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 407 5 WIDTH,7 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_LT RET +bcid 408 6 WIDTH,7 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,17 WIDTH,1 M_LT RET +bcid 409 7 WIDTH,6 CALL_ARG_VAL,2,0 WIDTH,4 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 LNOT AND WIDTH,5 CONCATENATE,2 WIDTH,6 PAD ADD RET +bcid 410 8 WIDTH,6 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_NEQU RET +bcid 411 9 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 412 10 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND RET +bcid 413 11 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 SLICE,1 NOT AND RET +bcid 414 12 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 SLICE,1 AND RET +bcid 415 13 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,31 WIDTH,1 SLICE,1 CALL_ARG_VAL,5,0 NOT AND AND RET +bcid 416 14 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 AND AND RET +bcid 417 15 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,31 WIDTH,1 SLICE,1 CALL_ARG_VAL,5,0 OR NOT AND RET +bcid 418 16 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 AND AND RET +bcid 419 17 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND WIDTH,3 OPT_CONST,1 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,4,0 AND WIDTH,3 OPT_CONST,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,5,0 AND WIDTH,3 OPT_CONST,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,6,0 AND WIDTH,3 OPT_CONST,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,7,0 AND WIDTH,3 OPT_CONST,0 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,8,0 AND WIDTH,3 OPT_CONST,2 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,9,0 AND WIDTH,3 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 420 18 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 OR OR CALL_ARG_VAL,5,0 NOT AND RET +bcid 421 19 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 422 20 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,13 CALL_ARG_VAL,3,0 WIDTH,32 PAD WIDTH,13 CALL_ARG_VAL,4,0 WIDTH,32 PAD OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU AND RET +bcid 423 21 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,13 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,13 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 424 22 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 WIDTH,32 PAD WIDTH,5 CALL_ARG_VAL,4,0 WIDTH,32 PAD OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 M_NEQU AND AND RET +bcid 425 23 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 426 24 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 427 25 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,31 CALL_ARG_VAL,3,0 WIDTH,32 PAD WIDTH,31 CALL_ARG_VAL,4,0 WIDTH,32 PAD OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU AND RET +bcid 428 26 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,31 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,31 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 429 27 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,512 CALL_ARG_VAL,3,0 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,8 CALL_ARG_VAL,5,0 WIDTH,512 MULTI_CONCATENATE,1,64 CONST,0,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 430 28 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU OR RET +bcid 431 29 WIDTH,13 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 ADD RET +sid ramp_gen_0000 +bcid 432 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU AND RET +bcid 433 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 434 2 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,8 SHIFT_L RET +bcid 435 3 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,8 SHIFT_L RET +bcid 436 4 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,8 SHIFT_L RET +bcid 437 5 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,4 WIDTH,8 SHIFT_L RET +bcid 438 6 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,5 WIDTH,8 SHIFT_L RET +bcid 439 7 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,6 WIDTH,8 SHIFT_L RET +sid dac_regfile +bcid 440 0 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,46,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,48,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU CALL_ARG_VAL,49,0 CALL_ARG_VAL,50,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,51,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 441 1 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,46,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,48,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,50,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,51,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 442 2 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,44,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,46,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,48,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,50,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,51,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 443 3 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,44,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,46,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,48,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,50,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,51,0 OPT_CONST,10 WIDTH,22 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 444 4 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,44,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,46,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,48,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,50,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,51,0 OPT_CONST,4 WIDTH,6 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 445 5 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 OPT_CONST,539362576 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,3,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,5,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,6,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,7,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,8,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,9,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,10,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,11,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,12,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,13,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,14,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,15,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,16,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,17,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,18,0 OPT_CONST,10 WIDTH,22 SLICE,1 WIDTH,1 CALL_ARG_VAL,19,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,20,0 OPT_CONST,10 WIDTH,22 SLICE,1 CALL_ARG_VAL,21,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 446 6 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 OPT_CONST,539362576 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,3,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,5,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,6,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,7,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,10 CALL_ARG_VAL,8,0 WIDTH,32 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,9,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,10,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,11,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,12,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,13,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,14,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,15,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,16,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,17,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,18,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,19,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,20,0 OPT_CONST,4 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,21,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,22,0 OPT_CONST,4 WIDTH,6 SLICE,1 CALL_ARG_VAL,23,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 447 7 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 OPT_CONST,539362576 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,3,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,5,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,6,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,7,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,8,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,9,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,10,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,11,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,10 CALL_ARG_VAL,12,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,13,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,14,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,15,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,16,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,17,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,18,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,19,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,20,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,21,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,22,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,23,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,24,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,25,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,26,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,27,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,28,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,29,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 448 8 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 OPT_CONST,539362576 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,3,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,5,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,6,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,7,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,8,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,9,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,10,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,11,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,10 CALL_ARG_VAL,12,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,13,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,14,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,15,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,16,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,17,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,18,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,19,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,20,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,21,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,22,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,23,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,24,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,25,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,26,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,27,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,28,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,29,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,30,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,31,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,32,0 OPT_CONST,1 WIDTH,2 SLICE,1 CALL_ARG_VAL,33,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 449 9 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 OPT_CONST,539362576 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,3,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,5,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,6,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,7,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,8,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,9,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,10,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,11,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,10 CALL_ARG_VAL,12,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,13,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,14,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,15,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,16,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,17,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,18,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,19,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,20,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,21,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,22,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,23,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,24,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,25,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,26,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,27,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,28,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,29,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,30,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,31,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,32,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,33,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,34,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,35,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 450 10 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 451 11 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 452 12 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 453 13 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 454 14 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 M_EQU RET +bcid 455 15 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 M_EQU RET +bcid 456 16 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 M_EQU RET +bcid 457 17 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 M_EQU RET +bcid 458 18 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU RET +bcid 459 19 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 M_EQU RET +bcid 460 20 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,10 WIDTH,1 M_EQU RET +bcid 461 21 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,11 WIDTH,1 M_EQU RET +bcid 462 22 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,1 M_EQU RET +bcid 463 23 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,13 WIDTH,1 M_EQU RET +bcid 464 24 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,14 WIDTH,1 M_EQU RET +bcid 465 25 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,1 M_EQU RET +bcid 466 26 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 M_EQU RET +bcid 467 27 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,17 WIDTH,1 M_EQU RET +bcid 468 28 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,18 WIDTH,1 M_EQU RET +bcid 469 29 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,19 WIDTH,1 M_EQU RET +bcid 470 30 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 M_EQU RET +bcid 471 31 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,21 WIDTH,1 M_EQU RET +bcid 472 32 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,22 WIDTH,1 M_EQU RET +bcid 473 33 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,23 WIDTH,1 M_EQU RET +bcid 474 34 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,24 WIDTH,1 M_EQU RET +bcid 475 35 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,1 M_EQU RET +bcid 476 36 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,26 WIDTH,1 M_EQU RET +bcid 477 37 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,27 WIDTH,1 M_EQU RET +bcid 478 38 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,28 WIDTH,1 M_EQU RET +bcid 479 39 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,29 WIDTH,1 M_EQU RET +bcid 480 40 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,30 WIDTH,1 M_EQU RET +bcid 481 41 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 M_EQU RET +bcid 482 42 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,32 WIDTH,1 M_EQU RET +bcid 483 43 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,33 WIDTH,1 M_EQU RET +bcid 484 44 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,34 WIDTH,1 M_EQU RET +bcid 485 45 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,35 WIDTH,1 M_EQU RET +bcid 486 46 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,36 WIDTH,1 M_EQU RET +bcid 487 47 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,37 WIDTH,1 M_EQU RET +bcid 488 48 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,38 WIDTH,1 M_EQU RET +bcid 489 49 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,39 WIDTH,1 M_EQU RET +bcid 490 50 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,40 WIDTH,1 M_EQU RET +bcid 491 51 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,41 WIDTH,1 M_EQU RET +sid clk_regfile +bcid 492 0 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,24 WIDTH,8 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,24 WIDTH,8 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 493 1 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,20 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,20 WIDTH,4 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 494 2 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,16 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,16 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,16 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,16 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,16 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,16 WIDTH,4 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,16 WIDTH,4 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 495 3 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,9 WIDTH,7 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 496 4 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,6 WIDTH,3 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 497 5 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 498 6 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 499 7 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,39,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 500 8 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,39,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,41,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 501 9 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,24 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,20 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,39,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU CALL_ARG_VAL,41,0 CALL_ARG_VAL,42,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,43,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 EQU CALL_ARG_VAL,45,0 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 502 10 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 503 11 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 504 12 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 505 13 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 506 14 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 M_EQU RET +bcid 507 15 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 M_EQU RET +bcid 508 16 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 M_EQU RET +bcid 509 17 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 M_EQU RET +bcid 510 18 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU RET +bcid 511 19 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 M_EQU RET +bcid 512 20 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,10 WIDTH,1 M_EQU RET +bcid 513 21 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,11 WIDTH,1 M_EQU RET +bcid 514 22 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,1 M_EQU RET +bcid 515 23 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,13 WIDTH,1 M_EQU RET +bcid 516 24 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,14 WIDTH,1 M_EQU RET +bcid 517 25 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,1 M_EQU RET +bcid 518 26 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 M_EQU RET +bcid 519 27 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,17 WIDTH,1 M_EQU RET +bcid 520 28 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,18 WIDTH,1 M_EQU RET +bcid 521 29 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,19 WIDTH,1 M_EQU RET +bcid 522 30 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 M_EQU RET +bcid 523 31 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,21 WIDTH,1 M_EQU RET +sid da4008_chip_top +bcid 524 0 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 NOT AND OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,2 WIDTH,1 EQU OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD MITECONDNOINSTR,4 WIDTH,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 AND OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 EQU OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 OPT_CONST,1 SUBTRACT MITECONDNOINSTR,4 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 525 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 526 2 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 527 3 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 WIDTH,32 PAD OPT_CONST,31 WIDTH,1 NEQU WIDTH,5 MULTI_CONCATENATE,1,5 CALL_ARG_VAL,3,0 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,5 SLICE,1 ADD AND CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 528 4 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,31 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 SLICE,1 NOT WIDTH,32 CONCATENATE,2 CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 529 5 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 EQU AND CALL_ARG_VAL,4,0 NOT CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 530 6 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST_4ST,1,1 EQU CALL_ARG_VAL,3,0 OPT_CONST_4ST,1,1 EQU OR OPT_CONST_4ST,1,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 OPT_CONST,16 WIDTH,5 CALL_ARG_VAL,4,0 WIDTH,32 PAD WIDTH,1 M_GT AND OPT_CONST,1 WIDTH,5 CALL_ARG_VAL,4,0 WIDTH,32 PAD OPT_CONST,15 WIDTH,1 M_GT OPT_CONST,0 CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 531 7 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST_4ST,1,1 EQU WIDTH,4 OPT_CONST_4ST,15,15 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG,3 CALL_ARG_VAL,5,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 532 8 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 533 9 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 M_EQU AND RET +bcid 534 10 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1 WIDTH,1 M_EQU AND RET +bcid 535 11 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 NOT AND OPT_CONST,1 CALL_ARG_VAL,3,0 OPT_CONST,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 536 12 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND OPT_CONST,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 NOT CALL_ARG_VAL,4,0 AND AND OPT_CONST,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 537 13 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 SM_GT RET +bcid 538 14 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1 WIDTH,1 EQU WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 EQU AND AND RET +sid TB +bcid 539 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,6 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,6 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/cc/cc_dummy_file b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/cc/cc_dummy_file new file mode 100644 index 0000000..9ec9235 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/cc/cc_dummy_file @@ -0,0 +1,2 @@ +Dummy_file +Missing line/file info diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/cgname.json b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/cgname.json new file mode 100644 index 0000000..39f08d3 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/cgname.json @@ -0,0 +1,920 @@ +{ + "PDDW04SDGZ_H_G": [ + "PDDW04SDGZ_H_G", + "CQ4ek", + "module", + 12 + ], + "PDB3AC_V_G": [ + "PDB3AC_V_G", + "dviib", + "module", + 9 + ], + "PCLAMP_G": [ + "PCLAMP_G", + "DA1Pu", + "module", + 3 + ], + "PDUW04DGZ_H_G": [ + "PDUW04DGZ_H_G", + "YTwQz", + "module", + 26 + ], + "PVSS1ANA_V_G": [ + "PVSS1ANA_V_G", + "gL5Pd", + "module", + 95 + ], + "PVDD3A_H_G": [ + "PVDD3A_H_G", + "DTJPF", + "module", + 86 + ], + "PDDW08DGZ_V_G": [ + "PDDW08DGZ_V_G", + "K0TuH", + "module", + 15 + ], + "PRCUTA_G": [ + "PRCUTA_G", + "uuDJt", + "module", + 47 + ], + "dpram": [ + "dpram", + "bQxt6", + "module", + 135 + ], + "PRDW08DGZ_V_G": [ + "PRDW08DGZ_V_G", + "ZZxj5", + "module", + 49 + ], + "_vcs_unit__348857874": [ + "_vcs_unit__348857874", + "FgDcH", + "module", + 1 + ], + "PDUW16SDGZ_H_G": [ + "PDUW16SDGZ_H_G", + "iWZrk", + "module", + 40 + ], + "PDXOEDG_V_G": [ + "PDXOEDG_V_G", + "EZF3t", + "module", + 43 + ], + "PENDCAPA_G": [ + "PENDCAPA_G", + "wpYca", + "module", + 45 + ], + "sirv_gnrl_dffl": [ + "sirv_gnrl_dffl", + "BM4bj", + "module", + 127 + ], + "spi_bus_decoder_0000": [ + "spi_bus_decoder_0000", + "qLaCg", + "module", + 142 + ], + "PDDW08DGZ_H_G": [ + "PDDW08DGZ_H_G", + "C0gYT", + "module", + 14 + ], + "std": [ + "std", + "reYIK", + "module", + 2 + ], + "PVDD2ANA_V_G": [ + "PVDD2ANA_V_G", + "J6VbG", + "module", + 81 + ], + "PDUW12SDGZ_V_G": [ + "PDUW12SDGZ_V_G", + "qCQFW", + "module", + 37 + ], + "PDB3A_H_G": [ + "PDB3A_H_G", + "dfLHW", + "module", + 6 + ], + "PVSS1DGZ_H_G": [ + "PVSS1DGZ_H_G", + "Zp1LH", + "module", + 96 + ], + "PRUW16SDGZ_V_G": [ + "PRUW16SDGZ_V_G", + "psjSY", + "module", + 71 + ], + "PRDW16SDGZ_V_G": [ + "PRDW16SDGZ_V_G", + "YRh5I", + "module", + 59 + ], + "PDDW04SDGZ_V_G": [ + "PDDW04SDGZ_V_G", + "J6fGD", + "module", + 13 + ], + "PCLAMPC_H_G": [ + "PCLAMPC_H_G", + "UyGax", + "module", + 4 + ], + "PDDW04DGZ_V_G": [ + "PDDW04DGZ_V_G", + "sZaSM", + "module", + 11 + ], + "PCLAMPC_V_G": [ + "PCLAMPC_V_G", + "EyyeT", + "module", + 5 + ], + "PVDD1ANA_V_G": [ + "PVDD1ANA_V_G", + "BL1m7", + "module", + 77 + ], + "PDB3A_V_G": [ + "PDB3A_V_G", + "xqWfY", + "module", + 7 + ], + "PDDW12DGZ_H_G": [ + "PDDW12DGZ_H_G", + "atFKr", + "module", + 18 + ], + "PDB3AC_H_G": [ + "PDB3AC_H_G", + "LsJ1x", + "module", + 8 + ], + "PDDW04DGZ_H_G": [ + "PDDW04DGZ_H_G", + "Z62Gy", + "module", + 10 + ], + "PVSS1A_H_G": [ + "PVSS1A_H_G", + "aYKwj", + "module", + 90 + ], + "PRDW16SDGZ_H_G": [ + "PRDW16SDGZ_H_G", + "V63WF", + "module", + 58 + ], + "PDUW08DGZ_V_G": [ + "PDUW08DGZ_V_G", + "aEWK6", + "module", + 31 + ], + "PDUW12DGZ_V_G": [ + "PDUW12DGZ_V_G", + "NkwYe", + "module", + 35 + ], + "PDDW08SDGZ_H_G": [ + "PDDW08SDGZ_H_G", + "QjV6F", + "module", + 16 + ], + "PDUW16SDGZ_V_G": [ + "PDUW16SDGZ_V_G", + "qePm9", + "module", + 41 + ], + "PDDW12DGZ_V_G": [ + "PDDW12DGZ_V_G", + "eR5Zz", + "module", + 19 + ], + "rst_gen_unit": [ + "rst_gen_unit", + "anuMN", + "module", + 124 + ], + "PDUW16DGZ_H_G": [ + "PDUW16DGZ_H_G", + "M7qR3", + "module", + 38 + ], + "PDDW08SDGZ_V_G": [ + "PDDW08SDGZ_V_G", + "N1ndr", + "module", + 17 + ], + "ramp_gen_0000": [ + "ramp_gen_0000", + "AyqFm", + "module", + 129 + ], + "PDDW12SDGZ_H_G": [ + "PDDW12SDGZ_H_G", + "KpuhN", + "module", + 20 + ], + "ulink_descrambler_32": [ + "ulink_descrambler_32", + "yuek5", + "module", + 120 + ], + "PDDW12SDGZ_V_G": [ + "PDDW12SDGZ_V_G", + "Pzaun", + "module", + 21 + ], + "PDDW16DGZ_H_G": [ + "PDDW16DGZ_H_G", + "GzkJA", + "module", + 22 + ], + "systemregfile": [ + "systemregfile", + "qcK8J", + "module", + 115 + ], + "PRDW16DGZ_V_G": [ + "PRDW16DGZ_V_G", + "Jztd6", + "module", + 57 + ], + "PRUW08SDGZ_V_G": [ + "PRUW08SDGZ_V_G", + "VJ8Wg", + "module", + 63 + ], + "PRUW16SDGZ_H_G": [ + "PRUW16SDGZ_H_G", + "riJVY", + "module", + 70 + ], + "PVDD2ANA_H_G": [ + "PVDD2ANA_H_G", + "mZVHG", + "module", + 80 + ], + "PDDW16DGZ_V_G": [ + "PDDW16DGZ_V_G", + "StNiL", + "module", + 23 + ], + "PDDW16SDGZ_H_G": [ + "PDDW16SDGZ_H_G", + "HiTWu", + "module", + 24 + ], + "PDDW16SDGZ_V_G": [ + "PDDW16SDGZ_V_G", + "ebe78", + "module", + 25 + ], + "ulink_frame_receiver_0000": [ + "ulink_frame_receiver_0000", + "P3BwM", + "module", + 123 + ], + "PRDW08SDGZ_H_G": [ + "PRDW08SDGZ_H_G", + "S90qD", + "module", + 50 + ], + "PDUW04SDGZ_V_G": [ + "PDUW04SDGZ_V_G", + "mJZpP", + "module", + 29 + ], + "PVDD2DGZ_H_G": [ + "PVDD2DGZ_H_G", + "nULrd", + "module", + 82 + ], + "PDUW04DGZ_V_G": [ + "PDUW04DGZ_V_G", + "QGhk6", + "module", + 27 + ], + "syn_fwft_fifo": [ + "syn_fwft_fifo", + "gzftm", + "module", + 117 + ], + "reset_tb": [ + "reset_tb", + "Q3Wk7", + "module", + 148 + ], + "PDUW04SDGZ_H_G": [ + "PDUW04SDGZ_H_G", + "wGYhm", + "module", + 28 + ], + "PDUW08DGZ_H_G": [ + "PDUW08DGZ_H_G", + "KkPJH", + "module", + 30 + ], + "PRUW12SDGZ_V_G": [ + "PRUW12SDGZ_V_G", + "yt645", + "module", + 67 + ], + "PRDW12SDGZ_V_G": [ + "PRDW12SDGZ_V_G", + "zIUFF", + "module", + 55 + ], + "PDUW08SDGZ_H_G": [ + "PDUW08SDGZ_H_G", + "gxqJp", + "module", + 32 + ], + "pulse_generator": [ + "pulse_generator", + "aJYLF", + "module", + 126 + ], + "PRCUT_G": [ + "PRCUT_G", + "uQmb5", + "module", + 46 + ], + "PDUW12DGZ_H_G": [ + "PDUW12DGZ_H_G", + "HYpLe", + "module", + 34 + ], + "PDUW08SDGZ_V_G": [ + "PDUW08SDGZ_V_G", + "UxPrL", + "module", + 33 + ], + "PDUW12SDGZ_H_G": [ + "PDUW12SDGZ_H_G", + "uKPxf", + "module", + 36 + ], + "spi_sys_0000": [ + "spi_sys_0000", + "QT8j3", + "module", + 144 + ], + "PVDD1DGZ_V_G": [ + "PVDD1DGZ_V_G", + "sPggV", + "module", + 79 + ], + "iopad": [ + "iopad", + "ga3jL", + "module", + 114 + ], + "PRDW08DGZ_H_G": [ + "PRDW08DGZ_H_G", + "swWa5", + "module", + 48 + ], + "PDUW16DGZ_V_G": [ + "PDUW16DGZ_V_G", + "FDqaf", + "module", + 39 + ], + "PVSS1AC_H_G": [ + "PVSS1AC_H_G", + "EZJLH", + "module", + 92 + ], + "PRUW12DGZ_H_G": [ + "PRUW12DGZ_H_G", + "hpMjC", + "module", + 64 + ], + "PDXOEDG_H_G": [ + "PDXOEDG_H_G", + "IYQDs", + "module", + 42 + ], + "crc32": [ + "crc32", + "T59nH", + "module", + 122 + ], + "PVDD2POC_H_G": [ + "PVDD2POC_H_G", + "avdwk", + "module", + 84 + ], + "PENDCAP_G": [ + "PENDCAP_G", + "bhWYh", + "module", + 44 + ], + "PRDW08SDGZ_V_G": [ + "PRDW08SDGZ_V_G", + "JznNw", + "module", + 51 + ], + "PVSS3A_H_G": [ + "PVSS3A_H_G", + "jsR1C", + "module", + 106 + ], + "sirv_gnrl_xchecker": [ + "sirv_gnrl_xchecker", + "CjC7H", + "module", + 125 + ], + "PRDW16DGZ_H_G": [ + "PRDW16DGZ_H_G", + "EEqKt", + "module", + 56 + ], + "PRDW12DGZ_H_G": [ + "PRDW12DGZ_H_G", + "VaZm2", + "module", + 52 + ], + "PRDW12DGZ_V_G": [ + "PRDW12DGZ_V_G", + "ZKk4u", + "module", + 53 + ], + "da4008_chip_top": [ + "da4008_chip_top", + "ircEj", + "module", + 141 + ], + "PRDW12SDGZ_H_G": [ + "PRDW12SDGZ_H_G", + "fTzb4", + "module", + 54 + ], + "PRUW08DGZ_H_G": [ + "PRUW08DGZ_H_G", + "fLemy", + "module", + 60 + ], + "PVSS2ANA_H_G": [ + "PVSS2ANA_H_G", + "g8kcb", + "module", + 102 + ], + "PRUW08DGZ_V_G": [ + "PRUW08DGZ_V_G", + "EtT2L", + "module", + 61 + ], + "PRUW08SDGZ_H_G": [ + "PRUW08SDGZ_H_G", + "gwpgC", + "module", + 62 + ], + "PRUW12DGZ_V_G": [ + "PRUW12DGZ_V_G", + "pucZW", + "module", + 65 + ], + "PVDD3A_V_G": [ + "PVDD3A_V_G", + "t6fPF", + "module", + 87 + ], + "PRUW12SDGZ_H_G": [ + "PRUW12SDGZ_H_G", + "EkH6u", + "module", + 66 + ], + "PRUW16DGZ_H_G": [ + "PRUW16DGZ_H_G", + "AVYgt", + "module", + 68 + ], + "PRUW16DGZ_V_G": [ + "PRUW16DGZ_V_G", + "ErxQ3", + "module", + 69 + ], + "PVDD1A_H_G": [ + "PVDD1A_H_G", + "zNPu5", + "module", + 72 + ], + "PVDD1A_V_G": [ + "PVDD1A_V_G", + "CNBi6", + "module", + 73 + ], + "sirv_gnrl_ltch": [ + "sirv_gnrl_ltch", + "UTi0b", + "module", + 128 + ], + "PVDD1AC_H_G": [ + "PVDD1AC_H_G", + "W9VnM", + "module", + 74 + ], + "PVDD1AC_V_G": [ + "PVDD1AC_V_G", + "qn6Yx", + "module", + 75 + ], + "PVDD1ANA_H_G": [ + "PVDD1ANA_H_G", + "fEWTj", + "module", + 76 + ], + "awg_top": [ + "awg_top", + "J5zQK", + "module", + 137 + ], + "PVDD1DGZ_H_G": [ + "PVDD1DGZ_H_G", + "Eie6s", + "module", + 78 + ], + "PVSS2AC_V_G": [ + "PVSS2AC_V_G", + "YBQ1m", + "module", + 101 + ], + "PVSS3AC_V_G": [ + "PVSS3AC_V_G", + "i0k2A", + "module", + 109 + ], + "PVDD3AC_V_G": [ + "PVDD3AC_V_G", + "rZC3e", + "module", + 89 + ], + "PVDD2DGZ_V_G": [ + "PVDD2DGZ_V_G", + "LSxxn", + "module", + 83 + ], + "PVDD2POC_V_G": [ + "PVDD2POC_V_G", + "urn8Q", + "module", + 85 + ], + "PVDD3AC_H_G": [ + "PVDD3AC_H_G", + "U0PST", + "module", + 88 + ], + "tsdn28hpcpuhdb4096x128m4mw_170a_Int_Array": [ + "tsdn28hpcpuhdb4096x128m4mw_170a_Int_Array", + "bghMB", + "module", + 113 + ], + "PVSS1A_V_G": [ + "PVSS1A_V_G", + "ZmPik", + "module", + 91 + ], + "PVSS1AC_V_G": [ + "PVSS1AC_V_G", + "I7RzE", + "module", + 93 + ], + "PVSS1ANA_H_G": [ + "PVSS1ANA_H_G", + "HtwuV", + "module", + 94 + ], + "PVSS1DGZ_V_G": [ + "PVSS1DGZ_V_G", + "jHcbf", + "module", + 97 + ], + "PVSS2A_H_G": [ + "PVSS2A_H_G", + "usz4x", + "module", + 98 + ], + "PVSS2A_V_G": [ + "PVSS2A_V_G", + "fMI2k", + "module", + 99 + ], + "PVSS2AC_H_G": [ + "PVSS2AC_H_G", + "TqmdJ", + "module", + 100 + ], + "PVSS2ANA_V_G": [ + "PVSS2ANA_V_G", + "Md441", + "module", + 103 + ], + "PVSS2DGZ_H_G": [ + "PVSS2DGZ_H_G", + "ke5cH", + "module", + 104 + ], + "PVSS2DGZ_V_G": [ + "PVSS2DGZ_V_G", + "S5Dr6", + "module", + 105 + ], + "PVSS3A_V_G": [ + "PVSS3A_V_G", + "VSdee", + "module", + 107 + ], + "tsdn28hpcpuhdb4096x128m4mw_170a": [ + "tsdn28hpcpuhdb4096x128m4mw_170a", + "UJ4u7", + "module", + 112 + ], + "PVSS3AC_H_G": [ + "PVSS3AC_H_G", + "B0f3F", + "module", + 108 + ], + "PVSS3DGZ_H_G": [ + "PVSS3DGZ_H_G", + "rq1J0", + "module", + 110 + ], + "PVSS3DGZ_V_G": [ + "PVSS3DGZ_V_G", + "IZu3i", + "module", + 111 + ], + "DEM_PhaseSync_4008": [ + "DEM_PhaseSync_4008", + "sIRhK", + "module", + 138 + ], + "dacif_0000": [ + "dacif_0000", + "yeRHW", + "module", + 116 + ], + "dac_regfile": [ + "dac_regfile", + "LR0zI", + "module", + 118 + ], + "ulink_rx": [ + "ulink_rx", + "dteMU", + "module", + 119 + ], + "ulink_descrambler_128": [ + "ulink_descrambler_128", + "qxEhc", + "module", + 121 + ], + "sram_if": [ + "sram_if", + "NABmh", + "module", + 130 + ], + "sram_if_0000": [ + "sram_if_0000", + "nJgqZ", + "module", + 131 + ], + "sram_if_0001": [ + "sram_if_0001", + "z4wk8", + "module", + 132 + ], + "sram_if_0002": [ + "sram_if_0002", + "bEAZ8", + "module", + 133 + ], + "sram_dmux_w_0000": [ + "sram_dmux_w_0000", + "dc6nH", + "module", + 134 + ], + "clk_regfile": [ + "clk_regfile", + "jAdLC", + "module", + 136 + ], + "DA4008_DEM_Parallel_PRBS_1CH": [ + "DA4008_DEM_Parallel_PRBS_1CH", + "cQW1k", + "module", + 139 + ], + "DA4008_DEM_Parallel_PRBS_64CH": [ + "DA4008_DEM_Parallel_PRBS_64CH", + "q09PC", + "module", + 140 + ], + "spi_slave": [ + "spi_slave", + "eAsJz", + "module", + 143 + ], + "spi_if": [ + "spi_if", + "IHYdB", + "module", + 145 + ], + "clk_gen": [ + "clk_gen", + "MEIvW", + "module", + 146 + ], + "DEM_Reverse_64CH_0000": [ + "DEM_Reverse_64CH_0000", + "YnCHV", + "module", + 147 + ], + "DW_sync_0000": [ + "DW_sync_0000", + "zVfcK", + "module", + 149 + ], + "DW_pulse_sync_0000": [ + "DW_pulse_sync_0000", + "Ss3zK", + "module", + 150 + ], + "lvds_if": [ + "lvds_if", + "nS0i0", + "module", + 151 + ], + "TB": [ + "TB", + "sH4Fc", + "module", + 152 + ], + "...MASTER...": [ + "SIM", + "amcQw", + "module", + 153 + ] +} \ No newline at end of file diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/constraint.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/constraint.sdb new file mode 100644 index 0000000..82e87e8 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/constraint.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/covg_defs b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/covg_defs new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/.version b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/.version new file mode 100644 index 0000000..ed555f5 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/.version @@ -0,0 +1,4 @@ +O-2018.09-SP2_Full64 +Build Date = Feb 28 2019 22:34:30 +RedHat +Compile Location: /home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/AllModulesSkeletons.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/AllModulesSkeletons.sdb new file mode 100644 index 0000000..645927b Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/AllModulesSkeletons.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/HsimSigOptDb.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/HsimSigOptDb.sdb new file mode 100644 index 0000000..a582302 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/HsimSigOptDb.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/dumpcheck.db b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/dumpcheck.db new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/dve_debug.db.gz b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/dve_debug.db.gz new file mode 100644 index 0000000..a58895a Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/dve_debug.db.gz differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/fsearch/.create_fsearch_db b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/fsearch/.create_fsearch_db new file mode 100755 index 0000000..0efe198 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/fsearch/.create_fsearch_db @@ -0,0 +1,9 @@ +#!/bin/sh -h +PYTHONHOME=/opt/synopsys/vcs-mx/O-2018.09-SP2/etc/search/pyh +export PYTHONHOME +PYTHONPATH=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/pylib27 +export PYTHONPATH +LD_LIBRARY_PATH=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib:/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/pylib27 +export LD_LIBRARY_PATH +/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/vcsfind_create_index.exe -z "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/./idents_X4vtNx.xml.gz" "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" +\mv "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.db" diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/fsearch/check_fsearch_db b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/fsearch/check_fsearch_db new file mode 100755 index 0000000..1c1ff54 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/fsearch/check_fsearch_db @@ -0,0 +1,57 @@ +#!/bin/sh -h + +FILE_PATH="/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch" +lockfile="${FILE_PATH}"/lock + +FSearch_lock_release() { + echo "" > /dev/null +} +create_fsearch_db_ctrl() { + if [ -s "${FILE_PATH}"/fsearch.stat ]; then + if [ -s "${FILE_PATH}"/fsearch.log ]; then + echo "ERROR building identifier database failed. Check ${FILE_PATH}/fsearch.log" + else + cat "${FILE_PATH}"/fsearch.stat + fi + return + fi + nohup "$1" > "${FILE_PATH}"/fsearch.log 2>&1 193>/dev/null & + MY_PID=`echo $!` + BUILDER="pid ${MY_PID} ${USER}@${hostname}" + echo "INFO Started building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." + echo "INFO Still building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." > "${FILE_PATH}"/fsearch.stat + return +} + +dir_name=`/bin/dirname "$0"` +if [ "${dir_name}" = "." ]; then + cd $dir_name + dir_name=`/bin/pwd` +fi +if [ -d "$dir_name"/../../../../../../../../../../.. ]; then + cd "$dir_name"/../../../../../../../../../../.. +fi + +if [ -f "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db" ]; then + if [ ! -f "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.db" ]; then + if [ "$#" -eq 1 ] && [ "x$1" == "x-background" ]; then + trap FSearch_lock_release EXIT + ( + flock 193 + create_fsearch_db_ctrl "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db" + exit 193 + ) 193> "$lockfile" + rstat=$? + if [ "${rstat}"x != "193x" ]; then + exit $rstat + fi + else + "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db" + if [ -f "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then + rm -f "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" + fi + fi + elif [ -f "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then + rm -f "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" + fi +fi diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/fsearch/fsearch.stat b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/fsearch/fsearch.stat new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/fsearch/idents_X4vtNx.xml.gz b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/fsearch/idents_X4vtNx.xml.gz new file mode 100644 index 0000000..56532b3 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/fsearch/idents_X4vtNx.xml.gz differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz new file mode 100644 index 0000000..f24a0fd Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/src_files_verilog b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/src_files_verilog new file mode 100644 index 0000000..376b419 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/src_files_verilog @@ -0,0 +1,48 @@ +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/lib/tphn28hpcpgv18.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/lib/tsdn28hpcpuhdb4096x128m4mw_170a_ffg0p99v0c.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/DEM_Reverse.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/DEM_Reverse_64CH.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/DW_pulse_sync.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/DW_reset_sync.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/DW_stream_sync.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/DW_sync.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/LVDS_DRIVER.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/SPI_DRIVER.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/clk_gen.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/clock_tb.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/reset_tb.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/model/spi_if.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/awg/awg_ctrl.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/awg/awg_top.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/clk/clk_regfile.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/comm/pulse_generator.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/comm/ramp_gen.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/comm/sirv_gnrl_dffs.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/comm/sirv_gnrl_xchecker.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/comm/syncer.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/dac_regfile/dac_regfile.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/dacif/dacif.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/define/chip_define.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/define/chip_undefine.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/dem/DA4008_DEM_Parallel_PRBS_1CH.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/dem/DA4008_DEM_Parallel_PRBS_64CH.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/dem/DEM_PhaseSync_4008.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/fifo/syn_fwft_fifo.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/io/iopad.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/lvds/ulink_rx.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/memory/bhv_spram.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/memory/dpram.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/memory/spram.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/memory/sram_dmux.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/memory/sram_if.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/memory/tsmc_dpram.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/rstgen/rst_gen_unit.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/rstgen/rst_sync.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/spi/spi_bus_decoder.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/spi/spi_pll.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/spi/spi_slave.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/spi/spi_sys.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/systemregfile/systemregfile.v +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/top/da4008_chip_top.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/rtl/top/digital_top.sv +/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/TB.sv diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/topmodules b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/topmodules new file mode 100644 index 0000000..5dce012 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/topmodules @@ -0,0 +1 @@ +r’LžD•B’–\ƒ$…c–Cšs°1´S¤ ¦%ºg¿)!©t¬x"µ.º<8¦Y©S9Iƒ:“>­B°;“?»¹¨5¨7¥2›AŸ*')°.´Q)*¤ ¦$*+Ÿs£xB“Iµ,º8D“O¦X©PE“P‰6Ž›tŸn§ª7¯\³2¤[¦e¬Z¯>$ m‹Ž=¤¦:†2ˆB ;¤§Rªe¯i´ †F‰)¤B¦L¤m¦w¬l¯O†LŠ"¦V©I¨n¬Aµ»l ¥¶O \ No newline at end of file diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/vir.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/vir.sdb new file mode 100644 index 0000000..9b4dea7 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/debug_dump/vir.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/eblklvl.db b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/eblklvl.db new file mode 100644 index 0000000..2870040 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/eblklvl.db differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/elabmoddb.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/elabmoddb.sdb new file mode 100644 index 0000000..4d03f67 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/elabmoddb.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/external_functions b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/external_functions new file mode 100644 index 0000000..394a9dd --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/external_functions @@ -0,0 +1,129 @@ +pli $fsdbDumpvars novas_call_fsdbDumpvars - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpvarsES novas_call_fsdbDumpvarsES - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpMDA novas_call_fsdbDumpMDA - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpSVA novas_call_fsdbDumpSVA - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpvarsByFile novas_call_fsdbDumpvarsByFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbSuppress novas_call_fsdbSuppress - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpon novas_call_fsdbDumpon - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpoff novas_call_fsdbDumpoff - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbSwitchDumpfile novas_call_fsdbSwitchDumpfile - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpfile novas_call_fsdbDumpfile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbAutoSwitchDumpfile novas_call_fsdbAutoSwitchDumpfile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpFinish novas_call_fsdbDumpFinish - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpflush novas_call_fsdbDumpflush - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbLog novas_call_fsdbLog - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbAddRuntimeSignal novas_call_fsdbAddRuntimeSignal - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpSC novas_call_fsdbDumpSC - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpvarsToFile novas_call_fsdbDumpvarsToFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_create_transaction_stream novas_call_sps_create_transaction_stream - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_begin_transaction novas_call_sps_begin_transaction - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_end_transaction novas_call_sps_end_transaction - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_free_transaction novas_call_sps_free_transaction - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_add_attribute novas_call_sps_add_attribute - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_update_label novas_call_sps_update_label - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_add_relation novas_call_sps_add_relation - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbWhatif novas_call_fsdbWhatif - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $paa_init novas_call_paa_init - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $paa_sync novas_call_paa_sync - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpClassMethod novas_call_fsdbDumpClassMethod - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbSuppressClassMethod novas_call_fsdbSuppressClassMethod - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbSuppressClassProp novas_call_fsdbSuppressClassProp - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpMDAByFile novas_call_fsdbDumpMDAByFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_create_stream_begin novas_call_fsdbEvent_create_stream_begin - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_define_attribute novas_call_fsdbEvent_add_stream_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_create_stream_end novas_call_fsdbEvent_create_stream_end - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_begin novas_call_fsdbEvent_begin - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_set_label novas_call_fsdbEvent_set_label - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_attribute novas_call_fsdbEvent_add_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_tag novas_call_fsdbEvent_add_tag - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_end novas_call_fsdbEvent_end - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_relation novas_call_fsdbEvent_add_relation - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_get_error_code novas_call_fsdbEvent_get_error_code - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_stream_attribute novas_call_fsdbTrans_add_stream_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_scope_attribute novas_call_fsdbTrans_add_scope_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_interactive novas_call_sps_interactive - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_test novas_call_sps_test - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpClassObject novas_call_fsdbDumpClassObject - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpClassObjectByFile novas_call_fsdbDumpClassObjectByFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $ridbDump novas_call_ridbDump - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_flush_file novas_call_sps_flush_file - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpPSL novas_call_fsdbDumpPSL - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumplimit novas_call_fsdbDumplimit - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpvars novas_call_fsdbDumpvars - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsES novas_call_fsdbDumpvarsES - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDA novas_call_fsdbDumpMDA - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVA novas_call_fsdbDumpSVA - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsByFile novas_call_fsdbDumpvarsByFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppress novas_call_fsdbSuppress - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpon novas_call_fsdbDumpon - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpoff novas_call_fsdbDumpoff - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSwitchDumpfile novas_call_fsdbSwitchDumpfile - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpfile novas_call_fsdbDumpfile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbAutoSwitchDumpfile novas_call_fsdbAutoSwitchDumpfile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpFinish novas_call_fsdbDumpFinish - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpflush novas_call_fsdbDumpflush - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbLog novas_call_fsdbLog - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbAddRuntimeSignal novas_call_fsdbAddRuntimeSignal - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSC novas_call_fsdbDumpSC - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsToFile novas_call_fsdbDumpvarsToFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_create_transaction_stream novas_call_sps_create_transaction_stream - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_begin_transaction novas_call_sps_begin_transaction - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_end_transaction novas_call_sps_end_transaction - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_free_transaction novas_call_sps_free_transaction - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_add_attribute novas_call_sps_add_attribute - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_update_label novas_call_sps_update_label - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_add_relation novas_call_sps_add_relation - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbWhatif novas_call_fsdbWhatif - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $paa_init novas_call_paa_init - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $paa_sync novas_call_paa_sync - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassMethod novas_call_fsdbDumpClassMethod - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppressClassMethod novas_call_fsdbSuppressClassMethod - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppressClassProp novas_call_fsdbSuppressClassProp - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAByFile novas_call_fsdbDumpMDAByFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_create_stream_begin novas_call_fsdbEvent_create_stream_begin - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_define_attribute novas_call_fsdbEvent_add_stream_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_create_stream_end novas_call_fsdbEvent_create_stream_end - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_begin novas_call_fsdbEvent_begin - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_set_label novas_call_fsdbEvent_set_label - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_attribute novas_call_fsdbEvent_add_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_tag novas_call_fsdbEvent_add_tag - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_end novas_call_fsdbEvent_end - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_relation novas_call_fsdbEvent_add_relation - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_get_error_code novas_call_fsdbEvent_get_error_code - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_stream_attribute novas_call_fsdbTrans_add_stream_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_scope_attribute novas_call_fsdbTrans_add_scope_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_interactive novas_call_sps_interactive - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_test novas_call_sps_test - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassObject novas_call_fsdbDumpClassObject - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassObjectByFile novas_call_fsdbDumpClassObjectByFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $ridbDump novas_call_ridbDump - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_flush_file novas_call_sps_flush_file - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSL novas_call_fsdbDumpPSL - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDisplay novas_call_fsdbDisplay - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumplimit novas_call_fsdbDumplimit - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMem novas_call_fsdbDumpMem - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemNow novas_call_fsdbDumpMemNow - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemInScope novas_call_fsdbDumpMemInScope - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDANow novas_call_fsdbDumpMDANow - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAOnChange novas_call_fsdbDumpMDAOnChange - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAInScope novas_call_fsdbDumpMDAInScope - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemInFile novas_call_fsdbDumpMemInFile - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSLon novas_call_fsdbDumpPSLon - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSLoff novas_call_fsdbDumpPSLoff - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVAon novas_call_fsdbDumpSVAon - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVAoff novas_call_fsdbDumpSVAoff - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpStrength novas_call_fsdbDumpStrength - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSingle novas_call_fsdbDumpSingle - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpIO novas_call_fsdbDumpIO - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPattern novas_call_fsdbDumpPattern - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSubstituteHier novas_call_fsdbSubstituteHier - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $dumpports DumpPortsIeeeCALL - DumpPortsMISC +pli $lsi_dumpports DumpPortsLsiCALL - DumpPortsMISC +pli $dumpportson DumpPortsOnCALL - DumpPortsMISC +pli $dumpportsoff DumpPortsOffCALL - DumpPortsMISC +pli $dumpportsflush DumpPortsFlushCALL - DumpPortsMISC +pli $simlearn simLearnCall simLearnCheck simLearnMisc +pli $dumpportsall DumpPortsAllCALL - DumpPortsMISC +pli $dumpportslimit DumpPortsLimitCALL - DumpPortsMISC +pli $countdrivers CountDriversCALL - - +pli $vcsmemprof DMMemProfCALL DMMemProfCheck DMMemProfMISC diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/hslevel_callgraph.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/hslevel_callgraph.sdb new file mode 100644 index 0000000..a00346b Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/hslevel_callgraph.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/hslevel_level.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/hslevel_level.sdb new file mode 100644 index 0000000..4cd2f62 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/hslevel_level.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/hslevel_rtime_level.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/hslevel_rtime_level.sdb new file mode 100644 index 0000000..8153356 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/hslevel_rtime_level.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/hsscan_cfg.dat b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/hsscan_cfg.dat new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/indcall.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/indcall.sdb new file mode 100644 index 0000000..c8ddf48 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/indcall.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/indcall_32553.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/indcall_32553.sdb new file mode 100644 index 0000000..50736b6 Binary files /dev/null and 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b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/indcall_32575.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/indcall_32576.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/indcall_32576.sdb new file mode 100644 index 0000000..574a192 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/indcall_32576.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/indcall_32577.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/indcall_32577.sdb new file mode 100644 index 0000000..c482d66 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/indcall_32577.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/indcall_32578.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/indcall_32578.sdb new file mode 100644 index 0000000..0e5abe3 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/indcall_32578.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/indcall_32579.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/indcall_32579.sdb new file mode 100644 index 0000000..5dd9049 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/indcall_32579.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/nsparam.dat b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/nsparam.dat new file mode 100644 index 0000000..1afe863 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/nsparam.dat differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/pcc.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/pcc.sdb new file mode 100644 index 0000000..d7c1589 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/pcc.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/pcxpxmr.dat b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/pcxpxmr.dat new file mode 100644 index 0000000..ee5778d Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/pcxpxmr.dat differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/prof.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/prof.sdb new file mode 100644 index 0000000..76179fc Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/prof.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/rmapats.dat b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/rmapats.dat new file mode 100644 index 0000000..cc1f304 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/rmapats.dat differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/rmapats.so b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/rmapats.so new file mode 100755 index 0000000..6df9faa Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/rmapats.so differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/saifNetInfo.db b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/saifNetInfo.db new file mode 100644 index 0000000..a69d3f9 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/saifNetInfo.db @@ -0,0 +1,22 @@ +7 +TB.U_da4008_chip_top.U_iopad.PDDW08SDGZ_V_G_sync_out +C +Scal +TB.U_da4008_chip_top.U_iopad.PDUW08SDGZ_V_G_irq +C +Scal +TB.U_da4008_chip_top.U_iopad.PDUW08SDGZ_V_G_miso +C +Scal +tsmc_dpram +spram_512X8192_generation®BWEBA +All +tsmc_dpram +spram_512X8192_generation®BWEBB +All +tsmc_dpram +spram_512X8192_generation®U_CEBA +All +tsmc_dpram +spram_512X8192_generation®U_CEBB +All diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/simv.kdb b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/simv.kdb new file mode 100644 index 0000000..68eacf4 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/simv.kdb @@ -0,0 +1,16 @@ +rc file Version 1.0 + +[Design] +COMPILE_PATH=/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top +SystemC=FALSE +UUM=FALSE +KDB=FALSE +USE_NOVAS_HOME=FALSE +COSIM=FALSE +TOP=PCLAMP_G PCLAMPC_H_G PCLAMPC_V_G PDB3A_H_G PDB3A_V_G PDB3AC_H_G PDB3AC_V_G PDDW04DGZ_H_G PDDW04DGZ_V_G PDDW04SDGZ_H_G PDDW08DGZ_H_G PDDW08DGZ_V_G PDDW08SDGZ_H_G PDDW08SDGZ_V_G PDDW12DGZ_H_G PDDW12DGZ_V_G PDDW12SDGZ_H_G PDDW12SDGZ_V_G PDDW16DGZ_H_G PDDW16DGZ_V_G PDDW16SDGZ_H_G PDDW16SDGZ_V_G PDUW04DGZ_H_G PDUW04DGZ_V_G PDUW04SDGZ_H_G PDUW08DGZ_H_G PDUW08DGZ_V_G PDUW08SDGZ_H_G PDUW12DGZ_H_G PDUW12DGZ_V_G PDUW12SDGZ_H_G PDUW12SDGZ_V_G PDUW16DGZ_H_G PDUW16DGZ_V_G PDUW16SDGZ_H_G PDUW16SDGZ_V_G PDXOEDG_H_G PDXOEDG_V_G PENDCAP_G PENDCAPA_G PRCUT_G PRCUTA_G PRDW08DGZ_H_G PRDW08DGZ_V_G PRDW08SDGZ_H_G PRDW08SDGZ_V_G PRDW12DGZ_H_G PRDW12DGZ_V_G PRDW12SDGZ_H_G PRDW12SDGZ_V_G PRDW16DGZ_H_G PRDW16DGZ_V_G PRDW16SDGZ_H_G PRDW16SDGZ_V_G PRUW08DGZ_H_G PRUW08DGZ_V_G PRUW08SDGZ_H_G PRUW08SDGZ_V_G PRUW12DGZ_H_G PRUW12DGZ_V_G PRUW12SDGZ_H_G PRUW12SDGZ_V_G PRUW16DGZ_H_G PRUW16DGZ_V_G PRUW16SDGZ_H_G PRUW16SDGZ_V_G PVDD1A_H_G PVDD1A_V_G PVDD1AC_H_G PVDD1AC_V_G PVDD1ANA_H_G PVDD1ANA_V_G PVDD1DGZ_H_G PVDD1DGZ_V_G PVDD2ANA_H_G PVDD2ANA_V_G PVDD2DGZ_H_G PVDD2DGZ_V_G PVDD2POC_H_G PVDD2POC_V_G PVDD3A_H_G PVDD3A_V_G PVDD3AC_H_G PVDD3AC_V_G PVSS1A_H_G PVSS1A_V_G PVSS1AC_H_G PVSS1AC_V_G PVSS1ANA_H_G PVSS1ANA_V_G PVSS1DGZ_H_G PVSS1DGZ_V_G PVSS2A_H_G PVSS2A_V_G PVSS2AC_H_G PVSS2AC_V_G PVSS2ANA_H_G PVSS2ANA_V_G PVSS2DGZ_H_G PVSS2DGZ_V_G PVSS3A_H_G PVSS3A_V_G PVSS3AC_H_G PVSS3AC_V_G PVSS3DGZ_H_G PVSS3DGZ_V_G sirv_gnrl_xchecker sirv_gnrl_dffl sirv_gnrl_ltch clk_gen reset_tb TB +OPTION=-ssz -ssv -ssy +ELAB_OPTION=-ssz -ssv -ssy + +[Value] +WREALX=ffff534e50535f58 +WREALZ=ffff534e50535f5a diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/stitch_nsparam.dat b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/stitch_nsparam.dat new file mode 100644 index 0000000..0357d47 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/stitch_nsparam.dat differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/tt.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/tt.sdb new file mode 100644 index 0000000..f118f49 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/tt.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/ttIncr_32553.sdb b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/ttIncr_32553.sdb new file mode 100644 index 0000000..698630c Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/ttIncr_32553.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/ttIncr_32573.sdb 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b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/ttIncr_32579.sdb differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcs_rebuild b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcs_rebuild new file mode 100755 index 0000000..403c9c0 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcs_rebuild @@ -0,0 +1,4 @@ +#!/bin/sh -e +# This file is automatically generated by VCS. Any changes you make +# to it will be overwritten the next time VCS is run. +vcs '-full64' '-j8' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+all' '-debug_region+cell+encrypt' '-P' '/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab' '/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a' '+define+DUMP_FSDB' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-cm' 'line+cond+fsm+tgl+branch' '-cm_dir' './coverage/simv.vdb' '-f' 'filelist_vlg.f' '+incdir+./../../rtl/define' '+incdir+./../../rtl/qubitmcu' '+incdir+./../../model' 2>&1 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_master_hsim_elabout.db b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_master_hsim_elabout.db new file mode 100644 index 0000000..d941a4e --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_master_hsim_elabout.db @@ -0,0 +1,691 @@ +hsDirType 1 +fHsimDesignHasDebugNodes 63 +fNSParam 1024 +fLargeSizeSdfTest 0 +fHsimDelayGateMbme 0 +fNoMergeDelays 0 +fHsimAllMtmPat 0 +fHsimCertRaptMode 0 +fSharedMasterElab 0 +hsimLevelizeDone 1 +fHsimCompressDiag 1 +fHsimPowerOpt 0 +fLoopReportElab 0 +fHsimRtl 0 +fHsimCbkOptVec 1 +fHsimDynamicCcnHeur 1 +fHsimPvcs 0 +fHsimPvcsCcn 0 +fHsimOldLdr 0 +fHsimSingleDB 1 +uVfsGcLimit 50 +fHsimCompatSched 0 +fHsimCompatOrder 0 +fHsimTransUsingdoMpd32 0 +fHsimDynamicElabForGates 1 +fHsimDynamicElabForVectors 0 +fHsimDynamicElabForVectorsAlways 0 +fHsimDynamicElabForVectorsMinputs 0 +fHsimDeferForceSelTillReElab 0 +fHsimModByModElab 1 +fSvNettRealResType 0 +fHsimExprID 1 +fHsimSequdpon 0 +fHsimDatapinOpt 0 +fHsimExprPrune 0 +fHsimMimoGate 0 +fHsimNewChangeCheckFrankch 1 +fHsimNoSched0Front 0 +fHsimNoSched0FrontForMd 1 +fHsimScalReg 0 +fHsimNtbVl 0 +fHsimICTimeStamp 0 +fHsimICDiag 0 +fHsimNewCSDF 1 +vcselabIncrMode 2 +fHsimMPPackDelay 0 +fHsimMultDriver 0 +fHsimPart 0 +fHsimPrlComp 0 +fHsimPartTest 0 +fHsimTestChangeCheck 0 +fHsimTestFlatNodeOrder 0 +fHsimTestNState 0 +fHsimPartDebug 0 +fHsimPartFlags 0 +fHsimOdeSched0 0 +fHsimNewRootSig 1 +fHsimDisableRootSigModeOpt 0 +fHsimTestRootSigModeOpt 0 +fHsimIncrWriteOnce 0 +fHsimUnifInterfaceFlow 1 +fHsimUnifInterfaceFlowDiag 0 +fHsimUnifInterfaceFlowXmrDiag 0 +fHsimUnifInterfaceMultiDrvChk 1 +fHsimXVirForGenerateScope 0 +fHsimCongruencyIntTestI 0 +fHsimCongruencySVA 0 +fHsimCongruencySVADbg 0 +fHsimCongruencyLatchEdgeFix 0 +fHsimCongruencyFlopEdgeFix 0 +fHsimCongruencyXprop 0 +fHsimCongruencyXpropFix 0 +fHsimCongruencyXpropDbsEdge 0 +fHsimCongruencyResetRecoveryDbs 0 +fHsimCongruencyClockControlDiag 0 +fHsimCongruencySampleUpdate 0 +fHsimCongruencyFFDbsFix 0 +fHsimCongruency 0 +fHsimCongruencySlave 0 +fHsimCongruencyCombinedLoads 0 +fHsimCongruencyFGP 0 +fHsimDeraceClockDataUdp 0 +fHsimDeraceClockDataLERUpdate 0 +fHsimCongruencyPC 0 +fHsimCongruencyPCInl 0 +fHsimCongruencyPCDbg 0 +fHsimCongruencyPCNoReuse 0 +fHsimCongruencyDumpHier 0 +fHsimCongruencyResolution 0 +fHsimCongruencyEveBus 0 +fHsimHcExpr 0 +fHsCgOptModOpt 0 +fHsCgOptSlowProp 0 +fHsimCcnOpt 1 +fHsimCcnOpt2 1 +fHsimCcnOpt3 0 +fHsimSmdMap 0 +fHsimSmdDiag 0 +fHsimSmdSimProf 0 +fHsimSgdDiag 0 +fHsimRtDiagLite 0 +fHsimRtDiagLiteCevent 100 +fHsimRtDiag 0 +fHsimSkRtDiag 0 +fHsimDDBSRtdiag 0 +fHsimDbg 0 +fHsimCompWithGates 0 +fHsimMdbDebugOpt 0 +fHsimMdbDebugOptP1 0 +fHsimMdbDebugOptP2 0 +fHsimMdbPruneOpt 1 +fHsimMdbMemOpt 0 +hsimRandValue 0 +fHsimSimMemProfile 0 +fHsimSimTimeProfile 0 +fHsimElabMemProfile 0 +fHsimElabTimeProfile 0 +fHsimElabMemNodesProfile 0 +fHsimElabMemAllNodesProfile 0 +fHsimDisableVpdGatesProfile 0 +fHsimFileProfile 0 +fHsimCountProfile 0 +fHsimXmrDefault 1 +fHsimFuseWireAndReg 0 +fHsimFuseSelfDrvLogic 0 +fHsimFuseProcess 0 +fHsimNoStitchDump 0 +fHsimAllExtXmrs 0 +fHsimAllXmrs 1 +fHsimMvsimDb 0 +fHsimTaskFuncXmrs 0 +fHsimTaskFuncXmrsDbg 0 +fHsimAllTaskFuncXmrs 0 +fHsimPageArray 16383 +fHsimPageControls 16383 +hsDfsNodePageElems 0 +hsNodePageElems 0 +hsFlatNodePageElems 0 +hsGateMapPageElems 0 +hsGateOffsetPageElems 0 +hsGateInputOffsetPageElems 0 +hsDbsOffsetPageElems 0 +hsMinPulseWidthPageElems 0 +hsNodeUpPatternPageElems 0 +hsNodeDownPatternPageElems 0 +hsNodeUpOffsetPageElems 0 +hsNodeEblkOffsetPageElems 0 +hsNodeDownOffsetPageElems 0 +hsNodeUpdateOffsetPageElems 0 +hsSdfOffsetPageElems 0 +fHsimPageAllLevelData 0 +fHsimAggrCg 0 +fHsimViWire 1 +fHsimPcCbOpt 1 +fHsimAmsTunneling 0 +fHsimAmsTunnelingDiag 0 +fHsimScUpwardXmrNoSplit 1 +fHsimOrigNdbViewOnly 0 +fHsimVcsInterface 1 +fHsimVcsInterfaceAlias 1 +fHsimSVTypesIntf 1 +fUnifiedAssertCtrlDiag 0 +fHsimEnable2StateScal 0 +fHsimDisable2StateScalIbn 0 +fHsimVcsInterfaceAliasDbg 0 +fHsimVcsInterfaceDbg 0 +fHsimVcsVirtIntfDbg 0 +fHsimVcsAllIntfVarMem 0 +fHsimCheckVIDynLoadOffsets 0 +fHsimModInline 1 +fHsimModInlineDbg 0 +fHsimPCDrvLoadDbg 0 +fHsimDrvChk 1 +fHsimRtlProcessingNeeded 0 +fHsimGrpByGrpElab 0 +fHsimGrpByGrpElabMaster 0 +fHsimNoParentSplitPC 0 +fHsimNusymMode 0 +fHsimOneIntfPart 0 +fHsimCompressInSingleDb 2 +fHsimCompressFlatDb 0 +fHsimNoTime0Sched 1 +fHsimMdbVectorizeInstances 0 +fHsimMdbSplitGates 0 +fHsimDeleteInstances 0 +fHsimUserDeleteInstances 0 +fHsimDeleteGdb 0 +fHsimDeleteInstancesMdb 0 +fHsimShortInstMap 0 +fHsimMdbVectorizationDump 0 +fHsimScanVectorize 0 +fHsimParallelScanVectorize 0 +noInstsInVectorization 0 +cHsimNonReplicatedInstances 0 +fHsimScanRaptor 0 +fHsimConfigFileCount 0 +fHsimVectorConstProp 0 +fHsimPromoteParam 0 +fHsimNoVecInRaptor 0 +fRaptorDumpVal 0 +fRaptorVecNodes 0 +fRaptorVecNodes2 0 +fRaptorNonVecNodes 0 +fRaptorBdrNodes 0 +fRaptorVecGates 0 +fRaptorNonVecGates 0 +fRaptorTotalNodesBeforeVect 0 +fRaptorTotalGatesBeforeVect 0 +fHsimCountRaptorBits 0 +fHsimNewEvcd 1 +fHsimNewEvcdMX 0 +fHsimNewEvcdVecRoot 1 +fHsimNewEvcdForce 1 +fHsimNewEvcdTest 0 +fHsimNewEvcdObnDrv 1 +fHsimNewEvcdW 1 +fHsimNewEvcdWTest 0 +fHsimEvcdDbgFlags 0 +fHsimNewEvcdMultiDrvFmt 1 +fHsimDumpOffsetData 1 +fFlopGlitchDetect 0 +fHsimClkGlitch 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+fNewDtviFuse 0 +fHsimVcsGenTLS 1 +fAssertSuccDebugLevelDump 0 +fHsimMinputsChangeCheck 0 +fHsimClkLayout 0 +fHsimIslandLayout 0 +fHsimConfigSched0 0 +fHsimSelectFuseAfterDfuse 0 +vcsNettypeDbgOpt 4 +fHsimFoldedCell 0 +fHsimSimon2Mdb 0 +fHsimSWaveEmul 0 +fHsimSWaveDumpMDB 0 +fHsimSWaveDumpFlatData 0 +fHsimRenumberAlias 0 +fHsimAliasRenumbered 0 +fHilCgMode 115 +fHsimUnionOpt 0 +fHsimFuseSGDBoundaryNodes 0 +fHsimRemoveCapsVec 0 +fHsimSlowNfsRmapats 0 +fHsimCertRaptScal 0 +fHsimCertRaptMdbClock 0 +fHsCgOptMux 0 +fHsCgOptFrc 0 +fHsCgOpt30 0 +fHsLpNoCapsOpt 0 +fHsCgOpt4State 1 +fHashTableSize 12 +fSkipStrChangeOnDelay 1 +fHsimTcheckOpt 0 +fHsCgOptMuxMClk 0 +fHsCgOptMuxFrc 0 +fHsCgOptNoPcb 0 +fHsCgOptMin1 0 +fHsCgOptUdpChk 0 +fHsChkXForSlowSigProp 1 +fHsimVcsParallelDbg 0 +fHsimVcsParallelStrategy 0 +fHsimVcsParallelOpt 0 +fHsimVcsParallelSubLevel 4 +fHsimParallelEblk 0 +fHsimByteCodeParts 1 +fHsimByteCodePartTesting 0 +fHsimByteCodePartAssert 0 +fFgpNovlInComp 0 +fFutEventPRL 0 +fFgpNbaDelay 0 +fHsimDbsFlagsByteArray 0 +fHsimDbsFlagsByteArrayTC 0 +fHsimDbsFlagsThreadArray 0 +fHsimLevelCompaction 0 +fHsimLevelCompactionThreshold 0 +fHsimGateEdgeEventSched 0 +fHsimGateEdgeEventSchedThreshold 0 +fHsimGateEdgeEventSchedSanity 0 +fHsimSelectEdgeEventSched 0 +fHsimSelectEdgeEventSchedNoTempReuse 0 +fHsimSelectEdgeEventSchedThreshold 0 +fHsimMaxComboLevels 0 +fHsimEgschedDynelab 0 +fHsimUdpClkDynelab 0 +fUdpLayoutOnClk 0 +fHsimDiagClk 1 +fDbsPreCheck 0 +fHsimSched0Analysis 0 +fHsimMultiDriverSched0 0 +fHsimLargeIbnSched 0 +fFgpHierarchical 0 +fFgpHierAllElabModAsRoot 0 +fFgpHierPCElabModAsRoot 0 +fFgpAdjustDataLevelOfLatch 1 +fHsimUdpXedgeEval 0 +fFgpRaceCheck 0 +fFgpUnifyClk 0 +fFgpSmallClkTree 0 +fFgpSmallRtlClkTree 4 +fFgpNoRtlUnlink 0 +fFgpNoRtlAuxLevel 0 +fFgpNumPartitions 8 +fFgpMultiSocketCompile 0 +fFgpMultiSocketAfterGrping 0 +fFgpMultiSocketNCuts 1 +fFgpMultiSocketDiag 0 +fFgpMultiSocketRecomputePart 1 +fFgpDataDepOn 0 +fFgpDDIgnore 0 +fFgpXmrDepOn 0 +fFgpTbCbOn 0 +fFgpTbEvOn 1 +fFgpTbNoVSA 0 +fFgpTbEvXmr 0 +fFgpTbEvCgCall 1 +fFgpDisabledLevel 512 +fFgpSched0User 0 +fFgpNoSdDelayedNbas 1 +fFgpTimingFlags 0 +fFgpTcLoadThreshold 0 +fFgpSched0Level 0 +fHsimFgpMultiClock 0 +fFgpScanOptFix 0 +fFgpSched0UdpData 0 +fFgpSanityTest 0 +fFgpSanityTest_Eng 1 +fFgpAlternativeLevelization 0 +fFgpHighFanoutThreshold 1024 +fFgpSplitGroupLevels 1 +fFgpSplitGroupIbn 1 +fFgpSplitGroupGateEdge 1 +fFgpSplitGroupEval 3 +fFgpGroupingPerfDiag 0 +fFgpSplitGroupDiag 0 +fFgpStricDepModDiag 0 +fFgpIPProtect 0 +fFgpIPProtectStrict 0 +fFgpNoVirtualThreads 0 +fFgpLoadBalance0DiagComp 0 +fFgpLoadBalance0CompileTime 1 +fFgpDepositDiag 0 +fFgpEvtDiag.diagOn 0 +fFgpEvtDiag.printAllNodes 0 +fFgpMangleDiagLog 0 +fFgpMultiExclDiag 0 +fFgpSingleExclReason 0 +fHsDoFaninFanoutSanity 0 +fHsFgpNonDbsOva 1 +fFgpParallelTask 1 +fFgpIbnSched 0 +fFgpIbnSchedOpt 0 +fFgpIbnSchedNoLevel 0 +fFgpIbnSchedThreshold 0 +fFgpIbnSchedDyn 0 +fFgpObnSched 0 +fFgpMpStateByte 0 +fFgpTcStateByte 0 +fHsimVirtIntfDynLoadSched 0 +fHsimNetXmrDrvChk 0 +fFgpNoRtimeFgp 0 +fHsFgpGlSched0 0 +fFgpExclReason 0 +fHsimIslandByIslandElab 0 +fHsimIslandByIslandFlat 0 +fHsimIslandByIslandFlat1 0 +fHsimVpdIBIF 0 +fHsimXmrIBIF 0 +fHsimReportTime 0 +fHsimElabJ 0 +fHsimElabJ4SDF 0 +cElabProcs 0 +hf_fHsimElabJ 0 +fHsimElabJOpt 0 +fHsimElabJMMFactor 0 +fHsimOneInstCap 0 +fHsimSchedMinput 0 +fHsimSchedSeqPrim 0 +fHsimSchedRandom 0 +fHsimSchedAll 0 +fHsimSchedSelectFanout 0 +fHsimSchedSelectFanoutDebug 0 +fHsimSchedSelectFanoutRandom 0 +fFgpDynamicReadOn 0 +fHsCgOptAllUc 0 +fHsimNoReconvergenceSched0 0 +fHsimXmrRepl 0 +fZoix 0 +fHsimDfuseNewOpt 0 +fHsimBfuseNewOpt 0 +fFgpMbme 0 +fFgpXmrSched 0 +fHsimClearClkCaps 0 +fFgpHideXmrNodes 0 +fHsimDiagClkConfig 0 +fHsimDiagClkConfigDebug 0 +fHsimDiagClkConfigDumpAll 0 +fHsDiagClkConfigPara 0 +fHsimDiagClkConfigAn 0 +fHsimCanDumpClkConfig 0 +fFgpInitRout 0 +fFgpIgnoreExclSD 0 +fHsimAggrTCOpt 0 +fFgpNewAggrXmrIterFlow 0 +fFgpNoLocalReferer 0 +fHsCgOptNoClockFusing 0 +fHsClkWheelLimit 50000 +fHsFgpSchedCgUcLoads 1 +fHsimAdvanceUdpInfer 0 +fFgpIbnSchedIntf 0 +fHsCgOptNewSelCheck 1 +fFgpReportUnsafeFuncs 0 +fHsCgOptUncPrlThreshold 4 +fHsimCosimGatesProp 0 +fHsSVNettypePerfOpt 0 +fHsCgOptHashFixMap 1 +fHsimLowPowerRetAnalysisInChild 0 +fRetainWithDelayedSig 0 +fHsimChargeDecay 0 +fHsimCongruencyConfigFile 0 +fHsimCongruencyLogFile 0 +fHsimCoverageEnabled 1 +fHsimCoverageOptions 279 +fHsimCoverageDir ./coverage/simv.vdb diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_hsim_fegate.db b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_hsim_fegate.db new file mode 100644 index 0000000..8be0045 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_hsim_fegate.db differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_hsim_lvl.db b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_hsim_lvl.db new file mode 100644 index 0000000..861898a Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_hsim_lvl.db differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_hsim_merge.db b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_hsim_merge.db new file mode 100644 index 0000000..3e9e254 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_hsim_merge.db differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_hsim_name.db b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_hsim_name.db new file mode 100644 index 0000000..2c3116f Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_hsim_name.db differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_hsim_uds.db b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_hsim_uds.db new file mode 100644 index 0000000..12a2348 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_hsim_uds.db @@ -0,0 +1,5 @@ +vcselab_misc_midd.db 57445 +vcselab_misc_mnmn.db 2715 +vcselab_misc_hsim_name.db 18117 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1349204 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_midd.db b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_midd.db new file mode 100644 index 0000000..3b682e9 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_midd.db differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_mnmn.db b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_mnmn.db new file mode 100644 index 0000000..d30eaa6 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_mnmn.db differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_partition.db b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_partition.db new file mode 100644 index 0000000..45c0dfb Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_partition.db differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_partitionDbg.db b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_partitionDbg.db new file mode 100644 index 0000000..410c022 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_partitionDbg.db differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_vcselabref.db b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_vcselabref.db new file mode 100644 index 0000000..f76dd23 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_vcselabref.db differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_vpdnodenums b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_vpdnodenums new file mode 100644 index 0000000..c7400e4 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/simv.daidir/vcselab_misc_vpdnodenums differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/ucli.key b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/ucli.key new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/.diagnose.oneSearch b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/.diagnose.oneSearch new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/ToNetlist.log b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/ToNetlist.log new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/compiler.log b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/compiler.log new file mode 100644 index 0000000..c9b958d --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/compiler.log @@ -0,0 +1,262 @@ +*design* DebussyLib (btIdent Verdi_O-2018.09-SP2) +Command arguments: + +define+verilog + -sverilog + -f filelist_vlg.f + ../../../../rtl/define/chip_define.v + ../../../../lib/tphn28hpcpgv18.v + ../../../../lib/tsdn28hpcpuhdb4096x128m4mw_170a_ffg0p99v0c.v + ../../../../rtl/io/iopad.v + ../../../../rtl/systemregfile/systemregfile.v + ../../../../rtl/dacif/dacif.v + ../../../../rtl/fifo/syn_fwft_fifo.v + ../../../../rtl/dac_regfile/dac_regfile.v + ../../../../rtl/lvds/ulink_rx.sv + ../../../../rtl/rstgen/rst_gen_unit.v + ../../../../rtl/rstgen/rst_sync.v + ../../../../rtl/comm/sirv_gnrl_xchecker.v + ../../../../rtl/comm/pulse_generator.sv + ../../../../rtl/comm/sirv_gnrl_dffs.v + ../../../../rtl/comm/syncer.v + ../../../../rtl/comm/ramp_gen.v + ../../../../rtl/memory/tsmc_dpram.v + ../../../../rtl/memory/sram_if.sv + ../../../../rtl/memory/sram_dmux.sv + ../../../../rtl/memory/dpram.v + ../../../../rtl/memory/bhv_spram.v + ../../../../rtl/memory/spram.v + ../../../../rtl/clk/clk_regfile.v + ../../../../rtl/awg/awg_top.sv + ../../../../rtl/awg/awg_ctrl.v + ../../../../rtl/dem/DEM_PhaseSync_4008.sv + ../../../../rtl/dem/DA4008_DEM_Parallel_PRBS_1CH.v + ../../../../rtl/dem/DA4008_DEM_Parallel_PRBS_64CH.v + ../../../../rtl/top/da4008_chip_top.sv + ../../../../rtl/top/digital_top.sv + ../../../../rtl/spi/spi_bus_decoder.sv + ../../../../rtl/spi/spi_slave.v + ../../../../rtl/spi/spi_pll.v + ../../../../rtl/spi/spi_sys.v + ../../../../model/clock_tb.v + ../../../../model/spi_if.sv + ../../../../model/clk_gen.v + ../../../../model/DEM_Reverse_64CH.v + ../../../../model/DEM_Reverse.v + ../../../../model/reset_tb.v + ../../../../model/DW_stream_sync.v + ../../../../model/DW_reset_sync.v + ../../../../model/DW_sync.v + ../../../../model/DW_pulse_sync.v + ../../../../sim/chip_top/TB.sv + ../../../../rtl/define/chip_undefine.v + -top + TB + + +*Error* `include file "../define/chip_define.v" cannot be read +"../../../../rtl/io/iopad.v", 35: + +*Error* `include file "../define/chip_undefine.v" cannot be read +"../../../../rtl/io/iopad.v", 187: + +*Error* `include file "../define/chip_define.v" cannot be read +"../../../../rtl/memory/dpram.v", 2: + +*Error* `include file "../define/chip_undefine.v" cannot be read +"../../../../rtl/memory/dpram.v", 90: + +*Error* `include file "../define/chip_define.v" cannot be read +"../../../../rtl/top/da4008_chip_top.sv", 3: + +*Error* `include file "../define/chip_undefine.v" cannot be read +"../../../../rtl/top/da4008_chip_top.sv", 212: + +*Error* `include file "../define/chip_define.v" cannot be read +"../../../../rtl/top/digital_top.sv", 34: + +*Error* `include file "../define/chip_undefine.v" cannot be read +"../../../../rtl/top/digital_top.sv", 528: + +*Error* `include file "../../rtl/define/chip_define.v" cannot be read +"../../../../sim/chip_top/TB.sv", 1: + +*Error* `include file "../../model/SPI_DRIVER.sv" cannot be read +"../../../../sim/chip_top/TB.sv", 3: + +*Error* `include file "../../model/LVDS_DRIVER.sv" cannot be read +"../../../../sim/chip_top/TB.sv", 5: + +*Error* failed to find symbol 'my_drv' +"../../../../sim/chip_top/TB.sv", 81: + +*Error* failed to find symbol 'lvds_drv' +"../../../../sim/chip_top/TB.sv", 82: +Highest level modules: +PCLAMP_G +PCLAMPC_H_G +PCLAMPC_V_G +PDB3A_H_G +PDB3A_V_G +PDB3AC_H_G +PDB3AC_V_G +PDDW04DGZ_H_G +PDDW04DGZ_V_G +PDDW04SDGZ_H_G +PDDW08DGZ_H_G +PDDW08DGZ_V_G +PDDW08SDGZ_H_G +PDDW08SDGZ_V_G +PDDW12DGZ_H_G +PDDW12DGZ_V_G +PDDW12SDGZ_H_G +PDDW12SDGZ_V_G +PDDW16DGZ_H_G +PDDW16DGZ_V_G +PDDW16SDGZ_H_G +PDDW16SDGZ_V_G +PDUW04DGZ_H_G +PDUW04DGZ_V_G +PDUW04SDGZ_H_G +PDUW08DGZ_H_G +PDUW08DGZ_V_G +PDUW08SDGZ_H_G +PDUW12DGZ_H_G +PDUW12DGZ_V_G +PDUW12SDGZ_H_G +PDUW12SDGZ_V_G +PDUW16DGZ_H_G +PDUW16DGZ_V_G +PDUW16SDGZ_H_G +PDUW16SDGZ_V_G +PDXOEDG_H_G +PDXOEDG_V_G +PENDCAP_G +PENDCAPA_G +PRCUT_G +PRCUTA_G +PRDW08DGZ_H_G +PRDW08DGZ_V_G +PRDW08SDGZ_H_G +PRDW08SDGZ_V_G +PRDW12DGZ_H_G +PRDW12DGZ_V_G +PRDW12SDGZ_H_G +PRDW12SDGZ_V_G +PRDW16DGZ_H_G +PRDW16DGZ_V_G +PRDW16SDGZ_H_G +PRDW16SDGZ_V_G +PRUW08DGZ_H_G +PRUW08DGZ_V_G +PRUW08SDGZ_H_G +PRUW08SDGZ_V_G +PRUW12DGZ_H_G +PRUW12DGZ_V_G +PRUW12SDGZ_H_G +PRUW12SDGZ_V_G +PRUW16DGZ_H_G +PRUW16DGZ_V_G +PRUW16SDGZ_H_G +PRUW16SDGZ_V_G +PVDD1A_H_G +PVDD1A_V_G +PVDD1AC_H_G +PVDD1AC_V_G +PVDD1ANA_H_G +PVDD1ANA_V_G +PVDD1DGZ_H_G +PVDD1DGZ_V_G +PVDD2ANA_H_G +PVDD2ANA_V_G +PVDD2DGZ_H_G +PVDD2DGZ_V_G +PVDD2POC_H_G +PVDD2POC_V_G +PVDD3A_H_G +PVDD3A_V_G +PVDD3AC_H_G +PVDD3AC_V_G +PVSS1A_H_G +PVSS1A_V_G +PVSS1AC_H_G +PVSS1AC_V_G +PVSS1ANA_H_G +PVSS1ANA_V_G +PVSS1DGZ_H_G +PVSS1DGZ_V_G +PVSS2A_H_G +PVSS2A_V_G +PVSS2AC_H_G +PVSS2AC_V_G +PVSS2ANA_H_G +PVSS2ANA_V_G +PVSS2DGZ_H_G +PVSS2DGZ_V_G +PVSS3A_H_G +PVSS3A_V_G +PVSS3AC_H_G +PVSS3AC_V_G +PVSS3DGZ_H_G +PVSS3DGZ_V_G +sirv_gnrl_xchecker +sirv_gnrl_dffl +sirv_gnrl_ltch +clk_gen +reset_tb +TB + + +*Error* failed to find identifier lvds_drv +"../../../../sim/chip_top/TB.sv", 89: + +*Error* failed to find identifier lvds_drv.new +"../../../../sim/chip_top/TB.sv", 89: + +*Error* failed to find identifier lvds_drv.drv_if +"../../../../sim/chip_top/TB.sv", 91: + +*Error* failed to find identifier my_drv +"../../../../sim/chip_top/TB.sv", 94: + +*Error* failed to find identifier my_drv.new +"../../../../sim/chip_top/TB.sv", 94: + +*Error* failed to find identifier my_drv.file_path +"../../../../sim/chip_top/TB.sv", 95: + +*Error* failed to find identifier my_drv.itf +"../../../../sim/chip_top/TB.sv", 96: + +*Error* failed to find identifier lvds_drv.train_count +"../../../../sim/chip_top/TB.sv", 102: + +*Error* failed to find identifier lvds_drv.send_training +"../../../../sim/chip_top/TB.sv", 103: + +*Error* failed to find identifier lvds_drv.scrambler_en +"../../../../sim/chip_top/TB.sv", 104: + +*Error* failed to find identifier lvds_drv.send_frame_from_file +"../../../../sim/chip_top/TB.sv", 105: + +*Error* failed to find identifier my_drv.do_drive +"../../../../sim/chip_top/TB.sv", 108: + +*Error* failed to find identifier my_drv.do_drive +"../../../../sim/chip_top/TB.sv", 120: + +*Error* failed to find identifier my_drv.do_drive +"../../../../sim/chip_top/TB.sv", 131: + +*Error* failed to find identifier lvds_bus.data +"../../../../sim/chip_top/TB.sv", 218: + +*Error* failed to find identifier lvds_bus.valid +"../../../../sim/chip_top/TB.sv", 219: + +*Error* failed to find identifier lvds_bus.clk +"../../../../sim/chip_top/TB.sv", 220: + +*Error* view lvds_if is not defined for instance lvds_bus +"../../../../sim/chip_top/TB.sv", 69: +Total 31 error(s), 0 warning(s) diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/exe.log b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/exe.log new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/novas.log b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/novas.log new file mode 100644 index 0000000..157ce72 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/novas.log @@ -0,0 +1,10 @@ +Verdi (R) + +Release Verdi_O-2018.09-SP2 for (RH Linux x86_64/64bit) -- Thu Feb 21 04:40:56 PDT 2019 + +Copyright (c) 1999 - 2019 Synopsys, Inc. +This software and the associated documentation are proprietary to Synopsys, Inc. +This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. +All other use, reproduction, or distribution of this software is strictly prohibited. + + diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/novas.rc b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/novas.rc new file mode 100644 index 0000000..e39103d --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/novas.rc @@ -0,0 +1,1309 @@ +@verdi rc file Version 1.0 +[Library] +work = ./work +[Annotation] +3D_Active_Annotation = FALSE +[CommandSyntax.finsim] +InvokeCommand = +FullFileName = TRUE +Separator = . +SimPromptSign = ">" +HierNameLevel = 1 +RunContinue = "continue" +Finish = "quit" +UseAbsTime = FALSE +NextTime = "run 1" +NextNTime = "run ${SimBPTime}" +NextEvent = "run 1" +Reset = +ObjPosBreak = "break posedge ${SimBPObj}" +ObjNegBreak = "break negedge ${SimBPObj}" +ObjAnyBreak = "break change ${SimBPObj}" +ObjLevelBreak = +LineBreak = "breakline ${SimBPFile} ${SimBPLine}" +AbsTimeBreak = "break abstimeaf ${SimBPTime}" +RelTimeBreak = "break reltimeaf ${SimBPTime}" +EnableBP = "breakon ${SimBPId}" +DisableBP = "breakoff ${SimBPId}" +DeleteBP = "breakclr ${SimBPId}" +DeleteAllBP = "breakclr" +SimSetScope = "cd ${SimDmpObj}" +[CommandSyntax.ikos] +InvokeCommand = "setvar debussy true;elaborate -p ${SimTop} -s ${SimArch}; run until 0;fsdbInteractive; " +FullFileName = TRUE +NeedTimeUnit = TRUE +NormalizeTimeUnit = TRUE +Separator = / +HierNameLevel = 2 +RunContinue = "run" +Finish = "exit" +NextTime = "run ${SimBPTime} ${SimTimeUnit}" +NextNTime = "run for ${SimBPTime} ${SimTimeUnit}" +NextEvent = "step 1" +Reset = "reset" +ObjPosBreak = "stop if ${SimBPObj} = \"'1'\"" +ObjNegBreak = "stop if ${SimBPObj} = \"'0'\"" +ObjAnyBreak = +ObjLevelBreak = "stop if ${SimBPObj} = ${SimBPValue}" +LineBreak = "stop at ${SimBPFile}:${SimBPLine}" +AbsTimeBreak = +RelTimeBreak = +EnableBP = "enable ${SimBPId}" +DisableBP = "disable ${SimBPId}" +DeleteBP = "delete ${SimBPId}" +DeleteAllBP = "delete *" +[CommandSyntax.verisity] +InvokeCommand = +FullFileName = FALSE +Separator = . +SimPromptSign = "> " +HierNameLevel = 1 +RunContinue = "." +Finish = "$finish;" +NextTime = "$db_steptime(1);" +NextNTime = "$db_steptime(${SimBPTime});" +NextEvent = "$db_step;" +SimSetScope = "$scope(${SimDmpObj});" +Reset = "$reset;" +ObjPosBreak = "$db_breakonposedge(${SimBPObj});" +ObjNegBreak = "$db_breakonnegedge(${SimBPObj});" +ObjAnyBreak = "$db_breakwhen(${SimBPObj});" +ObjLevelBreak = "$db_breakwhen(${SimBPObj}, ${SimBPValue});" +LineBreak = "$db_breakatline(${SimBPLine}, ${SimBPScope}, \"${SimBPFile}\");" +AbsTimeBreak = "$db_breakbeforetime(${SimBPTime});" +RelTimeBreak = "$db_breakbeforetime(${SimBPTime});" +EnableBP = "$db_enablebreak(${SimBPId});" +DisableBP = "$db_disablebreak(${SimBPId});" +DeleteBP = "$db_deletebreak(${SimBPId});" +DeleteAllBP = "$db_deletebreak;" +FSDBInit = "$novasInteractive;" +FSDBDumpvars = "$novasDumpvars(0, ${SimDmpObj});" +FSDBDumpsingle = "$novasDumpsingle(${SimDmpObj});" +FSDBDumpvarsInFile = "$novasDumpvarsToFile(\"${SimDmpFile}\");" +FSDBDumpMem = "$novasDumpMemNow(${SimDmpObj}, ${SimDmpBegin}, ${SimDmpSize});" +[CoverageDetail] +cross_filter_limit = 1000 +branch_limit_vector_display = 50 +showgrid = TRUE +reuseFirst = TRUE +justify = TRUE +scrollbar_mode = per pane +test_combo_left_truncate = TRUE +instance_combo_left_truncate = TRUE +loop_navigation = TRUE +condSubExpr = 20 +tglMda = 1000 +linecoverable = 100000 +lineuncovered = 50000 +tglcoverable = 30000 +tgluncovered = 30000 +pendingMax = 1000 +show_full_more = FALSE +[CoverageHier] +showgrid = FALSE +[CoverageWeight] +Assert = 1 +Covergroup = 1 +Line = 1 +Condition = 1 +Toggle = 1 +FSM = 1 +Branch = 1 +[DesignTree] +IfShowModule = {TRUE, FALSE} +[DisabledMessages] +version = Verdi_O-2018.09-SP2 +[Editor] +editorName = TurboEditor +[Emacs] +EmacsFont = "Clean 14" +EmacsBG = white +EmacsFG = black +[Exclusion] +enableAsDefault = TRUE +saveAsDefault = TRUE +saveManually = TRUE +illegalBehavior = FALSE +DisplayExcludedItem = FALSE +adaptiveExclusion = TRUE +warningExcludeInstance = TRUE +favorite_exclude_annotation = "" +[FSM] +viewport = 65 336 387 479 +WndBk-FillColor = Gray3 +Background-FillColor = gray5 +prefKey_Link-FillColor = yellow4 +prefKey_Link-TextColor = black +Trap = red3 +Hilight = blue4 +Window = Gray3 +Selected = white +Trans. = green2 +State = black +Init. = black +SmartTips = TRUE +VectorFont = FALSE +StopAskBkgndColor = FALSE +ShowStateAction = FALSE +ShowTransAction = FALSE +ShowTransCond = FALSE +StateLable = NAME +StateValueRadix = ORIG +State-LineColor = ID_BLACK +State-LineWidth = 1 +State-FillColor = ID_BLUE2 +State-TextColor = ID_WHITE +Init_State-LineColor = ID_BLACK +Init_State-LineWidth = 2 +Init_State-FillColor = ID_YELLOW2 +Init_State-TextColor = ID_BLACK +Reset_State-LineColor = ID_BLACK +Reset_State-LineWidth = 2 +Reset_State-FillColor = ID_YELLOW7 +Reset_State-TextColor = ID_BLACK +Trap_State-LineColor = ID_RED2 +Trap_State-LineWidth = 2 +Trap_State-FillColor = ID_CYAN5 +Trap_State-TextColor = ID_RED2 +State_Action-LineColor = ID_BLACK +State_Action-LineWidth = 1 +State_Action-FillColor = ID_WHITE +State_Action-TextColor = ID_BLACK +Junction-LineColor = ID_BLACK +Junction-LineWidth = 1 +Junction-FillColor = ID_GREEN2 +Junction-TextColor = ID_BLACK +Connection-LineColor = ID_BLACK +Connection-LineWidth = 1 +Connection-FillColor = ID_GRAY5 +Connection-TextColor = ID_BLACK +prefKey_Port-LineColor = ID_BLACK +prefKey_Port-LineWidth = 1 +prefKey_Port-FillColor = ID_ORANGE6 +prefKey_Port-TextColor = ID_YELLOW2 +Transition-LineColor = ID_BLACK +Transition-LineWidth = 1 +Transition-FillColor = ID_WHITE +Transition-TextColor = ID_BLACK +Trans_Condition-LineColor = ID_BLACK +Trans_Condition-LineWidth = 1 +Trans_Condition-FillColor = ID_WHITE +Trans_Condition-TextColor = ID_ORANGE2 +Trans_Action-LineColor = ID_BLACK +Trans_Action-LineWidth = 1 +Trans_Action-FillColor = ID_WHITE +Trans_Action-TextColor = ID_GREEN2 +SelectedSet-LineColor = ID_RED2 +SelectedSet-LineWidth = 1 +SelectedSet-FillColor = ID_RED2 +SelectedSet-TextColor = ID_WHITE +StickSet-LineColor = ID_ORANGE5 +StickSet-LineWidth = 1 +StickSet-FillColor = ID_PURPLE6 +StickSet-TextColor = ID_BLACK +HilightSet-LineColor = ID_RED5 +HilightSet-LineWidth = 1 +HilightSet-FillColor = ID_RED7 +HilightSet-TextColor = ID_BLUE5 +ControlPoint-LineColor = ID_BLACK +ControlPoint-LineWidth = 1 +ControlPoint-FillColor = ID_WHITE +Bundle-LineColor = ID_BLACK +Bundle-LineWidth = 1 +Bundle-FillColor = ID_WHITE +Bundle-TextColor = ID_BLUE4 +QtBackground-FillColor = ID_GRAY6 +prefKey_Link-LineColor = ID_ORANGE2 +prefKey_Link-LineWidth = 1 +Selection-LineColor = ID_BLUE2 +Selection-LineWidth = 1 +[FSM_Dlg-Print] +Orientation = Landscape +[Form] +version = Verdi_O-2018.09-SP2 +[General] +autoSaveSession = FALSE +TclAutoSource = +cmd_enter_form = FALSE +SyncBrowserDir = TRUE +version = Verdi_O-2018.09-SP2 +SignalCaseInSensitive = FALSE +ShowWndCtntDuringResizing = FALSE +[GlobalProp] +ErrWindow_Font = Helvetica_M_R_12 +[Globals] +app_default_font = Bitstream Vera Sans,10,-1,5,50,0,0,0,0,0 +app_fixed_width_font = Courier,10,-1,5,50,0,0,0,0,0 +text_encoding = Unicode(utf8) +smart_resize = TRUE +smart_resize_child_limit = 2000 +tooltip_max_width = 200 +tooltip_max_height = 20 +tooltip_viewer_key = F3 +tooltip_display_time = 1000 +bookmark_name_length_limit = 12 +disable_tooltip = FALSE +auto_load_source = TRUE +max_array_size = 4096 +filter_when_typing = TRUE +filter_keep_children = TRUE +filter_syntax = Wildcards +filter_keystroke_interval = 800 +filter_case_sensitive = FALSE +filter_full_path = FALSE +load_detail_for_funcov = FALSE +sort_limit = 100000 +ignoreDBVersionChecking = FALSE +[HB] +ViewSchematic = FALSE +windowLayout = 0 0 804 500 182 214 804 148 +import_filter = *.v; *.vc; *.f +designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +import_filter_vhdl = *.vhd; *.vhdl; *.f +import_default_language = Verilog +import_filter_verilog = *.v; *.vc; *.f +simulation_file_type = *.fsdb;*.fsdb.gz;*.fsdb.bz2;*.ff;*.dump +PrefetchViewableAnnot = TRUE +[Hier] +filterTimeout = 1500 +[ImportLiberty] +SearchPriority = .lib++ +bSkipStateCell = False +bImportPowerInfo = False +bSkipFFCell = False +bScpecifyCellNameCase = False +bSpecifyPinNameCase = False +CellNameToCase = +PinNameToCase = +[Language] +EditWindow_Font = COURIER12 +Background = ID_WHITE +Comment = ID_GRAY4 +Keyword = ID_BLUE5 +UserKeyword = ID_GREEN2 +Text = ID_BLACK +SelText = ID_WHITE +SelBackground = ID_BLUE2 +[Library.Ikos] +pack = ./work.lib++ +vital = ./work.lib++ +work = ./work.lib++ +std = ${dls_std}.lib++ +ieee = ${dls_ieee}.lib++ +synopsys = ${dls_synopsys}.lib++ +silc = ${dls_silc}.lib++ +ikos = ${dls_ikos}.lib++ +novas = ${VOYAGER_LIB_VHDL}/${VOYAGER_MACHINE}/novas.lib++ +[MDT] +ART_RF_SP = spr[0-9]*bx[0-9]* +ART_RF_2P = dpr[0-9]*bx[0-9]* +ART_SRAM_SP = spm[0-9]*bx[0-9]* +ART_SRAM_DP = dpm[0-9]*bx[0-9]* +VIR_SRAM_SP = hdsd1_[0-9]*x[0-9]*cm4sw1 +VIR_SRAM_DP = hdsd2_[0-9]*x[0-9]*cm4sw1 +VIR_RF_SP = rfsd1_[0-9]*x[0-9]*cm2sw0 +VIR_RF_DP = rfsd2_[0-9]*x[0-9]*cm2sw1 +VIR_STAR_SRAM_SP = shsd1_[0-9]*x[0-9]*cm4sw0 +[NPExpanding] +functiongroups = FALSE +modules = FALSE +[NPFilter] +showAssertion = TRUE +showCoverGroup = TRUE +showProperty = TRUE +showSequence = TRUE +showDollarUnit = TRUE +[OldFontRC] +Wave_legend_window_font = -f COURIER12 -c ID_CYAN5 +Wave_value_window_font = -f COURIER12 -c ID_CYAN5 +Wave_curve_window_font = -f COURIER12 -c ID_CYAN5 +Wave_group_name_font = -f COURIER12 -c ID_GREEN5 +Wave_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_comment_string_font = -f COURIER12 -c ID_RED5 +HB_designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +Text_font = COURIER12 +nMemory_font = Fixed 14 +Wave_getsignal_form_font = -f COURIER12 +Text_annotFont = Helvetica_M_R_10 +[OtherEditor] +cmd1 = "xterm -font 9x15 -fg black -bg gray -e" +name = "vi" +options = "+${CurLine} ${CurFullFileName}" +[Power] +PowerDownInstance = ID_GRAY1 +RetentionSignal = ID_YELLOW2 +IsolationSignal = ID_RED6 +LevelShiftedSignal = ID_GREEN6 +PowerSwitchObject = ID_ORANGE5 +AlwaysOnObject = ID_GREEN5 +PowerNet = ID_RED2 +GroundNet = ID_RED2 +SimulationOnly = ID_CYAN3 +SRSN/SPA = ID_CYAN3 +CNSSignal = ID_CYAN3 +RPTRSignal = ID_CYAN3 +AcknowledgeSignal = ID_CYAN3 +BoundaryPort = ID_CYAN3 +DisplayInstrumentedCell = TRUE +ShowCmdByFile = FALSE +ShowPstAnnot = FALSE +ShowIsoSymbol = TRUE +ExtractIsoSameNets = FALSE +AnnotateSignal = TRUE +HighlightPowerObject = TRUE +HighlightPowerDomain = TRUE +TraceThroughInstruLowPower = FALSE +BrightenPowerColorInSchematicWindow = FALSE +ShowAlias = FALSE +ShowVoltage = TRUE +MatchTreeNodesCaseInsensitive = FALSE +SearchHBNodeDynamically = FALSE +ContinueTracingSupplyOrLogicNet = FALSE +[Print] +PrinterName = lp +FileName = test.ps +PaperSize = A4 - 210x297 (mm) +ColorPrint = FALSE +[PropertyTools] +saveWaveformStat = TRUE +savePropStat = FALSE +savePropDtl = TRUE +[QtDialog] +QwUserAskDlg = 798,487,324,134 +[Relationship] +hideRecursiceNode = FALSE +[Session Cache] +3 = string (session file name) +4 = string (session file name) +5 = string (session file name) +1 = /home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/novas_autosave.ses +2 = /home/shbyang/verdiLog/novas_autosave.ses +[Simulation] +scsPath = scsim +scsOption = +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +osciPath = gdb +osciOption = +vcsPath = simv +vcsOption = +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +speedsimPath = +speedsimOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +interactiveDebugging = {True, False} +KeepBreakPoints = False +ScsDebugAll = False +simType = {vcssv, xl, nc, vcs, mti, mti_vlog, vhnc, scs, mixnc} +thirdpartyIdx = -1 +iscCmdSep = FALSE +NoAppendOption = False +[SimulationPlus] +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +vcsPath = simv +vcsOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +speedsimPath = verilog +speedsimOption = +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +scsPath = scsim +scsOption = +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +vcs_svPath = simv +vcs_svOption = +simType = vcssv +thirdpartyIdx = -1 +interactiveDebugging = FALSE +KeepBreakPoints = FALSE +iscCmdSep = FALSE +ScsDebugAll = FALSE +NoAppendOption = FALSE +invokeSimPath = work +[SimulationPlus2] +eventDumpUnfinish = FALSE +[Source] +wordWrapOn = TRUE +viewReuse = TRUE +lineNumberOn = TRUE +warnOutdatedDlg = TRUE +showEncrypt = FALSE +loadInclude = FALSE +showColorForActive = FALSE +tabWidth = 8 +editor = vi +reload = Never +sync_active_to_source = TRUE +navigateAsColored = FALSE +navigateCovered = FALSE +navigateUncovered = TRUE +navigateExcluded = FALSE +not_ask_for_source_path = FALSE +expandMacroOn = TRUE +expandMacroInstancesThreshold = 10000 +[SourceVHDL] +vhSimType = ModelSim +ohSimType = VCS +[TclShell] +nLineSize = 1024 +[Test] +verbose_progress = FALSE +[TestBenchBrowser] +-showUVMDynamicHierTreeWin = FALSE +[Text] +hdlTypeName = blue4 +hdlLibrary = blue4 +viewport = 396 392 445 487 +hdlOther = ID_BLACK +hdlComment = ID_GRAY1 +hdlKeyword = ID_BLUE5 +hdlEntity = ID_BLACK +hdlEntityInst = ID_BLACK +hdlSignal = ID_RED2 +hdlInSignal = ID_RED2 +hdlOutSignal = ID_RED2 +hdlInOutSignal = ID_RED2 +hdlOperator = ID_BLACK +hdlMinus = ID_BLACK +hdlSymbol = ID_BLACK +hdlString = ID_BLACK +hdlNumberBase = ID_BLACK +hdlNumber = ID_BLACK +hdlLiteral = ID_BLACK +hdlIdentifier = ID_BLACK +hdlSystemTask = ID_BLACK +hdlParameter = ID_BLACK +hdlIncFile = ID_BLACK +hdlDataFile = ID_BLACK +hdlCDSkipIf = ID_GRAY1 +hdlMacro = ID_BLACK +hdlMacroValue = ID_BLACK +hdlPlainText = ID_BLACK +hdlOvaId = ID_PURPLE2 +hdlPslId = ID_PURPLE2 +HvlEId = ID_BLACK +HvlVERAId = ID_BLACK +hdlEscSignal = ID_BLACK +hdlEscInSignal = ID_BLACK +hdlEscOutSignal = ID_BLACK +hdlEscInOutSignal = ID_BLACK +textBackgroundColor = ID_GRAY6 +textHiliteBK = ID_BLUE5 +textHiliteText = ID_WHITE +textTracedMark = ID_GREEN2 +textLineNo = ID_BLACK +textFoldedLineNo = ID_RED5 +textUserKeyword = ID_GREEN2 +textParaAnnotText = ID_BLACK +textFuncAnnotText = ID_BLUE2 +textAnnotText = ID_BLACK +textUserDefAnnotText = ID_BLACK +ComputedSignal = ID_PURPLE5 +textAnnotTextShadow = ID_WHITE +parenthesisBGColor = ID_YELLOW5 +codeInParenthesis = ID_CYAN5 +text3DLight = ID_WHITE +text3DShadow = ID_BLACK +textHvlDriver = ID_GREEN3 +textHvlLoad = ID_YELLOW3 +textHvlDriverLoad = ID_BLUE3 +irOutline = ID_RED2 +irDriver = ID_YELLOW5 +irLoad = ID_BLACK +irBookMark = ID_YELLOW2 +irIndicator = ID_WHITE +irBreakpoint = ID_GREEN5 +irCurLine = ID_BLUE5 +hdlVhEntity = ID_BLACK +hdlArchitecture = ID_BLACK +hdlPackage = ID_BLUE5 +hdlRefPackage = ID_BLUE5 +hdlAlias = ID_BLACK +hdlGeneric = ID_BLUE5 +specialAnnotShadow = ID_BLUE1 +hdlZeroInHead = ID_GREEN2 +hdlZeroInComment = ID_GREEN2 +hdlPslHead = ID_BLACK +hdlPslComment = ID_BLACK +hdlSynopsysHead = ID_GREEN2 +hdlSynopsysComment = ID_GREEN2 +pdmlIdentifier = ID_BLACK +pdmlCommand = ID_BLACK +pdmlMacro = ID_BLACK +font = COURIER12 +annotFont = Helvetica_M_R_10 +[Text.1] +viewport = -10 20 1920 977 45 +[TextPrinter] +Orientation = Landscape +Indicator = FALSE +LineNum = TRUE +FontSize = 7 +Column = 2 +Annotation = TRUE +[Texteditor] +TexteditorFont = "Clean 14" +TexteditorBG = white +TexteditorFG = black +[ThirdParty] +ThirdPartySimTool = verisity surefire ikos finsim +[TurboEditor] +autoBackup = TRUE +[UserButton.mixnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +Button8 = "FSDB Ver" "call fsdbVersion" +Button9 = "Dump On" "call fsdbDumpon" +Button10 = "Dump Off" "call fsdbDumpoff" +Button11 = "All Tasks" "call" +Button12 = "Dump Selected Instance" "call fsdbDumpvars 1 ${SelInst}" +[UserButton.mti] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.mti_vlog] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.nc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.scs] +Button1 = "Dump All Signals" "call fsdbDumpvars(0, \"${TopScope}\");\n" +Button2 = "Next 1000 Time" "run 1000 \n" +Button3 = "Next ? Time" "run ${Arg:Next Time} \n" +Button4 = "Run Step" "step\n" +Button5 = "Show Variables" "ls -v {${SelVars}}\n" +[UserButton.vhnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.xl] +Button13 = "Dump Off" "$fsdbDumpoff;\n" +Button12 = "Dump On" "$fsdbDumpon;\n" +Button11 = "Delete Focus" "$db_deletefocus(${treeSelScope});\n" +Button10 = "Set Focus" "$db_setfocus(${treeSelScope});\n" +Button9 = "Deposit Variable" "$deposit(${SelVar},${Arg:New Value});\n" +Button8 = "Release Variable" "release ${SelVar};\n" +Button7 = "Force Variable" "force ${SelVar} = ${Arg:New Value};\n" +Button6 = "Show Variables" "$showvars(${SelVars});\n" +Button5 = "Next ? Event" "$db_step(${Arg:Next Event});\n" +Button4 = "Next Event" "$db_step(1);\n" +Button3 = "Next ? Time" "#${Arg:Next Time} $stop;.\n" +Button2 = "Next 1000 Time" "#1000 $stop;.\n" +Button1 = "Dump All Signals" "$fsdbDumpvars;\n" +[VIA] +viaLogViewerDefaultRuleOneSearchForm = "share/VIA/Apps/PredefinedRules/Misc/Onesearch_rule.rc" +[VIA.oneSearch.preference] +DefaultDisplayTimeUnit = "1.000000ns" +DefaultLogTimeUnit = "1.000000ns" +[VIA.oneSearch.preference.vgifColumnSettingRC] +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0] +parRuleSets = "" +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column0] +name = Severity +width = 60 +visualIndex = 1 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column1] +name = Code +width = 60 +visualIndex = 2 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column2] +name = Type +width = 60 +visualIndex = 3 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column3] +name = Time +width = 60 +visualIndex = 0 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column4] +name = Message +width = 2000 +visualIndex = 4 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[Vi] +ViFont = "Clean 14" +ViBG = white +ViFG = black +[Wave] +ovaEventSuccessColor = -c ID_CYAN5 +ovaEventFailureColor = -c ID_RED5 +ovaBooleanSuccessColor = -c ID_CYAN5 +ovaBooleanFailureColor = -c ID_RED5 +ovaAssertSuccessColor = -c ID_GREEN5 +ovaAssertFailureColor = -c ID_RED5 +ovaForbidSuccessColor = -c ID_GREEN5 +SigGroupRuleFile = +DisplayFileName = FALSE +waveform_vertical_scroll_bar = TRUE +scope_to_save_with_macro +open_file_dir +open_rc_file_dir +getSignalForm = 0 0 800 479 100 30 100 30 +viewPort = 0 27 1920 392 152 65 +signalSpacing = 5 +digitalSignalHeight = 15 +analogSignalHeight = 98 +commentSignalHeight = 98 +transactionSignalHeight = 98 +messageSignalHeight = 98 +minCompErrWidth = 4 +DragZoomTolerance = 4 +maxTransExpandedLayer = 10 +WaveMaxPoint = 512 +legendBackground = -c ID_BLACK +valueBackground = -c ID_BLACK +curveBackground = -c ID_BLACK +getSignalSignalList_BackgroundColor = -c ID_GRAY6 +glitchColor = -c ID_RED5 +cursor = -c ID_YELLOW5 -lw 1 -ls long_dashed +marker = -c ID_WHITE -lw 1 -ls dash_dot_l +usermarker = -c ID_GREEN5 -lw 1 -ls long_dashed +trace = -c ID_GRAY5 -lw 1 -ls long_dashed +grid = -c ID_WHITE -lw 1 -ls short_dashed +rulerBackground = -c ID_GRAY3 +rulerForeground = -c ID_YELLOW5 +busTextColor = -c ID_ORANGE8 +legendForeground = -c ID_CYAN5 +valueForeground = -c ID_CYAN5 +curveForeground = -c ID_CYAN5 +groupNameColor = -c ID_GREEN5 +commentStringColor = -c ID_RED5 +region(Active)Background = -c ID_YELLOW1 +region(NBA)Background = -c ID_RED1 +region(Re-Active)Background = -c ID_YELLOW3 +region(Re-NBA)Background = -c ID_RED3 +region(VHDL-Delta)Background = -c ID_ORANGE3 +region(Dump-Off)Background = -c ID_GRAY4 +High_Light = -c ID_GRAY2 +Input_Signal = -c ID_RED5 +Output_Signal = -c ID_GREEN5 +InOut_Signal = -c ID_BLUE5 +Net_Signal = -c ID_YELLOW5 +Register_Signal = -c ID_PURPLE5 +Verilog_Signal = -c ID_CYAN5 +VHDL_Signal = -c ID_ORANGE5 +SystemC_Signal = -c ID_BLUE7 +Dump_Off_Color = -c ID_BLUE2 +Compress_Bar_Color = -c ID_YELLOW4 +Vector_Dense_Block_Color = -c ID_ORANGE8 +Scalar_Dense_Block_Color = -c ID_GREEN6 +Analog_Dense_Block_Color = -c ID_PURPLE2 +Composite_Dense_Block_Color = -c ID_ORANGE5 +RPTR_Power_Off_Layer = -c ID_CYAN3 -stipple dots +DB_Power_Off_Layer = -c ID_BLUE4 -stipple dots +SPA_Driver_Power_Off_Layer = -c ID_ORANGE4 -stipple dots +SPA_Receiver_Power_Off_Layer = -c ID_GREEN5 -stipple dots +SRSN_Power_Off_Layer = -c ID_GREEN4 -stipple dots +Isolation_Power_Off_Layer = -c ID_RED4 -stipple dots +PD_Power_Off_Layer = -c ID_GRAY4 -stipple dots +Isolation_Layer = -c ID_RED4 -stipple vLine +Retention_Level_Trigger_Layer = -c ID_ORANGE1 -stipple fill_solid +Retention_Edge_Trigger_Layer = -c ID_YELLOW6 -stipple fill_solid +Driving_Power_Off_Layer = -c ID_YELLOW2 -stipple x +Toggle_Layer = -c ID_YELLOW4 -stipple slash +analogRealStyle = pwl +analogVoltageStyle = pwl +analogCurrentStyle = pwl +analogOthersStyle = pwl +busSignalLayer = -c ID_ORANGE8 +busXLayer = -c ID_RED5 +busZLayer = -c ID_ORANGE6 +busMixedLayer = -c ID_GREEN5 +busNotComputedLayer = -c ID_GRAY1 +busNoValueLayer = -c ID_BLUE2 +signalGridLayer = -c ID_WHITE +analogGridLayer = -c ID_GRAY6 +analogRulerLayer = -c ID_GRAY6 +keywordLayer = -c ID_RED5 +loadedLayer = -c ID_BLUE5 +loadingLayer = -c ID_BLACK +qdsCurMarkerLayer = -c ID_BLUE5 +qdsBrkMarkerLayer = -c ID_GREEN5 +qdsTrgMarkerLayer = -c ID_RED5 +arrowDefaultColor = -c ID_ORANGE6 +startNodeArrowColor = -c ID_WHITE +endNodeArrowColor = -c ID_YELLOW5 +propertyEventMatchColor = -c ID_GREEN5 +propertyEventNoMatchColor = -c ID_RED5 +propertyVacuousSuccessMatchColor = -c ID_YELLOW2 +propertyStatusBoundaryColor = -c ID_WHITE +propertyBooleanSuccessColor = -c ID_CYAN5 +propertyBooleanFailureColor = -c ID_RED5 +propertyAssertSuccessColor = -c ID_GREEN5 +propertyAssertFailureColor = -c ID_RED5 +propertyForbidSuccessColor = -c ID_GREEN5 +transactionForegroundColor = -c ID_YELLOW8 +transactionBackgroundColor = -c ID_BLACK +transactionHighLightColor = -c ID_CYAN6 +transactionRelationshipColor = -c ID_PURPLE6 +transactionErrorTypeColor = -c ID_RED5 +coverageFullyCoveredColor = -c ID_GREEN5 +coverageNoCoverageColor = -c ID_RED5 +coveragePartialCoverageColor = -c ID_YELLOW5 +coverageReferenceLineColor = -c ID_GRAY4 +messageForegroundColor = -c ID_YELLOW4 +messageBackgroundColor = -c ID_PURPLE1 +messageHighLightColor = -c ID_CYAN6 +messageInformationColor = -c ID_RED5 +ComputedAnnotColor = -c ID_PURPLE5 +fsvSecurityDataColor = -c ID_PURPLE3 +qdsAutoBusGroup = TRUE +qdsTimeStampMode = FALSE +qdsVbfBusOrderAscending = FALSE +openDumpFilter = *.fsdb;*.vf;*.jf +DumpFileFilter = *.vcd +RestoreSignalFilter = *.rc +SaveSignalFilter = *.rc +AddAliasFilter = *.alias;*.adb +CompareSignalFilter = *.err +ConvertFFFilter = *.vcd;*.out;*.tr0;*.xp;*.raw;*.wfm +Scroll_Ratio = 100 +Zoom_Ratio = 10 +EventSequence_SyncCursorTime = TRUE +EventSequence_Sorting = FALSE +EventSequence_RemoveGrid = FALSE +EventSequence_IsGridMode = FALSE +SetDefaultRadix_global = FALSE +DefaultRadix = Hex +SigSearchSignalMatchCase = FALSE +SigSearchSignalScopeOption = FALSE +SigSearchSignalSamenetInterface = FALSE +SigSearchSignalFullScope = FALSE +SigSearchSignalWithRegExp = FALSE +SigSearchDynamically = FALSE +SigDisplayBySelectionOrder = FALSE +SigDisplayRowMajor = FALSE +SigDragSelFollowColumn = FALSE +SigDisplayHierarchyBox = TRUE +SigDisplaySubscopeBox = TRUE +SigDisplayEmptyScope = TRUE +SigDisplaySignalNavigationBox = FALSE +SigDisplayFormBus = TRUE +SigShowSubProgram = TRUE +SigSearchScopeDynamically = TRUE +SigCollapseSubtreeNodes = FALSE +activeFileApplyToAnnotation = FALSE +GrpSelMode = TRUE +dispGridCount = FALSE +hierarchyName = FALSE +partial_level_name = FALSE +partial_level_head = 1 +partial_level_tail = 1 +displayMessageLabelOnly = TRUE +autoInsertDumpoffs = TRUE +displayMessageCallStack = FALSE +displayCallStackWithFullSections = TRUE +displayCallStackWithLastSection = FALSE +limitMessageMaxWidth = FALSE +messageMaxWidth = 50 +displayTransBySpecificColor = FALSE +fittedTransHeight = FALSE +snap = TRUE +gravitySnap = FALSE +displayLeadingZero = FALSE +displayGlitchs = FALSE +allfileTimeRange = FALSE +fixDelta = FALSE +displayCursorMarker = FALSE +autoUpdate = FALSE +restoreFromActiveFile = TRUE +restoreToEnd = FALSE +dispCompErr = TRUE +showMsgDes = TRUE +anaAutoFit = FALSE +anaAutoPattn = FALSE +anaAuto100VertFit = FALSE +displayDeltaY = FALSE +centerCursor = FALSE +denseBlockDrawing = TRUE +relativeFreqPrecision = 3 +showMarkerAbsolute = FALSE +showMarkerAdjacent = FALSE +showMarkerRelative = FALSE +showMarkerFrequency = FALSE +stickCursorMarkerOnWaveform = TRUE +keepMarkerAtEndTimeOfTransaction = FALSE +doubleClickToExpandTransaction = TRUE +expandTransactionAssociatedSignals = TRUE +expandTransactionAttributeSignals = FALSE +WaveExtendLastTick = TRUE +InOutSignal = FALSE +NetRegisterSignal = FALSE +VerilogVHDLSignal = FALSE +LabelMarker = TRUE +ResolveSymbolicLink = TRUE +signal_rc_abspath = TRUE +signal_rc_no_natural_bus_range = FALSE +save_scope_with_macro = FALSE +TipInSignalWin = FALSE +DisplayPackedSiganlInBitwiseManner = FALSE +DisplaySignalTypeAheadOfSignalName = TRUE ICON +TipInCurveWin = FALSE +MouseGesturesInCurveWin = TRUE +DisplayLSBsFirst = FALSE +PaintSpecificColorPattern = TRUE +ModuleName = TRUE +form_all_memory_signal = FALSE +formBusSignalFromPartSelects = FALSE +read_value_change_on_demand_for_drawing = FALSE +load_scopes_on_demand = on 5 +TransitionMode = TRUE +DisplayRadix = FALSE +SchemaX = FALSE +Hilight = TRUE +UseBeforeValue = FALSE +DisplayFileNameAheadOfSignalName = FALSE +DisplayFileNumberAheadOfSignalName = FALSE +DisplayValueSpace = TRUE +FitAnaByBusSize = FALSE +displayTransactionAttributeName = FALSE +expandOverlappedTrans = FALSE +dispSamplePointForAttrSig = TRUE +dispClassName = TRUE +ReloadActiveFileOnly = FALSE +NormalizeEVCD = FALSE +OverwriteAliasWithRC = TRUE +overlay_added_analog_signals = FALSE +case_insensitive = FALSE +vhdlVariableCalculate = TRUE +showError = TRUE +signal_vertical_scroll_bar = TRUE +showPortNameForDroppedInstance = FALSE +truncateFilePathInTitleBar = TRUE +filterPropVacuousSuccess = FALSE +includeLocalSignals = FALSE +encloseSignalsByGroup = TRUE +resaveSignals = TRUE +adjustBusPrefix = adjustBus_ +adjustBusBits = 1 +adjustBusSettings = 69889 +maskPowerOff = TRUE +maskIsolation = TRUE +maskRetention = TRUE +maskDrivingPowerOff = TRUE +maskToggle = TRUE +autoBackupSignals = off 5 "\"/home/shbyang/verdiLog\"" "\"novas_autosave_sig\"" +signal_rc_attribute = 65535 +signal_rc_alias_attribute = 0 +ConvertAttr1 = -inc FALSE +ConvertAttr2 = -hier FALSE +ConvertAttr3 = -ucase FALSE +ConvertAttr4 = -lcase FALSE +ConvertAttr5 = -org FALSE +ConvertAttr6 = -mem 24 +ConvertAttr7 = -deli . +ConvertAttr8 = -hier_scope FALSE +ConvertAttr9 = -inst_array FALSE +ConvertAttr10 = -vhdlnaming FALSE +ConvertAttr11 = -orgScope FALSE +analogFmtPrecision = Automatic 2 +confirmOverwrite = TRUE +confirmExit = TRUE +confirmGetAll = TRUE +printTimeRange = TRUE 0.000000 0.000000 0.000000 +printPageRange = TRUE 1 1 +printOption = 0 +printBasic = 1 0 0 FALSE FALSE +printDest = -printer {} +printSignature = {%f %h %t} {} +curveWindow_Drag&Drop_Mode = TRUE +hspiceIncOpenMode = TRUE +pcSelectMode = TRUE +hierarchyDelimiter = / +RecentFile1 = "\"/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdplus_000.fsdb\"" +open_file_time_range = FALSE +value_window_aligment = Right +signal_window_alignment = Auto +ShowDeltaTime = TRUE +legend_window_font = -f COURIER12 -c ID_CYAN5 +value_window_font = -f COURIER12 -c ID_CYAN5 +curve_window_font = -f COURIER12 -c ID_CYAN5 +group_name_font = -f COURIER12 -c ID_GREEN5 +ruler_value_font = -f COURIER12 -c ID_CYAN5 +analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +comment_string_font = -f COURIER12 -c ID_RED5 +getsignal_form_font = -f COURIER12 +SigsCheckNum = on 1000 +filter_synthesized_net = off n +filterOutNet = on +filter_synthesized_instance = off +filterOutInstance = on +showGroupTree = TRUE +hierGroupDelim = / +MsgSeverityColor = {y \"Severity\"==\"1\" ID_RED5} {y \"Severity\"==\"2\" ID_RED6} {y \"Severity\"==\"3\" ID_RED7} {y \"Severity\"==\"4\" ID_RED8} {y \"Severity\"==\"5\" ID_ORANGE5} {y \"Severity\"==\"6\" ID_ORANGE6} {y \"Severity\"==\"7\" ID_ORANGE7} {y \"Severity\"==\"8\" \ +ID_GREEN7} {y \"Severity\"==\"9\" ID_GREEN6} {y \"Severity\"==\"10\" ID_GREEN5} +AutoApplySeverityColor = TRUE +AutoAdjustMsgWidthByLabel = off +verilogStrengthDispType = type1 +waveDblClkActiveTrace = on +autoConnectTBrowser = FALSE +connectTBrowserInContainer = TRUE +SEQShowComparisonIcon = TRUE +SEQAddDriverLoadInSameGroup = TRUE +autoSyncCursorMarker = FALSE +autoSyncHorizontalRange = FALSE +autoSyncVerticalScroll = FALSE +[cov_hier_name_column] +justify = TRUE +[coverageColors] +sou_uncov = TRUE +sou_pc = TRUE +sou_cov = TRUE +sou_exuncov = TRUE +sou_excov = TRUE +sou_unreach = TRUE +sou_unreachcon = TRUE +sou_fillColor_uncov = red +sou_fillColor_pc = yellow +sou_fillColor_cov = green3 +sou_fillColor_exuncov = grey +sou_fillColor_excov = #3C9371 +sou_fillColor_unreach = grey +sou_fillColor_unreachcon = orange +numberOfBins = 6 +rangeMin_0 = 0 +rangeMax_0 = 20 +fillColor_0 = #FF6464 +rangeMin_1 = 20 +rangeMax_1 = 40 +fillColor_1 = #FF9999 +rangeMin_2 = 40 +rangeMax_2 = 60 +fillColor_2 = #FF8040 +rangeMin_3 = 60 +rangeMax_3 = 80 +fillColor_3 = #FFFF99 +rangeMin_4 = 80 +rangeMax_4 = 100 +fillColor_4 = #99FF99 +rangeMin_5 = 100 +rangeMax_5 = 100 +fillColor_5 = #64FF64 +[coveragesetting] +assertTopoMode = FALSE +urgAppendOptions = +group_instance_new_format_name = TRUE +showvalue = FALSE +computeGroupsScoreByRatio = FALSE +computeGroupsScoreByInst = FALSE +showConditionId = FALSE +showfullhier = FALSE +nameLeftAlignment = TRUE +showAllInfoInTooltips = FALSE +copyItemHvpName = TRUE +ignoreGroupWeight = FALSE +absTestName = FALSE +HvpMergeTool = +ShowMergeMenuItem = FALSE +fsmScoreMode = transition +[eco] +NameRule = +IsFreezeSilicon = FALSE +cellQuantityManagement = FALSE +ManageMode = INSTANCE_NAME +SpareCellsPinsManagement = TRUE +LogCommitReport = FALSE +InputPinStatus = 1 +OutputPinStatus = 2 +RevisedComponentColor = ID_BLUE5 +SpareCellColor = ID_RED5 +UserName = shbyang +CommentFormat = Novas ECO updated by ${UserName} ${Date} ${Time} +PrefixN = eco_n +PrefixP = eco_p +PrefixI = eco_i +DefaultTieUpNet = 1'b1 +DefaultTieDownNet = 1'b0 +MultipleInstantiations = TRUE +KeepClockPinConnection = FALSE +KeepAsyncResetPinConnection = FALSE +ScriptFileModeType = 1 +MagmaScriptPower = VDD +MagmaScriptGround = GND +ShowModeMsg = TRUE +AstroScriptPower = VDD +AstroScriptGround = VSS +ClearFloatingPorts = FALSE +[eco_connection] +Port/NetIsUnique = TRUE +SerialNet = 0 +SerialPort = 0 +SerialInst = 0 +[finsim] +TPLanguage = Verilog +TPName = Super-FinSim +TPPath = TOP.sim +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[hvpsetting] +importExcelXMLOptions = +use_test_loca_as_source = FALSE +autoTurnOffHideMeetGoalInit = FALSE +autoTurnOffHideMeetGoal = TRUE +autoTurnOffModifierInit = FALSE +autoTurnOffModifier = TRUE +enableNumbering = TRUE +autoSaveCheck = TRUE +autoSaveTime = 5 +ShowMissingScore = TRUE +enableFeatureId = FALSE +enable_HVP_FEAT_ID = FALSE +enableMeasureConcealment = FALSE +HvpCloneHierShowMsgAgain = 1 +HvpCloneHierType = tree +HvpCloneHierMetrics = Line,Cond,FSM,Toggle,Branch,Assert +autoRecalPlanAfterLoadingCovDBUserDataPlan = false +warnMeAutoRecalPlanAfterLoadingCovDBUserDataPlan = true +autoRecalExclWithPlan = false +warnMeAutoRecalExclWithPlan = true +autoRecalPlanWithExcl = false +warnMeAutoRecalPlanWithExcl = true +warnPopupWarnWhenMultiFilters = true +warnPopupWarnIfHvpReadOnly = true +unmappedObjsReportLevel = def_var_inst +unmappedObjsReportInst = true +unmappedObjsNumOfObjs = High +[ikos] +TPLanguage = VHDL +TPName = Voyager +TPPath = vsh +TPOption = -X +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[imp] +options = NULL +libPath = NULL +libDir = NULL +[nCompare] +ErrorViewport = 80 180 800 550 +EditorViewport = 409 287 676 475 +EditorHeightWidth = 802 380 +WaveCommand = "novas" +WaveArgs = "-nWave" +[nCompare.Wnd0] +ViewByHier = FALSE +[nMemory] +dispMode = ADDR_HINT +addrColWidth = 120 +valueColWidth = 100 +showCellBitRangeWithAddr = TRUE +wordsShownInOneRow = 8 +syncCursorTime = FALSE +fixCellColumnWidth = FALSE +font = Courier 12 +[planColors] +plan_fillColor_inactive = lightGray +plan_fillColor_warning = orange +plan_fillColor_error = red +plan_fillColor_invalid = #F0DCDB +plan_fillColor_subplan = lightGray +[schematics] +viewport = 178 262 638 516 +schBackgroundColor = black lineSolid +schBackgroundColor_qt = #000000 qt_solidLine 1 +schBodyColor = orange6 lineSolid +schBodyColor_qt = #ffb973 qt_solidLine 1 +schAsmBodyColor = blue7 lineSolid +schAsmBodyColor_qt = #a5a5ff qt_solidLine 1 +schPortColor = orange6 lineSolid +schPortColor_qt = #ffb973 qt_solidLine 1 +schCellNameColor = Gray6 lineSolid +schCellNameColor_qt = #e0e0e0 qt_solidLine 1 +schCLKNetColor = red6 lineSolid +schCLKNetColor_qt = #ff7373 qt_solidLine 1 +schPWRNetColor = red4 lineSolid +schPWRNetColor_qt = #ff0101 qt_solidLine 1 +schGNDNetColor = cyan4 lineSolid +schGNDNetColor_qt = #01ffff qt_solidLine 1 +schSIGNetColor = green8 lineSolid +schSIGNetColor_qt = #cdffcd qt_solidLine 1 +schTraceColor = yellow4 lineSolid +schTraceColor_qt = #ffff01 qt_solidLine 2 +schBackAnnotateColor = white lineSolid +schBackAnnotateColor_qt = #ffffff qt_solidLine 1 +schValue0 = yellow4 lineSolid +schValue0_qt = #ffff01 qt_solidLine 1 +schValue1 = green3 lineSolid +schValue1_qt = #008000 qt_solidLine 1 +schValueX = red4 lineSolid +schValueX_qt = #ff0101 qt_solidLine 1 +schValueZ = purple7 lineSolid +schValueZ_qt = #ffcdff qt_solidLine 1 +dimColor = cyan2 lineSolid +dimColor_qt = #008080 qt_solidLine 1 +schPreSelColor = green4 lineDash +schPreSelColor_qt = #01ff01 qt_dashLine 2 +schSIGBusNetColor = green8 lineSolid +schSIGBusNetColor_qt = #cdffcd qt_solidLine +schGNDBusNetColor = cyan4 lineSolid +schGNDBusNetColor_qt = #01ffff qt_solidLine +schPWRBusNetColor = red4 lineSolid +schPWRBusNetColor_qt = #ff0101 qt_solidLine +schCLKBusNetColor = red6 lineSolid +schCLKBusNetColor_qt = #ff7373 qt_solidLine +schEdgeSensitiveColor = orange6 lineSolid +schEdgeSensitiveColor_qt = #ffb973 qt_solidLine +schAnnotColor = cyan4 lineSolid +schAnnotColor_qt = #01ffff qt_solidLine +schInstNameColor = orange6 lineSolid +schInstNameColor_qt = #ffb973 qt_solidLine +schPortNameColor = cyan4 lineSolid +schPortNameColor_qt = #01ffff qt_solidLine +schAsmLatchColor = cyan4 lineSolid +schAsmLatchColor_qt = #01ffff qt_solidLine +schAsmRegColor = cyan4 lineSolid +schAsmRegColor_qt = #01ffff qt_solidLine +schAsmTriColor = cyan4 lineSolid +schAsmTriColor_qt = #01ffff qt_solidLine +pre_select = True +ShowPassThroughNet = False +ComputedAnnotColor = ID_PURPLE5 +[schematics_print] +Signature = FALSE +DesignName = PCU +DesignerName = bai +SignatureLocation = LowerRight +MultiPage = TRUE +AutoSliver = FALSE +[sourceColors] +BackgroundActive = gray88 +BackgroundInactive = lightgray +InactiveCode = dimgray +Selection = darkblue +Standard = black +Keyword = blue +Comment = gray25 +Number = black +String = black +Identifier = darkred +Inline = green +colorIdentifier = green +Value = darkgreen +MacroBackground = white +Missing = #400040 +[specColors] +top_plan_linked = #ADFFA6 +top_plan_ignore = #D3D3D3 +top_plan_todo = #EECBAD +sub_plan_ignore = #919191 +sub_plan_todo = #EFAFAF +sub_plan_linked = darkorange +[spec_link_setting] +use_spline = true +goto_section = false +exclude_ignore = true +truncate_abstract = false +abstract_length = 999 +compare_strategy = 2 +auto_apply_margin = FALSE +margin_top = 0.80 +margin_bottom = 0.80 +margin_left = 0.50 +margin_right = 0.50 +margin_unit = inches +[spiceDebug] +ThroughNet = ID_YELLOW5 +InstrumentSig = ID_GREEN5 +InterfaceElement = ID_GREEN5 +Run-timeInterfaceElement = ID_BLUE5 +HighlightThroughNet = TRUE +HighlightInterfaceElement = TRUE +HighlightRuntimeInterfaceElement = TRUE +HighlightSameNet = TRUE +[surefire] +TPLanguage = Verilog +TPName = SureFire +TPPath = verilog +TPOption = +AddImportArgument = TRUE +LineBreakWithScope = TRUE +StopAfterCompileOption = -tcl +[turboSchema_Printer_Options] +Orientation = Landscape +[turbo_library] +bdb_load_scope = +[vdCovFilteringSearchesStrings] +keepLastUsedFiltersMaxNum = 10 +[verisity] +TPLanguage = Verilog +TPName = "Verisity SpeXsim" +TPPath = vlg +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = TRUE +StopAfterCompileOption = -s +[wave.0] +viewPort = 0 27 1920 392 152 65 +[wave.1] +viewPort = 127 219 960 332 100 65 +[wave.2] +viewPort = 38 314 686 205 100 65 +[wave.3] +viewPort = 63 63 700 400 65 41 +[wave.4] +viewPort = 84 84 700 400 65 41 +[wave.5] +viewPort = 92 105 700 400 65 41 +[wave.6] +viewPort = 0 0 700 400 65 41 +[wave.7] +viewPort = 21 21 700 400 65 41 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/novas_autosave.ses b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/novas_autosave.ses new file mode 100644 index 0000000..e1765b4 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/novas_autosave.ses @@ -0,0 +1,85 @@ +@verdi rc file Version 1.0 +[General] +saveDB = TRUE +relativePath = FALSE +saveSingleView = FALSE +saveNWaveWinId = +VerdiVersion = Verdi_O-2018.09-SP2 +[KeyNote] +Line1 = Automatic Backup 0 +Line2 = Save Open Database Information: Yes +Line3 = Path Option: Absolute Paths +Line4 = Windows Option: All Windows +[TestBench] +ConstrViewShow = 0 +InherViewShow = 0 +FSDBMsgShow = 0 +AnnotationShow = 0 +Console = FALSE +powerDumped = 0 +[hb] +postSimFile = /home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdplus_000.fsdb +syncTime = 291747108 +viewport = 0 27 1920 977 0 0 189 1918 +activeNode = "TB" +activeScope = "TB" +activeFile = "../../../../sim/chip_top/TB.sv" +interactiveMode = False +viewType = Source +simulatorMode = False +sourceBeginLine = 315 +baMode = False +srcLineNum = True +AutoWrap = True +IdentifyFalseLogic = False +syncSignal = False +traceMode = Hierarchical +showTraceInSchema = True +paMode = False +funcMode = False +powerAwareAnnot = True +amsAnnot = True +traceCrossHier = True +DnDtraceCrossHierOnly = True +traceIncTopPort = False +leadingZero = False +signalPane = False +Scope1 = "TB" +Scope2 = "TB.clk_40g_inst" +Scope3 = "TB.U_da4008_chip_top" +Scope4 = "TB.U_da4008_chip_top.digital_top.U_awg_top" +multipleSelection = 1 322 5 0 0 +sdfCheckUndef = FALSE +simFlow = FALSE +[hb.design] +importCmd = "-sverilog" "-f" "filelist_vlg.f" "-top" "TB" +invokeDir = /home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g +[hb.sourceTab.1] +scope = TB +File = /home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/TB.sv +Line = 316 +[nMemoryManager] +WaveformFile = /home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdplus_000.fsdb +UserActionNum = 0 +nMemWindowNum = 0 +[wave.0] +viewPort = 0 27 1920 309 152 65 +primaryWindow = TRUE +SessionFile = /home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/novas_autosave.ses.wave.0 +displayGrid = FALSE +hierarchicalName = FALSE +snap = TRUE +displayLeadingZeros = FALSE +fixDelta = FALSE +displayCursorMarker = FALSE +autoUpdate = FALSE +highlightGlitchs = FALSE +waveformSyncCursorMarker = FALSE +waveformSyncHorizontalRange = FALSE +waveformSyncVerticalscroll = FALSE +displayErrors = TRUE +displayMsgSymbols = TRUE +showMsgDescriptions = TRUE +autoFit = FALSE +displayDeltaY = FALSE +centerCursor = FALSE diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/novas_autosave.ses.config b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/novas_autosave.ses.config new file mode 100644 index 0000000..47836c8 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/novas_autosave.ses.config @@ -0,0 +1,55 @@ +[qBaseWindowStateGroup] +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\Verdi=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\nWave=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\hdlHier=1 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+Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\size=@Size(1920 977) +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_width=1920 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_height=977 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/novas_autosave.ses.png b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/novas_autosave.ses.png new file mode 100644 index 0000000..2191939 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/novas_autosave.ses.png differ diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/novas_autosave.ses.wave.0 b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/novas_autosave.ses.wave.0 new file mode 100644 index 0000000..368a825 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/novas_autosave.ses.wave.0 @@ -0,0 +1,57 @@ +Magic 271485 +Revision Verdi_O-2018.09-SP2 + +; Window Layout +viewPort 0 27 1920 309 152 65 + +; File list: +; openDirFile [-d delimiter] [-s time_offset] [-rf auto_bus_rule_file] path_name file_name +openDirFile -d / "" "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdplus_000.fsdb" + +; file time scale: +; fileTimeScale ### s|ms|us|ns|ps + +; signal spacing: +signalSpacing 5 + +; windowTimeUnit is used for zoom, cursor & marker +; waveform viewport range +zoom 134289743.767873 134518596.178090 +cursor 291747108.000000 +marker 291769308.000000 + +; user define markers +; userMarker time_pos marker_name color linestyle +; visible top row signal index +top 0 +; marker line index +markerPos 1 + +; event list +; addEvent event_name event_expression +; curEvent event_name + + + +COMPLEX_EVENT_BEGIN + + +COMPLEX_EVENT_END + + + +; toolbar current search type +; curSTATUS search_type +curSTATUS ByChange + + +addGroup "G1" +activeDirFile "" "/home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdplus_000.fsdb" +addSignal -w analog -ds pwc -h 98 -UNSIGNED -HEX /TB/cs_wave[7:0] +addSignal -c ID_CYAN6 -ls solid -lw 1 -h 15 -UNSIGNED -HEX -holdScope cnt_c[5:0] +addSignal -h 15 -holdScope clk_40g +addGroup "G2" + +; getSignalForm Scope Hierarchy Status +; active file of getSignalForm + diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/pes.bat b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/pes.bat new file mode 100644 index 0000000..7c6e4ac --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/pes.bat @@ -0,0 +1,3 @@ +where +detach +quit diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/turbo.log b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/turbo.log new file mode 100644 index 0000000..e5be389 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/turbo.log @@ -0,0 +1,3 @@ +Command Line: /opt/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/bin/Novas -sverilog -f filelist_vlg.f -top TB -ssf verdplus_000.fsdb -nologo +uname(Linux cryo1 3.10.0-1160.92.1.el7.x86_64 #1 SMP Tue Jun 20 11:48:01 UTC 2023 x86_64) +au time 5150.715472 126.554022 61.746470 delta 1618165760 1618165760 total 2043252736 2043252736 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/verdi.cmd b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/verdi.cmd new file mode 100644 index 0000000..9161df9 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/verdi.cmd @@ -0,0 +1,1100 @@ +sidCmdLineBehaviorAnalysisOpt -incr -clockSkew 0 -loopUnroll 0 -bboxEmptyModule 0 -cellModel 0 -bboxIgnoreProtected 0 +debImport "-sverilog" "-f" "filelist_vlg.f" "-top" "TB" +debLoadSimResult \ + /home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdplus_000.fsdb +wvCreateWindow +srcHBSelect "TB.U_da4008_chip_top" -win $_nTrace1 +srcHBSelect "TB.clk_40g_inst" -win $_nTrace1 +srcHBSelect "TB.U_da4008_chip_top.digital_top.U_awg_top" -win $_nTrace1 +srcHBSelect "TB.U_da4008_chip_top.digital_top.U_awg_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_da4008_chip_top.digital_top.U_awg_top" -delim \ + "." +srcHBSelect "TB.U_da4008_chip_top.digital_top.U_awg_top" -win $_nTrace1 +srcHBSelect "TB.U_da4008_chip_top.digital_top.U_awg_top.cmd_fifo_inst" -win \ + $_nTrace1 +srcHBSelect "TB.U_da4008_chip_top.digital_top.U_awg_top.start_dffr" -win \ + $_nTrace1 +srcHBSelect "TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst" -win \ + $_nTrace1 +srcHBSelect "TB.U_da4008_chip_top.digital_top.U_awg_top" -win $_nTrace1 +srcHBSelect "TB.U_da4008_chip_top.digital_top.U_awg_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_da4008_chip_top.digital_top.U_awg_top" -delim \ + "." +srcHBSelect "TB.U_da4008_chip_top.digital_top.U_awg_top" -win $_nTrace1 +srcHBSelect "TB.U_da4008_chip_top.digital_top.U_awg_top.awg_ctrl_inst" -win \ + $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wave_data_out" -line 67 -pos 1 -win $_nTrace1 +srcSelect -win $_nTrace1 -range {66 67 2 11 17 6} -backward +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wave_valid_out" -line 68 -pos 1 -win $_nTrace1 +srcSelect -signal "wave_data_out" -line 67 -pos 1 -win $_nTrace1 +wvAddSignal -win $_nWave2 \ + "/TB/U_da4008_chip_top/digital_top/U_awg_top/wave_valid_out" \ + "/TB/U_da4008_chip_top/digital_top/U_awg_top/wave_data_out\[511:0\]" +wvSetPosition -win $_nWave2 {("G1" 0)} +wvSetPosition -win $_nWave2 {("G1" 2)} +wvSetPosition -win $_nWave2 {("G1" 2)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 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134362119.198043 134507406.188585 +wvZoom -win $_nWave2 134392008.292655 134472752.165753 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {105 105 8 9 8 1} -backward +srcDeselectAll -win $_nTrace1 +srcHBSelect "TB.U_da4008_chip_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_da4008_chip_top" -delim "." +srcHBSelect "TB.U_da4008_chip_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {15 16 4 1 7 1} +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {22 23 11 1 1 1} +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {23 28 2 1 9 1} -backward +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {29 37 12 1 1 1} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "CcalRsv0" -line 59 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {29 74 2 1 1 1} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {24 27 1 1 2 1} +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +wvSetCursor -win $_nWave2 134430815.425407 -snap {("G2" 0)} +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 134397761.955640 -snap {("G1" 3)} +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 134436906.123096 -snap {("G1" 3)} +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 134397280.477565 -snap {("G1" 3)} +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut 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+wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 129262090.441503 138783628.353488 +wvZoom -win $_nWave2 134264162.534797 134871678.668716 +wvZoom -win $_nWave2 134381898.219568 134473913.185588 +wvZoom -win $_nWave2 134397042.006394 134400334.133980 +wvSetCursor -win $_nWave2 134397740.871786 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 134397732.000000 +wvSetCursor -win $_nWave2 134397770.318366 -snap {("G1" 0)} +wvSetCursor -win $_nWave2 134397727.130049 +wvSetCursor -win $_nWave2 134398942.292229 -snap {("G1" 2)} +wvSetCursor -win $_nWave2 134398942.292229 -snap {("G1" 2)} +wvSetCursor -win $_nWave2 134398292.504375 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 134398447.589694 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 134398956.033966 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 134398942.292229 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 134398946.218440 -snap {("G1" 2)} +wvSetCursor -win $_nWave2 134398946.218440 -snap {("G1" 2)} +wvSetCursor -win $_nWave2 134398946.218440 -snap {("G1" 2)} +wvSetCursor -win $_nWave2 134398944.255334 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 134398942.292229 +wvSetCursor -win $_nWave2 134398944.255334 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cs_wave" -line 323 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSelectSignal -win $_nWave2 {( "G1" 4 )} +wvSetCursor -win $_nWave2 134398459.368326 -snap {("G2" 0)} +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 134397681.978627 -snap {("G1" 4)} +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSelectSignal -win $_nWave2 {( "G1" 2 )} +wvSelectSignal -win $_nWave2 {( "G1" 4 )} +wvGoToGroup -win $_nWave2 "G2" +wvSelectGroup -win $_nWave2 {G2} +wvSelectSignal -win $_nWave2 {( "G1" 4 )} +wvSelectGroup -win $_nWave2 {G2} +wvSetPosition -win $_nWave2 {("G1" 0)} +wvCollapseGroup -win $_nWave2 "G1" +wvSelectGroup -win $_nWave2 {G2} +wvExpandGroup -win $_nWave2 "G1" +wvSelectGroup -win $_nWave2 {G2} +wvSelectGroup -win $_nWave2 {G2} +wvSelectSignal -win $_nWave2 {( "G1" 4 )} +wvGoToGroup -win $_nWave2 "G2" +wvSetPosition -win $_nWave2 {("G1" 4)} +wvSetPosition -win $_nWave2 {("G2" 0)} +wvMoveSelected -win $_nWave2 +wvSetPosition -win $_nWave2 {("G2" 1)} +wvSetPosition -win $_nWave2 {("G2" 1)} +wvSelectGroup -win $_nWave2 {G2} +wvSelectSignal -win $_nWave2 {( "G2" 1 )} +wvSelectSignal -win $_nWave2 {( "G2" 1 )} +wvSelectSignal -win $_nWave2 {( "G2" 1 )} +wvSetCursor -win $_nWave2 134397387.512833 -snap {("G2" 1)} +wvSelectGroup -win $_nWave2 {G2} +wvSelectSignal -win $_nWave2 {( "G2" 1 )} +wvSelectSignal -win $_nWave2 {( "G1" 2 )} +wvSelectSignal -win $_nWave2 {( "G2" 1 )} +wvSetCursor -win $_nWave2 134397503.336045 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 134397493.520519 -snap {("G1" 3)} +srcActiveTrace "TB.cs_wave\[7:0\]" -win $_nTrace1 -TraceByDConWave -TraceTime \ + 26916 -TraceValue 00000000 +wvSetCursor -win $_nWave2 134397452.295307 -snap {("G2" 1)} +wvSelectSignal -win $_nWave2 {( "G2" 1 )} +wvSelectSignal -win $_nWave2 {( "G2" 1 )} +wvSetCursor -win $_nWave2 134397731.056260 -snap {("G1" 2)} +wvSetCursor -win $_nWave2 134397617.196152 -snap {("G1" 2)} +wvZoom -win $_nWave2 134397595.601994 134397607.380626 +wvSetCursor -win $_nWave2 134397597.378879 -snap {("G2" 1)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSelectSignal -win $_nWave2 {( "G2" 1 )} +wvSelectSignal -win $_nWave2 {( "G2" 1 )} +wvSelectSignal -win $_nWave2 {( "G2" 1 )} +wvSelectSignal -win $_nWave2 {( "G1" 2 )} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G2" 1 )} +wvSelectSignal -win $_nWave2 {( "G2" 1 )} +wvSelectSignal -win $_nWave2 {( "G2" 1 )} +wvSelectGroup -win $_nWave2 {G2} +wvGetSignalOpen -win $_nWave2 +wvGetSignalSetScope -win $_nWave2 "/PCLAMPC_H_G" +wvGetSignalSetScope -win $_nWave2 "/_\$novas_unit__1" +wvGetSignalSetScope -win $_nWave2 "/clk_gen" +wvGetSignalSetScope -win $_nWave2 "/reset_tb" +wvGetSignalSetScope -win $_nWave2 "/sirv_gnrl_dffl" +wvGetSignalSetScope -win $_nWave2 "/sirv_gnrl_xchecker" +wvGetSignalSetScope -win $_nWave2 "/sirv_gnrl_ltch/LTCH_PROC" +wvGetSignalSetScope -win $_nWave2 "/sirv_gnrl_dffl" +wvGetSignalSetScope -win $_nWave2 "/TB" +wvSetPosition -win $_nWave2 {("G2" 1)} +wvSetPosition -win $_nWave2 {("G2" 1)} +wvAddSignal -win $_nWave2 -clear +wvAddSignal -win $_nWave2 -group {"G1" \ +{/TB/U_da4008_chip_top/digital_top/U_awg_top/wave_valid_out} \ +{/TB/U_da4008_chip_top/digital_top/U_awg_top/wave_data_out\[511:0\]} \ +{/TB/cs_wave\[7:0\]} -height 52 \ +} +wvAddSignal -win $_nWave2 -group {"G2" \ +{/TB/cs_wave\[7:0\]} \ +} +wvAddSignal -win $_nWave2 -group {"G3" \ +} +wvSetPosition -win $_nWave2 {("G2" 1)} +wvGetSignalClose -win $_nWave2 +wvGetSignalOpen -win $_nWave2 +wvGetSignalSetScope -win $_nWave2 "/PCLAMPC_H_G" +wvGetSignalSetScope -win $_nWave2 "/sirv_gnrl_ltch" +wvGetSignalSetScope -win $_nWave2 "/TB" +wvSelectGroup -win $_nWave2 {G3} +wvSelectGroup -win $_nWave2 {G2} +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSetPosition -win $_nWave2 {("G2" 4)} +wvSetPosition -win $_nWave2 {("G2" 4)} +wvAddSignal -win $_nWave2 -clear +wvAddSignal -win $_nWave2 -group {"G1" \ +{/TB/U_da4008_chip_top/digital_top/U_awg_top/wave_valid_out} \ +{/TB/U_da4008_chip_top/digital_top/U_awg_top/wave_data_out\[511:0\]} \ +{/TB/cs_wave\[7:0\]} -height 52 \ +} +wvAddSignal -win $_nWave2 -group {"G2" \ +{/TB/cs_wave\[7:0\]} \ +{/TB/cs_wave\[7:0\]} \ +{/TB/cs_wave\[7:0\]} \ +{/TB/data_out\[63:0\]} \ +} +wvAddSignal -win $_nWave2 -group {"G3" \ +} +wvSelectSignal -win $_nWave2 {( "G2" 3 4 )} +wvSetPosition -win $_nWave2 {("G2" 4)} +wvSelectSignal -win $_nWave2 {( "G2" 4 )} +wvSelectSignal -win $_nWave2 {( "G2" 2 3 4 )} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G2" 1)} +verdiWindowPreviousLayout -win $_Verdi_1 +verdiDockWidgetSetCurTab -dock windowDock_nWave_2 +wvZoom -win $_nWave2 134393363.843887 134479900.391200 +wvSelectSignal -win $_nWave2 {( "G2" 1 )} +wvSelectGroup -win $_nWave2 {G2} +wvSelectSignal -win $_nWave2 {( "G2" 1 )} +wvSelectSignal -win $_nWave2 {( "G2" 1 )} +wvSelectGroup -win $_nWave2 {G3} +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSelectGroup -win $_nWave2 {G1} +wvSelectSignal -win $_nWave2 {( "G1" 2 )} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G3" 0)} +wvSetPosition -win $_nWave2 {("G2" 1)} +wvSelectGroup -win $_nWave2 {G1} +wvTpfCloseForm -win $_nWave2 +wvGetSignalClose -win $_nWave2 +wvCloseWindow -win $_nWave2 +wvCreateWindow +wvAddSignal -win $_nWave3 "/TB/cs_wave\[7:0\]" +wvSetPosition -win $_nWave3 {("G1" 0)} +wvSetPosition -win $_nWave3 {("G1" 1)} +wvSetPosition -win $_nWave3 {("G1" 1)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 130416216.249016 136475376.738462 +wvZoom -win $_nWave3 134170222.062079 134517079.192065 +wvZoom -win $_nWave3 134394221.031454 134474885.480288 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 129981990.697674 137695207.728086 +wvZoomIn -win $_nWave3 +wvZoom -win $_nWave3 134299690.451502 134499764.954080 +wvSetCursor -win $_nWave3 134343714.000368 -snap {("G1" 1)} +wvSelectSignal -win $_nWave3 {( "G1" 1 )} +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G1" 1)} +wvSetCursor -win $_nWave3 134396924.035043 -snap {("G1" 1)} +wvSetMarker -win $_nWave3 134399436.000000 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvSetCursor -win $_nWave3 134399064.068590 -snap {("G1" 1)} +wvSetCursor -win $_nWave3 134397945.584117 -snap {("G1" 1)} +wvSetMarker -win $_nWave3 134397972.000000 +wvSetMarker -win $_nWave3 134398908.000000 +wvSelectGroup -win $_nWave3 {G1} +wvSetCursor -win $_nWave3 134398691.240433 -snap {("G2" 0)} +wvZoom -win $_nWave3 134397080.622791 134400823.817495 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rst_n" -line 318 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_c" -line 322 -pos 1 -win $_nTrace1 +srcSelect -win $_nTrace1 -range {322 323 4 2 4 1} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_c" -line 322 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G1" 0)} +wvCollapseGroup -win $_nWave3 "G1" +wvExpandGroup -win $_nWave3 "G1" +wvSelectSignal -win $_nWave3 {( "G1" 2 )} +wvChangeDisplayAttr -win $_nWave3 -c ID_PURPLE5 -lw 1 -ls solid +wvZoom -win $_nWave3 134349810.792163 134468664.478263 +wvZoom -win $_nWave3 134395736.366693 134400272.225912 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G1" 2 )} +wvSetPosition -win $_nWave3 {("G1" 2)} +wvExpandBus -win $_nWave3 {("G1" 2)} +wvSelectSignal -win $_nWave3 {( "G1" 2 )} +wvSelectSignal -win $_nWave3 {( "G1" 2 )} +wvSelectSignal -win $_nWave3 {( "G1" 2 )} +wvSetPosition -win $_nWave3 {("G1" 2)} +wvCollapseBus -win $_nWave3 {("G1" 2)} +wvSetPosition -win $_nWave3 {("G1" 2)} +wvSetCursor -win $_nWave3 134507752.074226 -snap {("G1" 1)} +wvZoom -win $_nWave3 134393503.598726 134489749.284148 +wvSetCursor -win $_nWave3 134449230.826216 -snap {("G1" 1)} +wvSetCursor -win $_nWave3 134397463.617957 -snap {("G1" 2)} +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 134396660.135789 134404178.433219 +wvZoom -win $_nWave3 134397664.368530 134397924.393128 +wvSearchNext -win $_nWave3 +wvSetSearchMode -win $_nWave3 -posedge +wvSearchNext -win $_nWave3 +wvSearchNext -win $_nWave3 +wvSearchPrev -win $_nWave3 +wvSearchPrev -win $_nWave3 +wvSearchPrev -win $_nWave3 +wvSetSearchMode -win $_nWave3 -negedge +wvSearchPrev -win $_nWave3 +wvSetSearchMode -win $_nWave3 -value +wvSearchNext -win $_nWave3 +wvSearchPrev -win $_nWave3 +wvSetSearchMode -win $_nWave3 -value 44 +wvSearchNext -win $_nWave3 +wvSearchPrev -win $_nWave3 +wvSearchPrev -win $_nWave3 +wvSetSearchMode -win $_nWave3 -value 3 +wvSearchPrev -win $_nWave3 +wvSearchPrev -win $_nWave3 +wvSearchNext -win $_nWave3 +wvSetSearchMode -win $_nWave3 -analog +wvSetSearchMode -win $_nWave3 -analog * +wvSearchNext -win $_nWave3 +wvSetSearchMode -win $_nWave3 -analog 33 +wvSearchPrev -win $_nWave3 +wvSetSearchMode -win $_nWave3 -analog 33 +wvSearchPrev -win $_nWave3 +wvSetSearchMode -win $_nWave3 -analog 33 +wvSearchNext -win $_nWave3 +wvSetSearchMode -win $_nWave3 -analog 33 +wvSearchNext -win $_nWave3 +wvSetSearchMode -win $_nWave3 -analog 33 +wvSearchNext -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G1" 1 )} +wvSetSearchMode -win $_nWave3 -analog 33 +wvSearchPrev -win $_nWave3 +wvSetSearchMode -win $_nWave3 -analog 33 +wvSearchNext -win $_nWave3 +wvSetCursor -win $_nWave3 134397766.703762 +wvSetSearchMode -win $_nWave3 -analog * +wvSearchPrev -win $_nWave3 +wvSetSearchMode -win $_nWave3 -analog * +wvSearchNext -win $_nWave3 +wvSetSearchMode -win $_nWave3 -anyChange +wvSelectSignal -win $_nWave3 {( "G1" 2 )} +wvSetSearchMode -win $_nWave3 -value 3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSearchNext -win $_nWave3 +wvSetSearchMode -win $_nWave3 -value 17 +wvSearchNext -win $_nWave3 +wvSetSearchMode -win $_nWave3 -posedge +wvSearchNext -win $_nWave3 +wvSearchNext -win $_nWave3 +wvSearchNext -win $_nWave3 +wvSearchPrev -win $_nWave3 +wvSearchPrev -win $_nWave3 +wvSetSearchMode -win $_nWave3 -anyChange +wvSearchNext -win $_nWave3 +wvSearchNext -win $_nWave3 +wvSearchNext -win $_nWave3 +wvSetSearchMode -win $_nWave3 -analog * +wvSelectSignal -win $_nWave3 {( "G1" 1 )} +wvSetSearchMode -win $_nWave3 -analog * +wvSetSearchMode -win $_nWave3 -analog * +wvSearchNext -win $_nWave3 +wvSetSearchMode -win $_nWave3 -analog * +wvSearchNext -win $_nWave3 +wvSetSearchMode -win $_nWave3 -analog MAX +wvSearchNext -win $_nWave3 +wvSetSearchMode -win $_nWave3 -analog MAX 22 +wvSearchNext -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetSearchMode -win $_nWave3 -analog MAX +wvSearchNext -win $_nWave3 +wvSetSearchMode -win $_nWave3 -analog MAX +wvSearchPrev -win $_nWave3 +wvSetSearchMode -win $_nWave3 -analog MAX +wvSearchPrev -win $_nWave3 +wvSetSearchMode -win $_nWave3 -analog MAX +wvSearchPrev -win $_nWave3 +wvSetSearchMode -win $_nWave3 -analog MAX +wvSearchPrev -win $_nWave3 +wvSetCursor -win $_nWave3 134397876.248979 -snap {("G1" 1)} +wvSetSearchMode -win $_nWave3 -analog MIN +wvSearchPrev -win $_nWave3 +wvSetSearchMode -win $_nWave3 -analog MIN +wvSearchNext -win $_nWave3 +wvSetSearchMode -win $_nWave3 -analog MIN +wvSearchNext -win $_nWave3 +wvSetSearchMode -win $_nWave3 -analog MIN +wvSetSearchMode -win $_nWave3 -analog MIN 33 +wvSearchNext -win $_nWave3 +wvSearchNext -win $_nWave3 +wvSetSearchMode -win $_nWave3 -anyChange +wvSearchNext -win $_nWave3 +wvSearchNext -win $_nWave3 +wvSearchNext -win $_nWave3 +wvSetCursor -win $_nWave3 134397831.593592 -snap {("G1" 1)} +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvSetCursor -win $_nWave3 134397824.771264 -snap {("G1" 1)} +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk_40g" -line 317 -pos 1 -win $_nTrace1 +srcSelect -win $_nTrace1 -range {317 318 7 9 4 1} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk_40g" -line 317 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 134397713.753002 -snap {("G1" 3)} +wvSetCursor -win $_nWave3 134397723.676421 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-win $_nWave3 +wvZoomOut -win $_nWave3 +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G1" 1)} +wvZoomValue -win $_nWave3 -node {("G1" 1)} -range 96.817373 87.746538 +wvZoomValue -win $_nWave3 -node {("G1" 1)} -range 94.873624 88.301894 +wvZoomValue -win $_nWave3 -node {("G1" 1)} -range 93.666574 89.240714 +wvZoomValue -win $_nWave3 -node {("G1" 1)} -range 94.253676 89.872980 +wvZoomValue -win $_nWave3 -node {("G1" 1)} -range 94.164275 91.973926 +wvZoomValue -win $_nWave3 -node {("G1" 1)} -range 93.046749 92.487985 +wvZoomValue -win $_nWave3 -node {("G1" 1)} -range 92.795873 92.636227 +wvZoomAll -win $_nWave3 +wvZoom -win $_nWave3 287665857.522719 294013549.464043 +wvZoom -win $_nWave3 291708394.787658 291844660.088724 +wvZoomValue -win $_nWave3 -node {("G1" 1)} -range 92.730711 92.709533 +wvZoomValue -win $_nWave3 -node {("G1" 1)} -range 92.722717 92.714288 +wvZoomValue -win $_nWave3 -node {("G1" 1)} -range 92.720739 92.717728 +wvSetCursor -win $_nWave3 291740571.924882 -snap {("G1" 1)} +wvSetCursor -win $_nWave3 291740571.924882 -snap {("G1" 1)} +srcActiveTrace "TB.cs_wave\[7:0\]" -win $_nTrace1 -TraceByDConWave -TraceTime \ + 134471460 -TraceValue 00000000 +wvZoomIn -win $_nWave3 +wvZoomAll -win $_nWave3 +wvZoom -win $_nWave3 127819433.182111 143688663.035420 +wvZoom -win $_nWave3 133601245.609275 135446504.894543 +wvZoom -win $_nWave3 134324164.720960 134459505.741883 +wvZoom -win $_nWave3 134395023.049088 134399381.078384 +wvZoom -win $_nWave3 134397621.754603 134397845.243285 +wvSelectSignal -win $_nWave3 {( "G1" 1 )} +wvExpandBus -win $_nWave3 {("G1" 1)} +wvScrollUp -win $_nWave3 1 +wvSelectSignal -win $_nWave3 {( "G1" 4 )} +wvScrollUp -win $_nWave3 3 +wvSelectSignal -win $_nWave3 {( "G1" 1 )} +wvSetPosition -win $_nWave3 {("G1" 1)} +wvCollapseBus -win $_nWave3 {("G1" 1)} +wvSetPosition -win $_nWave3 {("G1" 1)} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G1" 1)} +wvSetPosition -win $_nWave3 {("G1" 0)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cs_wave" -line 333 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cs_wave" -line 323 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G1" 1)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +debExit diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/verdi.cmd.bak b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/verdi.cmd.bak new file mode 100644 index 0000000..4b2e9e4 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/verdi.cmd.bak @@ -0,0 +1,459 @@ +sidCmdLineBehaviorAnalysisOpt -incr -clockSkew 0 -loopUnroll 0 -bboxEmptyModule 0 -cellModel 0 -bboxIgnoreProtected 0 +debImport "-sverilog" "-f" "filelist_vlg.f" "-top" "TB" +debLoadSimResult \ + /home/shbyang/Desktop/workplace/lin-win-share/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdplus_000.fsdb +wvCreateWindow +verdiWindowResize -win $_Verdi_1 "587" "176" "1057" "712" +srcHBSelect "TB.clk_40g_inst" -win $_nTrace1 +srcHBSelect "TB.U_da4008_chip_top.U_iopad" -win $_nTrace1 +srcHBSelect "TB.U_da4008_chip_top.digital_top" -win $_nTrace1 +srcHBSelect "TB.U_da4008_chip_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_da4008_chip_top" -delim "." +srcHBSelect "TB.U_da4008_chip_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "MSB_OUT" -line 24 -pos 1 -win $_nTrace1 +srcSelect -signal "LSB_OUT" -line 25 -pos 1 -win $_nTrace1 +wvAddSignal -win $_nWave2 "/TB/U_da4008_chip_top/MSB_OUT\[63:0\]" \ + "/TB/U_da4008_chip_top/LSB_OUT\[63:0\]" +wvSetPosition -win $_nWave2 {("G1" 0)} +wvSetPosition -win $_nWave2 {("G1" 2)} +wvSetPosition -win $_nWave2 {("G1" 2)} +wvZoomOut -win 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+wvSetPosition -win $_nWave2 {("G2" 2)} +wvSetPosition -win $_nWave2 {("G2" 2)} +wvSetPosition -win $_nWave2 {("G2/digital_top" 0)} +wvAddSubGroup -win $_nWave2 -holdpost {digital_top} +wvAddSignal -win $_nWave2 "/TB/U_da4008_chip_top/digital_top/clk" \ + "/TB/U_da4008_chip_top/digital_top/rst_n" \ + "/TB/U_da4008_chip_top/digital_top/sync_in" \ + "/TB/U_da4008_chip_top/digital_top/sync_out" \ + "/TB/U_da4008_chip_top/digital_top/cfgid\[4:0\]" \ + "/TB/U_da4008_chip_top/digital_top/sclk" \ + "/TB/U_da4008_chip_top/digital_top/csn" \ + "/TB/U_da4008_chip_top/digital_top/mosi" \ + "/TB/U_da4008_chip_top/digital_top/miso" \ + "/TB/U_da4008_chip_top/digital_top/oen" \ + "/TB/U_da4008_chip_top/digital_top/irq" \ + "/TB/U_da4008_chip_top/digital_top/wave_data_out\[63:0\]" \ + "/TB/U_da4008_chip_top/digital_top/wave_data_valid" \ + "/TB/U_da4008_chip_top/digital_top/lvds_data\[3:0\]" \ + "/TB/U_da4008_chip_top/digital_top/lvds_valid\[0:0\]" \ + "/TB/U_da4008_chip_top/digital_top/lvds_clk\[0:0\]" \ + "/TB/U_da4008_chip_top/digital_top/phase_tap\[2:0\]" \ + "/TB/U_da4008_chip_top/digital_top/Rterm\[3:0\]" \ + "/TB/U_da4008_chip_top/digital_top/PrbsEn" \ + "/TB/U_da4008_chip_top/digital_top/Set\[63:0\]" \ + "/TB/U_da4008_chip_top/digital_top/CasAddr\[2:0\]" \ + "/TB/U_da4008_chip_top/digital_top/CasDw\[2:0\]" \ + "/TB/U_da4008_chip_top/digital_top/IMainCtrl\[9:0\]" \ + "/TB/U_da4008_chip_top/digital_top/IBleedCtrl\[3:0\]" \ + "/TB/U_da4008_chip_top/digital_top/ICkCml\[3:0\]" \ + "/TB/U_da4008_chip_top/digital_top/CurRsv0\[31:0\]" \ + "/TB/U_da4008_chip_top/digital_top/CurRsv1\[31:0\]" \ + "/TB/U_da4008_chip_top/digital_top/CcalRstn\[0:0\]" \ + "/TB/U_da4008_chip_top/digital_top/EnAllP\[3:0\]" \ + "/TB/U_da4008_chip_top/digital_top/DccEn\[0:0\]" \ + "/TB/U_da4008_chip_top/digital_top/CasGateCkCtrl\[0:0\]" \ + "/TB/U_da4008_chip_top/digital_top/SpiEnPi\[0:0\]" \ + "/TB/U_da4008_chip_top/digital_top/SpiEnQec\[0:0\]" \ + "/TB/U_da4008_chip_top/digital_top/SpiEnDcc\[0:0\]" \ + "/TB/U_da4008_chip_top/digital_top/SpiQecCtrlIp\[4:0\]" \ + "/TB/U_da4008_chip_top/digital_top/SpiQecCtrlIn\[4:0\]" \ + "/TB/U_da4008_chip_top/digital_top/SpiQecCtrlQp\[4:0\]" \ + "/TB/U_da4008_chip_top/digital_top/SpiQecCtrlQn\[4:0\]" \ + "/TB/U_da4008_chip_top/digital_top/SpiDccCtrlIup\[5:0\]" \ + "/TB/U_da4008_chip_top/digital_top/SpiDccCtrlIdn\[5:0\]" \ + "/TB/U_da4008_chip_top/digital_top/SpiDccCtrlQup\[5:0\]" \ + "/TB/U_da4008_chip_top/digital_top/SpiDccCtrlQdn\[5:0\]" \ + "/TB/U_da4008_chip_top/digital_top/SpiSiqNOut\[7:0\]" \ + "/TB/U_da4008_chip_top/digital_top/SpiSiqPOut\[7:0\]" \ + "/TB/U_da4008_chip_top/digital_top/SpiSiPOut\[3:0\]" \ + "/TB/U_da4008_chip_top/digital_top/SpiSqPOut\[3:0\]" \ + "/TB/U_da4008_chip_top/digital_top/CrtlCrossOverN\[2:0\]" \ + "/TB/U_da4008_chip_top/digital_top/CrtlCrossOverP\[2:0\]" \ + "/TB/U_da4008_chip_top/digital_top/CcalRsv0\[31:0\]" \ + "/TB/U_da4008_chip_top/digital_top/CcalRsv1\[31:0\]" \ + "/TB/U_da4008_chip_top/digital_top/SelCk10GDig\[3:0\]" \ + "/TB/U_da4008_chip_top/digital_top/SelCk2p5GDig\[3:0\]" \ + "/TB/U_da4008_chip_top/digital_top/SelCk625MDig\[8:0\]" \ + "/TB/U_da4008_chip_top/digital_top/P2sDataEn\[15:0\]" \ + "/TB/U_da4008_chip_top/digital_top/P2sEnAllP\[15:0\]" \ + "/TB/U_da4008_chip_top/digital_top/EnPiP\[15:0\]" \ + "/TB/U_da4008_chip_top/digital_top/CkDivRstn\[15:0\]" \ + "/TB/U_da4008_chip_top/digital_top/p2srsv0\[31:0\]" \ + "/TB/U_da4008_chip_top/digital_top/p2srsv1\[31:0\]" \ + "/TB/U_da4008_chip_top/digital_top/CkRxSw\[15:0\]" \ + "/TB/U_da4008_chip_top/digital_top/RstnCk\[15:0\]" \ + "/TB/U_da4008_chip_top/digital_top/CtrlZin\[15:0\]" +wvSetPosition -win $_nWave2 {("G2/digital_top" 0)} +wvSetPosition -win $_nWave2 {("G2/digital_top" 62)} +wvSetPosition -win $_nWave2 {("G2" 2)} +wvSetPosition -win $_nWave2 {("G2" 2)} +wvSetPosition -win $_nWave2 {("G2/slv[3:0]" 0)} +wvAddSubGroup -win $_nWave2 -holdpost {slv[3:0]} +wvAddSubGroup -win $_nWave2 -holdpost {slv[3](sram_if)} +wvSetPosition -win $_nWave2 {("G2/slv[3:0]" 0)} +wvSetPosition -win $_nWave2 {("G2/slv[3:0]/slv[3](sram_if)" 0)} +wvAddSignal -win $_nWave2 "/TB/U_da4008_chip_top/digital_top/slv\[3\]/clk" \ + "/TB/U_da4008_chip_top/digital_top/slv\[3\]/addr\[19:0\]" \ + "/TB/U_da4008_chip_top/digital_top/slv\[3\]/din\[31:0\]" \ + "/TB/U_da4008_chip_top/digital_top/slv\[3\]/dout\[31:0\]" \ + "/TB/U_da4008_chip_top/digital_top/slv\[3\]/rden" \ + "/TB/U_da4008_chip_top/digital_top/slv\[3\]/wren" \ + "/TB/U_da4008_chip_top/digital_top/slv\[3\]/wben\[3:0\]" +wvSetPosition -win $_nWave2 {("G2/slv[3:0]/slv[3](sram_if)" 0)} +wvSetPosition -win $_nWave2 {("G2/slv[3:0]/slv[3](sram_if)" 7)} +wvSetPosition -win $_nWave2 {("G2" 2)} +wvSetPosition -win $_nWave2 {("G2/slv[3:0]" 0)} +wvAddSubGroup -win $_nWave2 -holdpost {slv[2](sram_if)} +wvSetPosition -win $_nWave2 {("G2/slv[3:0]" 0)} +wvSetPosition -win $_nWave2 {("G2/slv[3:0]/slv[2](sram_if)" 0)} +wvAddSignal -win $_nWave2 "/TB/U_da4008_chip_top/digital_top/slv\[2\]/clk" \ + "/TB/U_da4008_chip_top/digital_top/slv\[2\]/addr\[19:0\]" \ + "/TB/U_da4008_chip_top/digital_top/slv\[2\]/din\[31:0\]" \ + "/TB/U_da4008_chip_top/digital_top/slv\[2\]/dout\[31:0\]" \ + "/TB/U_da4008_chip_top/digital_top/slv\[2\]/rden" \ + "/TB/U_da4008_chip_top/digital_top/slv\[2\]/wren" \ + "/TB/U_da4008_chip_top/digital_top/slv\[2\]/wben\[3:0\]" +wvSetPosition -win $_nWave2 {("G2/slv[3:0]/slv[2](sram_if)" 0)} +wvSetPosition -win $_nWave2 {("G2/slv[3:0]/slv[2](sram_if)" 7)} +wvSetPosition -win $_nWave2 {("G2/slv[3:0]" 0)} +wvAddSubGroup -win $_nWave2 -holdpost {slv[1](sram_if)} +wvSetPosition -win $_nWave2 {("G2/slv[3:0]" 0)} +wvSetPosition -win $_nWave2 {("G2/slv[3:0]/slv[1](sram_if)" 0)} +wvAddSignal -win $_nWave2 "/TB/U_da4008_chip_top/digital_top/slv\[1\]/clk" \ + "/TB/U_da4008_chip_top/digital_top/slv\[1\]/addr\[19:0\]" \ + "/TB/U_da4008_chip_top/digital_top/slv\[1\]/din\[31:0\]" \ + "/TB/U_da4008_chip_top/digital_top/slv\[1\]/dout\[31:0\]" \ + "/TB/U_da4008_chip_top/digital_top/slv\[1\]/rden" \ + "/TB/U_da4008_chip_top/digital_top/slv\[1\]/wren" \ + "/TB/U_da4008_chip_top/digital_top/slv\[1\]/wben\[3:0\]" +wvSetPosition -win $_nWave2 {("G2/slv[3:0]/slv[1](sram_if)" 0)} +wvSetPosition -win $_nWave2 {("G2/slv[3:0]/slv[1](sram_if)" 7)} +wvSetPosition -win $_nWave2 {("G2/slv[3:0]" 0)} +wvAddSubGroup -win $_nWave2 -holdpost {slv[0](sram_if)} +wvSetPosition -win $_nWave2 {("G2/slv[3:0]" 0)} +wvSetPosition -win $_nWave2 {("G2/slv[3:0]/slv[0](sram_if)" 0)} +wvAddSignal -win $_nWave2 "/TB/U_da4008_chip_top/digital_top/slv\[0\]/clk" \ + "/TB/U_da4008_chip_top/digital_top/slv\[0\]/addr\[19:0\]" \ + "/TB/U_da4008_chip_top/digital_top/slv\[0\]/din\[31:0\]" \ + "/TB/U_da4008_chip_top/digital_top/slv\[0\]/dout\[31:0\]" \ + "/TB/U_da4008_chip_top/digital_top/slv\[0\]/rden" \ + "/TB/U_da4008_chip_top/digital_top/slv\[0\]/wren" \ + "/TB/U_da4008_chip_top/digital_top/slv\[0\]/wben\[3:0\]" +wvSetPosition -win $_nWave2 {("G2/slv[3:0]/slv[0](sram_if)" 0)} +wvSetPosition -win $_nWave2 {("G2/slv[3:0]/slv[0](sram_if)" 7)} +wvSetPosition -win $_nWave2 {("G2/slv[3:0]" 0)} +wvSetPosition -win $_nWave2 {("G2" 2)} +wvSetPosition -win $_nWave2 {("G2" 2)} +wvSetPosition -win $_nWave2 {("G2/mst(sram_if)" 0)} +wvAddSubGroup -win $_nWave2 -holdpost {mst(sram_if)} +wvAddSignal -win $_nWave2 "/TB/U_da4008_chip_top/digital_top/mst/clk" \ + "/TB/U_da4008_chip_top/digital_top/mst/addr\[24:0\]" \ + "/TB/U_da4008_chip_top/digital_top/mst/din\[31:0\]" \ + "/TB/U_da4008_chip_top/digital_top/mst/dout\[31:0\]" \ + "/TB/U_da4008_chip_top/digital_top/mst/rden" \ + "/TB/U_da4008_chip_top/digital_top/mst/wren" \ + "/TB/U_da4008_chip_top/digital_top/mst/wben\[3:0\]" +wvSetPosition -win $_nWave2 {("G2/mst(sram_if)" 0)} +wvSetPosition -win $_nWave2 {("G2/mst(sram_if)" 7)} +wvSetPosition -win $_nWave2 {("G2" 2)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollUp -win $_nWave2 34 +wvSetPosition -win $_nWave2 {("G2" 0)} +wvCollapseGroup -win $_nWave2 "G2" +wvSelectGroup -win $_nWave2 {G2} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G3" 0)} +wvSetPosition -win $_nWave2 {("G1" 2)} +wvSelectGroup -win $_nWave2 {G1} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G3" 0)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wave_data_out" -line 52 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wave_data_valid" -line 53 -pos 1 -win $_nTrace1 +srcHBSelect "TB.spi_bus" -win $_nTrace1 +srcHBSelect "TB.clk_inst" -win $_nTrace1 +srcHBSelect "TB.clk_40g_inst" -win $_nTrace1 +srcHBSelect "TB.U_da4008_chip_top" -win $_nTrace1 +srcHBSelect "TB.U_da4008_chip_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_da4008_chip_top" -delim "." +srcHBSelect "TB.U_da4008_chip_top" -win $_nTrace1 +srcHBSelect "TB.U_da4008_chip_top.U_DEM_PhaseSync_4008" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "LSB_OUT" -line 25 -pos 1 -win $_nTrace1 +srcSelect -signal "MSB_OUT" -line 24 -pos 1 -win $_nTrace1 +wvAddSignal -win $_nWave2 "/TB/U_da4008_chip_top/LSB_OUT\[63:0\]" \ + "/TB/U_da4008_chip_top/MSB_OUT\[63:0\]" +wvSetPosition -win $_nWave2 {("G3" 0)} +wvSetPosition -win $_nWave2 {("G3" 2)} +wvSetPosition -win $_nWave2 {("G3" 2)} +wvZoomOut -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G3" 1 2 )} +wvSetRadix -win $_nWave2 -format UDec +srcDeselectAll -win $_nTrace1 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G3" 2 )} +srcDeselectAll -win $_nTrace1 +srcSearchString "wave sram" -win $_nTrace1 -prev -case +srcSearchString "wave sram" -win $_nTrace1 -prev -case +srcSearchString "wave sram" -win $_nTrace1 -next -case +srcSearchString "wave sram" -win $_nTrace1 -next -case +srcSearchString "wave sram" -win $_nTrace1 -next -case +srcSearchString "wave sram" -win $_nTrace1 -next -case +srcHBSelect "TB.U_da4008_chip_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_da4008_chip_top" -delim "." +srcHBSelect "TB.U_da4008_chip_top" -win $_nTrace1 +srcSearchString "wave sram" -win $_nTrace1 -prev -case +srcSearchString "awg_top" -win $_nTrace1 -next -case +srcSearchString "awg_top" -win $_nTrace1 -prev -case +srcSearchString "awg_top" -win $_nTrace1 -next -case +srcSearchString "awg_top" -win $_nTrace1 -next -case +srcSearchString "awg_top" -win $_nTrace1 -next -case +srcSearchString "awg_top" -win $_nTrace1 -next -case +srcSearchString "awg" -win $_nTrace1 -next -case +srcSearchString "awg" -win $_nTrace1 -prev -case +srcSearchString "awg" -win $_nTrace1 -prev -case +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PI_mosi" -line 8 -pos 1 -win $_nTrace1 +srcHBSelect "TB.U_da4008_chip_top.digital_top" -win $_nTrace1 +srcHBSelect "TB.U_da4008_chip_top.DEM_VLD_dffr" -win $_nTrace1 +srcHBSelect "TB.U_da4008_chip_top.U_DEM_PhaseSync_4008" -win $_nTrace1 +srcHBSelect "TB.U_da4008_chip_top.U_iopad" -win $_nTrace1 +srcHBSelect "TB.U_da4008_chip_top.digital_top" -win $_nTrace1 +srcHBSelect "TB.U_da4008_chip_top.digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_da4008_chip_top.digital_top" -delim "." +srcHBSelect "TB.U_da4008_chip_top.digital_top" -win $_nTrace1 +srcSearchString "awg_top" -win $_nTrace1 -next -case +srcSearchString "awg_top" -win $_nTrace1 -next -case +srcSearchString "awg_top" -win $_nTrace1 -prev -case +srcSelect -win $_nTrace1 -range {381 381 1 1 4 11} +srcSearchString "awg_top" -win $_nTrace1 -prev -case +srcSelect -win $_nTrace1 -range {388 388 3 4 3 1} +nsMsgSwitchTab -tab general +srcSearchString "awg_top" -win $_nTrace1 -prev -case +srcSelect -win $_nTrace1 -range {388 388 1 2 1 1} +srcSearchString "awg_top" -win $_nTrace1 -prev -case +srcSelect -win $_nTrace1 -range {381 381 1 1 4 11} +srcSearchString "awg_top" -win $_nTrace1 -prev -case +srcSelect -win $_nTrace1 -range {388 388 3 4 3 1} +srcSearchString "awg_top" -win $_nTrace1 -prev -case +srcSelect -win $_nTrace1 -range {388 388 1 2 1 1} +srcSearchString "awg_top" -win $_nTrace1 -prev -case +srcSelect -win $_nTrace1 -range {381 381 1 1 4 11} +srcSearchString "awg_top" -win $_nTrace1 -prev -case +srcSelect -win $_nTrace1 -range {388 388 3 4 3 1} +srcSearchString "awg_top" -win $_nTrace1 -prev -case +srcSelect -win $_nTrace1 -range {388 388 1 2 1 1} +srcSearchString "awg_top" -win $_nTrace1 -prev -case +srcSelect -win $_nTrace1 -range {381 381 1 1 4 11} +wvSelectGroup -win $_nWave2 {G3} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G2" 0)} +wvSelectGroup -win $_nWave2 {G2} +wvSelectGroup -win $_nWave2 {G2} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "awg_busy" -line 411 -pos 1 -win $_nTrace1 +srcSelect -win $_nTrace1 -range {389 411 7 8 2 5} -backward +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_pulse" -line 391 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk" -line 389 -pos 2 -win $_nTrace1 +srcSelect -signal "ch0_rstn_o" -line 390 -pos 1 -win $_nTrace1 +srcSelect -signal "sync_pulse" -line 391 -pos 1 -win $_nTrace1 +srcSelect -signal "wave_awrdata" -line 392 -pos 2 -win $_nTrace1 +srcSelect -signal "wave_awren" -line 393 -pos 2 -win $_nTrace1 +srcSelect -signal "wave_arwaddr" -line 394 -pos 2 -win $_nTrace1 +srcSelect -signal "wave_awrmask" -line 395 -pos 2 -win $_nTrace1 +srcSelect -win $_nTrace1 -signal "slv\[2\].din" -line 396 -pos 1 +srcSelect -win $_nTrace1 -signal "slv\[2\].wren" -line 397 -pos 1 +srcSelect -win $_nTrace1 -signal "slv\[2\].addr\[18:0\]" -line 398 -pos 1 +srcSelect -win $_nTrace1 -signal "slv\[2\].rden" -line 399 -pos 1 +srcSelect -win $_nTrace1 -signal "slv\[2\].dout" -line 400 -pos 1 +srcSelect -win $_nTrace1 -signal "slv\[1\].din" -line 401 -pos 1 +srcSelect -win $_nTrace1 -signal "slv\[1\].wren" -line 402 -pos 1 +srcSelect -win $_nTrace1 -signal "slv\[1\].wren" -line 402 -pos 1 +srcSelect -win $_nTrace1 -signal "slv\[1\].addr\[7 :0\]" -line 403 -pos 1 +srcSelect -win $_nTrace1 -signal "slv\[1\].wren" -line 402 -pos 1 +srcSelect -win $_nTrace1 -signal "slv\[1\].rden" -line 404 -pos 1 +srcSelect -win $_nTrace1 -signal "slv\[1\].dout" -line 405 -pos 1 +srcSelect -signal "wave_data_out_bank" -line 406 -pos 1 -win $_nTrace1 +srcSelect -signal "awg_data_valid" -line 407 -pos 1 -win $_nTrace1 +srcSelect -signal "cmd_fifo_empty" -line 408 -pos 2 -win $_nTrace1 +srcSelect -signal "cmd_fifo_full" -line 409 -pos 2 -win $_nTrace1 +srcSelect -signal "awg_status" -line 410 -pos 1 -win $_nTrace1 +srcSelect -signal "awg_busy" -line 411 -pos 1 -win $_nTrace1 +wvAddSignal -win $_nWave2 "/TB/U_da4008_chip_top/digital_top/clk" \ + "/TB/U_da4008_chip_top/digital_top/ch0_rstn_o" \ + "/TB/U_da4008_chip_top/digital_top/sync_pulse" \ + "/TB/U_da4008_chip_top/digital_top/wave_awrdata\[511:0\]" \ + "/TB/U_da4008_chip_top/digital_top/wave_awren\[0:0\]" \ + "/TB/U_da4008_chip_top/digital_top/wave_arwaddr\[12:0\]" \ + "/TB/U_da4008_chip_top/digital_top/wave_awrmask\[63:0\]" \ + "/TB/U_da4008_chip_top/digital_top/slv\[2\]/din\[31:0\]" \ + "/TB/U_da4008_chip_top/digital_top/slv\[2\]/wren" \ + "/TB/U_da4008_chip_top/digital_top/slv\[2\]/addr\[18:0\]" \ + "/TB/U_da4008_chip_top/digital_top/slv\[2\]/rden" \ + "/TB/U_da4008_chip_top/digital_top/slv\[2\]/dout\[31:0\]" \ + "/TB/U_da4008_chip_top/digital_top/slv\[1\]/din\[31:0\]" \ + "/TB/U_da4008_chip_top/digital_top/slv\[1\]/addr\[7:0\]" \ + "/TB/U_da4008_chip_top/digital_top/slv\[1\]/wren" \ + "/TB/U_da4008_chip_top/digital_top/slv\[1\]/rden" \ + "/TB/U_da4008_chip_top/digital_top/slv\[1\]/dout\[31:0\]" \ + "/TB/U_da4008_chip_top/digital_top/wave_data_out_bank\[511:0\]" \ + "/TB/U_da4008_chip_top/digital_top/awg_data_valid" \ + "/TB/U_da4008_chip_top/digital_top/cmd_fifo_empty" \ + "/TB/U_da4008_chip_top/digital_top/cmd_fifo_full" \ + "/TB/U_da4008_chip_top/digital_top/awg_status\[2:0\]" \ + "/TB/U_da4008_chip_top/digital_top/awg_busy" +wvSetPosition -win $_nWave2 {("G2" 0)} +wvSetPosition -win $_nWave2 {("G2" 23)} +wvSetPosition -win $_nWave2 {("G2" 23)} +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvSetCursor -win $_nWave2 135609782.382826 -snap {("G2" 22)} +wvSelectSignal -win $_nWave2 {( "G2" 21 )} +wvSelectSignal -win $_nWave2 {( "G2" 22 )} +wvSelectSignal -win $_nWave2 {( "G2" 20 )} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G2" 8 )} +wvSelectSignal -win $_nWave2 {( "G2" 7 )} +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvSelectSignal -win $_nWave2 {( "G2" 12 )} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +debExit diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/verdi_perf_err.log b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdiLog/verdi_perf_err.log new file mode 100644 index 0000000..e69de29 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdplus.log b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdplus.log new file mode 100644 index 0000000..8e7c22f --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdplus.log @@ -0,0 +1,2 @@ +File Name Time +./verdplus_000.fsdb 0 to 479,076,480 diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdplus.vf b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdplus.vf new file mode 100644 index 0000000..1ef6a51 --- /dev/null +++ b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdplus.vf @@ -0,0 +1,7 @@ +@FSDB rc file Version 1.0 +[VRTL_FILE_HEADER] +# !! DON'T EDIT [VRTL_FILE_HEADER] SESSION !! +Version = 1 +[VRTL_FILE_SOURCE] +FileType = switch +File1 = ./verdplus_000.fsdb diff --git a/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdplus_000.fsdb b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdplus_000.fsdb new file mode 100644 index 0000000..d8a5882 Binary files /dev/null and b/DA4008_V1.2/sim/chip_top/work_RTL/sine_1g/verdplus_000.fsdb differ diff --git a/wave/flattop/flattop.txt b/wave/flattop/flattop.txt new file mode 100644 index 0000000..59e3d23 --- /dev/null +++ b/wave/flattop/flattop.txt @@ -0,0 +1,71 @@ +00100000 +0000000c +04000002 +800003e8 +04004002 +00200000 +00000100 +04030100 +0b090706 +110f0e0c +17161412 +1d1c1a19 +2422211f +2a282725 +302f2d2c +37353332 +3d3b3a38 +4342403e +4a484645 +504e4d4b +56555351 +5c5b5958 +6361605e +69676664 +6f6e6c6b +76747271 +7c7a7977 +82817f7d +89878584 +8f8d8c8a +95949290 +9b9a9897 +a2a09f9d +a8a6a5a3 +aeadabaa +b5b3b1b0 +bbb9b8b6 +c1c0bebc +c8c6c4c3 +c3c4c6c8 +bcbec0c1 +b6b8b9bb +b0b1b3b5 +aaabadae +a3a5a6a8 +9d9fa0a2 +97989a9b +90929495 +8a8c8d8f +84858789 +7d7f8182 +77797a7c +71727476 +6b6c6e6f +64666769 +5e606163 +58595b5c +51535556 +4b4d4e50 +4546484a +3e404243 +383a3b3d +32333537 +2c2d2f30 +2527282a +1f212224 +191a1c1d +12141617 +0c0e0f11 +0607090b +00010304 diff --git a/wave/flattop/flattop_lvds.txt b/wave/flattop/flattop_lvds.txt new file mode 100644 index 0000000..36a09c2 --- /dev/null +++ b/wave/flattop/flattop_lvds.txt @@ -0,0 +1,67 @@ +bcbcbcbc +30000040 +04030100 +0b090706 +110f0e0c +17161412 +1d1c1a19 +2422211f +2a282725 +302f2d2c +37353332 +3d3b3a38 +4342403e +4a484645 +504e4d4b +56555351 +5c5b5958 +6361605e +69676664 +6f6e6c6b +76747271 +7c7a7977 +82817f7d +89878584 +8f8d8c8a +95949290 +9b9a9897 +a2a09f9d +a8a6a5a3 +aeadabaa +b5b3b1b0 +bbb9b8b6 +c1c0bebc +c8c6c4c3 +c3c4c6c8 +bcbec0c1 +b6b8b9bb +b0b1b3b5 +aaabadae +a3a5a6a8 +9d9fa0a2 +97989a9b +90929495 +8a8c8d8f +84858789 +7d7f8182 +77797a7c +71727476 +6b6c6e6f +64666769 +5e606163 +58595b5c +51535556 +4b4d4e50 +4546484a +3e404243 +383a3b3d +32333537 +2c2d2f30 +2527282a +1f212224 +191a1c1d +12141617 +0c0e0f11 +0607090b +00010304 +b92107cf diff --git a/wave/gen_flattop.csh b/wave/gen_flattop.csh new file mode 100755 index 0000000..9e715cc --- /dev/null +++ b/wave/gen_flattop.csh @@ -0,0 +1,16 @@ + +set echo +set -e + + +python ../da4008_gen_transaction.py \ + --type flattop \ + --start_addr 0 \ + --rise_samples 128 \ + --hold_cycles 1000 \ + --fall_samples 128 \ + --hold_value 200 \ + --lvds_addr 0x3000 \ + --output ./flattop/flattop.txt + +