62 lines
3.9 KiB
Plaintext
62 lines
3.9 KiB
Plaintext
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[dprof-info] generating timeline profile dprof.dir/timeline.txt
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Chronologic VCS simulator copyright 1991-2018
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Contains Synopsys proprietary information.
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Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64; Mar 13 18:07 2026
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*Verdi* Loading libsscore_vcs201809.so
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FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
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(C) 1996 - 2019 by Synopsys, Inc.
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*Verdi* FSDB: The switch FSDB file size might not match the input size (500MB) because of performance concerns.
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*Verdi* FSDB: To have the FSDB file size match the input size (500MB), set the FSDB_ENV_PRECISE_AUTOSWITCH environment, though the dumping performance might decrease.
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*Verdi* : Enable automatic switching of the FSDB file.
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*Verdi* : (Filename='./verdplus', Limit Size=500MB, File Amount=1000000).
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*Verdi* : Create FSDB file './verdplus_000.fsdb'
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*Verdi* : Create the file './verdplus.log' to log the time range of each FSDB file.
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*Verdi* : Create virtual FSDB file './verdplus.vf' to log each FSDB file.
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*Verdi* : Begin traversing the scopes, layer (0).
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*Verdi* : End of traversing.
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*Verdi* : Begin traversing the MDAs, layer (0).
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*Verdi* : Enable +mda and +packedmda dumping.
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*Verdi* : End of traversing the MDAs.
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========================================
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Testbench started at 0
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========================================
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Phase 1: Training with correct patterns...
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Link ready at 104675000
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Phase 2: Sending a correct frame...
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WRITE: addr=291 data=a000000aa0000009a0000008a0000007a0000006a0000005a0000004a0000003a0000002a0000001a00000000000000000000000000000000000000000000000 mask=fffffffffff00000
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Write detected: addr=292 data=a000000aa0000009a0000008a0000007a0000006a0000005a0000004a0000013a0000012a0000011a0000010a000000fa000000ea000000da000000ca000000b mask=0000000fffffffff
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Error: "../../sim/lvds/TB.sv", 311: TB: at time 106695200 ps
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Unexpected write address: 292
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Error: "../../sim/lvds/TB.sv", 312: TB: at time 106695200 ps
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Byte mask mismatch: 0000000fffffffff
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Error: "../../sim/lvds/TB.sv", 313: TB: at time 106695200 ps
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Byte mask high part not zero: 0000000f
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Correct frame write verified.
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WRITE: addr=292 data=a000000aa0000009a0000008a0000007a0000006a0000005a0000004a0000013a0000012a0000011a0000010a000000fa000000ea000000da000000ca000000b mask=0000000fffffffff
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Phase 3: Sending a frame with bad CRC...
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WRITE: addr=291 data=a000000aa0000009a0000008a0000007a0000006a0000005a0000004a0000003a0000002a0000001a0000000a000000fa000000ea000000da000000ca000000b mask=fffffffffff00000
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CRC error detected at 109615000
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WRITE: addr=292 data=a000000aa0000009a0000008a0000007a0000006a0000005a0000004a0000013a0000012a0000011a0000010a000000fa000000ea000000da000000ca000000b mask=0000000fffffffff
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CRC_ERROR pulse at 109625000
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Link down as expected.
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Phase 4: Re-training...
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Link ready again.
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WRITE: addr=291 data=a000000aa0000009a0000008a0000007a0000006a0000005a0000004a0000003a0000002a0000001a0000000a000000fa000000ea000000da000000ca000000b mask=fffffffffff00000
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WRITE: addr=292 data=a000000aa0000009a0000008a0000007a0000006a0000005a0000004a0000013a0000012a0000011a0000010a000000fa000000ea000000da000000ca000000b mask=0000000fffffffff
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Phase 5: Testing delay_tap adjustment...
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Final delay_tap = 3
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Phase 6: Testing with descrambler enabled (header not scrambled)...
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Link ready for scrambled data.
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WRITE: addr=291 data=a000000aa0000009b0000009b0000008b0000007b0000006b0000005b0000004b0000003b0000002b0000001b0000000a000000ea000000da000000ca000000b mask=00ffffffffff0000
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Scrambled test passed (no CRC error).
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========================================
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Testbench finished at 127115000
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========================================
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$finish called from file "../../sim/lvds/TB.sv", line 463.
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$finish at simulation time 127115000
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[dprof-info] generating dprof summary report in dprof.txt
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V C S S i m u l a t i o n R e p o r t
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Time: 127115000 ps
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CPU Time: 0.340 seconds; Data structure size: 0.1Mb
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Fri Mar 13 18:07:28 2026
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