213 lines
11 KiB
Systemverilog
213 lines
11 KiB
Systemverilog
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`include "../define/chip_define.v"
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module da4008_chip_top (
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//spi port
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input PI_sclk // Spi Clock
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,input PI_csn // Spi Chip Select active low
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,input PI_mosi // Spi Mosi
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,output PO_miso // Spi Miso
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//irq
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,output PO_irq
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//system port
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,input PI_async_rstn
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,input PI_sync_in
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,output PO_sync_out
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,input clk
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//lvds rx
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,input [3 :0] lvds_data
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,input [0 :0] lvds_valid
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,input [0 :0] lvds_clk
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,output [2 :0] phase_tap
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//DAC Data
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,output [6 :0] MSB_OUT [63:0]
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,output [4 :0] LSB_OUT [63:0]
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,output MSB_DUM [63:0]
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,output DEM_VLD
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//DAC Cfg Port
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,output [3 :0] Rterm
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,output [2 :0] CasAddr
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,output [2 :0] CasDw
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,output [9 :0] IMainCtrl
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,output [3 :0] IBleedCtrl
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,output [3 :0] ICkCml
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,output [31 :0] CurRsv0
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,output [31 :0] CurRsv1
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//CLK Cfg Port
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,output [0 :0] CcalRstn
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,output [3 :0] EnAllP
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,output [0 :0] DccEn
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,output [0 :0] CasGateCkCtrl
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,output [0 :0] SpiEnPi
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,output [0 :0] SpiEnQec
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,output [0 :0] SpiEnDcc
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,output [4 :0] SpiQecCtrlIp
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,output [4 :0] SpiQecCtrlIn
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,output [4 :0] SpiQecCtrlQp
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,output [4 :0] SpiQecCtrlQn
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,output [5 :0] SpiDccCtrlIup
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,output [5 :0] SpiDccCtrlIdn
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,output [5 :0] SpiDccCtrlQup
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,output [5 :0] SpiDccCtrlQdn
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,output [7 :0] SpiSiqNOut
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,output [7 :0] SpiSiqPOut
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,output [3 :0] SpiSiPOut
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,output [3 :0] SpiSqPOut
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,output [2 :0] CrtlCrossOverN
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,output [2 :0] CrtlCrossOverP
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,output [31 :0] CcalRsv0
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,output [31 :0] CcalRsv1
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,output [3 :0] SelCk10GDig
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,output [3 :0] SelCk2p5GDig
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,output [8 :0] SelCk625MDig
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,output [15 :0] P2sDataEn
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,output [15 :0] P2sEnAllP
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,output [15 :0] EnPiP
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,output [15 :0] CkDivRstn
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,output [31 :0] p2srsv0
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,output [31 :0] p2srsv1
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,output [15 :0] CkRxSw
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,output [15 :0] RstnCk
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,output [15 :0] CtrlZin
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);
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//------------------------------iopad instantiation start--------------------------------------
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// iopad
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//---------------------------------------------------------------------------------------------
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wire async_rstn ;
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wire sync_in ;
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wire sync_out ;
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wire sclk ;
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wire csn ;
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wire mosi ;
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wire miso ;
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wire oen ;
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wire irq ;
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iopad U_iopad (
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//+++++++++++++++++++++++++++++++++++++++++++++//
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// PAD Strat //
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//+++++++++++++++++++++++++++++++++++++++++++++//
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.PI_async_rstn ( PI_async_rstn )
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,.PI_sync_in ( PI_sync_in )
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,.PO_sync_out ( PO_sync_out )
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,.PI_sclk ( PI_sclk )
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,.PI_csn ( PI_csn )
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,.PI_mosi ( PI_mosi )
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,.PO_miso ( PO_miso )
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,.PO_irq ( PO_irq )
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//+++++++++++++++++++++++++++++++++++++++++++++//
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// PAD End //
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//+++++++++++++++++++++++++++++++++++++++++++++//
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//+++++++++++++++++++++++++++++++++++++++++++++//
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// Internal signal Start //
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//+++++++++++++++++++++++++++++++++++++++++++++//
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,.async_rstn ( async_rstn )
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,.sync_in ( sync_in )
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,.sync_out ( sync_out )
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,.sclk ( sclk )
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,.csn ( csn )
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,.mosi ( mosi )
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,.miso ( miso )
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,.oen ( oen )
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,.irq_n ( ~irq )
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);
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//------------------------------spi_slave instantiation start----------------------------------
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// spi_slave
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//---------------------------------------------------------------------------------------------
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wire [7 :0] wave_data_out [63:0] ;
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wire wave_data_valid ;
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wire [14 :0] Set [63:0] ;
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wire PrbsEn ;
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digital_top digital_top (
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.clk ( clk )
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,.rst_n ( async_rstn )
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,.sync_in ( sync_in )
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,.sync_out ( sync_out )
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,.cfgid ( 5'b00000 )
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,.sclk ( sclk )
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,.csn ( csn )
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,.mosi ( mosi )
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,.miso ( miso )
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,.oen ( oen )
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,.irq ( irq )
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,.wave_data_out ( wave_data_out )
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,.wave_data_valid ( wave_data_valid )
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,.lvds_data ( lvds_data )
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,.lvds_valid ( lvds_valid )
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,.lvds_clk ( lvds_clk )
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,.phase_tap ( phase_tap )
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,.Rterm ( Rterm )
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,.PrbsEn ( PrbsEn )
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,.Set ( Set )
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,.CasAddr ( CasAddr )
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,.CasDw ( CasDw )
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,.IMainCtrl ( IMainCtrl )
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,.IBleedCtrl ( IBleedCtrl )
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,.ICkCml ( ICkCml )
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,.CurRsv0 ( CurRsv0 )
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,.CurRsv1 ( CurRsv1 )
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,.CcalRstn ( CcalRstn )
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,.EnAllP ( EnAllP )
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,.DccEn ( DccEn )
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,.CasGateCkCtrl ( CasGateCkCtrl )
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,.SpiEnPi ( SpiEnPi )
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,.SpiEnQec ( SpiEnQec )
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,.SpiEnDcc ( SpiEnDcc )
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,.SpiQecCtrlIp ( SpiQecCtrlIp )
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,.SpiQecCtrlIn ( SpiQecCtrlIn )
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,.SpiQecCtrlQp ( SpiQecCtrlQp )
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,.SpiQecCtrlQn ( SpiQecCtrlQn )
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,.SpiDccCtrlIup ( SpiDccCtrlIup )
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,.SpiDccCtrlIdn ( SpiDccCtrlIdn )
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,.SpiDccCtrlQup ( SpiDccCtrlQup )
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,.SpiDccCtrlQdn ( SpiDccCtrlQdn )
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,.SpiSiqNOut ( SpiSiqNOut )
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,.SpiSiqPOut ( SpiSiqPOut )
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,.SpiSiPOut ( SpiSiPOut )
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,.SpiSqPOut ( SpiSqPOut )
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,.CrtlCrossOverN ( CrtlCrossOverN )
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,.CrtlCrossOverP ( CrtlCrossOverP )
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,.CcalRsv0 ( CcalRsv0 )
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,.CcalRsv1 ( CcalRsv1 )
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,.SelCk10GDig ( SelCk10GDig )
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,.SelCk2p5GDig ( SelCk2p5GDig )
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,.SelCk625MDig ( SelCk625MDig )
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,.P2sDataEn ( P2sDataEn )
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,.P2sEnAllP ( P2sEnAllP )
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,.EnPiP ( EnPiP )
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,.CkDivRstn ( CkDivRstn )
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,.p2srsv0 ( p2srsv0 )
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,.p2srsv1 ( p2srsv1 )
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,.CkRxSw ( CkRxSw )
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,.RstnCk ( RstnCk )
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,.CtrlZin ( CtrlZin )
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);
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//------------------------------spi_slave instantiation start----------------------------------
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// DEM
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//---------------------------------------------------------------------------------------------
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sirv_gnrl_dffr #(1) DEM_VLD_dffr (wave_data_valid, DEM_VLD, clk, async_rstn);
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DEM_PhaseSync_4008 U_DEM_PhaseSync_4008 (
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.clk ( clk )
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,.prbs_en ( PrbsEn )
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,.RST_N ( async_rstn )
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,.dem_set ( Set )
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,.data_in ( wave_data_out )
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,.MSB_OUT ( MSB_OUT )
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,.LSB_OUT ( LSB_OUT )
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,.MSB_DUM ( MSB_DUM )
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);
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endmodule
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`include "../define/chip_undefine.v"
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