102 lines
2.4 KiB
Coq
102 lines
2.4 KiB
Coq
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//`define FPGA_XIL
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//`define SMIC_IC
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`define BEHAVIOUR_SIM
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module spram #(
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parameter width =16,
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parameter depth =1024
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)(
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clka,
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ena,
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dina,
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addra,
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clkb,
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enb,
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doutb,
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addrb
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);
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///////////////////////////////////////////////////////
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//Function
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///////////////////////////////////////////////////////
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function integer clog2(input integer depth);
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begin
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for(clog2=0;depth>0;clog2=clog2+1)
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depth =depth>>1;
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end
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endfunction
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localparam aw = clog2(depth-1);
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///////////////////////////////////////////////////////
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//Input declaration
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///////////////////////////////////////////////////////
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input clka;
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input ena;
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input [width-1:0] dina;
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input [aw-1:0] addra;
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input clkb;
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input enb;
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output [width-1:0] doutb;
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input [aw-1:0] addrb;
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///////////////////////////////////////////////////////
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//SRAM
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///////////////////////////////////////////////////////
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`ifdef BEHAVIOUR_SIM
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bhv_spram #(
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.width (width ),
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.depth (depth )
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)bhv_spram(
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.clka (clka ),
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.ena (ena ),
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.dina (dina ),
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.addra (addra ),
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.clkb (clkb ),
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.enb (enb ),
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.doutb (doutb ),
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.addrb (addrb )
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);
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`elsif XINLINX_FPGA
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xil_spram #(
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.dw (width ),
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.depth (depth )
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)xil_spram(
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.wrclk (clka ),
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.wren (ena ),
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.wrdata (dina ),
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.wraddr (addra ),
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.rdclk (clkb ),
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.rden (enb ),
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.rddata (doutb ),
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.rdaddr (addrb )
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);
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`elsif SMIC_IC
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smic_spram #(
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.width (width),
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.depth (depth)
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)smic_spram(
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.CLKB (clka ),
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.CENB (ena ),
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.AB (addra ),
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.DB (dina ),
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.CLKA (clkb ),
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.CENA (enb ),
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.AA (addrb ),
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.QA (doutb )
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);
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`endif
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endmodule
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//`undef FPGA_XIL
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