54 lines
1.6 KiB
Systemverilog
54 lines
1.6 KiB
Systemverilog
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module pulse_generator #(
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parameter DATA_WIDTH = 16
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)(
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input logic clk,
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input logic rst_n,
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input logic pulse_en,
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input logic [DATA_WIDTH-1:0] delay,
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input logic [DATA_WIDTH-1:0] width,
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input logic inv_en,
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output logic pulse
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);
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logic [DATA_WIDTH-1:0] counter; // 用于延迟和宽度计数
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logic pulse_delay_done;
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logic pulse_width_done;
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assign pulse_delay_done = (counter == delay);
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assign pulse_width_done = (counter == width);
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localparam SM_IDLE = 0;
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localparam SM_WAIT = 1;
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localparam SM_WORK = 2;
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logic [1:0] current_state;
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always @(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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current_state <= SM_IDLE;
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end else begin
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case(current_state)
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SM_IDLE: current_state <= pulse_en ? SM_WAIT : SM_IDLE;
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SM_WAIT: current_state <= pulse_delay_done ? SM_WORK : SM_WAIT;
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SM_WORK: current_state <= pulse_width_done ? SM_IDLE : SM_WORK;
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endcase
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end
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end
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always @(posedge clk) begin
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case(current_state)
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SM_IDLE: counter <= 1;
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SM_WAIT: counter <= pulse_delay_done ? 1 : (counter + 1);
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SM_WORK: counter <= pulse_width_done ? 1 : (counter + 1);
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endcase
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end
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always @(posedge clk) begin
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case(current_state)
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SM_IDLE: pulse <= inv_en;
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SM_WAIT: pulse <= pulse_delay_done ? ~inv_en : inv_en;
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SM_WORK: pulse <= pulse_width_done ? inv_en : ~inv_en;
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endcase
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end
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endmodule
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