181 lines
9.2 KiB
Systemverilog
181 lines
9.2 KiB
Systemverilog
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//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : awg_top.v
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// Department :
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// Author : hdzhang
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2026-03-01 hdzhang awg-top
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module awg_top (
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//system port
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input clk // System Main Clock
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,input rst_n // Spi Reset active low
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,input start
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//----------------------------from spi-----------------------------------------------------------
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//Wave storage read/write signal
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//A-port
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,input [511:0] wave_awrdata
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,input [0 :0] wave_awren
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,input [12 :0] wave_arwaddr
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,input [63 :0] wave_awrmask
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//B-port
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,input [31 :0] wave_bwrdata
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,input [0 :0] wave_bwren
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,input [18 :0] wave_brwaddr
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,input [0 :0] wave_brden
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,output [31 :0] wave_brddata
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//cmd fifo read-write signal
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,input [31 :0] cmd_fifo_bwrdata
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,input [0 :0] cmd_fifo_bwren
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,input [7 :0] cmd_fifo_brwaddr
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,input [0 :0] cmd_fifo_brden
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,output [31 :0] cmd_fifo_brddata
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//----------------------------to system regfile------------------------------------------------------
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//CMD FIFO Empty & Full
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,output cmd_fifo_empty
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,output cmd_fifo_full
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//AWG Ctrl Status
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,output [2 :0] status
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,output wave_busy
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//----------------------------to DEM----------------------------------------------------------------
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,output [511:0] wave_data_out
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,output wave_valid_out
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);
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wire start_r;
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sirv_gnrl_dffr #(1) start_dffr (start, start_r, clk, rst_n);
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wire start_posedge = start && ~start_r;
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wire sync_start;
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sirv_gnrl_dffr #(1) sync_start_dffr (start_posedge, sync_start, clk, rst_n);
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wire cmd_fifo_rd_en ;
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wire [31 :0] cmd_fifo_data ;
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//wire cmd_fifo_empty ;
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wire sram_rd_en ;
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wire [12 :0] sram_rd_addr ;
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wire [511:0] sram_rd_data ;
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awg_ctrl awg_ctrl_inst(
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.clk ( clk )
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,.rst_n ( rst_n )
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,.start ( sync_start )
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,.cmd_fifo_rd_en ( cmd_fifo_rd_en )
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,.cmd_fifo_data ( cmd_fifo_data )
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,.cmd_fifo_empty ( cmd_fifo_empty )
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,.sram_rd_en ( sram_rd_en )
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,.sram_rd_addr ( sram_rd_addr )
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,.sram_rd_data ( sram_rd_data )
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,.wave_data_out ( wave_data_out )
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,.wave_valid_out ( wave_valid_out )
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,.status ( status )
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,.wave_busy ( wave_busy )
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);
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//wire cmd_fifo_full ;
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wire cmd_fifo_almost_full ;
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wire cmd_fifo_almost_empty;
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wire cmd_fifo_prog_full ;
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wire cmd_fifo_prog_empty ;
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wire [5 :0] cmd_fifo_cnt ;
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syn_fwft_fifo #(.width(32), .depth(64), .prog_full_thre(32), .prog_empty_thre(16))
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cmd_fifo_inst(
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.clk ( clk )
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,.rst ( ~rst_n )
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,.clr ( 1'b0 )
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,.wr_en ( cmd_fifo_bwren )
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,.rd_en ( cmd_fifo_rd_en )
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,.din ( cmd_fifo_bwrdata )
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,.dout ( cmd_fifo_data )
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,.full ( cmd_fifo_full )
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,.empty ( cmd_fifo_empty )
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,.almost_full ( cmd_fifo_almost_full )
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,.almost_empty ( cmd_fifo_almost_empty )
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,.prog_full ( cmd_fifo_prog_full )
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,.prog_empty ( cmd_fifo_prog_empty )
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,.cnt ( cmd_fifo_cnt )
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);
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//------------------------------------------------------------------------------------------
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// wave sram
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//------------------------------------------------------------------------------------------
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sram_if #(19, 32) wave_sram_muxin (clk);
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sram_if #(19,512) wave_sram_muxout(clk);
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assign wave_sram_muxin.addr = wave_brwaddr[18:0] ;
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assign wave_sram_muxin.din = wave_bwrdata ;
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assign wave_sram_muxin.wben = 4'b1111 ;
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assign wave_sram_muxin.wren = wave_bwren ;
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assign wave_sram_muxin.rden = wave_brden ;
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assign wave_brddata = wave_sram_muxin.dout ;
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sram_dmux_w #(.ADDR_WIDTH(19), .DATA_WIDTH_I(32), .DATA_WIDTH_O(512))
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U_sram_dmux_w(
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.clk ( clk )
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,.rst_n ( rst_n )
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,.port_in ( wave_sram_muxin )
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,.port_out ( wave_sram_muxout )
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);
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//Wave Memory Clock
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wire [0 :0] Wave_PortClk = clk ;
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//The wave storage A port is connected to the internal AWG controller
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wire [18 :0] Wave_PortAAddr = wave_awren ? {wave_arwaddr[12:0],6'b0} : {sram_rd_addr[12:0],6'b0};
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wire [511 :0] Wave_PortADataIn = wave_awrdata ;
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wire [0 :0] Wave_PortAWriteEnable = ~wave_awren ;
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wire [0 :0] Wave_PortAChipEnable = ~wave_awren&~sram_rd_en ;
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wire [512/8-1:0] Wave_PortAByteWriteEnable = ~wave_awrmask ;
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wire [511 :0] Wave_PortADataOut ;
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assign sram_rd_data = Wave_PortADataOut ;
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//The B port of the wave storage connects to an external SPI bus decode
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wire [18 :0] Wave_PortBAddr = wave_sram_muxout.addr[18:0] ;
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wire [511 :0] Wave_PortBDataIn = wave_sram_muxout.din ;
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wire [0 :0] Wave_PortBWriteEnable = ~wave_sram_muxout.wren & wave_sram_muxout.rden ;
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wire [0 :0] Wave_PortBChipEnable = ~(wave_sram_muxout.wren | wave_sram_muxout.rden) ;
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wire [512/8-1:0] Wave_PortBByteWriteEnable = ~wave_sram_muxout.wben ;
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wire [511 :0] Wave_PortBDataOut ;
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assign wave_sram_muxout.dout = Wave_PortBDataOut ;
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dpram #(.DATAWIDTH(512), .ADDRWIDTH(19)) wave_dpram(
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.PortClk ( Wave_PortClk )
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,.PortAAddr ( Wave_PortAAddr )
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,.PortADataIn ( Wave_PortADataIn )
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,.PortAWriteEnable ( Wave_PortAWriteEnable )
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,.PortAChipEnable ( Wave_PortAChipEnable )
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,.PortAByteWriteEnable ( Wave_PortAByteWriteEnable )
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,.PortADataOut ( Wave_PortADataOut )
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,.PortBAddr ( Wave_PortBAddr )
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,.PortBDataIn ( Wave_PortBDataIn )
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,.PortBWriteEnable ( Wave_PortBWriteEnable )
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,.PortBChipEnable ( Wave_PortBChipEnable )
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,.PortBByteWriteEnable ( Wave_PortBByteWriteEnable )
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,.PortBDataOut ( Wave_PortBDataOut )
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);
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endmodule
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