22 lines
849 B
Tcl
22 lines
849 B
Tcl
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set ports_clock_root [get_ports [all_fanout -flat -clock_tree -level 0]]
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set input [remove_from_collection [all_inputs] $ports_clock_root]
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set design_signals [remove_from_collection $input [get_ports test* -quiet]]
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set mems [all_macro_cells]
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set regs [remove_from_collection [all_registers] mems]
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group_path -default
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group_path -name R2R -from $regs -to $regs
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group_path -name R2M -from $regs -to $mems
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group_path -name M2R -from $mems -to $regs
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group_path -name M2M -from $mems -to $mems
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group_path -name I2R -from $design_signals -to $regs
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group_path -name I2M -from $design_signals -to $mems
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group_path -name R2O -from $regs -to [all_outputs]
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group_path -name M2O -from $mems -to [all_outputs]
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group_path -name INOUT -from $design_signals -to [all_outputs]
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group_path -name GATING -from [all_registers] -to [get_pins -hier */E]
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