2026-03-14 17:51:22 +08:00
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`include "../../rtl/define/chip_define.v"
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`include "../../model/SPI_DRIVER.sv"
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`include "../../model/LVDS_DRIVER.sv"
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`timescale 1ns/1ps
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module TB ();
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//###################################
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// Generate Clocks & Reset
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//###################################
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//Generate Clock
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localparam PERIOD = 1.536;
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logic clk ;
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//clk
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clock_tb #(
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.PERIOD ( PERIOD )
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,.PHASE ( 0 )
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)clk_inst (
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.clk_out ( clk )
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);
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//clk_40g
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logic clk_40g;
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clock_tb #(
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.PERIOD ( 0.024)
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,.PHASE ( 0 )
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)clk_40g_inst (
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.clk_out ( clk_40g )
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);
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//Generate Reset
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logic rst_n;
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int file_path;
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string CONFIG_FILE = "";
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string DATA_O_FILE = "";
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parameter string CASE_TEMP = "../../case_temp.txt";
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parameter string DATA_TEMP = "../../data_temp.txt";
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parameter string LVDS_FILE = "../../../../case/lvds/0305/lvds.txt";
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initial begin
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file_path = $fopen(CASE_TEMP, "r");
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if(file_path != 0) begin
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$fscanf(file_path, "%s", CONFIG_FILE);
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$display(CONFIG_FILE);
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$fclose(file_path);
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end
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file_path = $fopen(DATA_TEMP, "r");
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if(file_path != 0) begin
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$fscanf(file_path, "%s", DATA_O_FILE);
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$display(DATA_O_FILE);
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$fclose(file_path);
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end
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$fsdbAutoSwitchDumpfile(500, "./verdplus.fsdb", 1000000);
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$fsdbDumpvars();
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$fsdbDumpMDA();
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end
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//###################################
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// configure the dut
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//###################################
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virtual spi_if vif;
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spi_if spi_bus(.clk(clk), .rstn(rst_n));
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virtual lvds_if lvds_vif;
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lvds_if lvds_bus(.clk(clk));
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initial begin
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spi_bus.sclk = 1'b1;
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spi_bus.mosi = 1'b0;
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spi_bus.csn = 1'b1;
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vif = spi_bus;
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2026-03-17 10:02:36 +08:00
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lvds_bus.data = 'b0;
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lvds_bus.valid = 'b0;
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2026-03-14 17:51:22 +08:00
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lvds_vif = lvds_bus;
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end
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spi_driver my_drv;
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lvds_driver lvds_drv;
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logic start;
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initial begin
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rst_n = 1'b0;
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start = 1'b0;
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lvds_drv = new();
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//lvds_drv.file_path = LVDS_FILE;
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lvds_drv.drv_if = lvds_vif;
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my_drv = new();
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my_drv.file_path = CONFIG_FILE;
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my_drv.itf = vif;
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# 20;
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rst_n = 1'b1;
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file_path = $fopen(DATA_O_FILE, "w");
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my_drv.do_drive(file_path);
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$fclose(file_path);
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2026-03-17 10:02:36 +08:00
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//lvds_drv.do_drive();
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lvds_drv.train_count = 100; // ÉèÖÃѵÁ·´ÎÊý
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lvds_drv.send_training(); // ·¢ËÍѵÁ·ÐòÁÐ
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//lvds_drv.scrambler_en = 1;
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lvds_drv.send_frame_from_file(LVDS_FILE); // ·¢ËÍÊý¾ÝÖ¡
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# 3000;
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2026-03-14 17:51:22 +08:00
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start = 1'b1;
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# PERIOD;
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# PERIOD;
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start = 1'b0;
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# 30000;
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file_path = $fopen(DATA_O_FILE, "w");
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my_drv.do_drive(file_path);
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$fclose(file_path);
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start = 1'b1;
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# PERIOD;
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# PERIOD;
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start = 1'b0;
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# 30000;
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file_path = $fopen(DATA_O_FILE, "w");
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my_drv.do_drive(file_path);
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$fclose(file_path);
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2026-03-18 12:29:11 +08:00
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////////////////////////////////////////////////////////////////////////////////////////
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//Trig
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////////////////////////////////////////////////////////////////////////////////////////
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2026-03-14 17:51:22 +08:00
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start = 1'b1;
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# PERIOD;
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# PERIOD;
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start = 1'b0;
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# 30000;
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$finish(0);
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end
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////////////////////////////////////////////////////////////////////////////////////////
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//DUT
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////////////////////////////////////////////////////////////////////////////////////////
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//sync_out
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logic sync_out ;
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//irq
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logic irq ;
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//lvds rx
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logic [3 :0] lvds_data = '0;
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logic [0 :0] lvds_valid = '0;
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logic [0 :0] lvds_clk = '0;
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//DAC Data
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2026-03-17 10:02:36 +08:00
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logic [6 :0] MSB_POS_OUT [31:0] ;
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logic [4 :0] LSB_POS_OUT [31:0] ;
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logic MSB_POS_DUM [31:0] ;
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logic [6 :0] MSB_NEG_OUT [31:0] ;
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logic [4 :0] LSB_NEG_OUT [31:0] ;
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logic MSB_NEG_DUM [31:0] ;
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logic DEM_VLD ;
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2026-03-14 17:51:22 +08:00
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//DAC Cfg Port
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logic [3 :0] Rterm ;
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logic [2 :0] CasAddr ;
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logic [2 :0] CasDw ;
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logic [9 :0] IMainCtrl ;
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logic [3 :0] IBleedCtrl ;
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logic [3 :0] ICkCml ;
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logic [31 :0] CurRsv0 ;
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logic [31 :0] CurRsv1 ;
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//CLK Cfg Port
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logic [0 :0] CcalRstn ;
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logic [3 :0] EnAllP ;
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logic [0 :0] DccEn ;
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logic [0 :0] CasGateCkCtrl ;
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logic [0 :0] SpiEnPi ;
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logic [0 :0] SpiEnQec ;
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logic [0 :0] SpiEnDcc ;
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logic [4 :0] SpiQecCtrlIp ;
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logic [4 :0] SpiQecCtrlIn ;
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logic [4 :0] SpiQecCtrlQp ;
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logic [4 :0] SpiQecCtrlQn ;
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logic [5 :0] SpiDccCtrlIup ;
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logic [5 :0] SpiDccCtrlIdn ;
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logic [5 :0] SpiDccCtrlQup ;
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logic [5 :0] SpiDccCtrlQdn ;
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logic [7 :0] SpiSiqNOut ;
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logic [7 :0] SpiSiqPOut ;
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logic [3 :0] SpiSiPOut ;
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logic [3 :0] SpiSqPOut ;
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logic [2 :0] CrtlCrossOverN ;
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logic [2 :0] CrtlCrossOverP ;
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logic [31 :0] CcalRsv0 ;
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logic [31 :0] CcalRsv1 ;
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logic [3 :0] SelCk10GDig ;
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logic [3 :0] SelCk2p5GDig ;
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logic [8 :0] SelCk625MDig ;
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logic [15 :0] P2sDataEn ;
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logic [15 :0] P2sEnAllP ;
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logic [15 :0] EnPiP ;
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logic [15 :0] CkDivRstn ;
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logic [31 :0] p2srsv0 ;
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logic [31 :0] p2srsv1 ;
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logic [15 :0] CkRxSw ;
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logic [15 :0] RstnCk ;
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logic [15 :0] CtrlZin ;
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2026-03-17 10:02:36 +08:00
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logic [2 :0] phase_tap ;
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2026-03-14 17:51:22 +08:00
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da4008_chip_top U_da4008_chip_top (
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.PI_sclk ( spi_bus.sclk )
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,.PI_csn ( spi_bus.csn )
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,.PI_mosi ( spi_bus.mosi )
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,.PO_miso ( spi_bus.miso )
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,.PO_irq ( irq )
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,.PI_async_rstn ( rst_n )
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,.PI_sync_in ( start )
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,.PO_sync_out ( sync_out )
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,.clk ( clk )
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,.lvds_data ( lvds_bus.data )
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,.lvds_valid ( lvds_bus.valid )
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2026-03-17 10:02:36 +08:00
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,.phase_tap ( phase_tap )
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2026-03-14 17:51:22 +08:00
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,.lvds_clk ( lvds_bus.clk )
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2026-03-17 10:02:36 +08:00
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,.MSB_POS_OUT0 ( MSB_POS_OUT[0 ] )
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,.MSB_POS_OUT1 ( MSB_POS_OUT[1 ] )
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,.MSB_POS_OUT2 ( MSB_POS_OUT[2 ] )
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,.MSB_POS_OUT3 ( MSB_POS_OUT[3 ] )
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,.MSB_POS_OUT4 ( MSB_POS_OUT[4 ] )
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,.MSB_POS_OUT5 ( MSB_POS_OUT[5 ] )
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,.MSB_POS_OUT6 ( MSB_POS_OUT[6 ] )
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,.MSB_POS_OUT7 ( MSB_POS_OUT[7 ] )
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,.MSB_POS_OUT8 ( MSB_POS_OUT[8 ] )
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,.MSB_POS_OUT9 ( MSB_POS_OUT[9 ] )
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,.MSB_POS_OUT10 ( MSB_POS_OUT[10] )
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,.MSB_POS_OUT11 ( MSB_POS_OUT[11] )
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,.MSB_POS_OUT12 ( MSB_POS_OUT[12] )
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,.MSB_POS_OUT13 ( MSB_POS_OUT[13] )
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,.MSB_POS_OUT14 ( MSB_POS_OUT[14] )
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,.MSB_POS_OUT15 ( MSB_POS_OUT[15] )
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,.MSB_POS_OUT16 ( MSB_POS_OUT[16] )
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,.MSB_POS_OUT17 ( MSB_POS_OUT[17] )
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,.MSB_POS_OUT18 ( MSB_POS_OUT[18] )
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,.MSB_POS_OUT19 ( MSB_POS_OUT[19] )
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,.MSB_POS_OUT20 ( MSB_POS_OUT[20] )
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,.MSB_POS_OUT21 ( MSB_POS_OUT[21] )
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,.MSB_POS_OUT22 ( MSB_POS_OUT[22] )
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,.MSB_POS_OUT23 ( MSB_POS_OUT[23] )
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,.MSB_POS_OUT24 ( MSB_POS_OUT[24] )
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,.MSB_POS_OUT25 ( MSB_POS_OUT[25] )
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,.MSB_POS_OUT26 ( MSB_POS_OUT[26] )
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,.MSB_POS_OUT27 ( MSB_POS_OUT[27] )
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,.MSB_POS_OUT28 ( MSB_POS_OUT[28] )
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,.MSB_POS_OUT29 ( MSB_POS_OUT[29] )
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,.MSB_POS_OUT30 ( MSB_POS_OUT[30] )
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,.MSB_POS_OUT31 ( MSB_POS_OUT[31] )
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,.LSB_POS_OUT0 ( LSB_POS_OUT[0 ] )
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,.LSB_POS_OUT1 ( LSB_POS_OUT[1 ] )
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,.LSB_POS_OUT2 ( LSB_POS_OUT[2 ] )
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,.LSB_POS_OUT3 ( LSB_POS_OUT[3 ] )
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,.LSB_POS_OUT4 ( LSB_POS_OUT[4 ] )
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,.LSB_POS_OUT5 ( LSB_POS_OUT[5 ] )
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,.LSB_POS_OUT6 ( LSB_POS_OUT[6 ] )
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,.LSB_POS_OUT7 ( LSB_POS_OUT[7 ] )
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,.LSB_POS_OUT8 ( LSB_POS_OUT[8 ] )
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,.LSB_POS_OUT9 ( LSB_POS_OUT[9 ] )
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,.LSB_POS_OUT10 ( LSB_POS_OUT[10] )
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,.LSB_POS_OUT11 ( LSB_POS_OUT[11] )
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,.LSB_POS_OUT12 ( LSB_POS_OUT[12] )
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,.LSB_POS_OUT13 ( LSB_POS_OUT[13] )
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,.LSB_POS_OUT14 ( LSB_POS_OUT[14] )
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,.LSB_POS_OUT15 ( LSB_POS_OUT[15] )
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,.LSB_POS_OUT16 ( LSB_POS_OUT[16] )
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,.LSB_POS_OUT17 ( LSB_POS_OUT[17] )
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,.LSB_POS_OUT18 ( LSB_POS_OUT[18] )
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,.LSB_POS_OUT19 ( LSB_POS_OUT[19] )
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,.LSB_POS_OUT20 ( LSB_POS_OUT[20] )
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,.LSB_POS_OUT21 ( LSB_POS_OUT[21] )
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,.LSB_POS_OUT22 ( LSB_POS_OUT[22] )
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,.LSB_POS_OUT23 ( LSB_POS_OUT[23] )
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,.LSB_POS_OUT24 ( LSB_POS_OUT[24] )
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,.LSB_POS_OUT25 ( LSB_POS_OUT[25] )
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,.LSB_POS_OUT26 ( LSB_POS_OUT[26] )
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,.LSB_POS_OUT27 ( LSB_POS_OUT[27] )
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,.LSB_POS_OUT28 ( LSB_POS_OUT[28] )
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,.LSB_POS_OUT29 ( LSB_POS_OUT[29] )
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,.LSB_POS_OUT30 ( LSB_POS_OUT[30] )
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,.LSB_POS_OUT31 ( LSB_POS_OUT[31] )
|
|
|
|
|
,.MSB_POS_DUM0 ( MSB_POS_DUM[0 ] )
|
|
|
|
|
,.MSB_POS_DUM1 ( MSB_POS_DUM[1 ] )
|
|
|
|
|
,.MSB_POS_DUM2 ( MSB_POS_DUM[2 ] )
|
|
|
|
|
,.MSB_POS_DUM3 ( MSB_POS_DUM[3 ] )
|
|
|
|
|
,.MSB_POS_DUM4 ( MSB_POS_DUM[4 ] )
|
|
|
|
|
,.MSB_POS_DUM5 ( MSB_POS_DUM[5 ] )
|
|
|
|
|
,.MSB_POS_DUM6 ( MSB_POS_DUM[6 ] )
|
|
|
|
|
,.MSB_POS_DUM7 ( MSB_POS_DUM[7 ] )
|
|
|
|
|
,.MSB_POS_DUM8 ( MSB_POS_DUM[8 ] )
|
|
|
|
|
,.MSB_POS_DUM9 ( MSB_POS_DUM[9 ] )
|
|
|
|
|
,.MSB_POS_DUM10 ( MSB_POS_DUM[10] )
|
|
|
|
|
,.MSB_POS_DUM11 ( MSB_POS_DUM[11] )
|
|
|
|
|
,.MSB_POS_DUM12 ( MSB_POS_DUM[12] )
|
|
|
|
|
,.MSB_POS_DUM13 ( MSB_POS_DUM[13] )
|
|
|
|
|
,.MSB_POS_DUM14 ( MSB_POS_DUM[14] )
|
|
|
|
|
,.MSB_POS_DUM15 ( MSB_POS_DUM[15] )
|
|
|
|
|
,.MSB_POS_DUM16 ( MSB_POS_DUM[16] )
|
|
|
|
|
,.MSB_POS_DUM17 ( MSB_POS_DUM[17] )
|
|
|
|
|
,.MSB_POS_DUM18 ( MSB_POS_DUM[18] )
|
|
|
|
|
,.MSB_POS_DUM19 ( MSB_POS_DUM[19] )
|
|
|
|
|
,.MSB_POS_DUM20 ( MSB_POS_DUM[20] )
|
|
|
|
|
,.MSB_POS_DUM21 ( MSB_POS_DUM[21] )
|
|
|
|
|
,.MSB_POS_DUM22 ( MSB_POS_DUM[22] )
|
|
|
|
|
,.MSB_POS_DUM23 ( MSB_POS_DUM[23] )
|
|
|
|
|
,.MSB_POS_DUM24 ( MSB_POS_DUM[24] )
|
|
|
|
|
,.MSB_POS_DUM25 ( MSB_POS_DUM[25] )
|
|
|
|
|
,.MSB_POS_DUM26 ( MSB_POS_DUM[26] )
|
|
|
|
|
,.MSB_POS_DUM27 ( MSB_POS_DUM[27] )
|
|
|
|
|
,.MSB_POS_DUM28 ( MSB_POS_DUM[28] )
|
|
|
|
|
,.MSB_POS_DUM29 ( MSB_POS_DUM[29] )
|
|
|
|
|
,.MSB_POS_DUM30 ( MSB_POS_DUM[30] )
|
|
|
|
|
,.MSB_POS_DUM31 ( MSB_POS_DUM[31] )
|
|
|
|
|
,.MSB_NEG_OUT0 ( MSB_NEG_OUT[0 ] )
|
|
|
|
|
,.MSB_NEG_OUT1 ( MSB_NEG_OUT[1 ] )
|
|
|
|
|
,.MSB_NEG_OUT2 ( MSB_NEG_OUT[2 ] )
|
|
|
|
|
,.MSB_NEG_OUT3 ( MSB_NEG_OUT[3 ] )
|
|
|
|
|
,.MSB_NEG_OUT4 ( MSB_NEG_OUT[4 ] )
|
|
|
|
|
,.MSB_NEG_OUT5 ( MSB_NEG_OUT[5 ] )
|
|
|
|
|
,.MSB_NEG_OUT6 ( MSB_NEG_OUT[6 ] )
|
|
|
|
|
,.MSB_NEG_OUT7 ( MSB_NEG_OUT[7 ] )
|
|
|
|
|
,.MSB_NEG_OUT8 ( MSB_NEG_OUT[8 ] )
|
|
|
|
|
,.MSB_NEG_OUT9 ( MSB_NEG_OUT[9 ] )
|
|
|
|
|
,.MSB_NEG_OUT10 ( MSB_NEG_OUT[10] )
|
|
|
|
|
,.MSB_NEG_OUT11 ( MSB_NEG_OUT[11] )
|
|
|
|
|
,.MSB_NEG_OUT12 ( MSB_NEG_OUT[12] )
|
|
|
|
|
,.MSB_NEG_OUT13 ( MSB_NEG_OUT[13] )
|
|
|
|
|
,.MSB_NEG_OUT14 ( MSB_NEG_OUT[14] )
|
|
|
|
|
,.MSB_NEG_OUT15 ( MSB_NEG_OUT[15] )
|
|
|
|
|
,.MSB_NEG_OUT16 ( MSB_NEG_OUT[16] )
|
|
|
|
|
,.MSB_NEG_OUT17 ( MSB_NEG_OUT[17] )
|
|
|
|
|
,.MSB_NEG_OUT18 ( MSB_NEG_OUT[18] )
|
|
|
|
|
,.MSB_NEG_OUT19 ( MSB_NEG_OUT[19] )
|
|
|
|
|
,.MSB_NEG_OUT20 ( MSB_NEG_OUT[20] )
|
|
|
|
|
,.MSB_NEG_OUT21 ( MSB_NEG_OUT[21] )
|
|
|
|
|
,.MSB_NEG_OUT22 ( MSB_NEG_OUT[22] )
|
|
|
|
|
,.MSB_NEG_OUT23 ( MSB_NEG_OUT[23] )
|
|
|
|
|
,.MSB_NEG_OUT24 ( MSB_NEG_OUT[24] )
|
|
|
|
|
,.MSB_NEG_OUT25 ( MSB_NEG_OUT[25] )
|
|
|
|
|
,.MSB_NEG_OUT26 ( MSB_NEG_OUT[26] )
|
|
|
|
|
,.MSB_NEG_OUT27 ( MSB_NEG_OUT[27] )
|
|
|
|
|
,.MSB_NEG_OUT28 ( MSB_NEG_OUT[28] )
|
|
|
|
|
,.MSB_NEG_OUT29 ( MSB_NEG_OUT[29] )
|
|
|
|
|
,.MSB_NEG_OUT30 ( MSB_NEG_OUT[30] )
|
|
|
|
|
,.MSB_NEG_OUT31 ( MSB_NEG_OUT[31] )
|
|
|
|
|
,.LSB_NEG_OUT0 ( LSB_NEG_OUT[0 ] )
|
|
|
|
|
,.LSB_NEG_OUT1 ( LSB_NEG_OUT[1 ] )
|
|
|
|
|
,.LSB_NEG_OUT2 ( LSB_NEG_OUT[2 ] )
|
|
|
|
|
,.LSB_NEG_OUT3 ( LSB_NEG_OUT[3 ] )
|
|
|
|
|
,.LSB_NEG_OUT4 ( LSB_NEG_OUT[4 ] )
|
|
|
|
|
,.LSB_NEG_OUT5 ( LSB_NEG_OUT[5 ] )
|
|
|
|
|
,.LSB_NEG_OUT6 ( LSB_NEG_OUT[6 ] )
|
|
|
|
|
,.LSB_NEG_OUT7 ( LSB_NEG_OUT[7 ] )
|
|
|
|
|
,.LSB_NEG_OUT8 ( LSB_NEG_OUT[8 ] )
|
|
|
|
|
,.LSB_NEG_OUT9 ( LSB_NEG_OUT[9 ] )
|
|
|
|
|
,.LSB_NEG_OUT10 ( LSB_NEG_OUT[10] )
|
|
|
|
|
,.LSB_NEG_OUT11 ( LSB_NEG_OUT[11] )
|
|
|
|
|
,.LSB_NEG_OUT12 ( LSB_NEG_OUT[12] )
|
|
|
|
|
,.LSB_NEG_OUT13 ( LSB_NEG_OUT[13] )
|
|
|
|
|
,.LSB_NEG_OUT14 ( LSB_NEG_OUT[14] )
|
|
|
|
|
,.LSB_NEG_OUT15 ( LSB_NEG_OUT[15] )
|
|
|
|
|
,.LSB_NEG_OUT16 ( LSB_NEG_OUT[16] )
|
|
|
|
|
,.LSB_NEG_OUT17 ( LSB_NEG_OUT[17] )
|
|
|
|
|
,.LSB_NEG_OUT18 ( LSB_NEG_OUT[18] )
|
|
|
|
|
,.LSB_NEG_OUT19 ( LSB_NEG_OUT[19] )
|
|
|
|
|
,.LSB_NEG_OUT20 ( LSB_NEG_OUT[20] )
|
|
|
|
|
,.LSB_NEG_OUT21 ( LSB_NEG_OUT[21] )
|
|
|
|
|
,.LSB_NEG_OUT22 ( LSB_NEG_OUT[22] )
|
|
|
|
|
,.LSB_NEG_OUT23 ( LSB_NEG_OUT[23] )
|
|
|
|
|
,.LSB_NEG_OUT24 ( LSB_NEG_OUT[24] )
|
|
|
|
|
,.LSB_NEG_OUT25 ( LSB_NEG_OUT[25] )
|
|
|
|
|
,.LSB_NEG_OUT26 ( LSB_NEG_OUT[26] )
|
|
|
|
|
,.LSB_NEG_OUT27 ( LSB_NEG_OUT[27] )
|
|
|
|
|
,.LSB_NEG_OUT28 ( LSB_NEG_OUT[28] )
|
|
|
|
|
,.LSB_NEG_OUT29 ( LSB_NEG_OUT[29] )
|
|
|
|
|
,.LSB_NEG_OUT30 ( LSB_NEG_OUT[30] )
|
|
|
|
|
,.LSB_NEG_OUT31 ( LSB_NEG_OUT[31] )
|
|
|
|
|
,.MSB_NEG_DUM0 ( MSB_NEG_DUM[0 ] )
|
|
|
|
|
,.MSB_NEG_DUM1 ( MSB_NEG_DUM[1 ] )
|
|
|
|
|
,.MSB_NEG_DUM2 ( MSB_NEG_DUM[2 ] )
|
|
|
|
|
,.MSB_NEG_DUM3 ( MSB_NEG_DUM[3 ] )
|
|
|
|
|
,.MSB_NEG_DUM4 ( MSB_NEG_DUM[4 ] )
|
|
|
|
|
,.MSB_NEG_DUM5 ( MSB_NEG_DUM[5 ] )
|
|
|
|
|
,.MSB_NEG_DUM6 ( MSB_NEG_DUM[6 ] )
|
|
|
|
|
,.MSB_NEG_DUM7 ( MSB_NEG_DUM[7 ] )
|
|
|
|
|
,.MSB_NEG_DUM8 ( MSB_NEG_DUM[8 ] )
|
|
|
|
|
,.MSB_NEG_DUM9 ( MSB_NEG_DUM[9 ] )
|
|
|
|
|
,.MSB_NEG_DUM10 ( MSB_NEG_DUM[10] )
|
|
|
|
|
,.MSB_NEG_DUM11 ( MSB_NEG_DUM[11] )
|
|
|
|
|
,.MSB_NEG_DUM12 ( MSB_NEG_DUM[12] )
|
|
|
|
|
,.MSB_NEG_DUM13 ( MSB_NEG_DUM[13] )
|
|
|
|
|
,.MSB_NEG_DUM14 ( MSB_NEG_DUM[14] )
|
|
|
|
|
,.MSB_NEG_DUM15 ( MSB_NEG_DUM[15] )
|
|
|
|
|
,.MSB_NEG_DUM16 ( MSB_NEG_DUM[16] )
|
|
|
|
|
,.MSB_NEG_DUM17 ( MSB_NEG_DUM[17] )
|
|
|
|
|
,.MSB_NEG_DUM18 ( MSB_NEG_DUM[18] )
|
|
|
|
|
,.MSB_NEG_DUM19 ( MSB_NEG_DUM[19] )
|
|
|
|
|
,.MSB_NEG_DUM20 ( MSB_NEG_DUM[20] )
|
|
|
|
|
,.MSB_NEG_DUM21 ( MSB_NEG_DUM[21] )
|
|
|
|
|
,.MSB_NEG_DUM22 ( MSB_NEG_DUM[22] )
|
|
|
|
|
,.MSB_NEG_DUM23 ( MSB_NEG_DUM[23] )
|
|
|
|
|
,.MSB_NEG_DUM24 ( MSB_NEG_DUM[24] )
|
|
|
|
|
,.MSB_NEG_DUM25 ( MSB_NEG_DUM[25] )
|
|
|
|
|
,.MSB_NEG_DUM26 ( MSB_NEG_DUM[26] )
|
|
|
|
|
,.MSB_NEG_DUM27 ( MSB_NEG_DUM[27] )
|
|
|
|
|
,.MSB_NEG_DUM28 ( MSB_NEG_DUM[28] )
|
|
|
|
|
,.MSB_NEG_DUM29 ( MSB_NEG_DUM[29] )
|
|
|
|
|
,.MSB_NEG_DUM30 ( MSB_NEG_DUM[30] )
|
|
|
|
|
,.MSB_NEG_DUM31 ( MSB_NEG_DUM[31] )
|
2026-03-14 17:51:22 +08:00
|
|
|
,.DEM_VLD ( DEM_VLD )
|
|
|
|
|
,.Rterm ( Rterm )
|
|
|
|
|
,.CasAddr ( CasAddr )
|
|
|
|
|
,.CasDw ( CasDw )
|
|
|
|
|
,.IMainCtrl ( IMainCtrl )
|
|
|
|
|
,.IBleedCtrl ( IBleedCtrl )
|
|
|
|
|
,.ICkCml ( ICkCml )
|
|
|
|
|
,.CurRsv0 ( CurRsv0 )
|
|
|
|
|
,.CurRsv1 ( CurRsv1 )
|
|
|
|
|
,.CcalRstn ( CcalRstn )
|
|
|
|
|
,.EnAllP ( EnAllP )
|
|
|
|
|
,.DccEn ( DccEn )
|
|
|
|
|
,.CasGateCkCtrl ( CasGateCkCtrl )
|
|
|
|
|
,.SpiEnPi ( SpiEnPi )
|
|
|
|
|
,.SpiEnQec ( SpiEnQec )
|
|
|
|
|
,.SpiEnDcc ( SpiEnDcc )
|
|
|
|
|
,.SpiQecCtrlIp ( SpiQecCtrlIp )
|
|
|
|
|
,.SpiQecCtrlIn ( SpiQecCtrlIn )
|
|
|
|
|
,.SpiQecCtrlQp ( SpiQecCtrlQp )
|
|
|
|
|
,.SpiQecCtrlQn ( SpiQecCtrlQn )
|
|
|
|
|
,.SpiDccCtrlIup ( SpiDccCtrlIup )
|
|
|
|
|
,.SpiDccCtrlIdn ( SpiDccCtrlIdn )
|
|
|
|
|
,.SpiDccCtrlQup ( SpiDccCtrlQup )
|
|
|
|
|
,.SpiDccCtrlQdn ( SpiDccCtrlQdn )
|
|
|
|
|
,.SpiSiqNOut ( SpiSiqNOut )
|
|
|
|
|
,.SpiSiqPOut ( SpiSiqPOut )
|
|
|
|
|
,.SpiSiPOut ( SpiSiPOut )
|
|
|
|
|
,.SpiSqPOut ( SpiSqPOut )
|
|
|
|
|
,.CrtlCrossOverN ( CrtlCrossOverN )
|
|
|
|
|
,.CrtlCrossOverP ( CrtlCrossOverP )
|
|
|
|
|
,.CcalRsv0 ( CcalRsv0 )
|
|
|
|
|
,.CcalRsv1 ( CcalRsv1 )
|
|
|
|
|
,.SelCk10GDig ( SelCk10GDig )
|
|
|
|
|
,.SelCk2p5GDig ( SelCk2p5GDig )
|
|
|
|
|
,.SelCk625MDig ( SelCk625MDig )
|
|
|
|
|
,.P2sDataEn ( P2sDataEn )
|
|
|
|
|
,.P2sEnAllP ( P2sEnAllP )
|
|
|
|
|
,.EnPiP ( EnPiP )
|
|
|
|
|
,.CkDivRstn ( CkDivRstn )
|
|
|
|
|
,.p2srsv0 ( p2srsv0 )
|
|
|
|
|
,.p2srsv1 ( p2srsv1 )
|
|
|
|
|
,.CkRxSw ( CkRxSw )
|
|
|
|
|
,.RstnCk ( RstnCk )
|
|
|
|
|
,.CtrlZin ( CtrlZin )
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
//DEM_Reverse_64CH
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
2026-03-17 10:02:36 +08:00
|
|
|
logic vld_out ;
|
2026-03-14 17:51:22 +08:00
|
|
|
logic [7 :0] data_out [63:0] ;
|
|
|
|
|
|
|
|
|
|
DEM_Reverse_64CH U_DEM_Reverse_64CH (
|
|
|
|
|
.clk ( clk )
|
2026-03-17 10:02:36 +08:00
|
|
|
,.msb_pos_in ( MSB_POS_OUT )
|
|
|
|
|
,.lsb_pos_in ( LSB_POS_OUT )
|
|
|
|
|
,.msb_neg_in ( MSB_NEG_OUT )
|
|
|
|
|
,.lsb_neg_in ( LSB_NEG_OUT )
|
2026-03-14 17:51:22 +08:00
|
|
|
,.vld_in ( DEM_VLD )
|
|
|
|
|
,.vld_out ( vld_out )
|
|
|
|
|
,.data_out ( data_out )
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
logic [7 :0] data_out_r [63:0] ;
|
2026-03-17 10:02:36 +08:00
|
|
|
logic vld_out_r ;
|
2026-03-14 17:51:22 +08:00
|
|
|
|
|
|
|
|
always @(posedge clk_40g) begin
|
|
|
|
|
data_out_r <= data_out ;
|
|
|
|
|
vld_out_r <= vld_out ;
|
|
|
|
|
end
|
|
|
|
|
///////////////////////////////////////////////////////////////////////
|
|
|
|
|
//DA4008 DEM output data save
|
|
|
|
|
///////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
|
|
|
|
wire add_cnt = vld_out_r;
|
|
|
|
|
wire end_cnt = 1'b0;
|
|
|
|
|
|
|
|
|
|
logic [5 :0] cnt_c;
|
|
|
|
|
wire [5 :0] cnt_n = end_cnt ? 6'h0 :
|
|
|
|
|
add_cnt ? cnt_c + 1'b1 :
|
|
|
|
|
cnt_c ;
|
|
|
|
|
|
|
|
|
|
always @(posedge clk_40g or negedge rst_n) begin
|
|
|
|
|
if(rst_n==1'b0) begin
|
|
|
|
|
cnt_c <= 6'd0;
|
|
|
|
|
end
|
|
|
|
|
else begin
|
|
|
|
|
cnt_c <= cnt_n;
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
logic [7:0] cs_wave;
|
|
|
|
|
always @(posedge clk_40g or negedge rst_n) begin
|
|
|
|
|
if(rst_n==1'b0) begin
|
|
|
|
|
cs_wave <= 16'h0;
|
|
|
|
|
end
|
|
|
|
|
else begin
|
|
|
|
|
case(cnt_c)
|
|
|
|
|
6'd0 : cs_wave <= {~data_out_r[0 ][7],data_out_r[0 ][6:0]};
|
|
|
|
|
6'd1 : cs_wave <= {~data_out_r[1 ][7],data_out_r[1 ][6:0]};
|
|
|
|
|
6'd2 : cs_wave <= {~data_out_r[2 ][7],data_out_r[2 ][6:0]};
|
|
|
|
|
6'd3 : cs_wave <= {~data_out_r[3 ][7],data_out_r[3 ][6:0]};
|
|
|
|
|
6'd4 : cs_wave <= {~data_out_r[4 ][7],data_out_r[4 ][6:0]};
|
|
|
|
|
6'd5 : cs_wave <= {~data_out_r[5 ][7],data_out_r[5 ][6:0]};
|
|
|
|
|
6'd6 : cs_wave <= {~data_out_r[6 ][7],data_out_r[6 ][6:0]};
|
|
|
|
|
6'd7 : cs_wave <= {~data_out_r[7 ][7],data_out_r[7 ][6:0]};
|
|
|
|
|
6'd8 : cs_wave <= {~data_out_r[8 ][7],data_out_r[8 ][6:0]};
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6'd9 : cs_wave <= {~data_out_r[9 ][7],data_out_r[9 ][6:0]};
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6'd10 : cs_wave <= {~data_out_r[10][7],data_out_r[10][6:0]};
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6'd11 : cs_wave <= {~data_out_r[11][7],data_out_r[11][6:0]};
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6'd12 : cs_wave <= {~data_out_r[12][7],data_out_r[12][6:0]};
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6'd13 : cs_wave <= {~data_out_r[13][7],data_out_r[13][6:0]};
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6'd14 : cs_wave <= {~data_out_r[14][7],data_out_r[14][6:0]};
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6'd15 : cs_wave <= {~data_out_r[15][7],data_out_r[15][6:0]};
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6'd16 : cs_wave <= {~data_out_r[16][7],data_out_r[16][6:0]};
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6'd17 : cs_wave <= {~data_out_r[17][7],data_out_r[17][6:0]};
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6'd18 : cs_wave <= {~data_out_r[18][7],data_out_r[18][6:0]};
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6'd19 : cs_wave <= {~data_out_r[19][7],data_out_r[19][6:0]};
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6'd20 : cs_wave <= {~data_out_r[20][7],data_out_r[20][6:0]};
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6'd21 : cs_wave <= {~data_out_r[21][7],data_out_r[21][6:0]};
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6'd22 : cs_wave <= {~data_out_r[22][7],data_out_r[22][6:0]};
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6'd23 : cs_wave <= {~data_out_r[23][7],data_out_r[23][6:0]};
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6'd24 : cs_wave <= {~data_out_r[24][7],data_out_r[24][6:0]};
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6'd25 : cs_wave <= {~data_out_r[25][7],data_out_r[25][6:0]};
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6'd26 : cs_wave <= {~data_out_r[26][7],data_out_r[26][6:0]};
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6'd27 : cs_wave <= {~data_out_r[27][7],data_out_r[27][6:0]};
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6'd28 : cs_wave <= {~data_out_r[28][7],data_out_r[28][6:0]};
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6'd29 : cs_wave <= {~data_out_r[29][7],data_out_r[29][6:0]};
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6'd30 : cs_wave <= {~data_out_r[30][7],data_out_r[30][6:0]};
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6'd31 : cs_wave <= {~data_out_r[31][7],data_out_r[31][6:0]};
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6'd32 : cs_wave <= {~data_out_r[32][7],data_out_r[32][6:0]};
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6'd33 : cs_wave <= {~data_out_r[33][7],data_out_r[33][6:0]};
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6'd34 : cs_wave <= {~data_out_r[34][7],data_out_r[34][6:0]};
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6'd35 : cs_wave <= {~data_out_r[35][7],data_out_r[35][6:0]};
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6'd36 : cs_wave <= {~data_out_r[36][7],data_out_r[36][6:0]};
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6'd37 : cs_wave <= {~data_out_r[37][7],data_out_r[37][6:0]};
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6'd38 : cs_wave <= {~data_out_r[38][7],data_out_r[38][6:0]};
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6'd39 : cs_wave <= {~data_out_r[39][7],data_out_r[39][6:0]};
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6'd40 : cs_wave <= {~data_out_r[40][7],data_out_r[40][6:0]};
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6'd41 : cs_wave <= {~data_out_r[41][7],data_out_r[41][6:0]};
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6'd42 : cs_wave <= {~data_out_r[42][7],data_out_r[42][6:0]};
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6'd43 : cs_wave <= {~data_out_r[43][7],data_out_r[43][6:0]};
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6'd44 : cs_wave <= {~data_out_r[44][7],data_out_r[44][6:0]};
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6'd45 : cs_wave <= {~data_out_r[45][7],data_out_r[45][6:0]};
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6'd46 : cs_wave <= {~data_out_r[46][7],data_out_r[46][6:0]};
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6'd47 : cs_wave <= {~data_out_r[47][7],data_out_r[47][6:0]};
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6'd48 : cs_wave <= {~data_out_r[48][7],data_out_r[48][6:0]};
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6'd49 : cs_wave <= {~data_out_r[49][7],data_out_r[49][6:0]};
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6'd50 : cs_wave <= {~data_out_r[50][7],data_out_r[50][6:0]};
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6'd51 : cs_wave <= {~data_out_r[51][7],data_out_r[51][6:0]};
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6'd52 : cs_wave <= {~data_out_r[52][7],data_out_r[52][6:0]};
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6'd53 : cs_wave <= {~data_out_r[53][7],data_out_r[53][6:0]};
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6'd54 : cs_wave <= {~data_out_r[54][7],data_out_r[54][6:0]};
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6'd55 : cs_wave <= {~data_out_r[55][7],data_out_r[55][6:0]};
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6'd56 : cs_wave <= {~data_out_r[56][7],data_out_r[56][6:0]};
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6'd57 : cs_wave <= {~data_out_r[57][7],data_out_r[57][6:0]};
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6'd58 : cs_wave <= {~data_out_r[58][7],data_out_r[58][6:0]};
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6'd59 : cs_wave <= {~data_out_r[59][7],data_out_r[59][6:0]};
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6'd60 : cs_wave <= {~data_out_r[60][7],data_out_r[60][6:0]};
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6'd61 : cs_wave <= {~data_out_r[61][7],data_out_r[61][6:0]};
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6'd62 : cs_wave <= {~data_out_r[62][7],data_out_r[62][6:0]};
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6'd63 : cs_wave <= {~data_out_r[63][7],data_out_r[63][6:0]};
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endcase
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end
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end
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endmodule
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