add test_net2spi_therm

This commit is contained in:
yangshenbo 2026-05-20 14:43:24 +08:00
commit 00b866b19b
111 changed files with 69625 additions and 0 deletions

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@ -0,0 +1,844 @@
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_ACTUAL_FREQ">100.00000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">No_buffer</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">50.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">50.00000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">50</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_ACTUAL_FREQ">125.00000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">No_buffer</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">50.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">100.00000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_ACTUAL_FREQ">300.00000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">50.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">125.00000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">125</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">300.00000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">300</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">den</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVCLK">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE1_AUTO">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE2_AUTO">0.26666666666666666</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE3_AUTO">1.0666666666666667</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE4_AUTO">4.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE5_AUTO">2.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE6_AUTO">1.6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE7_AUTO">0.6666666666666666</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_D_MAX">93.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_D_MIN">1.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK0">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK1">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK2">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK3">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL0">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL1">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_ONCHIP</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock Freq (MHz) Input Jitter (UI)</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary_________100.000____________0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">Min_O_Jitter</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_3">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV3">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV4">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV5">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV6">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV7">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">HIGH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">15.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">7.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">30</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">15</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">12</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">AUTO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_MAX">128.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_MIN">2.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZE_CLOCKING_STRUCTURE_EN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">clk_out1__200.00000______0.000______50.0_______85.182_____76.967</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">clk_out2__750.00000______0.000______50.0_______67.716_____76.967</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">clk_out3__187.50000______0.000______50.0_______86.155_____76.967</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">clk_out4__50.00000______0.000______50.0______108.951_____76.967</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">clk_out5__100.00000______0.000______50.0_______96.283_____76.967</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">clk_out6__125.00000______0.000______50.0_______92.548_____76.967</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">clk_out7__300.00000______0.000______50.0_______79.341_____76.967</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_O_MAX">128.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_O_MIN">1.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASESHIFT_MODE">LATENCY</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV3">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV4">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_REG">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRECISION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">MMCM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REF_CLK_FREQ">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">resetn</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VCO_MAX">1600.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VCO_MIN">800.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">System_clk_wiz</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DRP">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">85.182</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">76.967</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">200</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">Buffer</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">67.716</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">76.967</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">750</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">Buffer</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">86.155</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">76.967</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">187.5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">Buffer</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">108.951</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">76.967</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">50</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">Buffer</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">96.283</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">76.967</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">Buffer</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">92.548</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">76.967</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">125</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">Buffer</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">79.341</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">76.967</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">300</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">System_clk_wiz</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLOCK_MONITOR">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK0">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK3">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL0">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_ONCHIP</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">Min_O_Jitter</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">HIGH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">15.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">7.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">30</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintexuplus</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcku5p</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffvb676</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../Test_NET_to_SPI.gen/sources_1/ip/System_clk_wiz</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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<xilinx:componentInstanceExtensions>
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</xilinx:configElementInfos>
<xilinx:boundaryDescriptionInfo>
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;clk_in1&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;clk_out1&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;clk_out2&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;clk_out3&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;clk_out4&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;clk_out5&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;clk_out6&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;clk_out7&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;clkfb_in&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;clkfb_out&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;locked&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physic
al_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}]},&quot;interfaces&quot;:{&quot;clock_CLKFB_IN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;v
alue_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLKFB_IN&quot;:[{&quot;physical_name&quot;:&quot;clkfb_in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;clock_CLKFB_OUT&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;mas
ter&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,
&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLKFB_OUT&quot;:[{&quot;physical_name&quot;:&quot;clkfb_out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;clock_CLK_IN1&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_sta
tic_object&quot;:false}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;CLK_IN1_BOARD_INTERFACE&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FRE
Q_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK_IN1&quot;:[{&quot;physical_name&quot;:&quot;clk_in1&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;clock_CLK_OUT1&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is
_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSE
RT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK_OUT1&quot;:[{&quot;physical_name&quot;:&quot;clk_out1&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;clock_CLK_OUT2&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is
_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE
&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK_OUT2&quot;:[{&quot;physical_name&quot;:&quot;clk_out2&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;clock_CLK_OUT3&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;i
s_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{
&quot;CLK_OUT3&quot;:[{&quot;physical_name&quot;:&quot;clk_out3&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;clock_CLK_OUT4&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips
_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK_OUT4&quot;:[{&quot;physical_name&quot;:&quot;clk_out4&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;clock_CLK_OUT5&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signa
l:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_
inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK_OUT5&quot;:[{&quot;physical_name&quot;:&quot;clk_out5&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;clock_CLK_OUT6&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;
:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips
_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK_OUT6&quot;:[{&quot;physical_name&quot;:&quot;clk_out6&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;clock_CLK_OUT7&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;
:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_
inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK_OUT7&quot;:[{&quot;physical_name&quot;:&quot;clk_out7&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}}}}}"/>
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READY&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TSTRB&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tstrb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TUSER&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TVALID&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;M_CLKIF&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;M_AXIS&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;r
esolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is
_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;m_axis_aclk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;S_AXIS&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;for
mat&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_objec
t&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tdata&quot;,&quot;physical_le
ft&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TDEST&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tdest&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TID&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TKEEP&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tkeep&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TLAST&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TREADY&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TSTRB&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tstrb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TUSER&quot;:[{&quot;physical_name&quot;
:&quot;s_axis_tuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TVALID&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;S_CLKIF&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;S_AXIS&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;val
ue&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;s_axis_aclk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:
&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;S_RSTIF&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;s_axis_aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}}}}}"/>
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View File

@ -0,0 +1,154 @@
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AS_TLAST&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;use
r&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;8&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tdata&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;63&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps
_used&quot;:&quot;none&quot;}],&quot;TDEST&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tdest&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TID&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TKEEP&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tkeep&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TLAST&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TREADY&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TSTRB&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tstrb&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TUSER&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;l
ogical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TVALID&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;M_CLKIF&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;M_AXIS&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generat
ed&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;m_axis_aclk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;S_AXIS
&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ip
s_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;8&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDEST_WIDTH&quot;:[{&quot;v
alue&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tdata&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;63&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TDEST&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tdest&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TID&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TKEEP&quot;:[{&quot;
physical_name&quot;:&quot;s_axis_tkeep&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TLAST&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TREADY&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TSTRB&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tstrb&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TUSER&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TVALID&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;S_CLKIF&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;param
eters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;S_AXIS&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;
default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;s_axis_aclk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;S_RSTIF&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLA
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<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;axis_rd_data_count&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;axis_wr_data_count&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axis_aclk&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axis_tdata&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axis_tkeep&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axis_tlast&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axis_tready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axis_tvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;prog_full&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axis_aclk&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;
:&quot;false&quot;}],&quot;s_axis_aresetn&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axis_tdata&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axis_tkeep&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axis_tlast&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axis_tready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axis_tvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}]},&quot;interfaces&quot;:{&quot;M_AXIS&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permiss
ion&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_infer
red&quot;:false,&quot;is_static_object&quot;:false}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;8&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;
value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tdata&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;63&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TDEST&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tdest&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TID&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TKEEP&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tkeep&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TLAST&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TREADY&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_lef
t&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TSTRB&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tstrb&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TUSER&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TVALID&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;M_CLKIF&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;M_AXIS&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_o
bject&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,
&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;m_axis_aclk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;S_AXIS&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TLAST&quot;:[{&quot;v
alue&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_ty
pe&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;8&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tdata&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;63&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}
],&quot;TDEST&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tdest&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TID&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TKEEP&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tkeep&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TLAST&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TREADY&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TSTRB&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tstrb&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TUSER&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:
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<xilinx:boundaryDescriptionInfo>
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;almost_full&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;axis_rd_data_count&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;axis_wr_data_count&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axis_tdata&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axis_tready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axis_tvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;prog_full&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axis_aclk&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axis_aresetn&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axis_tdata&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vect
or&quot;:&quot;true&quot;}],&quot;s_axis_tready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axis_tvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}]},&quot;interfaces&quot;:{&quot;M_AXIS&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_
type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred
&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;4&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tdata&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TDEST&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tdest&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;
physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TID&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TKEEP&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tkeep&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TLAST&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TREADY&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TSTRB&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tstrb&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TUSER&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TVALID&quot;:[{&quot;physical_name&quot;:&quot;m_axis
_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;S_AXIS&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TREA
DY&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;4&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;use
r&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tdata&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TDEST&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tdest&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TID&quot;:[{&quot;physical_name&quot;:
&quot;s_axis_tid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TKEEP&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tkeep&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TLAST&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TREADY&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TSTRB&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tstrb&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TUSER&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TVALID&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;no
ne&quot;}]}},&quot;S_CLKIF&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;S_AXIS&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;use
r&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;s_axis_aclk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;S_RSTIF&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permissi
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<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;m_axis_tdata&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axis_tkeep&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axis_tlast&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axis_tready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axis_tvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;prog_full&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axis_aclk&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axis_aresetn&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axis_tdata&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axis_tkeep&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;
s_axis_tlast&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axis_tready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axis_tvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}]},&quot;interfaces&quot;:{&quot;M_AXIS&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HA
S_TLAST&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user
&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;4&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tdata&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_
used&quot;:&quot;none&quot;}],&quot;TDEST&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tdest&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TID&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TKEEP&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tkeep&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TLAST&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TREADY&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TSTRB&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tstrb&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TUSER&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;lo
gical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TVALID&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;S_AXIS&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usa
ge&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TD
ATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;4&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tdata&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TDEST&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tdest&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;
,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TID&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TKEEP&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tkeep&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TLAST&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TREADY&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TSTRB&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tstrb&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TUSER&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TVALID&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical
_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;S_CLKIF&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;S_AXIS&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;1000000
00&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;s_axis_aclk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;S_RSTIF&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parame
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&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;10000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;aclk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;M_AXIS&quot;:{&quot;vlnv&quot;:&quot;x
ilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;
:false,&quot;is_static_object&quot;:false}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0
&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tdata&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TDEST&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tdest&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TID&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TKEEP&quot;:[{&quot;physical_n
ame&quot;:&quot;m_axis_tkeep&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TLAST&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TREADY&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TSTRB&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tstrb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TUSER&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TVALID&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;RSTIF&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;INS
ERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;S_AXIS&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_i
nferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;,&quot;val
ue_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;8&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;form
at&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tdata&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;63&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TDEST&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tdest&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TID&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TKEEP&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tkeep&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TLAST&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TREADY&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TSTRB&quot;:[{&quot;physical_name&quot;:
&quot;s_axis_tstrb&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TUSER&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TVALID&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}}}}}"/>
</xilinx:boundaryDescriptionInfo>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>

View File

@ -0,0 +1,122 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>axis_dwidth_8bTo64b</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axis_dwidth_converter" spirit:version="1.1"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKENIF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.ASSOCIATED_RESET"/>
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View File

@ -0,0 +1,115 @@
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">I</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">24</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../Test_NET_to_SPI.gen/axis_dwidth_converter_2/ip/axis_dwidth_converter_2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M_TDATA_NUM_BYTES" xilinx:valueSource="user"/>
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<xilinx:boundaryDescriptionInfo>
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;aclk&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;aresetn&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axis_tdata&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axis_tready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axis_tvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axis_tdata&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axis_tready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axis_tvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}]},&quot;interfaces&quot;:{&quot;CLKIF&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_p
ermission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;10000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long
&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;aclk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;M_AXIS&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve
_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is
_static_object&quot;:false}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;8&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;de
fault&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tdata&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;63&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TDEST&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tdest&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TID&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TKEEP&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tkeep&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TLAST&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TREADY&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logica
l_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TSTRB&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tstrb&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TUSER&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TVALID&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;RSTIF&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;por
t_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;S_AXIS&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;i
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_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is
_static_object&quot;:false}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:
&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tdata&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TDEST&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tdest&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TID&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TKEEP&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tkeep&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TLAST&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TREADY&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logic
al_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TSTRB&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tstrb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TUSER&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TVALID&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;RSTIF&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;po
rt_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;S_AXIS&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;
is_static_object&quot;:false}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;8&quot;,&quot;value_
src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tdata&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;63&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TDEST&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tdest&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used
&quot;:&quot;none&quot;}],&quot;TID&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TKEEP&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tkeep&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TLAST&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TREADY&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TSTRB&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tstrb&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TUSER&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TVALID&quot;:[{&quot;physical_name&quot;:&quot;s_axis_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logi
cal_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}}}}}"/>
</xilinx:boundaryDescriptionInfo>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>

View File

@ -0,0 +1,124 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>axis_dwidth_converter_4</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axis_dwidth_converter" spirit:version="1.1"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKENIF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.FREQ_HZ">10000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.PHASE">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">1</spirit:configurableElementValue>
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View File

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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_TKEEP" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_TLAST" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M_TDATA_NUM_BYTES" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S_TDATA_NUM_BYTES" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
<xilinx:boundaryDescriptionInfo>
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;aclk&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;aresetn&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axis_tdata&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axis_tkeep&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axis_tlast&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axis_tready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axis_tvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axis_tdata&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axis_tkeep&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axis_tlast&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axis_tread
y&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axis_tvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}]},&quot;interfaces&quot;:{&quot;CLKIF&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;
,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;10000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;aclk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;M_AXIS&quot;:{&quot;vlnv&quot;:&quot;
xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred
&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;4&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,
&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tdata&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TDEST&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tdest&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TID&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TKEEP&quot;:[{&quot;physical_n
ame&quot;:&quot;m_axis_tkeep&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TLAST&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TREADY&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TSTRB&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tstrb&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TUSER&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TVALID&quot;:[{&quot;physical_name&quot;:&quot;m_axis_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;RSTIF&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;INS
ERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;S_AXIS&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_i
nferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;,&quot;val
ue_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;8&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;form
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View File

@ -0,0 +1,500 @@
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.BUFG_LOC_2">X0Y7</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_BURST_MODE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CA_MIRROR">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CLKFBOUT_MULT">15</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CLKIN_PERIOD">10000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CLKOUT1_DIVIDE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CLKOUTPHY_MODE">VCO_2X</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_COLUMN_WIDTH">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_COMP_DENSITY">16Gb</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CWL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_Configuration">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DATABITS_PER_STROBE">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DATA_MASK">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DBAW">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DCI_CASCADE_CUTOFF">938</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DM_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DQS_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DQ_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_Ecc">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_HR_MIN_FREQ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_IO_VOLTAGE">1.2V</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_IS_CUSTOM">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_IS_FASTER_SPEED_RAM">No</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MAX_PERIOD">1600</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MCS_ECC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEMORY_PART">MT40A1G16RC-062E</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEMORY_TYPE">Components</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_COMP_WIDTH">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY">16Gb</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY_GB">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY_MB">16384</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_DEVICE_WIDTH">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_SIZE">4294967296</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MIN_PERIOD">750</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MODEL_SPEED_GRADE">DDR4_625_Timing</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MR0">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MR2">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_Mem_Add_Map">ROW_COLUMN_BANK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_ODT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_OUTPUT_DRV">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_RANK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_ROW_WIDTH">17</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_RTT_NOM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_RTT_WR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_SPEED_GRADE">062E</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_Slot">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_StackHeight">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_UI_CLOCK">250000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_USE_CS_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_USE_DM_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_VrefVoltage">0.84</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_nAL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_nCK_PER_CLK">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_nCS_PER_RANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tCCD_3ds">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tCK">1000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tCKE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tFAW">30</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tFAW_dlr">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tMRD">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRAS">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRCD">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tREFI">7800</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRFC">350</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRFC_dlr">190</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRP">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRRD"/>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRRD_L">7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRRD_S">6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRRD_dlr">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRTP">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tWR">15</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tWTR"/>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tWTR_L">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tWTR_S">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tXPR">90</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tZQCS">128</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tZQI">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tZQINIT">256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.MEM_TYPE">DDR4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.MMCM_IDX_BANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_RAMB18_LOC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_RAMB18_LOC_SC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_RAMB36_LOC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_RAMB36_LOC_SC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_SLICE_LOC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_SLICE_LOC_SC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.SYSCLK_CENTER_INFO">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CAL_INPUT_CLK_PERIOD">10000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT0_DIVIDE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT1_DIVIDE">15</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT2_DIVIDE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT3_DIVIDE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT4_DIVIDE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT6_DIVIDE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CUSTOM_PART_ATTRIBUTES">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.Debug_Signal">Disable</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LR_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT1_FREQ_HZ">100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT1_PHASE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT2_FREQ_HZ">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT2_PHASE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT3_FREQ_HZ">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT3_PHASE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT4_FREQ_HZ">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT4_PHASE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PING_PONG_PHY">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.Simulation_Mode">BFM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.System_Clock">Differential</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT1_FREQ_HZ">100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT2_FREQ_HZ">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT3_FREQ_HZ">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT4_FREQ_HZ">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AL_SEL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.ADDR_WIDTH">17</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.ControllerType">DDR4_SDRAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ACT_SKEW">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_0">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_1">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_10">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_13">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_14">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_15">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_16">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_17">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_2">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_3">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_4">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_5">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_6">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_7">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_8">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_9">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AUTO_AP_COL_A3">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AutoPrecharge">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiAddressWidth">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiArbitrationScheme">RD_PRI_REG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiDataWidth">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiIDWidth">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiNarrowBurst">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiSelection">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BA_SKEW_0">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BA_SKEW_1">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BG_SKEW_0">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BG_SKEW_1">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BurstLength">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BurstType">Sequential</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CKE_SKEW_0">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CKE_SKEW_3">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CK_SKEW_0">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT">15</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE">6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CS_SKEW_0">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Capacity">512</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ChipSelect">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Clamshell">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CustomParts">no_file_loaded</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DataMask">DM_NO_DBI</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DataWidth">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_EN_PARITY">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Ecc">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Enable_LVAUX">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod">10000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_LR_SKEW_0">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_LR_SKEW_1">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MCS_ECC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Mem_Add_Map">ROW_COLUMN_BANK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryName">MainMemory</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart">MT40A1G16RC-062E</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryType">Components</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryVoltage">1.2V</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_0">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_1">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_2">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_3">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_OnDieTermination">RZQ/6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Ordering">Normal</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_OutputDriverImpedenceControl">RZQ/7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_PAR_SKEW">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_PhyClockRatio">4:1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_RESTORE_CRC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_SAVE_RESTORE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_SELF_REFRESH">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Slot">Single</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Specify_MandD">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TREFI">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TRFC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TRFC_DLR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TXPR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TimePeriod">1000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_UserRefresh_ZQCS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_isCKEShared">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_isCustom">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_nCK_TREFI">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_nCK_TRFC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_nCK_TRFC_DLR">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.LR_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.MIGRATION">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.ODT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.StackHeight">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0_CLOCK_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0_DDR4_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">ddr4_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCI_Cascade">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_TERM_SYSCLK">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Debug_Signal">Disable</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Default_Bank_Selections">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_PP_4R_MIR">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_SysPorts">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Example_TG">SIMPLE_TG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IOPowerReduction">OFF</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IS_FROM_PHY">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MCS_DBG_EN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MCS_WO_DSP">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.No_Controller">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PARTIAL_RECONFIG_FLOW_MIG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PING_PONG_PHY">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phy_Only">Complete_Memory_Controller</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RECONFIG_XSDB_SAVE_RESTORE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reference_Clock">Differential</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SET_DW_TO_40">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Simulation_Mode">BFM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.System_Clock">Differential</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TIMING_3DS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TIMING_OP1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TIMING_OP2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintexuplus</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcku5p</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffvb676</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">I</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../Test_NET_to_SPI.gen/ddr4_0/ip/ddr4_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT1_FREQ_HZ" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.BANK_GROUP_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_AxiAddressWidth" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_AxiDataWidth" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_AxiNarrowBurst" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_AxiSelection" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasLatency" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasWriteLatency" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DataWidth" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_TimePeriod" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
<xilinx:boundaryDescriptionInfo>
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&quot;c0_ddr4_dm_dbi_n&quot;:[{&quot;direction&quot;:&quot;inout&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_dq&quot;:[{&quot;direction&quot;:&quot;inout&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_dqs_c&quot;:[{&quot;direction&quot;:&quot;inout&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_dqs_t&quot;:[{&quot;direction&quot;:&quot;inout&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_odt&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_reset_n&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_s_axi_araddr&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_arburst&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_arcache&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_arid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_v
ector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_arlen&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_arlock&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_arprot&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_arqos&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_arready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_s_axi_arsize&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_arvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_s_axi_awaddr&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_awburst&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_awcache&quot;:[{&quot;direction&quot;:&quot;in&quot;
,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_awid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_awlen&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_awlock&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_awprot&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_awqos&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_awready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_s_axi_awsize&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_awvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_s_axi_bid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;
c0_ddr4_s_axi_bready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_s_axi_bresp&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_bvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_s_axi_rdata&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_rid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_rlast&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_s_axi_rready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_s_axi_rresp&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_rvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_s_axi_wdata&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;
31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_wlast&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_s_axi_wready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_s_axi_wstrb&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_wvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_ui_clk&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_ui_clk_sync_rst&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_init_calib_complete&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_sys_clk_n&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_sys_clk_p&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;dbg_bus&quot;:[{&quot;direction&quot;:
&quot;out&quot;,&quot;physical_left&quot;:&quot;511&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;dbg_clk&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;sys_rst&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}]},&quot;interfaces&quot;:{&quot;ADDN_UI_CLKOUT1&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_ASYNC_RESET&quot;:[{&quot;value&quot;:&quot;c0_aresetn&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;AS
SOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;1e+08&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;dependent&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;
:&quot;user&quot;,&quot;resolve_type&quot;:&quot;dependent&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;addn_ui_clkout1&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;C0_DDR4&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:ddr4:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:ddr4_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;AXI_ARBITRATION_SCHEME&quot;:[{&quot;value&quot;:&quot;TDM&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;C0_DDR4_BOARD_INTERFACE&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;BURST_LENGTH&quot;:[{&quot;value&quot;:&quot;8&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_st
atic_object&quot;:false}],&quot;CAN_DEBUG&quot;:[{&quot;value&quot;:&quot;false&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;bool&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CAS_LATENCY&quot;:[{&quot;value&quot;:&quot;11&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CAS_WRITE_LATENCY&quot;:[{&quot;value&quot;:&quot;11&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CS_ENABLED&quot;:[{&quot;value&quot;:&quot;true&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;bool&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CUSTOM_PARTS&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;DATA_MASK_ENABLED&quot;:[{&quot;value&quot;:&quot;true&quot;,&quot;v
alue_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;bool&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;8&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;MEMORY_PART&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;MEMORY_TYPE&quot;:[{&quot;value&quot;:&quot;COMPONENTS&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;MEM_ADDR_MAP&quot;:[{&quot;value&quot;:&quot;ROW_COLUMN_BANK&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;SLOT&quot;:[{&quot;value&quot;:&quot;Single&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;r
esolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TIMEPERIOD_PS&quot;:[{&quot;value&quot;:&quot;1250&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;ACT_N&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_act_n&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ADR&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_adr&quot;,&quot;physical_left&quot;:&quot;16&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;16&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BA&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_ba&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BG&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_bg&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;CKE&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_cke&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical
_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;CK_C&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_ck_c&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;CK_T&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_ck_t&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;CS_N&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_cs_n&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;C_ID&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_c&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;DM_N&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_dm_dbi_n&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;DQ&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_dq&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;DQS_C&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_dqs_c&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;lo
gical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;DQS_T&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_dqs_t&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ODT&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_odt&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;PAR&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_parity&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RESET_N&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_reset_n&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;C0_DDR4_ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;val
ue&quot;:&quot;ACTIVE_LOW&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;C0_DDR4_CLOCK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;C0_DDR4_S_AXI:C0_DDR4_S_AXI_CTRL&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;c0_ddr4_aresetn:c0_ddr4_ui_clk_sync_rst&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission
&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;2.5e+08&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;dependent&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.00&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;all
&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_ui_clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;C0_DDR4_RESET&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_ui_clk_sync_rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;C0_DDR4_S_AXI&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:aximm:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:inter
face:aximm_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;memory_map_ref&quot;:&quot;C0_DDR4_MEMORY_MAP&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ARUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;AWUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;BUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;s
imulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;2.5e+08&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;dependent&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;HAS_BRESP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_BURST&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_CACHE&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,
&quot;is_static_object&quot;:false}],&quot;HAS_LOCK&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_PROT&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_QOS&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_REGION&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_RRESP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_WSTR
B&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ID_WIDTH&quot;:[{&quot;value&quot;:&quot;4&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;MAX_BURST_LENGTH&quot;:[{&quot;value&quot;:&quot;256&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;NUM_READ_OUTSTANDING&quot;:[{&quot;value&quot;:&quot;2&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;NUM_READ_THREADS&quot;:[{&quot;value&quot;:&quot;1
&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;NUM_WRITE_OUTSTANDING&quot;:[{&quot;value&quot;:&quot;2&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;NUM_WRITE_THREADS&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;AXI4&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_W
RITE&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;RUSER_BITS_PER_BYTE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;RUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;SUPPORTS_NARROW_BURST&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;WUSER_BITS_PER_BYTE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;WUSER_WIDTH&quot;:[{&quot;
value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;ARADDR&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_araddr&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARBURST&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_arburst&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARCACHE&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_arcache&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARID&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_arid&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARLEN&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_arlen&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARLOCK&quot;:[{&quot;physical_name&quot;
:&quot;c0_ddr4_s_axi_arlock&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARPROT&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_arprot&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARQOS&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_arqos&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARREADY&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_arready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARSIZE&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_arsize&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARUSER&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_aruser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARVALID&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_arvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:
&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWADDR&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_awaddr&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWBURST&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_awburst&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWCACHE&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_awcache&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWID&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_awid&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWLEN&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_awlen&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWLOCK&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_awlock&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;no
ne&quot;}],&quot;AWPROT&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_awprot&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWQOS&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_awqos&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWREADY&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_awready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWSIZE&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_awsize&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWUSER&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_awuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWVALID&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_awvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BID&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_bid&quot;,&quot;physical_l
eft&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BREADY&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_bready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BRESP&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_bresp&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BVALID&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_bvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RDATA&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_rdata&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RID&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_rid&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RLAST&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_rlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;por
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View File

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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
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View File

@ -0,0 +1,589 @@
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
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View File

@ -0,0 +1,595 @@
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View File

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View File

@ -0,0 +1,597 @@
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">fifo_generator_TCP_TX</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">5</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">3799</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">4096</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">4096</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">First_Word_Fall_Through</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">Single_Programmable_Full_Threshold_Constant</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">true</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintexuplus</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcku5p</spirit:configurableElementValue>
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View File

@ -0,0 +1,593 @@
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View File

@ -0,0 +1,587 @@
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sage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}}}}}"/>
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</spirit:design>

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e&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;u
ser&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;slowest_sync_clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;dbg_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RST&quot;
:[{&quot;physical_name&quot;:&quot;mb_debug_sys_rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;ext_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;RESET_BOARD_INTERFACE&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;ext_reset_in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_
right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;interconnect_low_rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;interconnect_aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;mb_rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.co
m:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PROCESSOR&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;mb_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;peripheral_high_rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;
resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PERIPHERAL&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;peripheral_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;peripheral_low_rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY
&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PERIPHERAL&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;peripheral_aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}}}}}"/>
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</spirit:design>

View File

@ -0,0 +1,746 @@
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_AV.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_AV.HAS_TKEEP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_AV.HAS_TLAST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_AV.HAS_TREADY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_AV.HAS_TSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_AV.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_AV.LAYERED_METADATA">undef</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_AV.PHASE">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_AV.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_AV.TDEST_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_AV.TID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_AV.TUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC0.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC0.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC0.HAS_TKEEP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC0.HAS_TLAST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC0.HAS_TREADY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC0.HAS_TSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC0.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC0.LAYERED_METADATA">undef</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC0.PHASE">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC0.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC0.TDEST_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC0.TID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC0.TUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC1.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC1.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC1.HAS_TKEEP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC1.HAS_TLAST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC1.HAS_TREADY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC1.HAS_TSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC1.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC1.LAYERED_METADATA">undef</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC1.PHASE">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC1.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC1.TDEST_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC1.TID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC1.TUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC2.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC2.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC2.HAS_TKEEP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC2.HAS_TLAST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC2.HAS_TREADY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC2.HAS_TSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC2.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC2.LAYERED_METADATA">undef</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC2.PHASE">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC2.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC2.TDEST_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC2.TID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC2.TUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC3.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC3.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC3.HAS_TKEEP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC3.HAS_TLAST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC3.HAS_TREADY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC3.HAS_TSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC3.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC3.LAYERED_METADATA">undef</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC3.PHASE">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC3.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC3.TDEST_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC3.TID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC3.TUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC4.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC4.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC4.HAS_TKEEP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC4.HAS_TLAST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC4.HAS_TREADY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC4.HAS_TSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC4.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC4.LAYERED_METADATA">undef</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC4.PHASE">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC4.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC4.TDEST_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC4.TID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC4.TUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC5.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC5.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC5.HAS_TKEEP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC5.HAS_TLAST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC5.HAS_TREADY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC5.HAS_TSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC5.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC5.LAYERED_METADATA">undef</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC5.PHASE">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC5.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC5.TDEST_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC5.TID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC5.TUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC6.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC6.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC6.HAS_TKEEP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC6.HAS_TLAST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC6.HAS_TREADY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC6.HAS_TSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC6.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC6.LAYERED_METADATA">undef</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC6.PHASE">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC6.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC6.TDEST_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC6.TID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC6.TUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC7.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC7.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC7.HAS_TKEEP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC7.HAS_TLAST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC7.HAS_TREADY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC7.HAS_TSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC7.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC7.LAYERED_METADATA">undef</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC7.PHASE">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC7.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC7.TDEST_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC7.TID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_PFC7.TUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_TS.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_TS.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_TS.HAS_TKEEP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_TS.HAS_TLAST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_TS.HAS_TREADY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_TS.HAS_TSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_TS.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_TS.LAYERED_METADATA">undef</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_TS.PHASE">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_TS.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_TS.TDEST_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_TS.TID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RX_TS.TUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_TX_TS.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_TX_TS.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_TX_TS.HAS_TREADY">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_TX_TS.LAYERED_METADATA">undef</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_TX_TS.PHASE">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_TX_TS.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_TX_TS.TDEST_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_TX_TS.TID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_TX_TS.TUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_PORT"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.PHASE">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_AXI_RSTN.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_ACLK.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_ACLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_ACLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_ACLK.PHASE">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_USR_CLK2.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_USR_CLK2.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_USR_CLK2.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_USR_CLK2.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_USR_CLK2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC0.HAS_TKEEP" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC0.HAS_TLAST" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC0.HAS_TREADY" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC0.HAS_TSTRB" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC0.TDATA_NUM_BYTES" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC0.TDEST_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC0.TID_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC0.TUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC1.HAS_TKEEP" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC1.HAS_TLAST" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC1.HAS_TREADY" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC1.HAS_TSTRB" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC1.TDATA_NUM_BYTES" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC1.TDEST_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC1.TID_WIDTH" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC3.TDATA_NUM_BYTES" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC3.TDEST_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC3.TID_WIDTH" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC4.TDATA_NUM_BYTES" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC4.TDEST_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC4.TID_WIDTH" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC6.HAS_TSTRB" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC7.HAS_TKEEP" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC7.HAS_TLAST" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC7.HAS_TSTRB" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC7.TDATA_NUM_BYTES" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC7.TDEST_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC7.TID_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_TX_PFC7.TUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_MDIO" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Frame_Filter" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MAC_Speed" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Make_MDIO_External" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Management_Frequency" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Management_Interface" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Number_of_Table_Entries" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Physical_Interface" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Statistics_Counters" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
<xilinx:boundaryDescriptionInfo>
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;glbl_rstn&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;gtx_clk&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;inband_clock_speed&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;inband_duplex_status&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;inband_link_status&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;mac_irq&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;mdc&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;mdio&quot;:[{&quot;direction&quot;:&quot;inout&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;pause_req&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;pause_val&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;15&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;rgmii_rx_ctl
&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;rgmii_rxc&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;rgmii_rxd&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;rgmii_tx_ctl&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;rgmii_txc&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;rgmii_txd&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;rx_axi_rstn&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;rx_axis_mac_tdata&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;rx_axis_mac_tlast&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;rx_axis_mac_tuser&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;rx_axis_mac_tvalid&quot;:[{&quot;direction&quot;:&quot;o
ut&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;rx_mac_aclk&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;rx_reset&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;rx_statistics_valid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;rx_statistics_vector&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;27&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_aclk&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_araddr&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_arready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_arvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_awaddr&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_awready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physica
l_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_awvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_bready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_bresp&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_bvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_rdata&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_resetn&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_rready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_rresp&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_rvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_wdata&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;
:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_wready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_wvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;speedis100&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;speedis10100&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;tx_axi_rstn&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;tx_axis_mac_tdata&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;tx_axis_mac_tlast&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;tx_axis_mac_tready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;tx_axis_mac_tuser&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;tx_axis_mac_tvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;
,&quot;is_vector&quot;:&quot;false&quot;}],&quot;tx_ifg_delay&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;tx_mac_aclk&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;tx_reset&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;tx_statistics_valid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;tx_statistics_vector&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}]},&quot;interfaces&quot;:{&quot;glbl_rstn&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,
&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;glbl_rstn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;gtx_clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:
&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;125000000&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;gtx_clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]
}},&quot;m_axis_rx&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long
&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object
&quot;:false}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:[{&quot;physical_name&quot;:&quot;rx_axis_mac_tdata&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TLAST&quot;:[{&quot;physical_name&quot;:&quot;rx_axis_mac_tlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TUSER&quot;:[{&quot;physical_name&quot;:&quot;rx_axis_mac_tuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_
right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TVALID&quot;:[{&quot;physical_name&quot;:&quot;rx_axis_mac_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;mac_irq&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:interrupt:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:interrupt_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;PortWidth&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;SENSITIVITY&quot;:[{&quot;value&quot;:&quot;EDGE_RISING&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;INTERRUPT&quot;:[{&quot;physical_name&quot;:&quot;mac_irq&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;mdio_external&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:mdio:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:mdio_io:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,
&quot;parameters&quot;:{&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;MDIO_BOARD_INTERFACE&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;CAN_DEBUG&quot;:[{&quot;value&quot;:&quot;false&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;bool&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;IO&quot;:[{&quot;physical_name&quot;:&quot;mdio&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;MDC&quot;:[{&quot;physical_name&quot;:&quot;mdc&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;rgmii&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:rgmii:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:rgmii_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;ETHERNET_BOARD_INTERFACE&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;us
age&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RD&quot;:[{&quot;physical_name&quot;:&quot;rgmii_rxd&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RXC&quot;:[{&quot;physical_name&quot;:&quot;rgmii_rxc&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RX_CTL&quot;:[{&quot;physical_name&quot;:&quot;rgmii_rx_ctl&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TD&quot;:[{&quot;physical_name&quot;:&quot;rgmii_txd&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TXC&quot;:[{&quot;physical_name&quot;:&quot;rgmii_txc&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TX_CTL&quot;:[{&quot;physical_name&quot;:&quot;rgmii_tx_ctl&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;rgmii_status&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:display_tri_mode_ethernet
_mac:rgmii_status:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:display_tri_mode_ethernet_mac:rgmii_status_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;duplex_status&quot;:[{&quot;physical_name&quot;:&quot;inband_duplex_status&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;link_speed&quot;:[{&quot;physical_name&quot;:&quot;inband_clock_speed&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;link_status&quot;:[{&quot;physical_name&quot;:&quot;inband_link_status&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;rx_axi_rstn&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;,&quot;value_sr
c&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;rx_axi_rstn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;rx_mac_aclk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_ASYNC_RESET&quot;:[{&quot;value&quot;:&quot;rx_axi_rstn:rx_reset&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;m_axis_rx:m_axis_rx_ts:m_axis_rx_av:m_axis_rx_pfc0:m_axis_rx_pfc1:m_axis_rx_pfc2:m_axis_rx_pfc3:m_axis_rx_pfc4:m_axis_rx_pfc5:m_axis_rx_pfc6:m_axis_rx_pfc7&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:t
rue}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;125000000&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;defaul
t&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;rx_mac_aclk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;rx_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]}
,&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;rx_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;rx_statistics&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:display_tri_mode_ethernet_mac:statistics:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:display_tri_mode_ethernet_mac:statistics_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;statistics_data&quot;:[{&quot;physical_name&quot;:&quot;rx_statistics_vector&quot;,&quot;physical_left&quot;:&quot;27&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;27&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;statistics_valid&quot;:[{&quot;physical_name&quot;:&quot;rx_statistics_valid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;s_axi&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:aximm:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:aximm_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;12&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_
object&quot;:false}],&quot;ARUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;AWUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;BUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;
,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_BRESP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_BURST&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_CACHE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_LOCK&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_PROT&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;non
e&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_QOS&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_REGION&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_RRESP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_WSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;
value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;MAX_BURST_LENGTH&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;NUM_READ_OUTSTANDING&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;NUM_READ_THREADS&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;NUM_WRITE_OUTSTANDING&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;NUM_WRITE_THREADS&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permis
sion&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;AXI4LITE&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;RUSER_BITS_PER_BYTE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;RUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;forma
t&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;SUPPORTS_NARROW_BURST&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;WUSER_BITS_PER_BYTE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;WUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;ARADDR&quot;:[{&quot;physical_name&quot;:&quot;s_axi_araddr&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;11&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARREADY&quot;:[{&quot;physical_name&quot;:&quot;s_axi_arready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARVALID&quot;:[{&quot;physical_name&quot;:&quot;s_axi_
arvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWADDR&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awaddr&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;11&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWREADY&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWVALID&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BREADY&quot;:[{&quot;physical_name&quot;:&quot;s_axi_bready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BRESP&quot;:[{&quot;physical_name&quot;:&quot;s_axi_bresp&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BVALID&quot;:[{&quot;physical_name&quot;:&quot;s_axi_bvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;
none&quot;}],&quot;RDATA&quot;:[{&quot;physical_name&quot;:&quot;s_axi_rdata&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RREADY&quot;:[{&quot;physical_name&quot;:&quot;s_axi_rready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RRESP&quot;:[{&quot;physical_name&quot;:&quot;s_axi_rresp&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RVALID&quot;:[{&quot;physical_name&quot;:&quot;s_axi_rvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WDATA&quot;:[{&quot;physical_name&quot;:&quot;s_axi_wdata&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WREADY&quot;:[{&quot;physical_name&quot;:&quot;s_axi_wready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WVALID&quot;:[{&quot;physical_name&quot;:&quot;s_axi_wvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;lo
gical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;s_axi_aclk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;s_axi&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value
_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;s_axi_aclk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;s_axi_resetn&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[
{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;s_axi_resetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;s_axis_pause&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_i
nferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;u
ndef&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;2&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:
&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:[{&quot;physical_name&quot;:&quot;pause_val&quot;,&quot;physical_left&quot;:&quot;15&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;15&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TVALID&quot;:[{&quot;physical_name&quot;:&quot;pause_req&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;s_axis_tx&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type
&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred
&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:[{&quot;physical_name&quot;:
&quot;tx_axis_mac_tdata&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TLAST&quot;:[{&quot;physical_name&quot;:&quot;tx_axis_mac_tlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TREADY&quot;:[{&quot;physical_name&quot;:&quot;tx_axis_mac_tready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TUSER&quot;:[{&quot;physical_name&quot;:&quot;tx_axis_mac_tuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;TVALID&quot;:[{&quot;physical_name&quot;:&quot;tx_axis_mac_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;tx_axi_rstn&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;sim
ulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;tx_axi_rstn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;tx_mac_aclk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_ASYNC_RESET&quot;:[{&quot;value&quot;:&quot;tx_axi_rstn:tx_reset&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;s_axis_tx:m_axis_tx_ts:s_axis_tx_av:s_axis_pause:s_axis_tx_pfc0:s_axis_tx_pfc1:s_axis_tx_pfc2:s_axis_tx_pfc3:s_axis_tx_pfc4:s_axis_tx_pfc5:s_axis_tx_pfc6:s_axis_tx_pfc7&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_pe
rmission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;125000000&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;
:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;tx_mac_aclk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;tx_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permissi
on&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;tx_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;tx_statistics&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:display_tri_mode_ethernet_mac:statistics:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:display_tri_mode_ethernet_mac:statistics_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;statistics_data&quot;:[{&quot;physical_name&quot;:&quot;tx_statistics_vector&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;statistics_valid&quot;:[{&quot;physical_name&quot;:&quot;tx_statistics_valid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}}}}}"/>
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</spirit:design>

View File

@ -0,0 +1,840 @@
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View File

@ -0,0 +1,351 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/03/05 17:27:12
// Design Name:
// Module Name: AddrCho_mux
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module AddrCho_mux(
input clk,
input reset,
input [31:0] one_mux_thre,
input tx_fifo_0_empty,
input [31:0] tx_fifo_0_pkgcnt,
output tx_fifo_0_rden,
input [31:0] tx_fifo_0_rddata,
input tx_fifo_1_empty,
input [31:0] tx_fifo_1_pkgcnt,
output tx_fifo_1_rden,
input [31:0] tx_fifo_1_rddata,
input tx_fifo_2_empty,
input [31:0] tx_fifo_2_pkgcnt,
output tx_fifo_2_rden,
input [31:0] tx_fifo_2_rddata,
input tx_fifo_3_empty,
input [31:0] tx_fifo_3_pkgcnt,
output tx_fifo_3_rden,
input [31:0] tx_fifo_3_rddata,
input tx_fifo_4_empty,
input [31:0] tx_fifo_4_pkgcnt,
output tx_fifo_4_rden,
input [31:0] tx_fifo_4_rddata,
input tx_fifo_5_empty,
input [31:0] tx_fifo_5_pkgcnt,
output tx_fifo_5_rden,
input [31:0] tx_fifo_5_rddata,
input tx_fifo_6_empty,
input [31:0] tx_fifo_6_pkgcnt,
output tx_fifo_6_rden,
input [31:0] tx_fifo_6_rddata,
input tx_fifo_7_empty,
input [31:0] tx_fifo_7_pkgcnt,
output tx_fifo_7_rden,
input [31:0] tx_fifo_7_rddata,
input tx_fifo_8_empty,
input [31:0] tx_fifo_8_pkgcnt,
output tx_fifo_8_rden,
input [31:0] tx_fifo_8_rddata,
input [14:0] int_i,
input [3:0] int_rslt,
output reg clr,
input tcpip_tx_fifo_full,
input tcpip_tx_fifo_af,
// input [9:0] tcpip_tx_fifo_wrcnt,
output reg tcpip_tx_fifo_wren,
output reg [31:0] tcpip_tx_fifo_wrdata,
output tcpip_tx_fifo_last,
output [3:0] mux_state
);
localparam idle =4'd0,
chn_judge =4'd1,
send_cmd =4'd2,
send_len =4'd3,
send_data =4'd4,
send_rest =4'd5,
send_end =4'd6;
//localparam one_mux_thre =256;
///////////////////////////////////////////////////////////////
//reg wire
///////////////////////////////////////////////////////////////
wire tx_fifo_x_rden;
wire [31:0] tx_fifo_x_rddata;
wire [15:0] tx_fifo_x_pkgcnt;
wire user_data_vld;
wire [31:0] user_data;
wire user_all_empty;
wire tx_fifo_x_empty;
reg [3:0] state;
reg [3:0] int_rslt_reg;
reg [31:0] len_reg;
reg [31:0] pkgcnt_reg;
reg [31:0] i;
reg [31:0] j;
reg [31:0] checksum;
reg ready;
reg [31:0] total_cnt;
assign mux_state = state;
assign user_data_vld = tx_fifo_x_rden && (~tx_fifo_x_empty);
assign user_data = tx_fifo_x_rddata;
assign user_all_empty ={tx_fifo_8_empty,tx_fifo_7_empty,tx_fifo_6_empty,tx_fifo_5_empty,tx_fifo_4_empty,tx_fifo_3_empty,tx_fifo_2_empty,tx_fifo_1_empty,tx_fifo_0_empty}==9'b1_1111_1111; // ?????????<EFBFBD><EFBFBD>??<EFBFBD><EFBFBD>???: user_all_empty --> 0
//assign tcpip_space_enough =(tx_all-tcpip_tx_fifo_wrcnt) >=tx_half;
///////////////////////////////////////////////////////////////
//mux10_1
///////////////////////////////////////////////////////////////
assign tx_fifo_0_rden = int_rslt_reg[3:0] == 4'd0 ? tx_fifo_x_rden : 1'b0;
assign tx_fifo_1_rden = int_rslt_reg[3:0] == 4'd1 ? tx_fifo_x_rden : 1'b0;
assign tx_fifo_2_rden = int_rslt_reg[3:0] == 4'd2 ? tx_fifo_x_rden : 1'b0;
assign tx_fifo_3_rden = int_rslt_reg[3:0] == 4'd3 ? tx_fifo_x_rden : 1'b0;
assign tx_fifo_4_rden = int_rslt_reg[3:0] == 4'd4 ? tx_fifo_x_rden : 1'b0;
assign tx_fifo_5_rden = int_rslt_reg[3:0] == 4'd5 ? tx_fifo_x_rden : 1'b0;
assign tx_fifo_6_rden = int_rslt_reg[3:0] == 4'd6 ? tx_fifo_x_rden : 1'b0;
assign tx_fifo_7_rden = int_rslt_reg[3:0] == 4'd7 ? tx_fifo_x_rden : 1'b0;
assign tx_fifo_8_rden = int_rslt_reg[3:0] == 4'd8 ? tx_fifo_x_rden : 1'b0;
assign tx_fifo_x_rddata = int_rslt_reg[3:0] == 4'd0 ? tx_fifo_0_rddata :
int_rslt_reg[3:0] == 4'd1 ? tx_fifo_1_rddata :
int_rslt_reg[3:0] == 4'd2 ? tx_fifo_2_rddata :
int_rslt_reg[3:0] == 4'd3 ? tx_fifo_3_rddata :
int_rslt_reg[3:0] == 4'd4 ? tx_fifo_4_rddata :
int_rslt_reg[3:0] == 4'd5 ? tx_fifo_5_rddata :
int_rslt_reg[3:0] == 4'd6 ? tx_fifo_6_rddata :
int_rslt_reg[3:0] == 4'd7 ? tx_fifo_7_rddata :
int_rslt_reg[3:0] == 4'd8 ? tx_fifo_8_rddata : 0;
assign tx_fifo_x_pkgcnt = int_rslt_reg[3:0] == 4'd0 ? tx_fifo_0_pkgcnt :
int_rslt_reg[3:0] == 4'd1 ? tx_fifo_1_pkgcnt :
int_rslt_reg[3:0] == 4'd2 ? tx_fifo_2_pkgcnt :
int_rslt_reg[3:0] == 4'd3 ? tx_fifo_3_pkgcnt :
int_rslt_reg[3:0] == 4'd4 ? tx_fifo_4_pkgcnt :
int_rslt_reg[3:0] == 4'd5 ? tx_fifo_5_pkgcnt :
int_rslt_reg[3:0] == 4'd6 ? tx_fifo_6_pkgcnt :
int_rslt_reg[3:0] == 4'd7 ? tx_fifo_7_pkgcnt :
int_rslt_reg[3:0] == 4'd8 ? tx_fifo_8_pkgcnt :0;
assign tx_fifo_x_empty = int_rslt_reg[3:0] == 4'd0 ? tx_fifo_0_empty :
int_rslt_reg[3:0] == 4'd1 ? tx_fifo_1_empty :
int_rslt_reg[3:0] == 4'd2 ? tx_fifo_2_empty :
int_rslt_reg[3:0] == 4'd3 ? tx_fifo_3_empty :
int_rslt_reg[3:0] == 4'd4 ? tx_fifo_4_empty :
int_rslt_reg[3:0] == 4'd5 ? tx_fifo_5_empty :
int_rslt_reg[3:0] == 4'd6 ? tx_fifo_6_empty :
int_rslt_reg[3:0] == 4'd7 ? tx_fifo_7_empty :
int_rslt_reg[3:0] == 4'd8 ? tx_fifo_8_empty : 1;
assign tx_fifo_x_rden = ready & !tcpip_tx_fifo_af & !tcpip_tx_fifo_full & !user_all_empty;
always@(posedge clk)begin
if(reset)begin
state <=0;
ready <=0;
checksum <=0;
clr <=0;
i <=0;
j <=0;
len_reg <=0;
int_rslt_reg <=0;
tcpip_tx_fifo_wren <=0;
tcpip_tx_fifo_wrdata <=0;
total_cnt <=0;
end
else begin
case(state)
idle:
begin
tcpip_tx_fifo_wren <= 1'b0;
checksum <= 0;
if(int_i!=0 && int_rslt!=4'hf && !tcpip_tx_fifo_full && !tcpip_tx_fifo_af)begin
state <= chn_judge;
// int_rslt_reg <= int_rslt;
end
else begin
state <= idle;
end
end
chn_judge:
begin
// clr <= 1'b0;
// int_rslt_reg <= int_rslt;
// if(tx_fifo_x_pkgcnt != 0)
if(state == chn_judge)
begin
if(tcpip_tx_fifo_af || tcpip_tx_fifo_full)
begin
tcpip_tx_fifo_wren <= 1'b0;
end
else if(int_i!=0 && int_rslt!=4'hf)
begin
int_rslt_reg <= int_rslt;
state <= send_cmd;
ready <= 1'b1;
clr <= 1'b0;
if(tx_fifo_x_pkgcnt <= one_mux_thre)
begin
// total_cnt <= total_cnt + tx_fifo_x_pkgcnt;
pkgcnt_reg <= tx_fifo_x_pkgcnt; // ??????
end
else
begin
// total_cnt <= total_cnt + one_mux_thre;
pkgcnt_reg <= one_mux_thre;
end
end
end
else
begin
// state <= send_end;
state <= chn_judge;
end
end
send_cmd:
begin
if((!user_data_vld) || tcpip_tx_fifo_af || tcpip_tx_fifo_full)
begin
tcpip_tx_fifo_wren <= 1'b0;
end
else
begin
tcpip_tx_fifo_wren <= 1'b1;
state <= send_len;
tcpip_tx_fifo_wrdata <= user_data; // cmd
len_reg <= 1'b0;
clr <= 1'b1;
end
end
send_len:
begin
if(!user_data_vld)
begin
tcpip_tx_fifo_wren <= 1'b0;
end
else
begin
clr <= 1'b1;
tcpip_tx_fifo_wren <= 1'b1;
tcpip_tx_fifo_wrdata <= user_data; // length
i <= 1;
len_reg <= user_data[19:0] >> 2;
if(user_data[19:0] == 32'd4)
begin
state <= send_rest;
end
else
begin
state <= send_data;
end
end
end
send_data:begin
if(user_data_vld )
begin
tcpip_tx_fifo_wren <= 1'b1;
tcpip_tx_fifo_wrdata <= user_data;
clr <= 1'b1;
if(i == (len_reg - 1)) // ???????<EFBFBD><EFBFBD>??
begin
i <= 0;
state <= send_rest;
end
else begin
i <= i+1;
state <= send_data;
end
end
else begin
i <= i;
tcpip_tx_fifo_wren <=1'b0;
end
end
send_rest:
begin
if(user_data_vld )
begin
tcpip_tx_fifo_wren <= 1'b1;
tcpip_tx_fifo_wrdata <= user_data;
clr <= 1'b0;
ready <= 1'b0;
j <= 0;
state <= send_end;
// if(int_i!=0 && int_rslt!=4'hf)
// begin
// state <= chn_judge;
// end
// else
// begin
// state <= send_end;
// end
end
else
begin
tcpip_tx_fifo_wren <= 1'b0;
end
end
send_end:
begin
tcpip_tx_fifo_wren <= 1'b0;
state <=idle;
clr <= 1'b0;
end
endcase
end
end
assign tcpip_tx_fifo_last = (state == send_end) ? 1'b1 : 1'b0;
ila_AddrCho_mux ila_AddrCho_mux_u(
.clk(clk),
.probe0({int_rslt_reg,int_rslt,tx_fifo_0_pkgcnt,tx_fifo_x_rden,ready,tcpip_tx_fifo_af,tcpip_tx_fifo_full,user_all_empty,state,tcpip_tx_fifo_wren,tx_fifo_0_empty,tx_fifo_1_empty,tx_fifo_2_empty,tx_fifo_3_empty,tx_fifo_4_empty,tcpip_tx_fifo_wrdata,user_data}), // 119
.probe1({user_data_vld,i,len_reg}),
.probe2({
tx_fifo_0_empty,
tx_fifo_0_rden,
tx_fifo_0_rddata,
tx_fifo_x_rden,
tx_fifo_x_empty
})
);
endmodule

View File

@ -0,0 +1,223 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/03/05 16:54:06
// Design Name:
// Module Name: AddrCho_mux_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module AddrCho_mux_top(
input clk,
input reset,
input [31:0] ch0_thre,
input [31:0] ch1_thre,
input [31:0] ch2_thre,
input [31:0] ch3_thre,
input [31:0] ch4_thre,
input [31:0] ch5_thre,
input [31:0] ch6_thre,
input [31:0] ch7_thre,
input [31:0] ch8_thre,
input [31:0] one_mux_thre,
input [31:0] int_mode,
input tx_fifo_0_empty,
input [31:0] tx_fifo_0_pkgcnt,
output tx_fifo_0_rden,
input [31:0] tx_fifo_0_rddata,
input tx_fifo_1_empty,
input [31:0] tx_fifo_1_pkgcnt,
output tx_fifo_1_rden,
input [31:0] tx_fifo_1_rddata,
input tx_fifo_2_empty,
input [31:0] tx_fifo_2_pkgcnt,
output tx_fifo_2_rden,
input [31:0] tx_fifo_2_rddata,
input tx_fifo_3_empty,
input [31:0] tx_fifo_3_pkgcnt,
output tx_fifo_3_rden,
input [31:0] tx_fifo_3_rddata,
input tx_fifo_4_empty,
input [31:0] tx_fifo_4_pkgcnt,
output tx_fifo_4_rden,
input [31:0] tx_fifo_4_rddata,
input tx_fifo_5_empty ,
input [31:0] tx_fifo_5_pkgcnt ,
output tx_fifo_5_rden ,
input [31:0] tx_fifo_5_rddata ,
input tx_fifo_6_empty ,
input [31:0] tx_fifo_6_pkgcnt ,
output tx_fifo_6_rden ,
input [31:0] tx_fifo_6_rddata ,
input tx_fifo_7_empty ,
input [31:0] tx_fifo_7_pkgcnt ,
output tx_fifo_7_rden ,
input [31:0] tx_fifo_7_rddata ,
input tx_fifo_8_empty ,
input [31:0] tx_fifo_8_pkgcnt ,
output tx_fifo_8_rden ,
input [31:0] tx_fifo_8_rddata ,
input tcpip_tx_fifo_full,
input tcpip_tx_fifo_af,
// input [9:0] tcpip_tx_fifo_wrcnt,
output tcpip_tx_fifo_wren,
output [31:0] tcpip_tx_fifo_wrdata,
output tcpip_tx_fifo_last,
output [3:0] mux_state
);
wire [8:0] empty;
wire [14:0] int_;
wire [3:0] int_rslt;
wire clr;
wire tx_fifo_0_empty_r;
wire tx_fifo_1_empty_r;
wire tx_fifo_2_empty_r;
wire tx_fifo_3_empty_r;
wire tx_fifo_4_empty_r;
wire tx_fifo_5_empty_r;
wire tx_fifo_6_empty_r;
wire tx_fifo_7_empty_r;
wire tx_fifo_8_empty_r;
assign tx_fifo_0_empty_r = (tx_fifo_0_pkgcnt == 32'b0) ? 1'b1 : 1'b0;
assign tx_fifo_1_empty_r = (tx_fifo_1_pkgcnt == 32'b0) ? 1'b1 : 1'b0;
assign tx_fifo_2_empty_r = (tx_fifo_2_pkgcnt == 32'b0) ? 1'b1 : 1'b0;
assign tx_fifo_3_empty_r = (tx_fifo_3_pkgcnt == 32'b0) ? 1'b1 : 1'b0;
assign tx_fifo_4_empty_r = (tx_fifo_4_pkgcnt == 32'b0) ? 1'b1 : 1'b0;
assign tx_fifo_5_empty_r = (tx_fifo_5_pkgcnt == 32'b0) ? 1'b1 : 1'b0;
assign tx_fifo_6_empty_r = (tx_fifo_6_pkgcnt == 32'b0) ? 1'b1 : 1'b0;
assign tx_fifo_7_empty_r = (tx_fifo_7_pkgcnt == 32'b0) ? 1'b1 : 1'b0;
assign tx_fifo_8_empty_r = (tx_fifo_8_pkgcnt == 32'b0) ? 1'b1 : 1'b0;
assign empty = {tx_fifo_8_empty_r,tx_fifo_7_empty_r,tx_fifo_6_empty_r,tx_fifo_5_empty_r,tx_fifo_4_empty_r,tx_fifo_3_empty_r,tx_fifo_2_empty_r,tx_fifo_1_empty_r,tx_fifo_0_empty_r};
send_int_gen_5ch send_int_gen_5ch_u(
.clk (clk ),
.nrst (~reset ),
.int_mode (int_mode ),
.ch0_thre (ch0_thre ),
.ch1_thre (ch1_thre ),
.ch2_thre (ch2_thre ),
.ch3_thre (ch3_thre ),
.ch4_thre (ch4_thre ),
.ch5_thre (ch5_thre ),
.ch6_thre (ch6_thre ),
.ch7_thre (ch7_thre ),
.ch8_thre (ch8_thre ),
.tx_fifo_0_empty (tx_fifo_0_empty_r ),
.tx_fifo_0_pkgcnt (tx_fifo_0_pkgcnt ),
.tx_fifo_1_empty (tx_fifo_1_empty_r ),
.tx_fifo_1_pkgcnt (tx_fifo_1_pkgcnt ),
.tx_fifo_2_empty (tx_fifo_2_empty_r ),
.tx_fifo_2_pkgcnt (tx_fifo_2_pkgcnt ),
.tx_fifo_3_empty (tx_fifo_3_empty_r ),
.tx_fifo_3_pkgcnt (tx_fifo_3_pkgcnt ),
.tx_fifo_4_empty (tx_fifo_4_empty_r ),
.tx_fifo_4_pkgcnt (tx_fifo_4_pkgcnt ),
.tx_fifo_5_empty (tx_fifo_5_empty_r ),
.tx_fifo_5_pkgcnt (tx_fifo_5_pkgcnt ),
.tx_fifo_6_empty (tx_fifo_6_empty_r ),
.tx_fifo_6_pkgcnt (tx_fifo_6_pkgcnt ),
.tx_fifo_7_empty (tx_fifo_7_empty_r ),
.tx_fifo_7_pkgcnt (tx_fifo_7_pkgcnt ),
.tx_fifo_8_empty (tx_fifo_8_empty_r ),
.tx_fifo_8_pkgcnt (tx_fifo_8_pkgcnt ),
.int_o (int_ )
);
int_arbitor int_arbitor (
.clk (clk ),
.nrst (~reset ),
.empty ({6'b11_1111,empty} ),
.int_i (int_ ),
.int_rslt (int_rslt ),
.clr (clr )
);
AddrCho_mux AddrCho_mux_u(
.clk (clk),
.reset (reset),
.one_mux_thre (one_mux_thre),
.tx_fifo_0_empty (tx_fifo_0_empty),
.tx_fifo_0_pkgcnt (tx_fifo_0_pkgcnt),
.tx_fifo_0_rden (tx_fifo_0_rden),
.tx_fifo_0_rddata (tx_fifo_0_rddata),
.tx_fifo_1_empty (tx_fifo_1_empty),
.tx_fifo_1_pkgcnt (tx_fifo_1_pkgcnt),
.tx_fifo_1_rden (tx_fifo_1_rden),
.tx_fifo_1_rddata (tx_fifo_1_rddata),
.tx_fifo_2_empty (tx_fifo_2_empty),
.tx_fifo_2_pkgcnt (tx_fifo_2_pkgcnt),
.tx_fifo_2_rden (tx_fifo_2_rden),
.tx_fifo_2_rddata (tx_fifo_2_rddata),
.tx_fifo_3_empty (tx_fifo_3_empty),
.tx_fifo_3_pkgcnt (tx_fifo_3_pkgcnt),
.tx_fifo_3_rden (tx_fifo_3_rden),
.tx_fifo_3_rddata (tx_fifo_3_rddata),
.tx_fifo_4_empty (tx_fifo_4_empty),
.tx_fifo_4_pkgcnt (tx_fifo_4_pkgcnt),
.tx_fifo_4_rden (tx_fifo_4_rden),
.tx_fifo_4_rddata (tx_fifo_4_rddata),
.tx_fifo_5_empty (tx_fifo_5_empty),
.tx_fifo_5_pkgcnt (tx_fifo_5_pkgcnt),
.tx_fifo_5_rden (tx_fifo_5_rden),
.tx_fifo_5_rddata (tx_fifo_5_rddata),
.tx_fifo_6_empty (tx_fifo_6_empty),
.tx_fifo_6_pkgcnt (tx_fifo_6_pkgcnt),
.tx_fifo_6_rden (tx_fifo_6_rden),
.tx_fifo_6_rddata (tx_fifo_6_rddata),
.tx_fifo_7_empty (tx_fifo_7_empty),
.tx_fifo_7_pkgcnt (tx_fifo_7_pkgcnt),
.tx_fifo_7_rden (tx_fifo_7_rden),
.tx_fifo_7_rddata (tx_fifo_7_rddata),
.tx_fifo_8_empty (tx_fifo_8_empty),
.tx_fifo_8_pkgcnt (tx_fifo_8_pkgcnt),
.tx_fifo_8_rden (tx_fifo_8_rden),
.tx_fifo_8_rddata (tx_fifo_8_rddata),
.int_i ({10'b0,int_}),
.int_rslt (int_rslt),
.clr (clr),
.tcpip_tx_fifo_full (tcpip_tx_fifo_full),
.tcpip_tx_fifo_af (tcpip_tx_fifo_af),
// .tcpip_tx_fifo_wrcnt (tcpip_tx_fifo_wrcnt),
.tcpip_tx_fifo_wren (tcpip_tx_fifo_wren),
.tcpip_tx_fifo_wrdata (tcpip_tx_fifo_wrdata),
.tcpip_tx_fifo_last (tcpip_tx_fifo_last),
.mux_state (mux_state)
);
endmodule

View File

@ -0,0 +1,737 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/03/03 14:46:04
// Design Name:
// Module Name: AddrCho
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module AddrCho_rx(
input clk_187m ,
input reset ,
output slot ,
// //**************tx interface********************** 上行的数是按照top模块的时钟给出去需要fifo转一下时钟
// input s0_user_tx_fifo_rdclk,
// output [11:0] s0_user_tx_fifo_rdcnt,
// input s0_user_tx_fifo_rden, // 标志 tcp 是否从这里拿数
// output [31:0] s0_user_tx_fifo_rddata,
// output s0_tx_m_axis_tvalid,
//**************rx interface********************** 下行的数是按照mux模块给的时钟给的所以时钟是不需要再转换
// output s0_user_rx_fifo_rdclk,
// input s0_user_rx_fifo_valid,
// output s0_user_rx_fifo_rden,
// input [31:0] s0_user_rx_fifo_rddata,
input s0_user_rx_tvalid ,
output s0_user_rx_tready ,
input [ 63: 0] s0_user_rx_tdata ,
input [ 7: 0] s0_user_rx_tkeep ,
input s0_user_rx_tlast ,
// 分接
// attenuator
// input atten_rx_in_fifo_rden,
// output [31:0] atten_rx_in_fifo_data,
// output atten_rx_in_fifo_full,
input atten_rx_in_fifo_ready ,
output [ 31: 0] atten_rx_in_fifo_data ,
output atten_rx_in_fifo_valid ,
output [ 9: 0] atten_rx_axis_rd_data_count,
//spi
// input c0_rx_in_fifo_rden,
// output [31:0] c0_rx_in_fifo_data,
// output c0_rx_in_fifo_full,
input c0_rx_in_fifo_ready ,
output [ 31: 0] c0_rx_in_fifo_data ,
output c0_rx_in_fifo_valid ,
output [ 9: 0] c0_rx_axis_rd_data_count ,
// input c1_rx_in_fifo_rden,
// output [31:0] c1_rx_in_fifo_data,
// output c1_rx_in_fifo_full,
input c1_rx_in_fifo_ready ,
output [ 31: 0] c1_rx_in_fifo_data ,
output c1_rx_in_fifo_valid ,
output [ 9: 0] c1_rx_axis_rd_data_count ,
// input c2_rx_in_fifo_rden,
// output [31:0] c2_rx_in_fifo_data,
// output c2_rx_in_fifo_full,
input c2_rx_in_fifo_ready ,
output [ 31: 0] c2_rx_in_fifo_data ,
output c2_rx_in_fifo_valid ,
output [ 9: 0] c2_rx_axis_rd_data_count ,
// input c3_rx_in_fifo_rden,
// output [31:0] c3_rx_in_fifo_data,
// output c3_rx_in_fifo_full,
input c3_rx_in_fifo_ready ,
output [ 31: 0] c3_rx_in_fifo_data ,
output c3_rx_in_fifo_valid ,
output [ 9: 0] c3_rx_axis_rd_data_count ,
// input c4_rx_in_fifo_rden,
// output [31:0] c4_rx_in_fifo_data,
// output c4_rx_in_fifo_full,
input c4_rx_in_fifo_ready ,
output [ 31: 0] c4_rx_in_fifo_data ,
output c4_rx_in_fifo_valid ,
output [ 9: 0] c4_rx_axis_rd_data_count ,
// input c4_rx_in_fifo_rden,
// output [31:0] c4_rx_in_fifo_data,
// output c4_rx_in_fifo_full,
input c5_rx_in_fifo_ready ,
output [ 31: 0] c5_rx_in_fifo_data ,
output c5_rx_in_fifo_valid ,
output [ 9: 0] c5_rx_axis_rd_data_count
);
wire [31 : 0] rx_in_fifo_data;
reg rx_in_fifo_rden ;
wire rx_in_fifo_full;
wire rx_in_fifo_empty;
wire [9 :0] wr_data_count;
wire [9 :0] rd_data_count;
//assign s0_user_rx_fifo_rdclk = clk_187m; // 读数据就用系统时钟
//assign s0_user_rx_fifo_rden = ~rx_in_fifo_full;
reg cx_rx_in_fifo_full;
wire m0_user_rx_tvalid;
wire m0_user_rx_tready;
wire [63:0]m0_user_rx_tdata ;
wire [7:0] m0_user_rx_tkeep ;
wire m0_user_rx_tlast ;
wire [31:0]axis_wr_data_count ;
wire [31:0]axis_rd_data_count ;
wire prog_full;
wire s0_user_rx_tready_o;
axis_data_fifo_addrcho axis_data_fifo_addrcho_rx_in(
.s_axis_aresetn(~reset), // input
.s_axis_aclk (clk_187m), // input
.s_axis_tvalid (s0_user_rx_tvalid && (~prog_full)), // input
.s_axis_tready (s0_user_rx_tready_o), // output
.s_axis_tdata (s0_user_rx_tdata ), // input [63:0]
.s_axis_tkeep (s0_user_rx_tkeep ), // input [7:0]
.s_axis_tlast (s0_user_rx_tlast ), // input
.axis_wr_data_count(axis_wr_data_count),
.axis_rd_data_count(axis_rd_data_count),
.prog_full(prog_full),
.m_axis_aclk (clk_187m), // input
.m_axis_tvalid (m0_user_rx_tvalid), // output
.m_axis_tready (m0_user_rx_tready), // input
.m_axis_tdata (m0_user_rx_tdata ), // output [63:0]
.m_axis_tkeep (m0_user_rx_tkeep ), // output [7:0]
.m_axis_tlast (m0_user_rx_tlast ) // output
);
assign s0_user_rx_tready = s0_user_rx_tready_o && (~prog_full);
wire width_m_axis_tvalid;
//wire width_m_axis_tready; // 用下一级FIFO
wire [31:0]width_m_axis_tdata ;
wire [3:0] width_m_axis_tkeep ;
wire width_m_axis_tlast ;
wire [63:0]m0_user_rx_tdata_w;
wire [7:0] m0_user_rx_tkeep_w;
assign m0_user_rx_tdata_w = {m0_user_rx_tdata[31:0],m0_user_rx_tdata[63:32]}; // 经过width converter高低位会反
assign m0_user_rx_tkeep_w = {m0_user_rx_tkeep[3:0],m0_user_rx_tkeep[7:4]};
axis_dwidth_converter_5 axis_dwidth_converter_5_addrcho_rx(
.aclk (clk_187m), // input
.aresetn (~reset), // input
.s_axis_tvalid(m0_user_rx_tvalid), // input
.s_axis_tready(m0_user_rx_tready), // output aurora不具备缓存数据的能力不论FIFO是否ready无条件接收数据
.s_axis_tdata (m0_user_rx_tdata_w ), // input [63:0]
.s_axis_tkeep (m0_user_rx_tkeep_w ), // input [7:0]
.s_axis_tlast (m0_user_rx_tlast ), // input
.m_axis_tvalid(width_m_axis_tvalid), // output
.m_axis_tready((~rx_in_fifo_full) ), // input
.m_axis_tdata (width_m_axis_tdata ), // output [31:0]
.m_axis_tkeep (width_m_axis_tkeep ), // output [3:0]
.m_axis_tlast (width_m_axis_tlast ) // output
);
fifo_generator_2 fifo_generator_2_rx(
.rst (reset), // input
.wr_clk(clk_187m), // input
.rd_clk(clk_187m), // input
.din (width_m_axis_tdata), // input [31:0]
.wr_en (width_m_axis_tvalid && width_m_axis_tkeep && (~rx_in_fifo_full)), // input 增加 width_m_axis_tkeep 的判断会输出keep=0,但valid=1的情况
.rd_en (rx_in_fifo_rden && (~cx_rx_in_fifo_full)), // input
.dout (rx_in_fifo_data), // output [31:0]
.full (), // output
.empty (rx_in_fifo_empty), // output
.prog_full(rx_in_fifo_full),
.rd_data_count(rd_data_count),
.wr_data_count(wr_data_count)
);
// attenuator
wire atten_rx_in_fifo_rden;
wire atten_rx_in_fifo_full;
wire atten_rx_in_fifo_empty;
//spi
wire c0_rx_in_fifo_rden;
wire c0_rx_in_fifo_full;
wire c0_rx_in_fifo_empty;
wire c1_rx_in_fifo_rden;
wire c1_rx_in_fifo_full;
wire c1_rx_in_fifo_empty;
wire c2_rx_in_fifo_rden;
wire c2_rx_in_fifo_full;
wire c2_rx_in_fifo_empty;
wire c3_rx_in_fifo_rden;
wire c3_rx_in_fifo_full;
wire c3_rx_in_fifo_empty;
wire c4_rx_in_fifo_rden;
wire c4_rx_in_fifo_full;
wire c4_rx_in_fifo_empty;
wire c5_rx_in_fifo_rden;
wire c5_rx_in_fifo_full;
wire c5_rx_in_fifo_empty;
//assign atten_rx_in_fifo_valid = ~atten_rx_in_fifo_full && (~atten_rx_in_fifo_empty);
//assign atten_rx_in_fifo_rden = atten_rx_in_fifo_ready & atten_rx_in_fifo_valid;
//
//assign c0_rx_in_fifo_valid = ~c0_rx_in_fifo_full && (~c0_rx_in_fifo_empty);
//assign c0_rx_in_fifo_rden = c0_rx_in_fifo_ready & c0_rx_in_fifo_valid;
//
//assign c1_rx_in_fifo_valid = ~c1_rx_in_fifo_full && (~c1_rx_in_fifo_empty);
//assign c1_rx_in_fifo_rden = c1_rx_in_fifo_ready & c1_rx_in_fifo_valid;
//
//assign c2_rx_in_fifo_valid = ~c2_rx_in_fifo_full && (~c2_rx_in_fifo_empty);
//assign c2_rx_in_fifo_rden = c2_rx_in_fifo_ready & c2_rx_in_fifo_valid;
//
//assign c3_rx_in_fifo_valid = ~c3_rx_in_fifo_full && (~c3_rx_in_fifo_empty);
//assign c3_rx_in_fifo_rden = c3_rx_in_fifo_ready & c3_rx_in_fifo_valid;
//
//assign c4_rx_in_fifo_valid = ~c4_rx_in_fifo_full && (~c4_rx_in_fifo_empty);
//assign c4_rx_in_fifo_rden = c4_rx_in_fifo_ready & c4_rx_in_fifo_valid;
assign atten_rx_in_fifo_valid = (~atten_rx_in_fifo_empty);
assign atten_rx_in_fifo_rden = atten_rx_in_fifo_ready & atten_rx_in_fifo_valid;
assign c0_rx_in_fifo_valid = (~c0_rx_in_fifo_empty);
assign c0_rx_in_fifo_rden = c0_rx_in_fifo_ready & c0_rx_in_fifo_valid;
assign c1_rx_in_fifo_valid = (~c1_rx_in_fifo_empty);
assign c1_rx_in_fifo_rden = c1_rx_in_fifo_ready & c1_rx_in_fifo_valid;
assign c2_rx_in_fifo_valid = (~c2_rx_in_fifo_empty);
assign c2_rx_in_fifo_rden = c2_rx_in_fifo_ready & c2_rx_in_fifo_valid;
assign c3_rx_in_fifo_valid = (~c3_rx_in_fifo_empty);
assign c3_rx_in_fifo_rden = c3_rx_in_fifo_ready & c3_rx_in_fifo_valid;
assign c4_rx_in_fifo_valid = (~c4_rx_in_fifo_empty);
assign c4_rx_in_fifo_rden = c4_rx_in_fifo_ready & c4_rx_in_fifo_valid;
assign c5_rx_in_fifo_valid = (~c5_rx_in_fifo_empty);
assign c5_rx_in_fifo_rden = c5_rx_in_fifo_ready & c5_rx_in_fifo_valid;
reg [31 : 0] rx_in_fifo_data_r1;
reg [31 : 0] rx_in_fifo_data_r2;
reg [31 : 0] rx_in_fifo_data_r3;
reg rx_in_fifo_valid_r1;
reg rx_in_fifo_valid_r2;
reg rx_in_fifo_valid_r3;
wire rx_in_fifo_valid_cx;
reg rx_in_fifo_valid_cx_r;
reg atten_tcp_rx_fifo_valid;
reg [31:0] atten_tcp_rx_fifo_rddata;
reg c0_tcp_rx_fifo_valid;
reg [31:0] c0_tcp_rx_fifo_rddata;
reg c1_tcp_rx_fifo_valid;
reg [31:0] c1_tcp_rx_fifo_rddata;
reg c2_tcp_rx_fifo_valid;
reg [31:0] c2_tcp_rx_fifo_rddata;
reg c3_tcp_rx_fifo_valid;
reg [31:0] c3_tcp_rx_fifo_rddata;
reg c4_tcp_rx_fifo_valid;
reg [31:0] c4_tcp_rx_fifo_rddata;
reg c5_tcp_rx_fifo_valid;
reg [31:0] c5_tcp_rx_fifo_rddata;
reg [19 : 0] rx_pkg_length;
reg [17 : 0] rx_pkg_cnt;
wire [17 : 0] rx_pkg_cnt_end;
reg [17 : 0] rx_pkg_cnt_r;
reg [2 : 0] rx_pkg_exaddr;
reg rx_pkg_wr;
//reg rx_pkg_valid;
always@(posedge clk_187m)
begin
if(reset)
begin
rx_in_fifo_rden <= 1'b0;
end
else if((rx_pkg_cnt == 18'b0) && (rx_pkg_cnt_r == 18'b0))
begin
rx_in_fifo_rden <= 1'b1;
end
end
always@(posedge clk_187m)
begin
if(reset)
begin
rx_pkg_cnt <= 18'b0;
end
else if((rx_pkg_cnt == rx_pkg_cnt_end) && (rx_in_fifo_rden && (~rx_in_fifo_empty) && (~cx_rx_in_fifo_full))) // 等最后一个数输出完
begin
rx_pkg_cnt <= 18'b0;
end
else if(rx_in_fifo_rden && (~rx_in_fifo_empty) && (~cx_rx_in_fifo_full)) // 每一个有效的数加1
begin
rx_pkg_cnt <= rx_pkg_cnt + 18'b1;
end
end
//always@(posedge clk_187m)
//begin
// if(reset) // 等最后一个数输出完
// begin
// rx_pkg_cnt <= 18'b0;
// end
// else if(rx_pkg_wr && (rx_pkg_cnt == rx_pkg_cnt_end ) && rx_in_fifo_valid_cx )begin
// rx_pkg_cnt <= 18'b0;
// end
// else if(!rx_pkg_wr && (rx_pkg_cnt == rx_pkg_cnt_end) && rx_in_fifo_valid_cx && rx_pkg_cnt > 1 && (~cx_rx_in_fifo_full))begin
// rx_pkg_cnt <= 18'b0;
// end
// else if(rx_in_fifo_rden && (~rx_in_fifo_empty) && (~cx_rx_in_fifo_full))begin // 每一个有效的数加1
// rx_pkg_cnt <= rx_pkg_cnt + 18'b1;
// end
//end
assign rx_pkg_cnt_end = (rx_pkg_wr) ? 18'd1 : (rx_pkg_length + 18'd1);
always@(posedge clk_187m)
begin
if(reset)
begin
// rx_pkg_cnt_r <= 18'b0;
rx_in_fifo_data_r1 <= 32'b0;
// rx_in_fifo_data_r2 <= 32'b0;
// rx_in_fifo_valid_r1 <= 1'b0;
// rx_in_fifo_valid_r2 <= 1'b0;
end
else if(rx_in_fifo_rden && (~rx_in_fifo_empty)&& (~cx_rx_in_fifo_full))
begin
// rx_pkg_cnt_r <= rx_pkg_cnt;
rx_in_fifo_data_r1 <= rx_in_fifo_data;
// rx_in_fifo_data_r2 <= rx_in_fifo_data_r1;
// rx_in_fifo_valid_r1 <= rx_in_fifo_rden && (~rx_in_fifo_empty);
// rx_in_fifo_valid_r2 <= rx_in_fifo_valid_r1;
end
end
always@(posedge clk_187m)
begin
if(reset)
begin
rx_pkg_cnt_r <= 18'b0;
// rx_in_fifo_data_r1 <= 32'b0;
rx_in_fifo_data_r2 <= 32'b0;
rx_in_fifo_data_r3 <= 32'b0;
rx_in_fifo_valid_r1 <= 1'b0;
rx_in_fifo_valid_r2 <= 1'b0;
rx_in_fifo_valid_r3 <= 1'b0;
rx_in_fifo_valid_cx_r <= 1'b0;
end
else
begin
rx_pkg_cnt_r <= rx_pkg_cnt;
// rx_in_fifo_data_r1 <= rx_in_fifo_data;
rx_in_fifo_data_r2 <= rx_in_fifo_data_r1;
rx_in_fifo_data_r3 <= rx_in_fifo_data_r2;
rx_in_fifo_valid_r1 <= rx_in_fifo_rden && (~rx_in_fifo_empty) && (~cx_rx_in_fifo_full);
rx_in_fifo_valid_r2 <= rx_in_fifo_valid_r1;
rx_in_fifo_valid_r3 <= rx_in_fifo_valid_r2;
rx_in_fifo_valid_cx_r <= rx_in_fifo_valid_cx;
end
end
assign rx_in_fifo_valid_cx = rx_in_fifo_valid_r1;
reg [4: 0] rx_pkg_slot;
always@(posedge clk_187m)
begin
// if(reset || ((rx_pkg_cnt == rx_pkg_cnt_end) && rx_in_fifo_valid_cx_r)) // 输出最后一个数
if(reset) // 输出最后一个数
begin
rx_pkg_length <= 20'b1;
rx_pkg_exaddr <= 'b0;
rx_pkg_wr <= 1'b0;
end
else if((rx_pkg_cnt == 18'b0) && (rx_in_fifo_rden && (~rx_in_fifo_empty) && (~cx_rx_in_fifo_full))) // cmd
begin
rx_pkg_wr <= rx_in_fifo_data[31];
end
else if((rx_pkg_cnt == 18'b1) && (rx_in_fifo_rden && (~rx_in_fifo_empty) && (~cx_rx_in_fifo_full)))
begin
rx_pkg_length <= rx_in_fifo_data[19:0] >> 2;
rx_pkg_exaddr <= rx_in_fifo_data[22:20];
rx_pkg_slot <= rx_in_fifo_data[27:23];
end
end
assign slot = rx_pkg_slot == 5'd4 ? 0
: rx_pkg_slot == 5'd15 ? 1
: 0;
always@(posedge clk_187m)
begin
if(reset || (rx_pkg_length == 20'b0))
begin
atten_tcp_rx_fifo_valid <= 1'b0;
atten_tcp_rx_fifo_rddata <= 32'b0;
c0_tcp_rx_fifo_valid <= 1'b0;
c0_tcp_rx_fifo_rddata <= 32'b0;
c1_tcp_rx_fifo_valid <= 1'b0;
c1_tcp_rx_fifo_rddata <= 32'b0;
c2_tcp_rx_fifo_valid <= 1'b0;
c2_tcp_rx_fifo_rddata <= 32'b0;
c3_tcp_rx_fifo_valid <= 1'b0;
c3_tcp_rx_fifo_rddata <= 32'b0;
c4_tcp_rx_fifo_valid <= 1'b0;
c4_tcp_rx_fifo_rddata <= 32'b0;
c5_tcp_rx_fifo_valid <= 1'b0;
c5_tcp_rx_fifo_rddata <= 32'b0;
// cx_rx_in_fifo_full <= 1'b0;
end
else if(rx_pkg_length > 20'b0)
begin
case(rx_pkg_exaddr)
12'b0:
begin
c0_tcp_rx_fifo_valid <= rx_in_fifo_valid_r2;
c0_tcp_rx_fifo_rddata <= rx_in_fifo_data_r2;
// cx_rx_in_fifo_full <= c0_rx_in_fifo_full;
atten_tcp_rx_fifo_valid <= 1'b0;
c1_tcp_rx_fifo_valid <= 1'b0;
c2_tcp_rx_fifo_valid <= 1'b0;
c3_tcp_rx_fifo_valid <= 1'b0;
c4_tcp_rx_fifo_valid <= 1'b0;
c5_tcp_rx_fifo_valid <= 1'b0;
end
12'b1:
begin
c1_tcp_rx_fifo_valid <= rx_in_fifo_valid_cx_r; // rx_in_fifo_valid_r2
c1_tcp_rx_fifo_rddata <= rx_in_fifo_data_r2;
// cx_rx_in_fifo_full <= c1_rx_in_fifo_full;
atten_tcp_rx_fifo_valid <= 1'b0;
c0_tcp_rx_fifo_valid <= 1'b0;
c2_tcp_rx_fifo_valid <= 1'b0;
c3_tcp_rx_fifo_valid <= 1'b0;
c4_tcp_rx_fifo_valid <= 1'b0;
c5_tcp_rx_fifo_valid <= 1'b0;
end
12'd2:
begin
c2_tcp_rx_fifo_valid <= rx_in_fifo_valid_cx_r;
c2_tcp_rx_fifo_rddata <= rx_in_fifo_data_r2;
// cx_rx_in_fifo_full <= c2_rx_in_fifo_full;
atten_tcp_rx_fifo_valid <= 1'b0;
c0_tcp_rx_fifo_valid <= 1'b0;
c1_tcp_rx_fifo_valid <= 1'b0;
c3_tcp_rx_fifo_valid <= 1'b0;
c4_tcp_rx_fifo_valid <= 1'b0;
c5_tcp_rx_fifo_valid <= 1'b0;
end
12'd3:
begin
c3_tcp_rx_fifo_valid <= rx_in_fifo_valid_cx_r;
c3_tcp_rx_fifo_rddata <= rx_in_fifo_data_r2;
// cx_rx_in_fifo_full <= c3_rx_in_fifo_full;
atten_tcp_rx_fifo_valid <= 1'b0;
c0_tcp_rx_fifo_valid <= 1'b0;
c1_tcp_rx_fifo_valid <= 1'b0;
c2_tcp_rx_fifo_valid <= 1'b0;
c4_tcp_rx_fifo_valid <= 1'b0;
c5_tcp_rx_fifo_valid <= 1'b0;
end
// 12'd4:
12'd7: //固件更新Bin
begin
c4_tcp_rx_fifo_valid <= rx_in_fifo_valid_cx_r;
c4_tcp_rx_fifo_rddata <= rx_in_fifo_data_r2;
// cx_rx_in_fifo_full <= c4_rx_in_fifo_full;
atten_tcp_rx_fifo_valid <= 1'b0;
c0_tcp_rx_fifo_valid <= 1'b0;
c1_tcp_rx_fifo_valid <= 1'b0;
c2_tcp_rx_fifo_valid <= 1'b0;
c3_tcp_rx_fifo_valid <= 1'b0;
c5_tcp_rx_fifo_valid <= 1'b0;
end
12'd5: //寄存器读写固件更新命令状态读取等
begin
c5_tcp_rx_fifo_valid <= rx_in_fifo_valid_cx_r;
c5_tcp_rx_fifo_rddata <= rx_in_fifo_data_r2;
// cx_rx_in_fifo_full <= c4_rx_in_fifo_full;
atten_tcp_rx_fifo_valid <= 1'b0;
c0_tcp_rx_fifo_valid <= 1'b0;
c1_tcp_rx_fifo_valid <= 1'b0;
c2_tcp_rx_fifo_valid <= 1'b0;
c3_tcp_rx_fifo_valid <= 1'b0;
c4_tcp_rx_fifo_valid <= 1'b0;
end
/*
12'd10,12'd11,12'd12,12'd13,12'd14,12'd15,12'd16,12'd17,12'd18,12'd19:
begin
atten_tcp_rx_fifo_valid <= rx_in_fifo_valid_r2;
atten_tcp_rx_fifo_rddata <= rx_in_fifo_data_r2;
c0_tcp_rx_fifo_valid <= 1'b0;
c1_tcp_rx_fifo_valid <= 1'b0;
c2_tcp_rx_fifo_valid <= 1'b0;
c3_tcp_rx_fifo_valid <= 1'b0;
c4_tcp_rx_fifo_valid <= 1'b0;
end
*/
default:
begin
c0_tcp_rx_fifo_valid <= 1'b0;
c0_tcp_rx_fifo_rddata <= 1'b0;
// cx_rx_in_fifo_full <= c0_rx_in_fifo_full;
atten_tcp_rx_fifo_valid <= 1'b0;
c1_tcp_rx_fifo_valid <= 1'b0;
c2_tcp_rx_fifo_valid <= 1'b0;
c3_tcp_rx_fifo_valid <= 1'b0;
c4_tcp_rx_fifo_valid <= 1'b0;
c5_tcp_rx_fifo_valid <= 1'b0;
end
/*
default:
begin
c0_tcp_rx_fifo_valid <= rx_in_fifo_valid_cx_r;
c0_tcp_rx_fifo_rddata <= rx_in_fifo_data_r2;
// cx_rx_in_fifo_full <= c0_rx_in_fifo_full;
atten_tcp_rx_fifo_valid <= 1'b0;
c1_tcp_rx_fifo_valid <= 1'b0;
c2_tcp_rx_fifo_valid <= 1'b0;
c3_tcp_rx_fifo_valid <= 1'b0;
c4_tcp_rx_fifo_valid <= 1'b0;
end
*/
endcase
end
end
always@(posedge clk_187m)
begin
if(reset)
begin
cx_rx_in_fifo_full <= 1'b0;
end
else
begin
case(rx_pkg_exaddr)
12'b0:
begin
cx_rx_in_fifo_full <= c0_rx_in_fifo_full;
end
12'b1:
begin
cx_rx_in_fifo_full <= c1_rx_in_fifo_full;
end
12'd2:
begin
cx_rx_in_fifo_full <= c2_rx_in_fifo_full;
end
12'd3:
begin
cx_rx_in_fifo_full <= c3_rx_in_fifo_full;
end
12'd7://12'd4:
begin
cx_rx_in_fifo_full <= c4_rx_in_fifo_full;
end
12'd5:
begin
cx_rx_in_fifo_full <= c5_rx_in_fifo_full;
end
/*
12'd10,12'd11,12'd12,12'd13,12'd14,12'd15,12'd16,12'd17,12'd18,12'd19:
begin
cx_rx_in_fifo_full <= atten_rx_in_fifo_full;
end
*/
default:
begin
cx_rx_in_fifo_full <= c0_rx_in_fifo_full;
end
endcase
end
end
fifo_generator_4 fifo_generator_4_rx_atten( // change fifo to get a more accurate fifo data count
.clk (clk_187m), // input
.srst (reset),
.din (atten_tcp_rx_fifo_rddata), // input [31:0]
.wr_en (atten_tcp_rx_fifo_valid), // input
.rd_en (atten_rx_in_fifo_rden), // input
.dout (atten_rx_in_fifo_data), // output [31:0]
.full (), // output
.prog_full (atten_rx_in_fifo_full),
.empty (atten_rx_in_fifo_empty), // output
.data_count (atten_rx_axis_rd_data_count) // output [10:0]
// .wr_rst_busy (),
// .rd_rst_busy ()
);
fifo_generator_4 fifo_generator_4_rx_c0( // change fifo to get a more accurate fifo data count
.clk (clk_187m), // input
.srst (reset),
.din (c0_tcp_rx_fifo_rddata), // input [31:0]
.wr_en (c0_tcp_rx_fifo_valid ), // input
.rd_en (c0_rx_in_fifo_rden ), // input
.dout (c0_rx_in_fifo_data), // output [31:0]
.full (), // output
.prog_full (c0_rx_in_fifo_full),
.empty (c0_rx_in_fifo_empty), // output
.data_count (c0_rx_axis_rd_data_count) // output [10:0]
// .wr_rst_busy (),
// .rd_rst_busy ()
);
fifo_generator_4 fifo_generator_4_rx_c1( // change fifo to get a more accurate fifo data count
.clk (clk_187m), // input
.srst (reset),
.din (c1_tcp_rx_fifo_rddata), // input [31:0]
.wr_en (c1_tcp_rx_fifo_valid), // input
.rd_en (c1_rx_in_fifo_rden), // input
.dout (c1_rx_in_fifo_data), // output [31:0]
.full (), // output
.prog_full (c1_rx_in_fifo_full),
.empty (c1_rx_in_fifo_empty), // output
.data_count (c1_rx_axis_rd_data_count) // output [10:0]
// .wr_rst_busy (),
// .rd_rst_busy ()
);
fifo_generator_4 fifo_generator_4_rx_c2( // change fifo to get a more accurate fifo data count
.clk (clk_187m), // input
.srst (reset),
.din (c2_tcp_rx_fifo_rddata), // input [31:0]
.wr_en (c2_tcp_rx_fifo_valid), // input
.rd_en (c2_rx_in_fifo_rden), // input
.dout (c2_rx_in_fifo_data), // output [31:0]
.full (), // output
.prog_full (c2_rx_in_fifo_full),
.empty (c2_rx_in_fifo_empty), // output
.data_count (c2_rx_axis_rd_data_count) // output [10:0]
// .wr_rst_busy (),
// .rd_rst_busy ()
);
fifo_generator_4 fifo_generator_4_rx_c3( // change fifo to get a more accurate fifo data count
.clk (clk_187m), // input
.srst (reset),
.din (c3_tcp_rx_fifo_rddata), // input [31:0]
.wr_en (c3_tcp_rx_fifo_valid), // input
.rd_en (c3_rx_in_fifo_rden), // input
.dout (c3_rx_in_fifo_data), // output [31:0]
.full (), // output
.prog_full (c3_rx_in_fifo_full),
.empty (c3_rx_in_fifo_empty), // output
.data_count (c3_rx_axis_rd_data_count) // output [10:0]
// .wr_rst_busy (),
// .rd_rst_busy ()
);
fifo_generator_4 fifo_generator_4_rx_c4( // change fifo to get a more accurate fifo data count
.clk (clk_187m), // input
.srst (reset),
.din (c4_tcp_rx_fifo_rddata), // input [31:0]
.wr_en (c4_tcp_rx_fifo_valid), // input
.rd_en (c4_rx_in_fifo_rden), // input
.dout (c4_rx_in_fifo_data), // output [31:0]
.full (), // output
.prog_full (c4_rx_in_fifo_full),
.empty (c4_rx_in_fifo_empty), // output
.data_count (c4_rx_axis_rd_data_count) // output [10:0]
// .wr_rst_busy (),
// .rd_rst_busy ()
);
fifo_generator_4 fifo_generator_4_rx_c5( // change fifo to get a more accurate fifo data count
.clk (clk_187m), // input
.srst (reset),
.din (c5_tcp_rx_fifo_rddata), // input [31:0]
.wr_en (c5_tcp_rx_fifo_valid), // input
.rd_en (c5_rx_in_fifo_rden), // input
.dout (c5_rx_in_fifo_data), // output [31:0]
.full (), // output
.prog_full (c5_rx_in_fifo_full),
.empty (c5_rx_in_fifo_empty), // output
.data_count (c5_rx_axis_rd_data_count) // output [10:0]
// .wr_rst_busy (),
// .rd_rst_busy ()
);
//width 443
ila_addrcho_rx inst_ila_addrcho_rx(
.clk(clk_187m),
.probe0({
prog_full,
s0_user_rx_tvalid,
s0_user_rx_tready,
s0_user_rx_tdata ,
s0_user_rx_tkeep ,
s0_user_rx_tlast ,
m0_user_rx_tvalid,
m0_user_rx_tready,
m0_user_rx_tdata ,
m0_user_rx_tkeep ,
m0_user_rx_tlast ,
width_m_axis_tvalid,
rx_in_fifo_full ,
width_m_axis_tdata ,
width_m_axis_tkeep ,
width_m_axis_tlast ,
rx_in_fifo_data ,
rx_in_fifo_rden ,
cx_rx_in_fifo_full ,
rx_in_fifo_data_r1,
rx_in_fifo_valid_cx,
rx_in_fifo_empty ,
rd_data_count,
wr_data_count,
rx_pkg_wr,
rx_pkg_cnt,
rx_pkg_length ,
rx_pkg_exaddr ,
c0_tcp_rx_fifo_rddata,
c0_tcp_rx_fifo_valid ,
c0_rx_in_fifo_rden ,
c0_rx_in_fifo_data ,
c0_rx_in_fifo_full ,
c0_rx_in_fifo_empty ,
c0_rx_axis_rd_data_count,
c0_rx_in_fifo_valid
})
);
endmodule

View File

@ -0,0 +1,436 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/03/04 09:57:24
// Design Name:
// Module Name: AddrCho_tx
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module AddrCho_tx(
input clk,
input reset,
// output intr,
//***************tx interface********************
input tx_fifo_0_tvalid,
output tx_fifo_0_tready,
input [31 : 0] tx_fifo_0_indata ,
input [31 : 0] tx_fifo_0_pkgcnt,
input tx_fifo_1_tvalid,
output tx_fifo_1_tready,
input [31 : 0] tx_fifo_1_indata ,
input [31 : 0] tx_fifo_1_pkgcnt,
input tx_fifo_2_tvalid,
output tx_fifo_2_tready,
input [31 : 0] tx_fifo_2_indata ,
input [31 : 0] tx_fifo_2_pkgcnt,
input tx_fifo_3_tvalid,
output tx_fifo_3_tready,
input [31 : 0] tx_fifo_3_indata ,
input [31 : 0] tx_fifo_3_pkgcnt,
input tx_fifo_4_tvalid,
output tx_fifo_4_tready,
input [31 : 0] tx_fifo_4_indata,
input [31 : 0] tx_fifo_4_pkgcnt,
input tx_fifo_5_tvalid,
output tx_fifo_5_tready,
input [31 : 0] tx_fifo_5_indata ,
input [31 : 0] tx_fifo_5_pkgcnt,
input tx_fifo_6_tvalid,
output tx_fifo_6_tready,
input [31 : 0] tx_fifo_6_indata ,
input [31 : 0] tx_fifo_6_pkgcnt,
input tx_fifo_7_tvalid,
output tx_fifo_7_tready,
input [31 : 0] tx_fifo_7_indata ,
input [31 : 0] tx_fifo_7_pkgcnt,
input tx_fifo_8_tvalid,
output tx_fifo_8_tready,
input [31 : 0] tx_fifo_8_indata ,
input [31 : 0] tx_fifo_8_pkgcnt,
//****************tcpip interface****************
// input tcpip_tx_fifo_full,
// input tcpip_tx_fifo_af,
// output tcpip_tx_fifo_wren,
// output [31:0] tcpip_tx_fifo_wrdata
input fifo_tx_m_axis_clk,
output fifo_tx_m_axis_tvalid,
input fifo_tx_m_axis_tready,
output [63:0] fifo_tx_m_axis_tdata ,
output [7:0] fifo_tx_m_axis_tkeep ,
output fifo_tx_m_axis_tlast
);
wire tx_fifo_0_rden;
wire [31 : 0] tx_fifo_0_wrdata;
wire tx_fifo_0_full;
wire tx_fifo_0_empty;
wire tx_fifo_1_rden;
wire [31 : 0] tx_fifo_1_wrdata;
wire tx_fifo_1_full;
wire tx_fifo_1_empty;
wire tx_fifo_2_rden;
wire [31 : 0] tx_fifo_2_wrdata;
wire tx_fifo_2_full;
wire tx_fifo_2_empty;
wire tx_fifo_3_rden;
wire [31 : 0] tx_fifo_3_wrdata;
wire tx_fifo_3_full;
wire tx_fifo_3_empty;
wire tx_fifo_4_rden;
wire [31 : 0] tx_fifo_4_wrdata;
wire tx_fifo_4_full;
wire tx_fifo_4_empty;
wire tx_fifo_5_rden;
wire [31 : 0] tx_fifo_5_wrdata;
wire tx_fifo_5_full;
wire tx_fifo_5_empty;
wire tx_fifo_6_rden;
wire [31 : 0] tx_fifo_6_wrdata;
wire tx_fifo_6_full;
wire tx_fifo_6_empty;
wire tx_fifo_7_rden;
wire [31 : 0] tx_fifo_7_wrdata;
wire tx_fifo_7_full;
wire tx_fifo_7_empty;
wire tx_fifo_8_rden;
wire [31 : 0] tx_fifo_8_wrdata;
wire tx_fifo_8_full;
wire tx_fifo_8_empty;
wire tcpip_tx_fifo_full;
wire tcpip_tx_fifo_af;
wire tcpip_tx_fifo_wren;
wire [31:0] tcpip_tx_fifo_wrdata;
wire [31:0] s0_user_tx_fifo_rddata_r;
//reg [31:0] s0_user_tx_fifo_rddata_r1;
wire [11:0] s0_user_tx_fifo_rdcnt_r;
wire [11:0] s0_user_tx_fifo_wrcnt_r;
wire tcpip_tx_fifo_last;
fifo_generator_addrcho_tx fifo_generator_addrcho_tx_0( // ?????FWFT????????rden??wrdata?????clk
.clk (clk), // input
.rst (reset), // input
.din (tx_fifo_0_indata), // input [31:0]
.wr_en (tx_fifo_0_tvalid & (~tx_fifo_0_full)), // input
.rd_en (tx_fifo_0_rden), // input
.dout (tx_fifo_0_wrdata), // output [31:0]
.full (), // output
.empty (tx_fifo_0_empty), // output
.prog_full (tx_fifo_0_full )
// .wr_rst_busy(), // output
// .rd_rst_busy() // output
);
assign tx_fifo_0_tready = ~tx_fifo_0_full;
fifo_generator_addrcho_tx fifo_generator_addrcho_tx_1(
.clk (clk), // input
.rst (reset), // input
.din (tx_fifo_1_indata), // input [31:0]
.wr_en (tx_fifo_1_tvalid & (~tx_fifo_1_full)), // input
.rd_en (tx_fifo_1_rden), // input
.dout (tx_fifo_1_wrdata), // output [31:0]
.full (), // output
.empty (tx_fifo_1_empty), // output
.prog_full (tx_fifo_1_full )
// .wr_rst_busy(), // output
// .rd_rst_busy() // output
);
assign tx_fifo_1_tready = ~tx_fifo_1_full;
fifo_generator_addrcho_tx fifo_generator_addrcho_tx_2(
.clk (clk), // input
.rst (reset), // input
.din (tx_fifo_2_indata), // input [31:0]
.wr_en (tx_fifo_2_tvalid & (~tx_fifo_2_full)), // input
.rd_en (tx_fifo_2_rden), // input
.dout (tx_fifo_2_wrdata), // output [31:0]
.full (), // output
.empty (tx_fifo_2_empty), // output
.prog_full (tx_fifo_2_full )
// .wr_rst_busy(), // output
// .rd_rst_busy() // output
);
assign tx_fifo_2_tready = ~tx_fifo_2_full;
fifo_generator_addrcho_tx fifo_generator_addrcho_tx_3(
.clk (clk), // input
.rst (reset), // input
.din (tx_fifo_3_indata), // input [31:0]
.wr_en (tx_fifo_3_tvalid & (~tx_fifo_3_full)), // input
.rd_en (tx_fifo_3_rden), // input
.dout (tx_fifo_3_wrdata), // output [31:0]
.full (), // output
.empty (tx_fifo_3_empty), // output
.prog_full (tx_fifo_3_full )
// .wr_rst_busy(), // output
// .rd_rst_busy() // output
);
assign tx_fifo_3_tready = ~tx_fifo_3_full;
fifo_generator_addrcho_tx fifo_generator_addrcho_tx_4(
.clk (clk), // input
.rst (reset), // input
.din (tx_fifo_4_indata), // input [31:0]
.wr_en (tx_fifo_4_tvalid & (~tx_fifo_4_full)), // input
.rd_en (tx_fifo_4_rden), // input
.dout (tx_fifo_4_wrdata), // output [31:0]
.full (), // output
.empty (tx_fifo_4_empty), // output
.prog_full (tx_fifo_4_full )
// .wr_rst_busy(), // output
// .rd_rst_busy() // output
);
assign tx_fifo_4_tready = ~tx_fifo_4_full;
fifo_generator_addrcho_tx fifo_generator_addrcho_tx_5(
.clk (clk), // input
.rst (reset), // input
.din (tx_fifo_5_indata), // input [31:0]
.wr_en (tx_fifo_5_tvalid & (~tx_fifo_5_full)), // input
.rd_en (tx_fifo_5_rden), // input
.dout (tx_fifo_5_wrdata), // output [31:0]
.full (), // output
.empty (tx_fifo_5_empty), // output
.prog_full (tx_fifo_5_full )
// .wr_rst_busy(), // output
// .rd_rst_busy() // output
);
assign tx_fifo_5_tready = ~tx_fifo_5_full;
fifo_generator_addrcho_tx fifo_generator_addrcho_tx_6(
.clk (clk), // input
.rst (reset), // input
.din (tx_fifo_6_indata), // input [31:0]
.wr_en (tx_fifo_6_tvalid & (~tx_fifo_6_full)), // input
.rd_en (tx_fifo_6_rden), // input
.dout (tx_fifo_6_wrdata), // output [31:0]
.full (), // output
.empty (tx_fifo_6_empty), // output
.prog_full (tx_fifo_6_full )
// .wr_rst_busy(), // output
// .rd_rst_busy() // output
);
assign tx_fifo_6_tready = ~tx_fifo_6_full;
fifo_generator_addrcho_tx fifo_generator_addrcho_tx_7(
.clk (clk), // input
.rst (reset), // input
.din (tx_fifo_7_indata), // input [31:0]
.wr_en (tx_fifo_7_tvalid & (~tx_fifo_7_full)), // input
.rd_en (tx_fifo_7_rden), // input
.dout (tx_fifo_7_wrdata), // output [31:0]
.full (), // output
.empty (tx_fifo_7_empty), // output
.prog_full (tx_fifo_7_full )
// .wr_rst_busy(), // output
// .rd_rst_busy() // output
);
assign tx_fifo_7_tready = ~tx_fifo_7_full;
fifo_generator_addrcho_tx fifo_generator_addrcho_tx_8(
.clk (clk), // input
.rst (reset), // input
.din (tx_fifo_8_indata), // input [31:0]
.wr_en (tx_fifo_8_tvalid & (~tx_fifo_8_full)), // input
.rd_en (tx_fifo_8_rden), // input
.dout (tx_fifo_8_wrdata), // output [31:0]
.full (), // output
.empty (tx_fifo_8_empty), // output
.prog_full (tx_fifo_8_full )
// .wr_rst_busy(), // output
// .rd_rst_busy() // output
);
assign tx_fifo_8_tready = ~tx_fifo_8_full;
AddrCho_mux_top AddrCho_mux_top_u(
.clk (clk),
.reset (reset),
.ch0_thre (32'd2), // ch0_thre
.ch1_thre (32'd2), // ch1_thre
.ch2_thre (32'd2), // ch2_thre
.ch3_thre (32'd2), // ch3_thre
.ch4_thre (32'd2), // ch4_thre
.ch5_thre (32'd2), // ch5_thre
.ch6_thre (32'd2), // ch6_thre
.ch7_thre (32'd2), // ch7_thre
.ch8_thre (32'd2), // ch8_thre
.one_mux_thre (32'd64), // one_mux_thre
.int_mode (32'b0), // int_mode
.tx_fifo_0_empty (tx_fifo_0_empty),
.tx_fifo_0_pkgcnt (tx_fifo_0_pkgcnt),
.tx_fifo_0_rden (tx_fifo_0_rden),
.tx_fifo_0_rddata (tx_fifo_0_wrdata),
.tx_fifo_1_empty (tx_fifo_1_empty),
.tx_fifo_1_pkgcnt (tx_fifo_1_pkgcnt),
.tx_fifo_1_rden (tx_fifo_1_rden),
.tx_fifo_1_rddata (tx_fifo_1_wrdata),
.tx_fifo_2_empty (tx_fifo_2_empty),
.tx_fifo_2_pkgcnt (tx_fifo_2_pkgcnt),
.tx_fifo_2_rden (tx_fifo_2_rden),
.tx_fifo_2_rddata (tx_fifo_2_wrdata),
.tx_fifo_3_empty (tx_fifo_3_empty),
.tx_fifo_3_pkgcnt (tx_fifo_3_pkgcnt),
.tx_fifo_3_rden (tx_fifo_3_rden),
.tx_fifo_3_rddata (tx_fifo_3_wrdata),
.tx_fifo_4_empty (tx_fifo_4_empty),
.tx_fifo_4_pkgcnt (tx_fifo_4_pkgcnt),
.tx_fifo_4_rden (tx_fifo_4_rden),
.tx_fifo_4_rddata (tx_fifo_4_wrdata),
.tx_fifo_5_empty (tx_fifo_5_empty),
.tx_fifo_5_pkgcnt (tx_fifo_5_pkgcnt),
.tx_fifo_5_rden (tx_fifo_5_rden),
.tx_fifo_5_rddata (tx_fifo_5_wrdata),
.tx_fifo_6_empty (tx_fifo_6_empty),
.tx_fifo_6_pkgcnt (tx_fifo_6_pkgcnt),
.tx_fifo_6_rden (tx_fifo_6_rden),
.tx_fifo_6_rddata (tx_fifo_6_wrdata),
.tx_fifo_7_empty (tx_fifo_7_empty),
.tx_fifo_7_pkgcnt (tx_fifo_7_pkgcnt),
.tx_fifo_7_rden (tx_fifo_7_rden),
.tx_fifo_7_rddata (tx_fifo_7_wrdata),
.tx_fifo_8_empty (tx_fifo_8_empty),
.tx_fifo_8_pkgcnt (tx_fifo_8_pkgcnt),
.tx_fifo_8_rden (tx_fifo_8_rden),
.tx_fifo_8_rddata (tx_fifo_8_wrdata),
.tcpip_tx_fifo_full (tcpip_tx_fifo_full),
.tcpip_tx_fifo_af (tcpip_tx_fifo_af),
// .tcpip_tx_fifo_wrcnt (tcpip_tx_fifo_wrcnt),
.tcpip_tx_fifo_wren (tcpip_tx_fifo_wren),
.tcpip_tx_fifo_wrdata (tcpip_tx_fifo_wrdata),
.tcpip_tx_fifo_last (tcpip_tx_fifo_last),
.mux_state (mux_state)
);
wire tcpip_tx_fifo_ready;
wire fifo_tx_s_axis_tvalid;
wire fifo_tx_s_axis_tready;
wire [31:0] fifo_tx_s_axis_tdata;
wire [3: 0] tcpip_tx_fifo_keep;
wire [3: 0] fifo_tx_s_axis_tkeep;
wire fifo_tx_s_axis_tlast;
assign tcpip_tx_fifo_keep = tcpip_tx_fifo_wren ? 4'hf:4'h0;
axis_data_fifo_tcp U_axis_data_fifo_tcp(
.s_axis_aresetn (~reset ),
.s_axis_aclk (clk ),
.s_axis_tvalid (tcpip_tx_fifo_wren ),
.s_axis_tready (tcpip_tx_fifo_ready ),
.s_axis_tdata (tcpip_tx_fifo_wrdata ),
.s_axis_tkeep (tcpip_tx_fifo_keep ),
.s_axis_tlast (tcpip_tx_fifo_last ),
.m_axis_tvalid (fifo_tx_s_axis_tvalid ),
.m_axis_tready (fifo_tx_s_axis_tready ),
.m_axis_tdata (fifo_tx_s_axis_tdata ),
.m_axis_tkeep (fifo_tx_s_axis_tkeep ),
.m_axis_tlast (fifo_tx_s_axis_tlast ),
.prog_full (tcpip_tx_fifo_af )
);
assign tcpip_tx_fifo_full = tcpip_tx_fifo_af;
wire [63:0] fifo_tx_m_axis_tdata_w;
wire [7 :0] fifo_tx_m_axis_tkeep_w;
axis_dwidth_converter_4 axis_dwidth_converter_4_auroratx(
.aclk (fifo_tx_m_axis_clk), // input
.aresetn (~reset), // input
.s_axis_tvalid(fifo_tx_s_axis_tvalid), // input fifo_tx_s_axis_tvalid && (~s0_user_tx_fifo_empty)
.s_axis_tready(fifo_tx_s_axis_tready), // output
.s_axis_tdata (fifo_tx_s_axis_tdata ), // input [31:0] fifo_tx_s_axis_tdata
.s_axis_tkeep (fifo_tx_s_axis_tkeep), // input [3:0]
.s_axis_tlast (fifo_tx_s_axis_tlast), // input
.m_axis_tvalid(fifo_tx_m_axis_tvalid), // output
.m_axis_tready(fifo_tx_m_axis_tready), // input
.m_axis_tdata (fifo_tx_m_axis_tdata_w ), // output [63:0]
.m_axis_tkeep (fifo_tx_m_axis_tkeep_w ), // output [7:0]
.m_axis_tlast (fifo_tx_m_axis_tlast ) // output
);
assign fifo_tx_m_axis_tdata = {fifo_tx_m_axis_tdata_w[31:0],fifo_tx_m_axis_tdata_w[63:32]};
assign fifo_tx_m_axis_tkeep = {fifo_tx_m_axis_tkeep_w[3:0],fifo_tx_m_axis_tkeep_w[7:4]};
//width 300
ila_addrcho_tx ila_addrcho_tx_inst(
.clk(clk),
.probe0({
tx_fifo_0_indata,
tx_fifo_0_tvalid,
tx_fifo_0_rden,
tx_fifo_0_wrdata,
tx_fifo_0_full,
tx_fifo_0_empty,
tx_fifo_4_indata,
tx_fifo_4_tvalid,
tx_fifo_4_rden,
tx_fifo_4_wrdata,
tx_fifo_4_full,
tx_fifo_4_empty,
tcpip_tx_fifo_wren ,
tcpip_tx_fifo_ready ,
tcpip_tx_fifo_wrdata ,
tcpip_tx_fifo_keep ,
tcpip_tx_fifo_last ,
fifo_tx_s_axis_tvalid ,
fifo_tx_s_axis_tready ,
fifo_tx_s_axis_tdata ,
fifo_tx_s_axis_tkeep ,
fifo_tx_m_axis_tvalid ,
fifo_tx_m_axis_tready ,
fifo_tx_m_axis_tdata ,
fifo_tx_m_axis_tkeep,
fifo_tx_m_axis_tlast
})
);
// ila_AddrCho ila_AddrCho_u(
// .clk(clk),
// .probe0({tx_fifo_0_pkgcnt,tx_fifo_0_wrdata,tx_fifo_0_wren,tx_fifo_0_rddata,tx_fifo_0_rden,tx_fifo_0_full,tx_fifo_0_empty,tx_fifo_0_af,tcpip_tx_fifo_full,tcpip_tx_fifo_af,tcpip_tx_fifo_wren,tcpip_tx_fifo_wrdata}) //168
//);
endmodule

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@ -0,0 +1,373 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/10/31 11:13:52
// Design Name:
// Module Name: MUX_DMUX
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MUX_DMUX(
//-----------时钟---复位--------------
input wire sys_clk_in ,//MUX系统时钟
input wire Rst_n ,//MUX系统时钟复位
//-------------Aurora----收发接口-------
input wire [ 63: 0] aurora_rx_s_axis_tdata ,
input wire aurora_rx_s_axis_tvalid ,
input wire [ 7: 0] aurora_rx_s_axis_tkeep ,
input wire aurora_rx_s_axis_tlast ,
output wire aurora_rx_s_axis_tready ,
output wire [ 63: 0] aurora_tx_m_axis_tdata ,
output wire aurora_tx_m_axis_tvalid ,
output wire [ 7: 0] aurora_tx_m_axis_tkeep ,
output wire aurora_tx_m_axis_tlast ,
input wire aurora_tx_m_axis_tready ,
// //-----------LVDS---主动上传----------
// input wire [ 31: 0] s_axis_rdata_rslt_LVDS ,
// input wire s_axis_rvalid_rslt_LVDS ,
// output wire s_axis_rready_rslt_LVDS ,
// output wire slot ,//槽位标志打包包头用
//-----------SPI---参数配置与被动上传----------
output wire spi_sclk_0 ,
output wire spi_csn_0 ,
output wire spi_mosi_0 ,
input wire spi_miso_0 ,
input wire irq ,//主动上传通知
//---------------固件更新----------------------
// output wire [ 31: 0] UP_Grade_tx_m_tdata ,
// output wire UP_Grade_tx_m_tvalid ,
// input wire UP_Grade_tx_m_tready ,
// input wire [ 31: 0] UP_Grade_rx_s_rdata ,
// input wire UP_Grade_rx_s_rvalid ,
// output wire UP_Grade_rx_s_rready ,
//------------DDR4--物理接口----------
output wire c0_DDR4_act_n ,
output wire [ 16: 0] c0_DDR4_adr ,
output wire [ 1: 0] c0_DDR4_ba ,
output wire [ 0: 0] c0_DDR4_bg ,
output wire [ 0: 0] c0_DDR4_ck_c ,
output wire [ 0: 0] c0_DDR4_ck_t ,
output wire [ 0: 0] c0_DDR4_cke ,
output wire [ 0: 0] c0_DDR4_cs_n ,
inout wire [ 3: 0] c0_DDR4_dm_n ,
inout wire [ 31: 0] c0_DDR4_dq ,
inout wire [ 3: 0] c0_DDR4_dqs_c ,
inout wire [ 3: 0] c0_DDR4_dqs_t ,
output wire [ 0: 0] c0_DDR4_odt ,
output wire c0_DDR4_reset_n ,
input wire c0_sys_clk_p ,
input wire c0_sys_clk_n ,
//------------寄存器控制操作 固件更新或状态读取-------------
input wire c5_rx_in_fifo_ready ,
output wire [ 31: 0] c5_rx_in_fifo_data ,
output wire c5_rx_in_fifo_valid
);
//*******************************************MUX 复分接模块 Start**************************************************************
wire mux_rstn ;
rst_mig_clk rst_mig_clk_inst (
.slowest_sync_clk (sys_clk_in ),// input wire slowest_sync_clk
.ext_reset_in (c0_ddr4_ui_clk_sync_rst ),// input wire ext_reset_in
.aux_reset_in (Rst_n ),// input wire aux_reset_in
.mb_debug_sys_rst (1'b0 ),// input wire mb_debug_sys_rst
.dcm_locked (Rst_n ),// input wire dcm_locked
.mb_reset ( ),// output wire mb_reset
.bus_struct_reset ( ),// output wire [0 : 0] bus_struct_reset
.peripheral_reset ( ),// output wire [0 : 0] peripheral_reset
.interconnect_aresetn (mux_rstn ),// output wire [0 : 0] interconnect_aresetn
.peripheral_aresetn ( ) // output wire [0 : 0] peripheral_aresetn
);
mux_dmux_l_top mux_dmux_l_top_i(
.clk (sys_clk_in ),//input
.rstn (mux_rstn ),//input
.slot (slot ),//output
//**************aurora rx**********************
.aurora_rx_s_axis_tvalid (aurora_rx_s_axis_tvalid ),//input
.aurora_rx_s_axis_tready (aurora_rx_s_axis_tready ),//output
.aurora_rx_s_axis_tdata (aurora_rx_s_axis_tdata ),//input [ 63: 0]
.aurora_rx_s_axis_tkeep (aurora_rx_s_axis_tkeep ),//input [ 7: 0]
.aurora_rx_s_axis_tlast (aurora_rx_s_axis_tlast ),//input
//**************aurora tx**********************
.aurora_tx_m_axis_tdata (aurora_tx_m_axis_tdata ),//output [ 63: 0]
.aurora_tx_m_axis_tvalid (aurora_tx_m_axis_tvalid ),//output
.aurora_tx_m_axis_tready (aurora_tx_m_axis_tready ),//input
.aurora_tx_m_axis_tkeep (aurora_tx_m_axis_tkeep ),//output [ 7: 0]
.aurora_tx_m_axis_tlast (aurora_tx_m_axis_tlast ),//output
.aurora_tx_m_axis_clk (sys_clk_in ),//input Aurora时钟用系统时钟时钟域转换在Aurora接口模块中做
//**************DDR4 interface**********************
(* ASSOCIATED_BUSIF = "ddr_s_axi" *)
.ddr_ui_clk (c0_ddr4_ui_clk ),// input /* synthesis syn_isclock = 1 */;
.M00_AXI_ARESET_OUT_N ( ),// output \
.ddr_s_axi_awid (c0_ddr4_s_axi_awid ),// output [3:0]
.ddr_s_axi_awaddr (c0_ddr4_s_axi_awaddr ),// output [31:0]
.ddr_s_axi_awlen (c0_ddr4_s_axi_awlen ),// output [7:0]
.ddr_s_axi_awsize (c0_ddr4_s_axi_awsize ),// output [2:0]
.ddr_s_axi_awburst (c0_ddr4_s_axi_awburst ),// output [1:0]
.ddr_s_axi_awlock (c0_ddr4_s_axi_awlock ),// output
.ddr_s_axi_awcache (c0_ddr4_s_axi_awcache ),// output [3:0]
.ddr_s_axi_awprot (c0_ddr4_s_axi_awprot ),// output [2:0]
.ddr_s_axi_awqos (c0_ddr4_s_axi_awqos ),// output [3:0]
.ddr_s_axi_awvalid (c0_ddr4_s_axi_awvalid ),// output
.ddr_s_axi_awready (c0_ddr4_s_axi_awready ),// input
.ddr_s_axi_wdata (c0_ddr4_s_axi_wdata ),// output [31:0]
.ddr_s_axi_wstrb (c0_ddr4_s_axi_wstrb ),// output [3:0]
.ddr_s_axi_wlast (c0_ddr4_s_axi_wlast ),// output
.ddr_s_axi_wvalid (c0_ddr4_s_axi_wvalid ),// output
.ddr_s_axi_wready (c0_ddr4_s_axi_wready ),// input
.ddr_s_axi_bid (c0_ddr4_s_axi_bid ),// input [3:0]
.ddr_s_axi_bresp (c0_ddr4_s_axi_bresp ),// input [1:0]
.ddr_s_axi_bvalid (c0_ddr4_s_axi_bvalid ),// input ***************************************
.ddr_s_axi_bready (c0_ddr4_s_axi_bready ),// output
.ddr_s_axi_arid (c0_ddr4_s_axi_arid ),// output [3:0]
.ddr_s_axi_araddr (c0_ddr4_s_axi_araddr ),// output [31:0]
.ddr_s_axi_arlen (c0_ddr4_s_axi_arlen ),// output [7:0]
.ddr_s_axi_arsize (c0_ddr4_s_axi_arsize ),// output [2:0]
.ddr_s_axi_arburst (c0_ddr4_s_axi_arburst ),// output [1:0]
.ddr_s_axi_arlock (c0_ddr4_s_axi_arlock ),// output
.ddr_s_axi_arcache (c0_ddr4_s_axi_arcache ),// output [3:0]
.ddr_s_axi_arprot (c0_ddr4_s_axi_arprot ),// output [2:0]
.ddr_s_axi_arqos (c0_ddr4_s_axi_arqos ),// output [3:0]
.ddr_s_axi_arvalid (c0_ddr4_s_axi_arvalid ),// output
.ddr_s_axi_arready (c0_ddr4_s_axi_arready ),// input
.ddr_s_axi_rid (c0_ddr4_s_axi_rid ),// input [3:0]
.ddr_s_axi_rdata (c0_ddr4_s_axi_rdata ),// input [31:0]
.ddr_s_axi_rresp (c0_ddr4_s_axi_rresp ),// input [1:0]
.ddr_s_axi_rlast (c0_ddr4_s_axi_rlast ),// input
.ddr_s_axi_rvalid (c0_ddr4_s_axi_rvalid ),// input
.ddr_s_axi_rready (c0_ddr4_s_axi_rready ),// output
.c5_rx_in_fifo_ready (c5_rx_in_fifo_ready ),//input
.c5_rx_in_fifo_data (c5_rx_in_fifo_data ),//output[31:0]
.c5_rx_in_fifo_valid (c5_rx_in_fifo_valid ),//output
// === SPI Interface 0 ===
.irq (irq ),//input SPI接收 导前 ASIC来
.spi_sclk_0 (spi_sclk_0 ),//output Spi Clock
.spi_csn_0 (spi_csn_0 ),//output Spi Chip Select active low
.spi_mosi_0 (spi_mosi_0 ),//output Spi Mosi
.spi_miso_0 (spi_miso_0 ),//input Spi Miso
// === SPI Interface 1 ===
.spi_sclk_1 ( ),//output Spi Clock
.spi_csn_1 ( ),//output Spi Chip Select active low
.spi_mosi_1 ( ),//output Spi Mosi
.spi_miso_1 ( ),//input Spi Miso
// === SPI Interface 2 ===
.spi_sclk_2 ( ),//output Spi Clock
.spi_csn_2 ( ),//output Spi Chip Select active low
.spi_mosi_2 ( ),//output Spi Mosi
.spi_miso_2 ( ),//input Spi Miso
// === SPI Interface 3 ===
.spi_sclk_3 ( ),//output Spi Clock
.spi_csn_3 ( ),//output Spi Chip Select active low
.spi_mosi_3 ( ),//output Spi Mosi
.spi_miso_3 ( ),//input Spi Miso
//axis port for rslt_push (in)-------LVDS数据
.s_axis_rdata_rslt_0 ( ),//input [ 31: 0]
.s_axis_rvalid_rslt_0 ( ),//input
.s_axis_rready_rslt_0 ( ),//output
.s_axis_rdata_rslt_1 ( ),//input [ 31: 0]
.s_axis_rvalid_rslt_1 ( ),//input
.s_axis_rready_rslt_1 ( ),//output
.s_axis_rdata_rslt_2 ( ),//input [ 31: 0]
.s_axis_rvalid_rslt_2 ( ),//input
.s_axis_rready_rslt_2 ( ),//output
.s_axis_rdata_rslt_3 ( ),//input [ 31: 0]
.s_axis_rvalid_rslt_3 ( ),//input
.s_axis_rready_rslt_3 ( ),//output
//**************rx interface********************** 改为固件更新使用
.ch4_ezq_tx_m_tdata ( ),//output [ 31: 0]
.ch4_ezq_tx_m_tvalid ( ),//output
.ch4_ezq_tx_m_tready ( ),//input
.ch4_ezq_rx_s_rdata ( ),//input [ 31: 0]
.ch4_ezq_rx_s_rvalid ( ),//input
.ch4_ezq_rx_s_rready ( ),//output
.SCK ( ),//output
.CWORD ( ),//output
.LE0 ( ),//output
.LE1 ( ),//output
.LE2 ( ),//output
.LE3 ( ),//output
.LE4 ( ),//output
.LE5 ( ),//output
.LE6 ( ),//output
.LE7 ( ),//output
.LE8 ( ),//output
.LE9 ( ) //output
);
//*******************************************MUX 复分接模块 End**************************************************************
//*******************************************DDR4 Start*********************************************************************
wire c0_init_calib_complete ;
wire c0_ddr4_ui_clk_sync_rst ;
wire c0_ddr4_ui_clk ;
reg c0_ddr4_aresetn ;
wire [ 3: 0] c0_ddr4_s_axi_awid ;
wire [ 31: 0] c0_ddr4_s_axi_awaddr ;
wire [ 7: 0] c0_ddr4_s_axi_awlen ;
wire [ 2: 0] c0_ddr4_s_axi_awsize ;
wire [ 1: 0] c0_ddr4_s_axi_awburst ;
wire [ 0: 0] c0_ddr4_s_axi_awlock ;
wire [ 3: 0] c0_ddr4_s_axi_awcache ;
wire [ 2: 0] c0_ddr4_s_axi_awprot ;
wire [ 3: 0] c0_ddr4_s_axi_awqos ;
wire c0_ddr4_s_axi_awvalid ;
wire c0_ddr4_s_axi_awready ;
wire [ 31: 0] c0_ddr4_s_axi_wdata ;
wire [ 3: 0] c0_ddr4_s_axi_wstrb ;
wire c0_ddr4_s_axi_wlast ;
wire c0_ddr4_s_axi_wvalid ;
wire c0_ddr4_s_axi_wready ;
wire c0_ddr4_s_axi_bready ;
wire [ 3: 0] c0_ddr4_s_axi_bid ;
wire [ 1: 0] c0_ddr4_s_axi_bresp ;
wire c0_ddr4_s_axi_bvalid ;
wire [ 3: 0] c0_ddr4_s_axi_arid ;
wire [ 31: 0] c0_ddr4_s_axi_araddr ;
wire [ 7: 0] c0_ddr4_s_axi_arlen ;
wire [ 2: 0] c0_ddr4_s_axi_arsize ;
wire [ 1: 0] c0_ddr4_s_axi_arburst ;
wire [ 0: 0] c0_ddr4_s_axi_arlock ;
wire [ 3: 0] c0_ddr4_s_axi_arcache ;
wire [ 2: 0] c0_ddr4_s_axi_arprot ;
wire [ 3: 0] c0_ddr4_s_axi_arqos ;
wire c0_ddr4_s_axi_arvalid ;
wire c0_ddr4_s_axi_arready ;
wire c0_ddr4_s_axi_rready ;
wire c0_ddr4_s_axi_rlast ;
wire c0_ddr4_s_axi_rvalid ;
wire [ 1: 0] c0_ddr4_s_axi_rresp ;
wire [ 3: 0] c0_ddr4_s_axi_rid ;
wire [ 31: 0] c0_ddr4_s_axi_rdata ;
//----------------DDR4 复位---------------
// rst_mig_clk rst_mig_clk_inst (
// .slowest_sync_clk (c0_ddr4_ui_clk ),// input wire slowest_sync_clk
// .ext_reset_in (c0_ddr4_ui_clk_sync_rst ),// input wire ext_reset_in
// .aux_reset_in (c0_init_calib_complete ),// input wire aux_reset_in
// .mb_debug_sys_rst (1'b0 ),// input wire mb_debug_sys_rst
// .dcm_locked (1'b1 ),// input wire dcm_locked
// .mb_reset ( ),// output wire mb_reset
// .bus_struct_reset ( ),// output wire [0 : 0] bus_struct_reset
// .peripheral_reset ( ),// output wire [0 : 0] peripheral_reset
// .interconnect_aresetn ( ),// output wire [0 : 0] interconnect_aresetn
// .peripheral_aresetn (c0_ddr4_aresetn ) // output wire [0 : 0] peripheral_aresetn
// );
always @(posedge c0_ddr4_ui_clk) begin
c0_ddr4_aresetn <= ~c0_ddr4_ui_clk_sync_rst;
end
ddr4_0 ddr4_0_inst (
.c0_init_calib_complete (c0_init_calib_complete ),// output wire c0_init_calib_complete vio
.dbg_clk ( ),// output wire dbg_clk
.dbg_bus ( ),// output wire [511 : 0] dbg_bus
.sys_rst ((~Rst_n) ),// input wire sys_rst
.c0_ddr4_ui_clk (c0_ddr4_ui_clk ),// output wire c0_ddr4_ui_clk
.c0_ddr4_ui_clk_sync_rst (c0_ddr4_ui_clk_sync_rst ),// output wire c0_ddr4_ui_clk_sync_rst
.c0_ddr4_aresetn (c0_ddr4_aresetn ),// input wire c0_ddr4_aresetn
//-----------------DDR4 物理接口---------------
.c0_sys_clk_p (c0_sys_clk_p ),// input wire c0_sys_clk_p
.c0_sys_clk_n (c0_sys_clk_n ),// input wire c0_sys_clk_n
.c0_ddr4_adr (c0_DDR4_adr ),// output wire [16 : 0] c0_ddr4_adr
.c0_ddr4_ba (c0_DDR4_ba ),// output wire [1 : 0] c0_ddr4_ba
.c0_ddr4_cke (c0_DDR4_cke ),// output wire [0 : 0] c0_ddr4_cke
.c0_ddr4_cs_n (c0_DDR4_cs_n ),// output wire [0 : 0] c0_ddr4_cs_n
.c0_ddr4_dm_dbi_n (c0_DDR4_dm_n ),// inout wire [3 : 0] c0_ddr4_dm_dbi_n
.c0_ddr4_dq (c0_DDR4_dq ),// inout wire [31 : 0] c0_ddr4_dq
.c0_ddr4_dqs_c (c0_DDR4_dqs_c ),// inout wire [3 : 0] c0_ddr4_dqs_c
.c0_ddr4_dqs_t (c0_DDR4_dqs_t ),// inout wire [3 : 0] c0_ddr4_dqs_t
.c0_ddr4_odt (c0_DDR4_odt ),// output wire [0 : 0] c0_ddr4_odt
.c0_ddr4_bg (c0_DDR4_bg ),// output wire [0 : 0] c0_ddr4_bg
.c0_ddr4_reset_n (c0_DDR4_reset_n ),// output wire c0_ddr4_reset_n
.c0_ddr4_act_n (c0_DDR4_act_n ),// output wire c0_ddr4_act_n
.c0_ddr4_ck_c (c0_DDR4_ck_c ),// output wire [0 : 0] c0_ddr4_ck_c
.c0_ddr4_ck_t (c0_DDR4_ck_t ),// output wire [0 : 0] c0_ddr4_ck_t
//-----------------DDR4 AXI接口---------------
.c0_ddr4_s_axi_awid (c0_ddr4_s_axi_awid ),// input wire [3 : 0] c0_ddr4_s_axi_awid
.c0_ddr4_s_axi_awaddr (c0_ddr4_s_axi_awaddr ),// input wire [31 : 0] c0_ddr4_s_axi_awaddr
.c0_ddr4_s_axi_awlen (c0_ddr4_s_axi_awlen ),// input wire [7 : 0] c0_ddr4_s_axi_awlen
.c0_ddr4_s_axi_awsize (c0_ddr4_s_axi_awsize ),// input wire [2 : 0] c0_ddr4_s_axi_awsize
.c0_ddr4_s_axi_awburst (c0_ddr4_s_axi_awburst ),// input wire [1 : 0] c0_ddr4_s_axi_awburst
.c0_ddr4_s_axi_awlock (c0_ddr4_s_axi_awlock ),// input wire [0 : 0] c0_ddr4_s_axi_awlock
.c0_ddr4_s_axi_awcache (c0_ddr4_s_axi_awcache ),// input wire [3 : 0] c0_ddr4_s_axi_awcache
.c0_ddr4_s_axi_awprot (c0_ddr4_s_axi_awprot ),// input wire [2 : 0] c0_ddr4_s_axi_awprot
.c0_ddr4_s_axi_awqos (c0_ddr4_s_axi_awqos ),// input wire [3 : 0] c0_ddr4_s_axi_awqos
.c0_ddr4_s_axi_awvalid (c0_ddr4_s_axi_awvalid ),// input wire c0_ddr4_s_axi_awvalid
.c0_ddr4_s_axi_awready (c0_ddr4_s_axi_awready ),// output wire c0_ddr4_s_axi_awready
.c0_ddr4_s_axi_wdata (c0_ddr4_s_axi_wdata ),// input wire [31 : 0] c0_ddr4_s_axi_wdata
.c0_ddr4_s_axi_wstrb (c0_ddr4_s_axi_wstrb ),// input wire [3 : 0] c0_ddr4_s_axi_wstrb
.c0_ddr4_s_axi_wlast (c0_ddr4_s_axi_wlast ),// input wire c0_ddr4_s_axi_wlast
.c0_ddr4_s_axi_wvalid (c0_ddr4_s_axi_wvalid ),// input wire c0_ddr4_s_axi_wvalid
.c0_ddr4_s_axi_wready (c0_ddr4_s_axi_wready ),// output wire c0_ddr4_s_axi_wready
.c0_ddr4_s_axi_bready (c0_ddr4_s_axi_bready ),// input wire c0_ddr4_s_axi_bready
.c0_ddr4_s_axi_bid (c0_ddr4_s_axi_bid ),// output wire [3 : 0] c0_ddr4_s_axi_bid
.c0_ddr4_s_axi_bresp (c0_ddr4_s_axi_bresp ),// output wire [1 : 0] c0_ddr4_s_axi_bresp
.c0_ddr4_s_axi_bvalid (c0_ddr4_s_axi_bvalid ),// output wire c0_ddr4_s_axi_bvalid
.c0_ddr4_s_axi_arid (c0_ddr4_s_axi_arid ),// input wire [3 : 0] c0_ddr4_s_axi_arid
.c0_ddr4_s_axi_araddr (c0_ddr4_s_axi_araddr ),// input wire [31 : 0] c0_ddr4_s_axi_araddr
.c0_ddr4_s_axi_arlen (c0_ddr4_s_axi_arlen ),// input wire [7 : 0] c0_ddr4_s_axi_arlen
.c0_ddr4_s_axi_arsize (c0_ddr4_s_axi_arsize ),// input wire [2 : 0] c0_ddr4_s_axi_arsize
.c0_ddr4_s_axi_arburst (c0_ddr4_s_axi_arburst ),// input wire [1 : 0] c0_ddr4_s_axi_arburst
.c0_ddr4_s_axi_arlock (c0_ddr4_s_axi_arlock ),// input wire [0 : 0] c0_ddr4_s_axi_arlock
.c0_ddr4_s_axi_arcache (c0_ddr4_s_axi_arcache ),// input wire [3 : 0] c0_ddr4_s_axi_arcache
.c0_ddr4_s_axi_arprot (c0_ddr4_s_axi_arprot ),// input wire [2 : 0] c0_ddr4_s_axi_arprot
.c0_ddr4_s_axi_arqos (c0_ddr4_s_axi_arqos ),// input wire [3 : 0] c0_ddr4_s_axi_arqos
.c0_ddr4_s_axi_arvalid (c0_ddr4_s_axi_arvalid ),// input wire c0_ddr4_s_axi_arvalid
.c0_ddr4_s_axi_arready (c0_ddr4_s_axi_arready ),// output wire c0_ddr4_s_axi_arready
.c0_ddr4_s_axi_rready (c0_ddr4_s_axi_rready ),// input wire c0_ddr4_s_axi_rready
.c0_ddr4_s_axi_rlast (c0_ddr4_s_axi_rlast ),// output wire c0_ddr4_s_axi_rlast
.c0_ddr4_s_axi_rvalid (c0_ddr4_s_axi_rvalid ),// output wire c0_ddr4_s_axi_rvalid
.c0_ddr4_s_axi_rresp (c0_ddr4_s_axi_rresp ),// output wire [1 : 0] c0_ddr4_s_axi_rresp
.c0_ddr4_s_axi_rid (c0_ddr4_s_axi_rid ),// output wire [3 : 0] c0_ddr4_s_axi_rid
.c0_ddr4_s_axi_rdata (c0_ddr4_s_axi_rdata ),// output wire [31 : 0] c0_ddr4_s_axi_rdata
.addn_ui_clkout1 ( )// output wire addn_ui_clkout1 与UI_CLK完全一致
);
//*******************************************DDR4 End********************************************************************************
endmodule

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@ -0,0 +1,502 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company: Quantum Communication Technology Co.,Ltd.,Anhui
//-----------------------------------------------------------------------------------------------------------------
// File Name : axi_rd.v
// Department : ASIC Group
// Author : PWY
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 1.0 2022-03-15 PWY
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device: Zynq-7 XC7Z100ffg900-2
// Tool versions: Vivado 2016.4
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
// +------------------------+
// +----------------+ | |
// | |--rw_to--------------- |
// | | | |
// | regflie |--burst_len----------- |
// | | | |
// | |--timeout_mode-------- |
// | | | | +-----------------+
// +----------------+ | | | |
// +----------------+ | | | |
// | |--in_fifo_rden-------- axi_rd | | |
// | | | | | |
// | *_out_fifo |--in_fifo_data-------- -----axi_bus-----| system_bus |
// | | | | | |
// | |--in_fifo_rdcnt------- | | |
// +----------------+ | | | |
// | | | |
// +----------------+ | | | |
// | |--rd_ptr-------------- | +-----------------+
// | addr_ctrl | | |
// | |--use_byte------------ |
// +----------------+ +------------------------+
`timescale 1ns / 1ps
module axi_rd #(
parameter TO_WIDTH = 6,
parameter DATA_WIDTH = 64,
parameter FIFO_DEPTH = 128
)(
// system signals
input clk // System clock 100MHZ
,input rst // System reset, hight active
// config signals
,input [TO_WIDTH-1 :0] rw_to // read timeout
,input [7 :0] burst_len // Axi read burst length
,input timout_mode // Timeout mode enable, hight active
,input [31 :0] start_addr // Start addr
,input [31 :0] end_addr // End addr
,output [5 :0] rd_state // Read status
// AXI read address channel signals
// Input fifo signals
,output [DATA_WIDTH-1 :0] out_fifo_din // Output fifo write data
,output out_fifo_wren // Output fifo write enable, hight active
,input out_fifo_pfull // Output fifo program full
// addr ctrl signals
,input [31 :0] ddr_use_byte // DDR memory used space
,output [31 :0] rd_ptr // read ptr
,output rd_round // read round
// axi read signals
/*AXI read address channel signals*/
,input ARREADY // Indicates slave is ready to accept a
,output [31 :0] ARADDR // read address
,output ARVALID // read address valid
,output [2 :0] ARSIZE //
,output [7 :0] ARLEN // Burst read length
,output [1 :0] ARBURST // Burst type
,output [3 :0] ARCACHE
,output [2 :0] ARPROT
,output [0 :0] ARLOCK
/*AXI read data channel signals*/
,output RREADY // read data ready
,input [DATA_WIDTH-1 :0] RDATA // read data
,input RLAST // Last read transaction
,input RVALID // read valid
/*AXI read response channel signals*/
,input [1 :0] RRESP // read response
);
////////////////////////////////////////////////
//log2 function
////////////////////////////////////////////////
function integer clog2(input integer depth);
begin
for(clog2=0;depth>0;clog2=clog2+1)
depth =depth>>1;
end
endfunction
localparam BW = clog2((DATA_WIDTH/8)-1);
/////////////////////////////////////////////////////////
//local parameter
/////////////////////////////////////////////////////////
//IDLE --> Idle status
//BLSEL --> Axi read burst length select status
//BLLD --> Axi read burst length load status
//WRADDR --> Axi read Addr op status
//WRDATA --> Axi read Data op status
//WARESP --> Axi read response status
localparam IDLE = 6'b000001,
BLSEL = 6'b000010,
BLLD = 6'b000100,
RDADDR = 6'b001000,
RDDATA = 6'b010000,
WTRESP = 6'b100000;
/////////////////////////////////////////////////////////
//reg & wire
/////////////////////////////////////////////////////////
//Initial read addr value
reg init_addr;
//read addr
reg [31:0] rd_addr;
//actual burst length
reg [7 :0] act_brlen;
//burst len load flag
reg [1 :0] brlen_loadflag;
//fsm current state
reg [5 :0] state_c;
//fsm next state
reg [5 :0] state_n;
//fsm state jump condition
wire idle2blsel_start; //IDLE to BLSEL
wire blsel2blld_start; //BLSEL to BLLD
wire blld2rdaddr_start; //BLLD to RDADDR
wire rdaddr2rddata_start; //RDADDR to RDDATA
wire rddata2wtresp_start; //RDDATA to WTRESP
wire wtresp2idle_start; //WTRESP to IDLE
//one time burst read done
wire brd_done;
//timeout count
reg [TO_WIDTH-1:0] to_cnt;
//BLSEL CNT
reg [1:0] blsel_cnt;
//ddr_use_byte_r
reg [31:0] ddr_use_byte_r;
//rd_round_r
reg rd_round_r;
//remsp_4k
wire [12:0] remsp_4k;
/////////////////////////////////////////////////////////
//FSM
/////////////////////////////////////////////////////////
/**********fsm first segment**********/
always @(posedge clk or posedge rst) begin
if(rst) begin
state_c <= IDLE;
end
else begin
state_c <= state_n;
end
end
/**********fsm second segment**********/
always @(*) begin
case(state_c)
IDLE : begin
if(idle2blsel_start) begin
state_n = BLSEL;
end
else begin
state_n = state_c;
end
end
BLSEL : begin
if(blsel2blld_start) begin
state_n = BLLD;
end
else begin
state_n = state_c;
end
end
BLLD : begin
if(blld2rdaddr_start) begin
state_n = RDADDR;
end
else begin
state_n = state_c;
end
end
RDADDR : begin
if(rdaddr2rddata_start) begin
state_n = RDDATA;
end
else begin
state_n = state_c;
end
end
RDDATA : begin
if(rddata2wtresp_start) begin
state_n = WTRESP;
end
else begin
state_n = state_c;
end
end
WTRESP : begin
if(wtresp2idle_start) begin
state_n = IDLE;
end
else begin
state_n = state_c;
end
end
default : begin
state_n = state_c;
end
endcase
end
/**********fsm third segment**********/
// assign idle2blsel_start = (state_c == IDLE ) ? (out_fifo_pfull != 1'b1) && ((ddr_use_byte>>BW)> 0): 1'b0;
assign idle2blsel_start = (state_c == IDLE ) && (out_fifo_pfull != 1'b1) && ((ddr_use_byte>>BW)> 0);
// assign idle2blsel_start = (state_c == IDLE ) ? (out_fifo_pfull != 1'b1) && ((ddr_use_byte>>BW) > (burst_len+1)): 1'b0;
assign blsel2blld_start = (state_c == BLSEL ) && |brlen_loadflag && (blsel_cnt > 2'b1);
assign blld2rdaddr_start = (state_c == BLLD );
assign rdaddr2rddata_start = (state_c == RDADDR) && ARREADY && ARVALID;
assign rddata2wtresp_start = (state_c == RDDATA) && RLAST && RVALID;
assign wtresp2idle_start = (state_c == WTRESP) && brd_done;
/**********fsm fourth segment**********/
/////////////////////////////////////////////////////////
//timeout count
/////////////////////////////////////////////////////////
always @(posedge clk or posedge rst) begin
if(rst) begin
to_cnt <= 0;
end
else begin
if(timout_mode && state_c == BLSEL) begin
if(to_cnt == rw_to) begin
to_cnt <= to_cnt;
end
else begin
to_cnt <= to_cnt + 1'b1;
end
end
else begin
to_cnt <= 0;
end
end
end
/////////////////////////////////////////////////////////
//blsel_cnt
/////////////////////////////////////////////////////////
always @(posedge clk or posedge rst) begin
if(rst) begin
blsel_cnt <= 2'b0;
end
else if(state_c == BLSEL) begin
blsel_cnt <= blsel_cnt + 1'b1;
end
else begin
blsel_cnt <= 2'b0;
end
end
/////////////////////////////////////////////////////////
//remsp_4k
/////////////////////////////////////////////////////////
assign remsp_4k = {1'b0,~rd_addr[11:0]} + 1'b1;
/////////////////////////////////////////////////////////
//brlen_loadflag
/////////////////////////////////////////////////////////
always @(posedge clk or posedge rst) begin
if(rst) begin
brlen_loadflag <= 2'b00;
end
else if(state_c == BLSEL) begin
if((ddr_use_byte>>BW) >= burst_len +1) begin
if(burst_len +1 >= remsp_4k >> BW) begin
brlen_loadflag <= 2'b11;
end
else begin
brlen_loadflag <= 2'b01;
end
end
else begin
if((ddr_use_byte>>BW) >= remsp_4k >> BW) begin
brlen_loadflag <= 2'b11;
end
else if(to_cnt == rw_to) begin
brlen_loadflag <= 2'b10;
end
else begin
brlen_loadflag <= 2'b00;
end
end
end
else begin
brlen_loadflag <= brlen_loadflag;
end
end
/////////////////////////////////////////////////////////
//init_addr
/////////////////////////////////////////////////////////
always @(posedge clk or posedge rst) begin
if(rst) begin
init_addr <= 1'b0;
end
else if(state_c == RDADDR) begin
init_addr <= 1'b1;
end
else begin
init_addr <= init_addr;
end
end
/////////////////////////////////////////////////////////
//rd_addr
/////////////////////////////////////////////////////////
always @(posedge clk or posedge rst) begin
if(rst) begin
rd_addr <= 32'h0;
end
else if(state_c == IDLE) begin
rd_addr <= init_addr==1'b0 ? start_addr : rd_addr;
end
else if(brd_done) begin
if(rd_addr == end_addr + 1'b1 - (act_brlen << BW)) begin
rd_addr <= start_addr;
end
else begin
rd_addr <= rd_addr + (act_brlen << BW);
end
end
else begin
rd_addr <= rd_addr;
end
end
/////////////////////////////////////////////////////////
//rd_round_r
/////////////////////////////////////////////////////////
always @(posedge clk or posedge rst) begin
if(rst) begin
rd_round_r <= 1'b0;
end
else if(brd_done && rd_addr == end_addr + 1'b1 - (act_brlen << BW)) begin
rd_round_r <= ~rd_round_r;
end
else begin
rd_round_r <= rd_round_r;
end
end
/////////////////////////////////////////////////////////
//rd_round
/////////////////////////////////////////////////////////
assign rd_round = rd_round_r;
/////////////////////////////////////////////////////////
//ARVALID
/////////////////////////////////////////////////////////
assign ARVALID = state_c == RDADDR;
/////////////////////////////////////////////////////////
//Burst Read data done OKAY:2'b00, EXOKAY:2'b01
/////////////////////////////////////////////////////////
assign brd_done = state_c == WTRESP;
//ddr_use_byte_r
always @(posedge clk or posedge rst) begin
if(rst) begin
ddr_use_byte_r <= 32'h0;
end
else if(state_c == BLSEL) begin
ddr_use_byte_r <= ddr_use_byte;
end
else begin
ddr_use_byte_r <= ddr_use_byte_r;
end
end
/////////////////////////////////////////////////////////
//act_brlen
/////////////////////////////////////////////////////////
always @(posedge clk or posedge rst) begin
if(rst) begin
act_brlen <= 8'h0;
end
else if(state_c == BLLD) begin
case(brlen_loadflag)
2'b01 : begin
act_brlen <= burst_len + 1'b1;
end
2'b10 : begin
act_brlen <= (ddr_use_byte_r>>BW);
end
2'b11 : begin
act_brlen <= (remsp_4k >> BW);
end
default : begin
act_brlen <= 8'h1;
end
endcase
end
else begin
act_brlen <= act_brlen;
end
end
/////////////////////////////////////////////////////////
//AWLEN
/////////////////////////////////////////////////////////
assign ARLEN = act_brlen - 1'b1;
/////////////////////////////////////////////////////////
//out_fifo_wren
/////////////////////////////////////////////////////////
assign out_fifo_wren = RREADY && RVALID;
/////////////////////////////////////////////////////////
//out_fifo_din
/////////////////////////////////////////////////////////
assign out_fifo_din = RDATA;
/////////////////////////////////////////////////////////
//rd_ptr
/////////////////////////////////////////////////////////
assign rd_ptr = rd_addr;
/////////////////////////////////////////////////////////
//ARADDR
/////////////////////////////////////////////////////////
assign ARADDR = rd_addr;
/////////////////////////////////////////////////////////
//ARSIZE
/////////////////////////////////////////////////////////
assign ARSIZE = BW;
/////////////////////////////////////////////////////////
//ARBURST
/////////////////////////////////////////////////////////
assign ARBURST = 2'b01;
/////////////////////////////////////////////////////////
//ARCACHE
/////////////////////////////////////////////////////////
assign ARCACHE = 4'b0010;
/////////////////////////////////////////////////////////
//ARPROT
/////////////////////////////////////////////////////////
assign ARPROT = 3'b000;
/////////////////////////////////////////////////////////
//ARLOCK
/////////////////////////////////////////////////////////
assign ARLOCK = 1'b0;
/////////////////////////////////////////////////////////
//RREADY
/////////////////////////////////////////////////////////
assign RREADY = 1'b1;
/////////////////////////////////////////////////////////
//RREADY
/////////////////////////////////////////////////////////
assign rd_state = state_c;
endmodule

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@ -0,0 +1,279 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company: Quantum Communication Technology Co.,Ltd.,Anhui
//-----------------------------------------------------------------------------------------------------------------
// File Name : axi_srd_cache.v
// Department : ASIC Group
// Author : PWY
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 1.0 2022-03-15 PWY
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device: Zynq-7 XC7Z100ffg900-2
// Tool versions: Vivado 2016.4
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module axi_srd_cache #(
parameter TO_WIDTH = 6 ,
parameter DATA_WIDTH = 64 ,
parameter FIFO_DEPTH = 64 ,
parameter PROG_FULL_THRE = 32
)(
// system signals
input clk // System clock 100MHZ
,input wr_rst // Write reset, hight active
,input rd_rst // Read reset, hight active
// config signals
,input [TO_WIDTH-1 :0] rw_to // Write timeout
,input [7 :0] burst_len // Axi write burst length
,input timout_mode // Timeout mode enable, hight active
,input [31 :0] start_addr // Start addr
,input [31 :0] end_addr // End addr
,output [5 :0] wr_state // Read status
,output [5 :0] rd_state // Read status
,output [31 :0] use_cnt_o // DDR memory used space
// AXI write channel signals
/* Input fifo signals */
,input [DATA_WIDTH-1 :0] in_fifo_data // Input fifo read data
// ,input [31:0] in_fifo_rdcnt // Input fifo read data count
,input [clog2(FIFO_DEPTH-1)-1:0] in_fifo_rdcnt // Input fifo read data count
,output in_fifo_rden // Input fifo read enable, hight active
/* AXI write address channel signals */
,input AWREADY // Indicates slave is ready to accept a
,output [31 :0] AWADDR // Write address
,output AWVALID // Write address valid
,output [2 :0] AWSIZE // Write size
,output [1 :0] AWBURST // Burst type
,output [3 :0] AWCACHE // Write cache
,output [2 :0] AWPROT // Write protect
,output [0 :0] AWLOCK // Write bus lock
/*AXI write data channel signals*/
,input WREADY // Write data ready
,output [7 :0] AWLEN // Burst write length
,output [DATA_WIDTH-1 :0] WDATA // Write data
,output WLAST // Last write transaction
,output WVALID // Write valid
,output [(DATA_WIDTH/8)-1 :0] WSTRB
/*AXI write response channel signals*/
,input [1 :0] BRESP // Write response
,input BVALID // Write reponse valid
,output BREADY // Response ready
// AXI read channel signals
/* Input fifo signals */
,input out_fifo_rden // Output fifo read enable, high active
,output [DATA_WIDTH-1 :0] out_fifo_data // Output fifo read data
,output out_fifo_empty // Output fifo empty
,output out_fifo_full // Output fifo full
,output out_fifo_af
/* AXI read address channel signals */
,input ARREADY // Indicates slave is ready to accept a
,output [31 :0] ARADDR // read address
,output ARVALID // read address valid
,output [2 :0] ARSIZE // read size
,output [7 :0] ARLEN // Burst read length
,output [1 :0] ARBURST // Burst type
,output [3 :0] ARCACHE
,output [2 :0] ARPROT
,output [0 :0] ARLOCK
/* AXI read data channel signals */
,output RREADY // read data ready
,input [DATA_WIDTH-1 :0] RDATA // read data
,input RLAST // Last read transaction
,input RVALID // read valid
/* AXI read response channel signals */
,input [1 :0] RRESP // read response
);
////////////////////////////////////////////////
//log2 function
////////////////////////////////////////////////
function integer clog2(input integer depth);
begin
for(clog2=0;depth>0;clog2=clog2+1)
depth =depth>>1;
end
endfunction
/////////////////////////////////////////////////////////
//wire
/////////////////////////////////////////////////////////
wire [31 :0] rd_ptr ; // Read ptr
wire [31 :0] wr_ptr ; // Write ptr
wire [31 :0] use_cnt ; // DDR memory used space
wire [31 :0] left_space ; // DDR memory left space
wire rd_round ;
wire wr_round ;
wire [DATA_WIDTH-1 :0] out_fifo_din ;// Output fifo write data
wire out_fifo_wren ;// Output fifo write enable, hight active
wire out_fifo_pfull ;// Output fifo program full
/////////////////////////////////////////////////////////
//addr_ctrl inst
/////////////////////////////////////////////////////////
/*
sdr_addr_ctrl U_sdr_addr_ctrl (
.start_addr ( start_addr )
,.end_addr ( end_addr )
,.rd_ptr ( rd_ptr )
,.wr_ptr ( wr_ptr )
,.wr_round ( wr_round )
,.rd_round ( rd_round )
,.use_cnt ( use_cnt )
,.left_space ( left_space )
);
*/
sdr_addr_ctrl U_sdr_addr_ctrl (
.clk ( clk )
,.rst ( wr_rst )
,.start_addr ( start_addr )
,.end_addr ( end_addr )
,.rd_ptr ( rd_ptr )
,.wr_ptr ( wr_ptr )
,.wr_round ( wr_round )
,.rd_round ( rd_round )
,.use_cnt ( use_cnt )
,.left_space ( left_space )
);
/////////////////////////////////////////////////////////
//axi_wr inst
/////////////////////////////////////////////////////////
axi_wr #(
.TO_WIDTH ( TO_WIDTH )
,.DATA_WIDTH ( DATA_WIDTH )
,.FIFO_DEPTH ( FIFO_DEPTH )
) U_axi_wr (
.clk ( clk )
,.rst ( wr_rst )
,.rw_to ( rw_to )
,.burst_len ( burst_len )
,.timout_mode ( timout_mode )
,.start_addr ( start_addr )
,.end_addr ( end_addr )
,.in_fifo_data ( in_fifo_data )
,.in_fifo_rdcnt ( in_fifo_rdcnt )
,.in_fifo_rden ( in_fifo_rden )
,.left_space ( left_space )
,.wr_ptr ( wr_ptr )
,.wr_state ( wr_state )
,.wr_round ( wr_round )
,.AWREADY ( AWREADY )
,.AWADDR ( AWADDR )
,.AWVALID ( AWVALID )
,.AWLEN ( AWLEN )
,.AWSIZE ( AWSIZE )
,.AWBURST ( AWBURST )
,.AWCACHE ( AWCACHE )
,.AWPROT ( AWPROT )
,.AWLOCK ( AWLOCK )
,.WREADY ( WREADY )
,.WDATA ( WDATA )
,.WLAST ( WLAST )
,.WVALID ( WVALID )
,.WSTRB ( WSTRB )
,.BRESP ( BRESP )
,.BVALID ( BVALID )
,.BREADY ( BREADY )
);
/////////////////////////////////////////////////////////
//axi_rd inst
/////////////////////////////////////////////////////////
axi_rd #(
.TO_WIDTH ( TO_WIDTH )
,.DATA_WIDTH ( DATA_WIDTH )
,.FIFO_DEPTH ( FIFO_DEPTH )
) axi_rd (
.clk ( clk )
,.rst ( rd_rst )
,.rw_to ( rw_to )
,.burst_len ( burst_len )
,.timout_mode ( timout_mode )
,.start_addr ( start_addr )
,.end_addr ( end_addr )
,.out_fifo_din ( out_fifo_din )
,.out_fifo_wren ( out_fifo_wren )
,.out_fifo_pfull ( out_fifo_pfull )
,.ddr_use_byte ( use_cnt )
,.rd_ptr ( rd_ptr )
,.rd_state ( rd_state )
,.rd_round ( rd_round )
,.ARREADY ( ARREADY )
,.ARADDR ( ARADDR )
,.ARVALID ( ARVALID )
,.ARSIZE ( ARSIZE )
,.ARLEN ( ARLEN )
,.ARBURST ( ARBURST )
,.ARCACHE ( ARCACHE )
,.ARPROT ( ARPROT )
,.ARLOCK ( ARLOCK )
,.RREADY ( RREADY )
,.RDATA ( RDATA )
,.RLAST ( RLAST )
,.RVALID ( RVALID )
,.RRESP ( RRESP )
);
/////////////////////////////////////////////////////////
//read syn_fwft_fifo inst
/////////////////////////////////////////////////////////
syn_fwft_fifo #(
.width ( DATA_WIDTH )
,.depth ( FIFO_DEPTH )
,.prog_full_thre ( PROG_FULL_THRE )
,.prog_empty_thre ( 6 )
,.DEBUG ( 1 )
) out_syn_fwft_fifo (
.clk ( clk )
,.rst ( rd_rst )
,.clr ( 1'b0 )
,.wr_en ( out_fifo_wren )
,.din ( out_fifo_din )
,.full ( out_fifo_full )
,.almost_full ( out_fifo_af )
,.prog_full ( out_fifo_pfull )
,.rd_en ( out_fifo_rden )
,.dout ( out_fifo_data )
,.empty ( out_fifo_empty )
,.almost_empty ( )
,.prog_empty ( )
,.cnt ( )
);
/////////////////////////////////////////////////////////
//use_cnt_o
/////////////////////////////////////////////////////////
assign use_cnt_o = use_cnt;
// ila_srd_cache ila_srd_cache_u(
// .clk(clk),
// .probe0({out_fifo_wren, out_fifo_din, out_fifo_full, out_fifo_pfull, out_fifo_rden, out_fifo_data, out_fifo_empty}) // 69
// );
endmodule

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@ -0,0 +1,540 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company: Quantum Communication Technology Co.,Ltd.,Anhui
//-----------------------------------------------------------------------------------------------------------------
// File Name : axi_wr.v
// Department : ASIC Group
// Author : PWY
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 1.0 2022-03-15 PWY
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device: Zynq-7 XC7Z100ffg900-2
// Tool versions: Vivado 2016.4
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
// +------------------------+
// +----------------+ | |
// | |--rw_to--------------- |
// | | | |
// | regflie |--burst_len----------- |
// | | | |
// | |--timeout_mode-------- |
// | | | | +-----------------+
// +----------------+ | | | |
// +----------------+ | | | |
// | |--in_fifo_rden-------- axi_wr | | |
// | | | | | |
// | *_in_fifo |--in_fifo_data-------- -----axi_bus-----| system_bus |
// | | | | | |
// | |--in_fifo_rdcnt------- | | |
// +----------------+ | | | |
// | | | |
// +----------------+ | | | |
// | |--wr_ptr-------------- | +-----------------+
// | addr_ctrl | | |
// | |--left_space---------- |
// +----------------+ +------------------------+
`timescale 1ns / 1ps
module axi_wr #(
parameter TO_WIDTH = 6,
parameter DATA_WIDTH = 64,
parameter FIFO_DEPTH = 128
)(
// system signals
input clk // System clock 100MHZ
,input rst // System reset, hight active
// config signals
,input [TO_WIDTH-1 :0] rw_to // Write timeout
,input [7 :0] burst_len // Axi write burst length
,input timout_mode // Timeout mode enable, hight active
,input [31 :0] start_addr // Start addr
,input [31 :0] end_addr // End addr
,output [5 :0] wr_state // Write status
// AXI write address channel signals
// Input fifo signals
,input [DATA_WIDTH-1 :0] in_fifo_data // Input fifo read data
// ,input [31:0] in_fifo_rdcnt // Input fifo read data count
,input [clog2(FIFO_DEPTH-1)-1:0] in_fifo_rdcnt // Input fifo read data count
,output in_fifo_rden // Input fifo read enable, hight active
// addr ctrl signals
,input [31 :0] left_space // DDR memory left space
,output [31 :0] wr_ptr // Write ptr
,output wr_round // Write round
// axi write signals
/*AXI write address channel signals*/
,input AWREADY // Indicates slave is ready to accept a
,output [31 :0] AWADDR // Write address
,output AWVALID // Write address valid
,output [2 :0] AWSIZE // Write size
,output [1 :0] AWBURST // Burst type
,output [3 :0] AWCACHE
,output [2 :0] AWPROT
,output [0 :0] AWLOCK
/*AXI write data channel signals*/
,input WREADY // Write data ready
,output [7 :0] AWLEN // Burst write length
,output [DATA_WIDTH-1 :0] WDATA // Write data
,output WLAST // Last write transaction
,output reg WVALID // Write valid
,output [(DATA_WIDTH/8)-1 :0] WSTRB
/*AXI write response channel signals*/
,input [1 :0] BRESP // Write response
,input BVALID // Write reponse valid
,output BREADY // Response ready
);
////////////////////////////////////////////////
//log2 function
////////////////////////////////////////////////
function integer clog2(input integer depth);
begin
for(clog2=0;depth>0;clog2=clog2+1)
depth =depth>>1;
end
endfunction
localparam BW = clog2((DATA_WIDTH/8)-1);
/////////////////////////////////////////////////////////
//local parameter
/////////////////////////////////////////////////////////
//IDLE --> Idle status
//BLSEL --> Axi write burst length select status
//BLLD --> Axi write burst length load status
//WRADDR --> Axi write Addr op status
//WRDATA --> Axi write Data op status
//WARESP --> Axi write response status
localparam IDLE = 6'b000001,
BLSEL = 6'b000010,
BLLD = 6'b000100,
WRADDR = 6'b001000,
WRDATA = 6'b010000,
WTRESP = 6'b100000;
/////////////////////////////////////////////////////////
//reg & wire
/////////////////////////////////////////////////////////
//Initial write addr value
reg init_addr;
//Burst write data count
reg [7 :0] bwr_cnt;
//write addr
reg [31:0] wr_addr;
//actual burst length
reg [7 :0] act_bwlen;
//burst len load flag
reg [1 :0] bwlen_loadflag;
//fsm current state
reg [5 :0] state_c;
//fsm next state
reg [5 :0] state_n;
//fsm state jump condition
wire idle2blsel_start; //IDLE to BLSEL
wire blsel2blld_start; //BLSEL to BLLD
wire blld2wraddr_start; //BLLD to WRADDR
wire wraddr2wrdata_start; //WRADDR to WRDATA
wire wrdata2wtresp_start; //WRDATA to WTRESP
wire wtresp2idle_start; //WTRESP to IDLE
//one time burst write done
wire bwr_done;
//timeout count
reg [TO_WIDTH-1:0] to_cnt;
//BLSEL CNT
reg [1:0] blsel_cnt;
//wr_round_r
reg wr_round_r;
//remsp_4k;
wire [12:0] remsp_4k;
/////////////////////////////////////////////////////////
//FSM
/////////////////////////////////////////////////////////
/**********fsm first segment**********/
always @(posedge clk or posedge rst) begin
if(rst) begin
state_c <= IDLE;
end
else begin
state_c <= state_n;
end
end
/**********fsm second segment**********/
always @(*) begin
case(state_c)
IDLE : begin
if(idle2blsel_start) begin
state_n = BLSEL;
end
else begin
state_n = IDLE;
end
end
BLSEL : begin
if(blsel2blld_start) begin
state_n = BLLD;
end
else begin
state_n = BLSEL;
end
end
BLLD : begin
if(blld2wraddr_start) begin
state_n = WRADDR;
end
else begin
state_n = BLLD;
end
end
WRADDR : begin
if(wraddr2wrdata_start) begin
state_n = WRDATA;
end
else begin
state_n = WRADDR;
end
end
WRDATA : begin
if(wrdata2wtresp_start) begin
state_n = WTRESP;
end
else begin
state_n = WRDATA;
end
end
WTRESP : begin
if(wtresp2idle_start) begin
state_n = IDLE;
end
else begin
state_n = WTRESP;
end
end
default : begin
state_n = IDLE;
end
endcase
end
/**********fsm third segment**********/
// assign idle2blsel_start = (state_c == IDLE ) ? (in_fifo_rdcnt > 0) && (left_space > 0): 1'b0;
assign idle2blsel_start = (state_c == IDLE ) ? (in_fifo_rdcnt > 0) && (left_space > ((burst_len+1)<<BW)): 1'b0;
assign blsel2blld_start = (state_c == BLSEL ) && |bwlen_loadflag && (blsel_cnt > 2'b1);
assign blld2wraddr_start = (state_c == BLLD );
assign wraddr2wrdata_start = (state_c == WRADDR) && AWREADY && AWVALID;
assign wrdata2wtresp_start = (state_c == WRDATA) && WLAST;
assign wtresp2idle_start = (state_c == WTRESP) && bwr_done;
/**********fsm fourth segment**********/
/////////////////////////////////////////////////////////
//Burst Write data count
/////////////////////////////////////////////////////////
always@(posedge clk or posedge rst)begin
if(rst)begin
bwr_cnt <= 8'd0;
end
else begin
if(state_c == WRDATA) begin
if(WREADY && WVALID)begin
bwr_cnt <= bwr_cnt + 1'b1;
end
else begin
bwr_cnt <= bwr_cnt;
end
end
else begin
bwr_cnt <= 8'd0;
end
end
end
/////////////////////////////////////////////////////////
//timeout count
/////////////////////////////////////////////////////////
always @(posedge clk or posedge rst) begin
if(rst) begin
to_cnt <= 0;
end
else begin
if(timout_mode && state_c == BLSEL) begin
if(to_cnt == rw_to) begin
to_cnt <= to_cnt;
end
else begin
to_cnt <= to_cnt + 1'b1;
end
end
else begin
to_cnt <= 0;
end
end
end
/////////////////////////////////////////////////////////
//blsel_cnt
/////////////////////////////////////////////////////////
always @(posedge clk or posedge rst) begin
if(rst) begin
blsel_cnt <= 2'b0;
end
else if(state_c == BLSEL) begin
blsel_cnt <= blsel_cnt + 1'b1;
end
else begin
blsel_cnt <= 2'b0;
end
end
/////////////////////////////////////////////////////////
//remsp_4k
/////////////////////////////////////////////////////////
assign remsp_4k = {1'b0,~wr_addr[11:0]} + 1'b1;
/////////////////////////////////////////////////////////
//bwlen_loadflag
/////////////////////////////////////////////////////////
always @(posedge clk or posedge rst) begin
if(rst) begin
bwlen_loadflag <= 2'b00;
end
else if(state_c == BLSEL) begin
if(in_fifo_rdcnt >= burst_len +1) begin
if(burst_len +1 >= remsp_4k >> BW) begin
bwlen_loadflag <= 2'b11;
end
else begin
bwlen_loadflag <= 2'b01;
end
end
else begin
if(in_fifo_rdcnt >= remsp_4k >> BW) begin
bwlen_loadflag <= 2'b11;
end else if(to_cnt == rw_to) begin
bwlen_loadflag <= 2'b10;
end
else begin
bwlen_loadflag <= 2'b00;
end
end
end
else begin
bwlen_loadflag <= bwlen_loadflag;
end
end
/////////////////////////////////////////////////////////
//init_addr
/////////////////////////////////////////////////////////
always @(posedge clk or posedge rst) begin
if(rst) begin
init_addr <= 1'b0;
end
else if(state_c == WRADDR) begin
init_addr <= 1'b1;
end
else begin
init_addr <= init_addr;
end
end
/////////////////////////////////////////////////////////
//wr_addr
/////////////////////////////////////////////////////////
always @(posedge clk or posedge rst) begin
if(rst) begin
wr_addr <= 32'h0;
end
else if(state_c == IDLE) begin
wr_addr <= init_addr==1'b0 ? start_addr : wr_addr;
end
else if(bwr_done) begin
if(wr_addr == end_addr + 1'b1 - (act_bwlen << BW)) begin
wr_addr <= start_addr;
end
else begin
wr_addr <= wr_addr + (act_bwlen << BW);
end
end
else begin
wr_addr <= wr_addr;
end
end
/////////////////////////////////////////////////////////
//wr_round_r
/////////////////////////////////////////////////////////
always @(posedge clk or posedge rst) begin
if(rst) begin
wr_round_r <= 1'b0;
end
else if(bwr_done && wr_addr == end_addr + 1'b1 - (act_bwlen << BW)) begin
wr_round_r <= ~wr_round_r;
end
else begin
wr_round_r <= wr_round_r;
end
end
/////////////////////////////////////////////////////////
//wr_round
/////////////////////////////////////////////////////////
assign wr_round = wr_round_r;
/////////////////////////////////////////////////////////
//AWVALID
/////////////////////////////////////////////////////////
assign AWVALID = state_c == WRADDR;
/////////////////////////////////////////////////////////
//WVALID
/////////////////////////////////////////////////////////
always @(posedge clk or posedge rst) begin
if(rst) begin
WVALID <= 1'b0;
end
else begin
if(state_c == WRDATA) begin
if(WREADY && bwr_cnt == AWLEN && WVALID ) begin
WVALID <= 1'b0;
end
else begin
WVALID <= 1'b1;
end
end
else begin
WVALID <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////
//Burst Write data last
/////////////////////////////////////////////////////////
assign WLAST = bwr_cnt == AWLEN && state_c == WRDATA && WVALID && WREADY;
/////////////////////////////////////////////////////////
//Burst Write data done OKAY:2'b00, EXOKAY:2'b01
/////////////////////////////////////////////////////////
assign bwr_done = BVALID && (BRESP==2'b00 || BRESP == 2'b01);
/////////////////////////////////////////////////////////
//act_bwlen
/////////////////////////////////////////////////////////
always @(posedge clk or posedge rst) begin
if(rst) begin
act_bwlen <= 8'h0;
end
else if(state_c == BLLD) begin
case(bwlen_loadflag)
2'b01 : begin
act_bwlen <= burst_len + 1'b1;
end
2'b10 : begin
act_bwlen <= in_fifo_rdcnt;
end
2'b11 : begin
act_bwlen <= (remsp_4k >> BW);
end
default : begin
act_bwlen <= 8'h1;
end
endcase
end
else begin
act_bwlen <= act_bwlen;
end
end
/////////////////////////////////////////////////////////
//AWLEN
/////////////////////////////////////////////////////////
assign AWLEN = act_bwlen - 1'b1;
/////////////////////////////////////////////////////////
//in_fifo_rden
/////////////////////////////////////////////////////////
assign in_fifo_rden = WREADY && WVALID;
/////////////////////////////////////////////////////////
//WDATA
/////////////////////////////////////////////////////////
assign WDATA = in_fifo_data;
/////////////////////////////////////////////////////////
//wr_ptr
/////////////////////////////////////////////////////////
assign wr_ptr = wr_addr;
/////////////////////////////////////////////////////////
//AWADDR
/////////////////////////////////////////////////////////
assign AWADDR = wr_addr;
/////////////////////////////////////////////////////////
//BREADY
/////////////////////////////////////////////////////////
assign BREADY = 1'b1;
/////////////////////////////////////////////////////////
//AWSIZE
/////////////////////////////////////////////////////////
assign AWSIZE = BW;
/////////////////////////////////////////////////////////
//AWBURST
/////////////////////////////////////////////////////////
assign AWBURST = 2'b01;
/////////////////////////////////////////////////////////
//AWCACHE
/////////////////////////////////////////////////////////
assign AWCACHE = 4'b0010;
/////////////////////////////////////////////////////////
//AWPROT
/////////////////////////////////////////////////////////
assign AWPROT = 3'b000;
/////////////////////////////////////////////////////////
//AWLOCK
/////////////////////////////////////////////////////////
assign AWLOCK = 1'b0;
/////////////////////////////////////////////////////////
//WSTRB
/////////////////////////////////////////////////////////
assign WSTRB = {(DATA_WIDTH/8){1'b1}};
/////////////////////////////////////////////////////////
//RREADY
/////////////////////////////////////////////////////////
assign wr_state = state_c;
endmodule

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@ -0,0 +1,825 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/02/28 15:03:51
// Design Name:
// Module Name: cache_spi
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module cache_axis#
(parameter DEBUG = 0
)(
input clk,
input reset,
input [31:0] rx_start_addr,
input [31:0] rx_end_addr,
input [31:0] tx_start_addr,
input [31:0] tx_end_addr,
//**************tx interface********************** 上行的数是按照top模块的时钟给出去需要fifo转一下时钟
//output tx_fifo_wren,
//output [31:0] tx_fifo_wrdata,
//output tx_fifo_full,
//output tx_fifo_af ,
//input tx_fifo_rden,
//output tx_fifo_empty,
output tx_out_m_axis_tvalid,
input tx_out_m_axis_tready,
output [31 : 0] tx_out_m_axis_tdata ,
output [31 : 0] tx_cache_pkg_cnt_o,
//**************rx interface********************** 下行的数是按照mux模块给的时钟给的所以时钟是不需要再转换
//input [31 : 0] rx_in_fifo_data,
//input [10 : 0] rx_axis_rd_data_count,
//output rx_in_fifo_rden,
input rx_in_s_axis_tvalid,
output rx_in_s_axis_tready,
input [31:0] rx_in_s_axis_tdata ,
output [31 : 0] rx_cache_pkg_cnt_o,
//**************srd_rx axi************************
input rx_AWREADY, // Indicates slave is ready to accept a
output [31:0] rx_AWADDR , // Write address
output rx_AWVALID, // Write address valid
output [2 :0] rx_AWSIZE , // Write size
output [1 :0] rx_AWBURST, // Burst type
output [3 :0] rx_AWCACHE, // Write cache
output [2 :0] rx_AWPROT , // Write protect
output [0 :0] rx_AWLOCK , // Write bus lock
input rx_WREADY, // Write data ready
output [7 :0] rx_AWLEN , // Burst write length
output [31:0] rx_WDATA , // Write data
output rx_WLAST , // Last write transaction
output rx_WVALID, // Write valid
output [3 :0] rx_WSTRB ,
input [1 :0] rx_BRESP , // Write response
input rx_BVALID, // Write reponse valid
output rx_BREADY, // Response ready
input rx_ARREADY, // Indicates slave is ready to accept a
output [31:0] rx_ARADDR , // read address
output rx_ARVALID, // read address valid
output [2 :0] rx_ARSIZE , // read size
output [7 :0] rx_ARLEN , // Burst read length
output [1 :0] rx_ARBURST, // Burst type
output [3 :0] rx_ARCACHE,
output [2 :0] rx_ARPROT ,
output [0 :0] rx_ARLOCK ,
output rx_RREADY , // read data ready
input [31:0] rx_RDATA , // read data
input rx_RLAST , // Last read transaction
input rx_RVALID , // read valid
input [1 :0] rx_RRESP , // read response
//**************srd_tx axi************************
input tx_AWREADY, // Indicates slave is ready to accept a
output [31:0] tx_AWADDR , // Write address
output tx_AWVALID, // Write address valid
output [2 :0] tx_AWSIZE , // Write size
output [1 :0] tx_AWBURST, // Burst type
output [3 :0] tx_AWCACHE, // Write cache
output [2 :0] tx_AWPROT , // Write protect
output [0 :0] tx_AWLOCK , // Write bus lock
input tx_WREADY, // Write data ready
output [7 :0] tx_AWLEN , // Burst write length
output [31:0] tx_WDATA , // Write data
output tx_WLAST , // Last write transaction
output tx_WVALID, // Write valid
output [3 :0] tx_WSTRB ,
input [1 :0] tx_BRESP , // Write response
input tx_BVALID, // Write reponse valid
output tx_BREADY, // Response ready
input tx_ARREADY, // Indicates slave is ready to accept a
output [31:0] tx_ARADDR , // read address
output tx_ARVALID, // read address valid
output [2 :0] tx_ARSIZE , // read size
output [7 :0] tx_ARLEN , // Burst read length
output [1 :0] tx_ARBURST, // Burst type
output [3 :0] tx_ARCACHE,
output [2 :0] tx_ARPROT ,
output [0 :0] tx_ARLOCK ,
output tx_RREADY , // read data ready
input [31:0] tx_RDATA , // read data
input tx_RLAST , // Last read transaction
input tx_RVALID , // read valid
input [1 :0] tx_RRESP , // read response
/*
//spi port
output sclk, // Spi Clock
output csn , // Spi Chip Select active low
output mosi, // Spi Mosi
input miso, // Spi Miso
input irq,
*/
//axis port
output [31:0] WDATA_axis_m,
output WVALID_axis_m,
input WREADY_axis_m,
input [31:0] RDATA_axis_s,
input RVALID_axis_s,
output RREADY_axis_s
);
//////////////////////////// axi_srd_cache ////////////////////////////////
wire fifo_wr_en;
wire [31:0] fifo_din;
wire fifo_full;
//wire fifo_almost_full;
//wire fifo_prog_full;
wire fifo_rd_en;
wire [31:0] fifo_dout;
wire fifo_empty;
//wire fifo_almost_empty;
//wire fifo_prog_empty;
wire [9:0] fifo_cnt;
// ddr
//wire [31 : 0] tx_axis_wr_data_count;
wire [5 : 0] rx_wr_state ;
wire [5 : 0] rx_rd_state ;
wire [31 : 0] rx_use_cnt_o;
//wire [31 : 0] rx_in_fifo_data;
//wire [10 : 0] rx_axis_rd_data_count;
//wire rx_in_fifo_rden ;
//wire rx_in_fifo_full;
reg rx_out_fifo_rden ;
wire [31 : 0] rx_out_fifo_data ;
wire rx_out_fifo_empty;
wire rx_out_fifo_full ;
//tx
wire [5 : 0] tx_wr_state ;
wire [5 : 0] tx_rd_state ;
wire [31 : 0] tx_use_cnt_o;
wire tx_in_fifo_rden ;
wire tx_out_fifo_rden ;
wire [31 : 0] tx_out_fifo_data ;
wire tx_out_fifo_full ;
//assign s0_user_rx_fifo_rdclk = clk; // 读数据就用系统时钟
//assign s0_user_rx_fifo_rden = ~rx_in_fifo_full;
//assign rx_s_axis_tvalid = (s0_user_rx_fifo_valid) & (~rx_out_fifo_full);
////////////////////////////////// spi //////////////////////////////////////////
//**********************************下行*******************************************
//fifo_generator_0 fifo_generator_0_rx( // change fifo to get a more accurate fifo data count
// .wr_clk (clk), // input
// .rd_clk (clk), // input
// .din (s0_user_rx_fifo_rddata), // input [31:0]
// .wr_en (rx_s_axis_tvalid), // input
// .rd_en (rx_in_fifo_rden), // input
// .rd_rst (reset),
// .wr_rst (reset),
// .dout (rx_in_fifo_data), // output [31:0]
// .full (rx_in_fifo_full), // output
// .empty (), // output
//// .wr_data_count(rx_axis_wr_data_count), // output [10:0]
// .rd_data_count(rx_axis_rd_data_count)
//);
// axis to cache
// wire [31 : 0] rx_in_fifo_data;
// wire [31 : 0] rx_axis_rd_data_count;
// wire rx_in_fifo_rden;
// wire rx_in_m_axis_tvalid;
// axis_data_fifo_cache axis_data_fifo_cache_rx(
// .s_axis_aresetn (~reset), // input
// .s_axis_aclk (clk), // input
// .s_axis_tvalid (rx_in_s_axis_tvalid), // input
// .s_axis_tready (rx_in_s_axis_tready), // output
// .s_axis_tdata (rx_in_s_axis_tdata ), // input [31:0]
// //output port
// .m_axis_tvalid (rx_in_m_axis_tvalid), // output
// .m_axis_tready (rx_in_fifo_rden), // input
// .m_axis_tdata (rx_in_fifo_data), // output [31:0]
// .axis_wr_data_count(), // output [31:0]
// .axis_rd_data_count(rx_axis_rd_data_count), // output [31:0]
// .almost_full (), // output
// .prog_full () // output
// );
// axis to cache
wire rx_in_m_axis_tvalid;
wire rx_in_s_axis_tready_o;
wire rx_in_fifo_rden;
wire [31 : 0] rx_in_fifo_data;
wire [31 : 0] rx_axis_rd_data_count;
wire [31 : 0] rx_axis_wr_data_count;
wire prog_full;
axis_data_fifo_cache axis_data_fifo_cache_rx(
.s_axis_aresetn (~reset), // input
.s_axis_aclk (clk), // input
.s_axis_tvalid (rx_in_s_axis_tvalid && (~prog_full)), // input
.s_axis_tready (rx_in_s_axis_tready_o), // output
.s_axis_tdata (rx_in_s_axis_tdata ), // input [31:0]
.m_axis_tvalid (rx_in_m_axis_tvalid), // output
.m_axis_tready (rx_in_fifo_rden), // input
.m_axis_tdata (rx_in_fifo_data), // output [31:0]
.axis_wr_data_count(rx_axis_wr_data_count), // output [31:0]
.axis_rd_data_count(rx_axis_rd_data_count), // output [31:0]
.almost_full (), // output
.prog_full (prog_full) // output
);
assign rx_in_s_axis_tready = rx_in_s_axis_tready_o && (~prog_full);
axi_srd_cache #(
.TO_WIDTH (16),
.DATA_WIDTH (32),
.FIFO_DEPTH (512),
.PROG_FULL_THRE (256)
)axi_srd_cache_rx(
// system signals
.clk (clk), // System clock input
.wr_rst (reset), // Write reset, hight active input
.rd_rst (reset), // Read reset, hight active input
// config signals
.rw_to (16'd50 ), // Write timeout input [TO_WIDTH-1 :0]
.burst_len (8'd3 ), // Axi write burst length input [31 :0]
.timout_mode (1'b1 ), // Timeout mode enable, hight active input
.start_addr (rx_start_addr), // Start addr input [31 :0] 32'h0000_0000
.end_addr (rx_end_addr ), // End addr input [31 :0] 32'h7FFF_FFFF
.wr_state (rx_wr_state ), // Read status output [5 :0]
.rd_state (rx_rd_state ), // Read status output [5 :0]
.use_cnt_o (rx_use_cnt_o ), // DDR memory used space output [31 :0]
// AXI write channel signals
/* Input fifo signals */
.in_fifo_data (rx_in_fifo_data ), // Input fifo read data input [DATA_WIDTH-1 :0]
.in_fifo_rdcnt (rx_axis_rd_data_count[10:0]), // Input fifo read data count input [clog2(FIFO_DEPTH-1)-1:0] rx_in_fifo_rdcnt
.in_fifo_rden (rx_in_fifo_rden ), // Input fifo read enable, hight active output
/* AXI write address channel signals */
.AWREADY (rx_AWREADY), // Indicates slave is ready to accept input
.AWADDR (rx_AWADDR ), // Write address output [31 :0]
.AWVALID (rx_AWVALID), // Write address valid output
.AWSIZE (rx_AWSIZE ), // Write size output [2 :0]
.AWBURST (rx_AWBURST), // Burst type output [1 :0]
.AWCACHE (rx_AWCACHE), // Write cache output [3 :0]
.AWPROT (rx_AWPROT ), // Write protect output [2 :0]
.AWLOCK (rx_AWLOCK ), // Write bus lock output [0 :0]
/*AXI write data channel signals*/
.WREADY (rx_WREADY), // Write data ready input
.AWLEN (rx_AWLEN ), // Burst write length output [7 :0]
.WDATA (rx_WDATA ), // Write data output [DATA_WIDTH-1 :0]
.WLAST (rx_WLAST ), // Last write transaction output
.WVALID (rx_WVALID), // Write valid output
.WSTRB (rx_WSTRB ), // output [(DATA_WIDTH/8)-1 :0]
/*AXI write response channel signals*/
.BRESP (rx_BRESP ), // Write response input [1 :0]
.BVALID (rx_BVALID), // Write reponse valid input
.BREADY (rx_BREADY), // Response ready output
// AXI read channel signals
/* Input fifo signals */
.out_fifo_rden ((rx_out_fifo_rden & (~rx_out_fifo_empty) & (~fifo_full))),// Output fifo read enable, high active input
.out_fifo_data (rx_out_fifo_data ),// Output fifo read data output [DATA_WIDTH-1 :0]
.out_fifo_empty (rx_out_fifo_empty ),// Output fifo empty output
.out_fifo_full (rx_out_fifo_full ),// Output fifo full output
/* AXI read address channel signals */
.ARREADY (rx_ARREADY), // Indicates slave is ready to accept input
.ARADDR (rx_ARADDR ), // read address output [31 :0]
.ARVALID (rx_ARVALID), // read address valid output
.ARSIZE (rx_ARSIZE ), // read size output [2 :0]
.ARLEN (rx_ARLEN ), // Burst read length output [7 :0]
.ARBURST (rx_ARBURST), // Burst type output [1 :0]
.ARCACHE (rx_ARCACHE), // output [3 :0]
.ARPROT (rx_ARPROT ), // output [2 :0]
.ARLOCK (rx_ARLOCK ), // output [0 :0]
/* AXI read data channel signals */
.RREADY (rx_RREADY), // read data ready output
.RDATA (rx_RDATA ), // read data input [DATA_WIDTH-1 :0]
.RLAST (rx_RLAST ), // Last read transaction input
.RVALID (rx_RVALID), // read valid input
/* AXI read response channel signals */
.RRESP (rx_RRESP ) // read response input [1 :0]
);
always@(posedge clk)
begin
// if(reset || fifo_almost_full || rx_out_fifo_empty)
if(reset || fifo_full || rx_out_fifo_empty) // srd fifo 未空且下一级fifo 未满就一直读
begin
rx_out_fifo_rden <= 1'b0;
end
else
begin
rx_out_fifo_rden <= 1'b1;
end
end
assign fifo_din = rx_out_fifo_data; // spi can repackage, no need to do here
assign fifo_wr_en = rx_out_fifo_rden && (~rx_out_fifo_empty)&& (~fifo_full); //
// rx 帧计数
reg [31 : 0] rx_cache_pkg_cnt;
reg [19 : 0] rx_pkg_length_in;
reg [17 : 0] rx_pkg_cnt_in;
reg [19 : 0] rx_pkg_length_out;
reg [17 : 0] rx_pkg_cnt_out;
// in
always@(posedge clk)
begin
if(reset || (rx_pkg_cnt_in == rx_pkg_length_in + 18'd2))
begin
rx_pkg_cnt_in <= 18'b0;
end
else if(rx_in_fifo_rden && (rx_axis_rd_data_count > 10'b0))
begin
rx_pkg_cnt_in <= rx_pkg_cnt_in + 18'b1;
end
end
always@(posedge clk)
begin
if(reset)
begin
rx_pkg_length_in <= 20'b0;
end
else if(rx_pkg_cnt_in == 18'b1)
begin
rx_pkg_length_in <= rx_in_fifo_data[19:0] >> 2;
end
end
// out
always@(posedge clk)
begin
if(reset || (rx_pkg_cnt_out == rx_pkg_length_out + 18'd2))
begin
rx_pkg_cnt_out <= 18'b0;
end
else if(rx_out_fifo_rden && (~rx_out_fifo_empty))
begin
rx_pkg_cnt_out <= rx_pkg_cnt_out + 18'b1;
end
end
always@(posedge clk)
begin
if(reset)
begin
rx_pkg_length_out <= 20'b0;
end
else if(rx_pkg_cnt_out == 18'b1)
begin
rx_pkg_length_out <= rx_out_fifo_data[19:0] >> 2;
end
end
//
always@(posedge clk)
begin
if(reset)
begin
rx_cache_pkg_cnt <= 32'b0;
end
else if(rx_pkg_cnt_in == rx_pkg_length_in + 18'd2)
begin
rx_cache_pkg_cnt <= rx_cache_pkg_cnt + 32'b1; // in
end
else if(rx_pkg_cnt_out == rx_pkg_length_out + 18'd2)
begin
rx_cache_pkg_cnt <= rx_cache_pkg_cnt - 32'b1; // out
end
end
assign rx_cache_pkg_cnt_o = rx_cache_pkg_cnt;
//********************************上行时钟转换****************************************
wire tx_out_s_axis_tready;
wire tx_out_fifo_empty;
wire tx_out_m_full;
wire tx_out_fifo_af;
axi_srd_cache #(
.TO_WIDTH (16),
.DATA_WIDTH (32),
.FIFO_DEPTH (512),
.PROG_FULL_THRE (256)
)axi_srd_cache_tx(
// system signals
.clk (clk), // System clock input
.wr_rst (reset), // Write reset, hight active input
.rd_rst (reset), // Read reset, hight active input
// config signals
.rw_to (16'd50 ), // Write timeout input [TO_WIDTH-1 :0]
.burst_len (8'd3 ), // Axi write burst length input [7 :0]
.timout_mode (1'b1 ), // Timeout mode enable, hight active input
.start_addr (tx_start_addr), // Start addr input [31 :0] 32'h8000_0000
.end_addr (tx_end_addr ), // End addr input [31 :0] 32'hFFFF_FFFF
.wr_state (tx_wr_state ), // Read status output [5 :0]
.rd_state (tx_rd_state ), // Read status output [5 :0]
.use_cnt_o (tx_use_cnt_o ), // DDR memory used space output [31 :0]
// AXI write channel signals
/* Input fifo signals */
.in_fifo_data (fifo_dout), // Input fifo read data input [DATA_WIDTH-1 :0]
.in_fifo_rdcnt (fifo_cnt ), // Input fifo read data count input [clog2(FIFO_DEPTH-1)-1:0] rx_in_fifo_rdcnt
.in_fifo_rden (tx_in_fifo_rden ), // Input fifo read enable, hight active output
/* AXI write address channel signals */
.AWREADY (tx_AWREADY), // Indicates slave is ready to accept input
.AWADDR (tx_AWADDR ), // Write address output [31 :0]
.AWVALID (tx_AWVALID), // Write address valid output
.AWSIZE (tx_AWSIZE ), // Write size output [2 :0]
.AWBURST (tx_AWBURST), // Burst type output [1 :0]
.AWCACHE (tx_AWCACHE), // Write cache output [3 :0]
.AWPROT (tx_AWPROT ), // Write protect output [2 :0]
.AWLOCK (tx_AWLOCK ), // Write bus lock output [0 :0]
/*AXI write data ctannel signals*/
.WREADY (tx_WREADY), // Write data ready input
.AWLEN (tx_AWLEN ), // Burst write length output [7 :0]
.WDATA (tx_WDATA ), // Write data output [DATA_WIDTH-1 :0]
.WLAST (tx_WLAST ), // Last write transaction output
.WVALID (tx_WVALID), // Write valid output
.WSTRB (tx_WSTRB ), // output [(DATA_WIDTH/8)-1 :0]
/*AXI write responte channel signals*/
.BRESP (tx_BRESP ), // Write response input [1 :0]
.BVALID (tx_BVALID), // Write reponse valid input
.BREADY (tx_BREADY), // Response ready output
// AXI read channel signals
/* Input fifo signals */
// .out_fifo_rden (tx_fifo_rden & (~tx_out_fifo_empty) ), // Output fifo read enable, high active input
// .out_fifo_data (tx_out_fifo_data ), // Output fifo read data output [DATA_WIDTH-1 :0]
// .out_fifo_empty (tx_out_fifo_empty), // Output fifo empty output
// .out_fifo_full (tx_out_fifo_full ), // Output fifo full output
// .out_fifo_af (tx_out_fifo_af),
.out_fifo_rden (tx_out_s_axis_tready & (~tx_out_fifo_empty) & (~tx_out_m_full) ), // Output fifo read enable, high active input
.out_fifo_data (tx_out_fifo_data ), // Output fifo read data output [DATA_WIDTH-1 :0]
.out_fifo_empty (tx_out_fifo_empty), // Output fifo empty output
.out_fifo_full (tx_out_fifo_full ), // Output fifo full output
.out_fifo_af (tx_out_fifo_af),
/* AXI read address channel signals */
.ARREADY (tx_ARREADY), // Indicates slave is ready to accept input
.ARADDR (tx_ARADDR ), // read address output [31 :0]
.ARVALID (tx_ARVALID), // read address valid output
.ARSIZE (tx_ARSIZE ), // read size output [2 :0]
.ARLEN (tx_ARLEN ), // Burst read length output [7 :0]
.ARBURST (tx_ARBURST), // Burst type output [1 :0]
.ARCACHE (tx_ARCACHE), // output [3 :0]
.ARPROT (tx_ARPROT ), // output [2 :0]
.ARLOCK (tx_ARLOCK ), // output [0 :0]
/* AXI read data channel signals */
.RREADY (tx_RREADY), // read data ready output
.RDATA (tx_RDATA ), // read data input [DATA_WIDTH-1 :0]
.RLAST (tx_RLAST ), // Last read transaction input
.RVALID (tx_RVALID), // read valid input
/* AXI read response channel signals */
.RRESP (tx_RRESP ) // read response input [1 :0]
);
assign fifo_rd_en = tx_in_fifo_rden && (~tx_out_fifo_full); // cache_tx 输入
//wire tx_out_s_axis_tvalid; // input
//wire tx_out_s_axis_tready; // output
//wire [31:0] tx_out_s_axis_tdata ; // input [31:0]
//wire tx_out_m_axis_tvalid; // output
//wire tx_out_m_axis_tready; // input
//wire [31:0] tx_out_m_axis_tdata ; // output [31:0]
//wire tx_out_m_full;
//output tx_fifo_wren,
//output [31:0] tx_fifo_wrdata,
//output tx_fifo_full,
//output tx_fifo_af ,
//input tx_fifo_rden,
//output tx_fifo_empty,
axis_data_fifo_cache axis_data_fifo_cache_tx(
.s_axis_aresetn (~reset), // input
.s_axis_aclk (clk), // input
.s_axis_tvalid (~tx_out_fifo_empty), // input
.s_axis_tready (tx_out_s_axis_tready), // output
.s_axis_tdata (tx_out_fifo_data ), // input [31:0]
.m_axis_tvalid (tx_out_m_axis_tvalid), // output
.m_axis_tready (tx_out_m_axis_tready), // input
.m_axis_tdata (tx_out_m_axis_tdata), // output [31:0]
.axis_wr_data_count(), // output [31:0]
.axis_rd_data_count(), // output [31:0]
.almost_full (), // output
.prog_full (tx_out_m_full) // output
);
//assign tx_fifo_wren = tx_out_fifo_rden;
//assign tx_fifo_wrdata = tx_out_fifo_data;
//assign tx_fifo_full = tx_out_fifo_full;
//assign tx_fifo_af = tx_out_fifo_af;
//assign tx_fifo_empty = tx_out_fifo_empty;
//assign tx_out_fifo_rden = tx_fifo_rden && (~tx_out_fifo_empty);
assign tx_out_fifo_rden = (~tx_out_fifo_empty) && tx_out_s_axis_tready;
// tx 帧计数
reg [31 : 0] tx_cache_pkg_cnt;
reg [19 : 0] tx_pkg_length_in;
reg [17 : 0] tx_pkg_cnt_in;
reg [19 : 0] tx_pkg_length_out;
reg [17 : 0] tx_pkg_cnt_out;
// in
always@(posedge clk)
begin
if(reset || (tx_in_fifo_rden && (tx_pkg_cnt_in == tx_pkg_length_in + 18'd1) && (tx_pkg_cnt_in > 18'b1)))
begin
tx_pkg_cnt_in <= 18'b0;
end
else if(tx_in_fifo_rden && (fifo_cnt > 'b0))
begin
tx_pkg_cnt_in <= tx_pkg_cnt_in + 18'b1;
end
end
always@(posedge clk)
begin
if(reset)
begin
tx_pkg_length_in <= 20'b0;
end
else if(tx_in_fifo_rden && (tx_pkg_cnt_in == 18'b1))
begin
tx_pkg_length_in <= fifo_dout[19:0] >> 2;
end
end
// out
always@(posedge clk)
begin
if(reset || (tx_out_fifo_rden && (tx_pkg_cnt_out == tx_pkg_length_out + 18'd1) && (tx_pkg_cnt_out > 18'b1)))
begin
tx_pkg_cnt_out <= 18'b0;
end
else if(tx_out_fifo_rden) // 是否要用用下一级FIFO的read en tx_fifo_rden
begin
tx_pkg_cnt_out <= tx_pkg_cnt_out + 18'b1;
end
end
always@(posedge clk)
begin
if(reset)
begin
tx_pkg_length_out <= 20'b0;
end
else if(tx_out_fifo_rden && (tx_pkg_cnt_out == 18'b1))
begin
tx_pkg_length_out <= tx_out_fifo_data[19:0] >> 2;
end
end
//
always@(posedge clk)
begin
if(reset)
begin
tx_cache_pkg_cnt <= 32'b0;
end
else if(tx_in_fifo_rden && (fifo_cnt > 'b0) && ((tx_pkg_cnt_in == tx_pkg_length_in) && (tx_pkg_cnt_in > 18'b0) || ((tx_pkg_cnt_in == 32'b1) && (fifo_dout[19:0] == 32'd4)))) // 使cnt变化对齐最后一个数
begin
tx_cache_pkg_cnt <= tx_cache_pkg_cnt + 32'b1; // in
end
else if(tx_out_fifo_rden && ((tx_pkg_cnt_out == tx_pkg_length_out) && (tx_pkg_cnt_out > 18'b0) || ((tx_pkg_cnt_out == 32'b1) && (tx_out_fifo_data[19:0] == 32'd4))))
begin
tx_cache_pkg_cnt <= tx_cache_pkg_cnt - 32'b1; // out
end
end
assign tx_cache_pkg_cnt_o = tx_cache_pkg_cnt;
//axis_data_fifo_2 axis_data_fifo_2_tx(
// .s_axis_aresetn (~reset ), // input
// .s_axis_aclk (clk ), // input /* synthesis syn_isclock = 1 */;
// .s_axis_tvalid (~tx_out_fifo_empty ), // input
// .s_axis_tready (tx_out_fifo_rden ), // output tx_s_axis_tready
// .s_axis_tdata (tx_out_fifo_data ), // input [31:0]
// .m_axis_aclk (s0_user_tx_fifo_rdclk ), // input /* synthesis syn_isclock = 1 */; 转换成tcp的时钟域
// .m_axis_tvalid (s0_tx_m_axis_tvalid ), // output
// .m_axis_tready (s0_user_tx_fifo_rden ), // input
// .m_axis_tdata (s0_user_tx_fifo_rddata), // output [31:0]
// .axis_wr_data_count(tx_axis_wr_data_count ) // output [31:0]
//);
//assign s0_user_tx_fifo_rdcnt = tx_axis_wr_data_count[11 : 0];
//////////////////////////////////FIFO to spi//////////////////////////////////////////////////
reg spi_rx_rd_en;
reg spi_rx_rd_en_r;
wire [31 : 0] spi_rx_dout;
wire spi_rx_dready;
wire spi_rx_empty;
wire spi_rx_almost_empty;
wire spi_rx_prog_empty;
wire [10 : 0] spi_rx_cnt;
wire spi_tx_wr_en;
wire [31 : 0] spi_tx_din;
wire spi_tx_full;
wire spi_tx_almost_full;
wire spi_tx_prog_full;
wire [31 : 0] WDATA_spi;
wire WVALID_spi;
wire WREADY_spi;
wire spi_busy;
wire spi_tlast_z;
wire spi_tlast;
wire [31 : 0] spi_length;
wire spi_wr;
wire [31 : 0] RDATA_spi;
wire RVALID_spi;
wire READY_spi;
//syn_std_fifo #(
// .width (32 ),
// .depth (1024),
// .prog_full_thre (512 ),
// .prog_empty_thre (16 )
//)syn_std_fifo_rx(
// .clk (clk), // input
// .rst (reset), // input rst,
// .wr_en (fifo_wr_en ), // input
// .din (fifo_din ), // input [width-1:0]
// .full (fifo_full ), // output
// .almost_full (fifo_almost_full ), // output
// .prog_full (fifo_prog_full ), // output
// .rd_en ((~spi_rx_empty) && (WREADY_spi)), // input
// .dout (spi_rx_dout ), // output [width-1:0]
// .empty (spi_rx_empty ), // output
// .almost_empty(spi_rx_almost_empty), // output
// .prog_empty (spi_rx_prog_empty ), // output
// .cnt (spi_rx_cnt ) // output [clog2(depth-1)-1:0]
//);
fifo_generator_0 fifo_generator_0_rx_master( // change fifo to get a more accurate fifo data count
.wr_clk (clk), // input
.rd_clk (clk), // input
.din (fifo_din), // input [31:0]
.wr_en (fifo_wr_en), // input
.rd_en ((~spi_rx_empty) && (WREADY_spi)), // input
.rd_rst (reset),
.wr_rst (reset),
.dout (spi_rx_dout), // output [31:0]
.full (fifo_full), // output
.empty (spi_rx_empty), // output
// .wr_data_count(rx_axis_wr_data_count), // output [10:0]
.rd_data_count(spi_rx_cnt)
);
fifo_generator_0 fifo_generator_0_tx_master( // change fifo to get a more accurate fifo data count
.wr_clk (clk), // input
.rd_clk (clk), // input
.din (spi_tx_din), // input [31:0]
.wr_en (spi_tx_wr_en), // input
.rd_en (fifo_rd_en), // input
.rd_rst (reset),
.wr_rst (reset),
.dout (fifo_dout), // output [31:0]
.full (spi_tx_full), // output
.empty (fifo_empty), // output
// .wr_data_count(rx_axis_wr_data_count), // output [10:0]
.rd_data_count(fifo_cnt)
);
always@(posedge clk)
begin
if((~spi_rx_empty) && WREADY_spi)
begin
spi_rx_rd_en <= 1'b1;
end
else if((spi_rx_cnt == 11'b0) || (~WREADY_spi)) //////////
begin
spi_rx_rd_en <= 1'b0;
end
spi_rx_rd_en_r <= spi_rx_rd_en && (~spi_rx_empty) && (WREADY_spi);
end
assign WDATA_axis_m = spi_rx_dout;
assign WVALID_axis_m = ~spi_rx_empty;
assign WREADY_spi = WREADY_axis_m;
assign spi_tx_din = RDATA_axis_s;
assign spi_tx_wr_en = RVALID_axis_s;
assign RREADY_axis_s = ~spi_tx_full;
//width 349
// generate
// if (DEBUG == 1) begin: debug_gen
// ila_cache_ezq2p0 ila_cache_ezq2p0_u(
// .clk(clk),
// .probe0({
// tx_out_m_axis_tvalid,
// // tx_out_m_axis_tready,
// tx_out_m_axis_tdata ,
// rx_in_s_axis_tvalid,
// rx_in_s_axis_tready,
// rx_in_s_axis_tdata ,
// rx_in_s_axis_tready_o,
// prog_full,
// rx_in_m_axis_tvalid,
// rx_in_fifo_rden,
// rx_in_fifo_data,
// rx_axis_rd_data_count,
// rx_out_fifo_data,
// rx_out_fifo_empty,
// rx_out_fifo_full,
// fifo_din,
// fifo_wr_en,
// // spi_rx_empty,
// WREADY_spi,
// spi_rx_dout,
// fifo_full,
// spi_rx_empty,
// RDATA_axis_s,
// RVALID_axis_s,
// spi_tx_full,
// rx_WREADY ,
// rx_AWLEN ,
// rx_WDATA ,
// rx_WLAST ,
// rx_WVALID ,
// rx_RREADY ,
// rx_RDATA ,
// rx_RLAST ,
// rx_RVALID
// })
// );
// end
// endgenerate
/*
spi_m_1 #
(.DEBUG(DEBUG))
spi_m_1_u(
.sys_clk (clk), // input
.sys_rst_n (~reset), // input
// fifo trans
.WDATA_spi (spi_rx_dout), // input [31 : 0]
.WVALID_spi (~spi_rx_empty), // input ~spi_rx_empty
.WREADY_spi (WREADY_spi), // output spi_rx_rd_en
.spi_busy (), // output ~ss
.tlast_zo (),
.tlast_o (),
.cmd_length_o (),
.cmd_wr_o (),
// fifo read
.READY_spi (~spi_tx_full), // input
.RVALID_spi_o (spi_tx_wr_en), // output
.RDATA_spi_o (spi_tx_din), // output [32 : 0]
// spi slave
.spi_slave_bit (miso), // input
.ss (csn), // output
.spi_clk (sclk), // output
.spi_master_bit (mosi), // output
.irq (irq)
);
*/
endmodule

View File

@ -0,0 +1,827 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/02/28 15:03:51
// Design Name:
// Module Name: cache_spi
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module cache_spi#
(parameter DEBUG = 0
)(
input clk,
input reset,
input [31: 0] rx_start_addr,
input [31: 0] rx_end_addr,
input [31: 0] tx_start_addr,
input [31: 0] tx_end_addr,
//**************tx interface********************** ???<EFBFBD><EFBFBD>????????top????????????????fifo???????
//output tx_fifo_wren,
//output [31:0] tx_fifo_wrdata,
//output tx_fifo_full,
//output tx_fifo_af ,
//input tx_fifo_rden,
//output tx_fifo_empty,
output tx_out_m_axis_tvalid,
input tx_out_m_axis_tready,
output [31: 0] tx_out_m_axis_tdata ,
output [31: 0] tx_cache_pkg_cnt_o,
//**************rx interface********************** ???<EFBFBD><EFBFBD>????????mux???????????????????????????????
//input [31 : 0] rx_in_fifo_data,
//input [10 : 0] rx_axis_rd_data_count,
//output rx_in_fifo_rden,
input rx_in_s_axis_tvalid,
output rx_in_s_axis_tready,
input [31: 0] rx_in_s_axis_tdata ,
output [31: 0] rx_cache_pkg_cnt_o,
//**************srd_rx axi************************
input rx_AWREADY, // Indicates slave is ready to accept a
output [31:0] rx_AWADDR , // Write address
output rx_AWVALID, // Write address valid
output [2 :0] rx_AWSIZE , // Write size
output [1 :0] rx_AWBURST, // Burst type
output [3 :0] rx_AWCACHE, // Write cache
output [2 :0] rx_AWPROT , // Write protect
output [0 :0] rx_AWLOCK , // Write bus lock
input rx_WREADY, // Write data ready
output [7 :0] rx_AWLEN , // Burst write length
output [31:0] rx_WDATA , // Write data
output rx_WLAST , // Last write transaction
output rx_WVALID, // Write valid
output [3 :0] rx_WSTRB ,
input [1 :0] rx_BRESP , // Write response
input rx_BVALID, // Write reponse valid
output rx_BREADY, // Response ready
input rx_ARREADY, // Indicates slave is ready to accept a
output [31:0] rx_ARADDR , // read address
output rx_ARVALID, // read address valid
output [2 :0] rx_ARSIZE , // read size
output [7 :0] rx_ARLEN , // Burst read length
output [1 :0] rx_ARBURST, // Burst type
output [3 :0] rx_ARCACHE,
output [2 :0] rx_ARPROT ,
output [0 :0] rx_ARLOCK ,
output rx_RREADY , // read data ready
input [31:0] rx_RDATA , // read data
input rx_RLAST , // Last read transaction
input rx_RVALID , // read valid
input [1 :0] rx_RRESP , // read response
//**************srd_tx axi************************
input tx_AWREADY, // Indicates slave is ready to accept a
output [31:0] tx_AWADDR , // Write address
output tx_AWVALID, // Write address valid
output [2 :0] tx_AWSIZE , // Write size
output [1 :0] tx_AWBURST, // Burst type
output [3 :0] tx_AWCACHE, // Write cache
output [2 :0] tx_AWPROT , // Write protect
output [0 :0] tx_AWLOCK , // Write bus lock
input tx_WREADY, // Write data ready
output [7 :0] tx_AWLEN , // Burst write length
output [31:0] tx_WDATA , // Write data
output tx_WLAST , // Last write transaction
output tx_WVALID, // Write valid
output [3 :0] tx_WSTRB ,
input [1 :0] tx_BRESP , // Write response
input tx_BVALID, // Write reponse valid
output tx_BREADY, // Response ready
input tx_ARREADY, // Indicates slave is ready to accept a
output [31:0] tx_ARADDR , // read address
output tx_ARVALID, // read address valid
output [2 :0] tx_ARSIZE , // read size
output [7 :0] tx_ARLEN , // Burst read length
output [1 :0] tx_ARBURST, // Burst type
output [3 :0] tx_ARCACHE,
output [2 :0] tx_ARPROT ,
output [0 :0] tx_ARLOCK ,
output tx_RREADY , // read data ready
input [31:0] tx_RDATA , // read data
input tx_RLAST , // Last read transaction
input tx_RVALID , // read valid
input [1 :0] tx_RRESP , // read response
//rslt_push port
input [31:0] s_axis_rdata_rslt,
input s_axis_rvalid_rslt,
output s_axis_rready_rslt,
//spi port
output sclk, // Spi Clock
output csn , // Spi Chip Select active low
output mosi, // Spi Mosi
input miso, // Spi Miso
input irq ,
//rx_spi port
output [31:0] m_axis_tdata_spi,
output m_axis_tvalid_spi,
input m_axis_tready_spi,
output [31:0] tx_cache_pkg_cnt_spi_o
);
//**********************************????*******************************************
// axis to cache
wire rx_in_m_axis_tvalid;
wire rx_in_s_axis_tready_o;
wire rx_in_fifo_rden;
wire [31 : 0] rx_in_fifo_data;
wire [31 : 0] rx_axis_rd_data_count;
wire [31 : 0] rx_axis_wr_data_count;
wire prog_full;
axis_data_fifo_cache axis_data_fifo_cache_rx(
.s_axis_aresetn (~reset), // input
.s_axis_aclk (clk), // input
.s_axis_tvalid (rx_in_s_axis_tvalid && (~prog_full)), // input
.s_axis_tready (rx_in_s_axis_tready_o), // output
.s_axis_tdata (rx_in_s_axis_tdata ), // input [31:0]
.m_axis_tvalid (rx_in_m_axis_tvalid), // output
.m_axis_tready (rx_in_fifo_rden), // input
.m_axis_tdata (rx_in_fifo_data), // output [31:0]
.axis_wr_data_count(rx_axis_wr_data_count), // output [31:0]
.axis_rd_data_count(rx_axis_rd_data_count), // output [31:0]
.almost_full (), // output
.prog_full (prog_full) // output
);
assign rx_in_s_axis_tready = rx_in_s_axis_tready_o && (~prog_full);
// rx ddr
wire [5 : 0] rx_wr_state ;
wire [5 : 0] rx_rd_state ;
wire [31 : 0] rx_use_cnt_o;
wire rx_out_fifo_rden ;
wire [31 : 0] rx_out_fifo_data ;
wire rx_out_fifo_empty;
wire rx_out_fifo_full ;
//rx fifo
wire rx_fifo_wr_en;
wire rx_spi_full;
wire [31 : 0] rx_spi_dout;
wire rx_spi_empty;
wire [8 : 0] rx_spi_cnt;
axi_srd_cache #(
.TO_WIDTH (16),
.DATA_WIDTH (32),
.FIFO_DEPTH (512),
.PROG_FULL_THRE (256)
)axi_srd_cache_rx(
// system signals
.clk (clk), // System clock input
.wr_rst (reset), // Write reset, hight active input
.rd_rst (reset), // Read reset, hight active input
// config signals
.rw_to (16'd10 ), // Write timeout input [TO_WIDTH-1 :0]
.burst_len (8'd3 ), // Axi write burst length input [7 :0]
.timout_mode (1'b1 ), // Timeout mode enable, hight active input
.start_addr (rx_start_addr), // Start addr input [31 :0] 32'h0000_0000
.end_addr (rx_end_addr ), // End addr input [31 :0] 32'h7FFF_FFFF
.wr_state (rx_wr_state ), // Read status output [5 :0]
.rd_state (rx_rd_state ), // Read status output [5 :0]
.use_cnt_o (rx_use_cnt_o ), // DDR memory used space output [31 :0]
// AXI write channel signals
/* Input fifo signals */
.in_fifo_data (rx_in_fifo_data ), // Input fifo read data input [DATA_WIDTH-1 :0]
.in_fifo_rdcnt (rx_axis_rd_data_count[9:0]), // Input fifo read data count input [clog2(FIFO_DEPTH-1)-1:0] rx_in_fifo_rdcnt
.in_fifo_rden (rx_in_fifo_rden ), // Input fifo read enable, hight active output
/* AXI write address channel signals */
.AWREADY (rx_AWREADY), // Indicates slave is ready to accept input
.AWADDR (rx_AWADDR ), // Write address output [31 :0]
.AWVALID (rx_AWVALID), // Write address valid output
.AWSIZE (rx_AWSIZE ), // Write size output [2 :0]
.AWBURST (rx_AWBURST), // Burst type output [1 :0]
.AWCACHE (rx_AWCACHE), // Write cache output [3 :0]
.AWPROT (rx_AWPROT ), // Write protect output [2 :0]
.AWLOCK (rx_AWLOCK ), // Write bus lock output [0 :0]
/*AXI write data channel signals*/
.WREADY (rx_WREADY), // Write data ready input
.AWLEN (rx_AWLEN ), // Burst write length output [7 :0]
.WDATA (rx_WDATA ), // Write data output [DATA_WIDTH-1 :0]
.WLAST (rx_WLAST ), // Last write transaction output
.WVALID (rx_WVALID), // Write valid output
.WSTRB (rx_WSTRB ), // output [(DATA_WIDTH/8)-1 :0]
/*AXI write response channel signals*/
.BRESP (rx_BRESP ), // Write response input [1 :0]
.BVALID (rx_BVALID), // Write reponse valid input
.BREADY (rx_BREADY), // Response ready output
// AXI read channel signals
/* Input fifo signals */
.out_fifo_rden (rx_out_fifo_rden ), // Output fifo read enable, high active input
.out_fifo_data (rx_out_fifo_data ), // Output fifo read data output [DATA_WIDTH-1 :0]
.out_fifo_empty (rx_out_fifo_empty), // Output fifo empty output
.out_fifo_full (rx_out_fifo_full ), // Output fifo full output
/* AXI read address channel signals */
.ARREADY (rx_ARREADY), // Indicates slave is ready to accept input
.ARADDR (rx_ARADDR ), // read address output [31 :0]
.ARVALID (rx_ARVALID), // read address valid output
.ARSIZE (rx_ARSIZE ), // read size output [2 :0]
.ARLEN (rx_ARLEN ), // Burst read length output [7 :0]
.ARBURST (rx_ARBURST), // Burst type output [1 :0]
.ARCACHE (rx_ARCACHE), // output [3 :0]
.ARPROT (rx_ARPROT ), // output [2 :0]
.ARLOCK (rx_ARLOCK ), // output [0 :0]
/* AXI read data channel signals */
.RREADY (rx_RREADY), // read data ready output
.RDATA (rx_RDATA ), // read data input [DATA_WIDTH-1 :0]
.RLAST (rx_RLAST ), // Last read transaction input
.RVALID (rx_RVALID), // read valid input
/* AXI read response channel signals */
.RRESP (rx_RRESP ) // read response input [1 :0]
);
//assign rx_out_fifo_rden = ~rx_out_fifo_empty & ~rx_spi_full & (rx_cache_pkg_cnt_o != 32'b0);
assign rx_out_fifo_rden = ~rx_out_fifo_empty & ~rx_spi_full;
assign rx_fifo_wr_en = rx_out_fifo_rden;
// rx ?????
reg rx_pkg_wr_in;
wire [17: 0] rx_pkg_cnt_in_end;
reg [17 :0] rx_pkg_length_in;
reg [17 :0] rx_pkg_cnt_in;
reg rx_pkg_wr_out;
wire [17: 0] rx_pkg_cnt_out_end;
reg [17: 0] rx_pkg_length_out;
reg [17: 0] rx_pkg_cnt_out;
reg [31: 0] rx_cache_pkg_cnt;
// in
always@(posedge clk)
begin
if(reset)
begin
rx_pkg_cnt_in <= 18'b0;
end
else if((rx_pkg_cnt_in == rx_pkg_cnt_in_end) & rx_pkg_wr_in)begin
rx_pkg_cnt_in <= 18'b0;
end
else if((rx_pkg_cnt_in == rx_pkg_cnt_in_end) & !rx_pkg_wr_in & (rx_pkg_cnt_in >=18'd2))begin
rx_pkg_cnt_in <= 18'b0;
end
else if(rx_in_fifo_rden)
begin
rx_pkg_cnt_in <= rx_pkg_cnt_in + 18'd1;
end
end
always@(posedge clk)
begin
if(reset)begin
rx_pkg_length_in <= 'b0;
rx_pkg_wr_in <= 'b0;
end
else if(rx_pkg_cnt_in == 18'b0 & rx_in_fifo_rden)begin
rx_pkg_wr_in <= rx_in_fifo_data[31];
end
else if(rx_pkg_cnt_in == 18'b1 & rx_in_fifo_rden)begin
rx_pkg_length_in <= rx_in_fifo_data[19:0] >> 2;
end
end
assign rx_pkg_cnt_in_end = rx_pkg_wr_in ? 18'd1 :rx_pkg_length_in + 18'd1;
// out
always@(posedge clk)
begin
if(reset)
begin
rx_pkg_cnt_out <= 'b0;
end
else if((rx_pkg_cnt_out == rx_pkg_cnt_out_end)& rx_pkg_wr_out)begin
rx_pkg_cnt_out <= 18'b0;
end
else if((rx_pkg_cnt_out == rx_pkg_cnt_out_end)& !rx_pkg_wr_out & (rx_pkg_cnt_out >=18'd2))begin
rx_pkg_cnt_out <= 18'b0;
end
else if(rx_out_fifo_rden)
begin
rx_pkg_cnt_out <= rx_pkg_cnt_out + 18'b1;
end
end
always@(posedge clk)
begin
if(reset)begin
rx_pkg_wr_out <= 'b0;
rx_pkg_length_out <= 'b0;
end
else if(rx_pkg_cnt_out == 18'b0 & rx_out_fifo_rden)begin
rx_pkg_wr_out <= rx_out_fifo_data[31];
end
else if(rx_pkg_cnt_out == 18'b1 & rx_out_fifo_rden)begin
rx_pkg_length_out <= rx_out_fifo_data[19:0] >> 2;
end
end
assign rx_pkg_cnt_out_end = rx_pkg_wr_out ? 18'd1 :rx_pkg_length_out + 18'd1;
//
always@(posedge clk)
begin
if(reset)
begin
rx_cache_pkg_cnt <= 32'b0;
end
else if(rx_pkg_cnt_in == rx_pkg_cnt_in_end)begin
if(rx_pkg_wr_in )begin
rx_cache_pkg_cnt <= rx_cache_pkg_cnt + 32'b1; // in
end else if(!rx_pkg_wr_in & (rx_pkg_cnt_in >=18'd2))begin
rx_cache_pkg_cnt <= rx_cache_pkg_cnt + 32'b1; // in
end
end
else if(rx_pkg_cnt_out == rx_pkg_cnt_out_end)begin
if(rx_pkg_wr_out & rx_out_fifo_rden)begin
rx_cache_pkg_cnt <= rx_cache_pkg_cnt - 32'b1; // in
end else if(!rx_pkg_wr_out & (rx_pkg_cnt_out >=18'd2)&rx_out_fifo_rden)begin
rx_cache_pkg_cnt <= rx_cache_pkg_cnt - 32'b1; // in
end
end
end
assign rx_cache_pkg_cnt_o = rx_cache_pkg_cnt;
//********************************????*******************************************
//tx ddr
wire [5 : 0] tx_wr_state ;
wire [5 : 0] tx_rd_state ;
wire [31 : 0] tx_use_cnt_o;
wire [31:0] tx_in_fifo_dout;
wire [9 :0] tx_in_fifo_cnt;
wire tx_in_fifo_rden ;
wire rslt_tx_rd_en;
wire rslt_tx_empty;
wire tx_out_fifo_rden ;
wire [31 : 0] tx_out_fifo_data ;
wire tx_out_fifo_empty;
wire tx_out_fifo_full ;
wire tx_out_m_full;
wire tx_out_s_axis_tready; // output
////////////////////////////////// spi //////////////////////////////////////////
//rslt_push fifo
axis_data_fifo_cache axis_data_fifo_cache_tx_rslt_push(
.s_axis_aresetn (~reset), // input
.s_axis_aclk (clk), // input
.s_axis_tvalid (tx_out_fifo_rden), // input
.s_axis_tready (tx_out_s_axis_tready), // output
.s_axis_tdata (tx_out_fifo_data ), // input [31:0]
.m_axis_tvalid (tx_out_m_axis_tvalid), // output
.m_axis_tready (tx_out_m_axis_tready), // input
.m_axis_tdata (tx_out_m_axis_tdata), // output [31:0]
.axis_wr_data_count(), // output [31:0]
.axis_rd_data_count(), // output [31:0]
.almost_full (), // output
.prog_full (tx_out_m_full) // output
);
assign tx_out_fifo_rden = (~tx_out_fifo_empty) && tx_out_s_axis_tready && (~tx_out_m_full);
axi_srd_cache #(
.TO_WIDTH (16),
.DATA_WIDTH (32),
.FIFO_DEPTH (512),
.PROG_FULL_THRE (256)
)axi_srd_cache_tx(
// system signals
.clk (clk), // System clock input
.wr_rst (reset), // Write reset, hight active input
.rd_rst (reset), // Read reset, hight active input
// config signals
.rw_to (16'd10 ), // Write timeout input [TO_WIDTH-1 :0]
.burst_len (8'd3 ), // Axi write burst length input [7 :0]
.timout_mode (1'b1 ), // Timeout mode enable, hight active input
.start_addr (tx_start_addr), // Start addr input [31 :0] 32'h8000_0000
.end_addr (tx_end_addr ), // End addr input [31 :0] 32'hFFFF_FFFF
.wr_state (tx_wr_state ), // Read status output [5 :0]
.rd_state (tx_rd_state ), // Read status output [5 :0]
.use_cnt_o (tx_use_cnt_o ), // DDR memory used space output [31 :0]
// AXI write channel signals
/* Input fifo signals */
.in_fifo_data (tx_in_fifo_dout), // Input fifo read data input [DATA_WIDTH-1 :0]
.in_fifo_rdcnt (tx_in_fifo_cnt ), // Input fifo read data count input [clog2(FIFO_DEPTH-1)-1:0] rx_in_fifo_rdcnt
.in_fifo_rden (tx_in_fifo_rden ), // output fifo read enable, hight active output
/* AXI write address channel signals */
.AWREADY (tx_AWREADY), // Indicates slave is ready to accept input
.AWADDR (tx_AWADDR ), // Write address output [31 :0]
.AWVALID (tx_AWVALID), // Write address valid output
.AWSIZE (tx_AWSIZE ), // Write size output [2 :0]
.AWBURST (tx_AWBURST), // Burst type output [1 :0]
.AWCACHE (tx_AWCACHE), // Write cache output [3 :0]
.AWPROT (tx_AWPROT ), // Write protect output [2 :0]
.AWLOCK (tx_AWLOCK ), // Write bus lock output [0 :0]
/*AXI write data ctannel signals*/
.WREADY (tx_WREADY), // Write data ready input
.AWLEN (tx_AWLEN ), // Burst write length output [7 :0]
.WDATA (tx_WDATA ), // Write data output [DATA_WIDTH-1 :0]
.WLAST (tx_WLAST ), // Last write transaction output
.WVALID (tx_WVALID), // Write valid output
.WSTRB (tx_WSTRB ), // output [(DATA_WIDTH/8)-1 :0]
/*AXI write responte channel signals*/
.BRESP (tx_BRESP ), // Write response input [1 :0]
.BVALID (tx_BVALID), // Write reponse valid input
.BREADY (tx_BREADY), // Response ready output
// AXI read channel signals
/* Input fifo signals */
.out_fifo_rden (tx_out_fifo_rden ), // Output fifo read enable, high active input
.out_fifo_data (tx_out_fifo_data ), // Output fifo read data output [DATA_WIDTH-1 :0]
.out_fifo_empty (tx_out_fifo_empty), // Output fifo empty output
.out_fifo_full (tx_out_fifo_full ), // Output fifo full output
.out_fifo_af (),
/* AXI read address channel signals */
.ARREADY (tx_ARREADY), // Indicates slave is ready to accept input
.ARADDR (tx_ARADDR ), // read address output [31 :0]
.ARVALID (tx_ARVALID), // read address valid output
.ARSIZE (tx_ARSIZE ), // read size output [2 :0]
.ARLEN (tx_ARLEN ), // Burst read length output [7 :0]
.ARBURST (tx_ARBURST), // Burst type output [1 :0]
.ARCACHE (tx_ARCACHE), // output [3 :0]
.ARPROT (tx_ARPROT ), // output [2 :0]
.ARLOCK (tx_ARLOCK ), // output [0 :0]
/* AXI read data channel signals */
.RREADY (tx_RREADY), // read data ready output
.RDATA (tx_RDATA ), // read data input [DATA_WIDTH-1 :0]
.RLAST (tx_RLAST ), // Last read transaction input
.RVALID (tx_RVALID), // read valid input
/* AXI read response channel signals */
.RRESP (tx_RRESP ) // read response input [1 :0]
);
assign rslt_tx_rd_en = tx_in_fifo_rden && (~tx_out_fifo_full); // cache_tx ????
// tx_rslt_push ?????
reg [31 : 0] tx_cache_pkg_cnt;
reg [19 : 0] tx_pkg_length_in;
reg [17 : 0] tx_pkg_cnt_in;
reg [19 : 0] tx_pkg_length_out;
reg [17 : 0] tx_pkg_cnt_out;
// in
always@(posedge clk)
begin
if(reset || (tx_in_fifo_rden && (tx_pkg_cnt_in == tx_pkg_length_in + 18'd1) && (tx_pkg_cnt_in > 18'b1)))
begin
tx_pkg_cnt_in <= 18'b0;
end
else if(tx_in_fifo_rden && (tx_in_fifo_cnt > 'b0))
begin
tx_pkg_cnt_in <= tx_pkg_cnt_in + 18'b1;
end
end
always@(posedge clk)
begin
if(reset)
begin
tx_pkg_length_in <= 20'b0;
end
else if(tx_in_fifo_rden && (tx_pkg_cnt_in == 18'b1))
begin
tx_pkg_length_in <= tx_in_fifo_dout[19:0] >> 2;
end
end
// out
always@(posedge clk)
begin
if(reset || (tx_out_fifo_rden && (tx_pkg_cnt_out == tx_pkg_length_out + 18'd1) && (tx_pkg_cnt_out > 18'b1)))
begin
tx_pkg_cnt_out <= 18'b0;
end
else if(tx_out_fifo_rden) // ?????????????FIFO??read en?????????? tx_fifo_rden
begin
tx_pkg_cnt_out <= tx_pkg_cnt_out + 18'b1;
end
end
always@(posedge clk)
begin
if(reset)
begin
tx_pkg_length_out <= 20'b0;
end
else if(tx_out_fifo_rden && (tx_pkg_cnt_out == 18'b1))
begin
tx_pkg_length_out <= tx_out_fifo_data[19:0] >> 2;
end
end
always@(posedge clk)
begin
if(reset)
begin
tx_cache_pkg_cnt <= 32'b0;
end
else if(tx_in_fifo_rden && (tx_in_fifo_cnt > 'b0) && ((tx_pkg_cnt_in == tx_pkg_length_in) && (tx_pkg_cnt_in > 18'b0) || ((tx_pkg_cnt_in == 32'b1) && (tx_in_fifo_dout[19:0] == 32'd4)))) // ?cnt?<EFBFBD><EFBFBD>????????????
begin
tx_cache_pkg_cnt <= tx_cache_pkg_cnt + 32'b1; // in
end
else if(tx_out_fifo_rden && ((tx_pkg_cnt_out == tx_pkg_length_out) && (tx_pkg_cnt_out > 18'b0) || ((tx_pkg_cnt_out == 32'b1) && (tx_out_fifo_data[19:0] == 32'd4))))
begin
tx_cache_pkg_cnt <= tx_cache_pkg_cnt - 32'b1; // out
end
end
assign tx_cache_pkg_cnt_o = tx_cache_pkg_cnt;
//////////////////////////////////FIFO to spi//////////////////////////////////////////////////
/*
wire WREADY_spi;
wire spi_busy;
wire spi_tlast_z;
wire spi_tlast;
wire [31 : 0] spi_length;
wire spi_wr;
wire [31 : 0] RDATA_spi;
wire RVALID_spi;
wire READY_spi;
*/
wire WREADY_spi;
fifo_generator_0 fifo_generator_0_rx_master( // change fifo to get a more accurate fifo data count
.wr_clk (clk), // input
.rd_clk (clk), // input
.din (rx_out_fifo_data), // input [31:0]
.wr_en (rx_fifo_wr_en), // input
.rd_en ((~rx_spi_empty) && (WREADY_spi)), // input
.rd_rst (reset),
.wr_rst (reset),
.dout (rx_spi_dout), // output [31:0]
.full (rx_spi_full), // output
.empty (rx_spi_empty), // output
// .wr_data_count(rx_axis_wr_data_count), // output [10:0]
.rd_data_count(rx_spi_cnt)
);
wire [31:0] rslt_tx_din;
wire rslt_tx_wr_en;
wire rslt_tx_full;
fifo_generator_0 fifo_generator_0_tx_master_rslt_push( // change fifo to get a more accurate fifo data count
.wr_clk (clk), // input
.rd_clk (clk), // input
.din (rslt_tx_din), // input [31:0]
.wr_en (rslt_tx_wr_en), // input
.rd_en (rslt_tx_rd_en), // input
.rd_rst (reset),
.wr_rst (reset),
.dout (tx_in_fifo_dout), // output [31:0]
.full (), // output
.prog_full (rslt_tx_full), // output
.empty (rslt_tx_empty), // output
// .wr_data_count(rx_axis_wr_data_count), // output [9:0]
.rd_data_count(tx_in_fifo_cnt) // output [9:0]
);
assign rslt_tx_din = s_axis_rdata_rslt;
assign rslt_tx_wr_en = s_axis_rvalid_rslt && ~rslt_tx_full;
assign s_axis_rready_rslt = ~rslt_tx_full;
wire spi_tx_wr_en;
wire tx_out_s_axis_tready_spi;
wire [31 : 0]spi_tx_din;
wire [31:0] wr_data_count_spi;
wire [31:0] rd_data_count_spi;
wire tx_out_m_full_spi;
axis_data_fifo_cache axis_data_fifo_cache_tx_spi(
.s_axis_aresetn (~reset), // input
.s_axis_aclk (clk), // input
.s_axis_tvalid (spi_tx_wr_en), // input
.s_axis_tready (tx_out_s_axis_tready_spi), // output
.s_axis_tdata (spi_tx_din ), // input [31:0]
.m_axis_tvalid (m_axis_tvalid_spi), // output
.m_axis_tready (m_axis_tready_spi), // input
.m_axis_tdata (m_axis_tdata_spi), // output [31:0]
.axis_wr_data_count(wr_data_count_spi), // output [31:0]
.axis_rd_data_count(rd_data_count_spi), // output [31:0]
.almost_full (), // output
.prog_full (tx_out_m_full_spi) // output
);
// tx_spi ?????
reg [19 : 0] tx_pkg_length_in_spi;
reg [19 : 0] tx_pkg_cnt_in_spi;
reg [19 : 0] tx_pkg_length_out_spi;
reg [19 : 0] tx_pkg_cnt_out_spi;
//in
always@(posedge clk)
begin
if(reset || ( spi_tx_wr_en && (tx_pkg_cnt_in_spi == tx_pkg_length_in_spi + 20'd1) && (tx_pkg_cnt_in_spi > 20'b1)))begin
tx_pkg_cnt_in_spi <= 20'b0;
end
else if(spi_tx_wr_en)begin
tx_pkg_cnt_in_spi <= tx_pkg_cnt_in_spi + 20'b1;
end
end
always@(posedge clk)
begin
if(reset)begin
tx_pkg_length_in_spi <= 20'b0;
end
else if(spi_tx_wr_en && (tx_pkg_cnt_in_spi == 20'b1))begin
tx_pkg_length_in_spi <= spi_tx_din[19:0] >> 2;
end
end
//out
always@(posedge clk)
begin
if(reset || (m_axis_tvalid_spi && (tx_pkg_cnt_out_spi == tx_pkg_length_out_spi + 20'b1) && (tx_pkg_cnt_out_spi > 20'b1)))begin
tx_pkg_cnt_out_spi <= 20'b0;
end
else if(m_axis_tvalid_spi)begin
tx_pkg_cnt_out_spi <= tx_pkg_cnt_out_spi + 20'b1;
end
end
always@(posedge clk)
begin
if(reset)begin
tx_pkg_length_out_spi <= 20'b0;
end
else if(m_axis_tvalid_spi && (tx_pkg_cnt_out_spi == 20'b1))begin
tx_pkg_length_out_spi <= m_axis_tdata_spi[19:0] >> 2;
end
end
// pkg_cnt
wire pkg_cnt_plus;
wire pkg_cnt_down;
reg [31:0] tx_cache_pkg_cnt_spi;
always@(posedge clk)
begin
if(reset)begin
tx_cache_pkg_cnt_spi <= 32'b0;
end
else if(pkg_cnt_plus)begin // ?cnt?<EFBFBD><EFBFBD>????????????
tx_cache_pkg_cnt_spi <= tx_cache_pkg_cnt_spi + 32'b1; // in
end
else if(pkg_cnt_down)begin
tx_cache_pkg_cnt_spi <= tx_cache_pkg_cnt_spi - 32'b1; // out
end
end
assign pkg_cnt_plus = spi_tx_wr_en && ( tx_pkg_cnt_in_spi == 20'b1 );
assign pkg_cnt_down = m_axis_tvalid_spi && ((tx_pkg_cnt_out_spi == (tx_pkg_length_out_spi + 1'b1)) && (tx_pkg_cnt_out_spi != 20'b1));
assign tx_cache_pkg_cnt_spi_o = tx_cache_pkg_cnt_spi;
spi_m_1 #
(.DEBUG(DEBUG))
spi_m_1_u(
.sys_clk (clk), // input
.sys_rst_n (~reset), // input
// fifo trans
.WDATA_spi (rx_spi_dout), // input [31 : 0]
.WVALID_spi (~rx_spi_empty), // input ~rx_spi_empty
.WREADY_spi (WREADY_spi), // output spi_rx_rd_en
.spi_busy (), // output ~ss
.tlast_zo (),
.tlast_o (),
.cmd_length_o (),
.cmd_wr_o (),
// fifo read
.READY_spi (~tx_out_m_full_spi && tx_out_s_axis_tready_spi ), // input
.RVALID_spi_o (spi_tx_wr_en), // output
.RDATA_spi_o (spi_tx_din), // output [32 : 0]
// spi slave
.spi_slave_bit (miso), // input
.ss (csn), // output
.spi_clk (sclk), // output
.spi_master_bit (mosi), // output
.irq (irq)
);
//width 245 122
generate
if (DEBUG == 1) begin: debug_gen
ila_cache_spi ila_cache_spi_u(
.clk(clk),
.probe0({
tx_out_m_axis_tvalid ,
tx_out_m_axis_tready ,
tx_out_m_axis_tdata ,
rx_in_s_axis_tvalid ,
rx_in_s_axis_tready ,
rx_in_s_axis_tdata ,
rx_in_m_axis_tvalid ,
rx_in_fifo_rden ,
rx_in_fifo_data ,
rx_axis_rd_data_count ,
rx_pkg_wr_in ,
rx_pkg_cnt_in_end ,
rx_pkg_length_in ,
rx_pkg_cnt_in ,
rx_pkg_wr_out ,
rx_pkg_cnt_out_end ,
rx_pkg_length_out ,
rx_pkg_cnt_out ,
rx_cache_pkg_cnt ,
rx_out_fifo_data ,
rx_out_fifo_empty ,
rx_out_fifo_full ,
rx_out_fifo_rden ,
rx_out_fifo_empty ,
rx_spi_full ,
rx_fifo_wr_en ,
rx_spi_empty ,
WREADY_spi ,
rx_spi_dout ,
spi_tx_wr_en ,
spi_tx_din ,
tx_out_m_full_spi ,
tx_out_s_axis_tready_spi ,
miso ,
csn ,
sclk ,
mosi
}),
.probe1({
rx_wr_state ,
rx_rd_state ,
rx_use_cnt_o ,
rx_WREADY ,
rx_AWLEN ,
rx_WDATA ,
rx_WLAST ,
rx_WVALID ,
rx_RREADY ,
rx_RDATA ,
rx_RLAST ,
rx_RVALID
}),
.probe2({
rslt_tx_din,
rslt_tx_wr_en,
rslt_tx_rd_en,
tx_in_fifo_dout,
rslt_tx_full,
rslt_tx_empty,
tx_in_fifo_cnt,
tx_in_fifo_rden,
tx_out_fifo_data,
tx_out_fifo_empty,
tx_out_fifo_full,
tx_out_fifo_rden,
tx_out_m_full,
tx_out_s_axis_tready,
tx_out_m_axis_tvalid,
tx_out_m_axis_tready
})
);
end
endgenerate
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//对输入的中断进行仲裁
//仲裁的原则
//////////////////////////////////////////////////////////////////////////////////
module int_arbitor(
input clk,
input nrst,
input [14:0] empty,
input [14:0] int_i,
output reg [3:0] int_rslt,
input clr //表示这个中断已经被接收
);
wire empty_0_14;
wire empty_1_14;
wire empty_2_14;
wire empty_3_14;
wire empty_4_14;
wire empty_5_14;
wire empty_6_14;
wire empty_7_14;
wire empty_8_14;
wire empty_9_14;
wire empty_10_14;
wire empty_11_14;
wire empty_12_14;
wire empty_13_14;
wire empty_14_14;
assign empty_0_14 =(empty[14:0]==15'b111_1111_1111_1111) ;
assign empty_1_14 =(empty[14:1]==14'b11_1111_1111_1111) ;
assign empty_2_14 =(empty[14:2]==13'b1_1111_1111_1111) ;
assign empty_3_14 =(empty[14:3]==12'b1111_1111_1111) ;
assign empty_4_14 =(empty[14:4]==11'b111_1111_1111) ;
assign empty_5_14 =(empty[14:5]==10'b11_1111_1111) ;
assign empty_6_14 =(empty[14:6]==9'b1_1111_1111) ;
assign empty_7_14 =(empty[14:7]==8'b1111_1111) ;
assign empty_8_14 =(empty[14:8]==7'b111_1111) ;
assign empty_9_14 =(empty[14:9]==6'b11_1111) ;
assign empty_10_14 =(empty[14:10]==5'b1_1111) ;
assign empty_11_14 =(empty[14:11]==4'b1111) ;
assign empty_12_14 =(empty[14:12]==3'b111) ;
assign empty_13_14 =(empty[14:13]==2'b11) ;
assign empty_14_14 =(empty[14:14]==1'b1) ;
wire [3:0] sel_0;
wire [3:0] sel_1;
wire [3:0] sel_2;
wire [3:0] sel_3;
wire [3:0] sel_4;
wire [3:0] sel_5;
wire [3:0] sel_6;
wire [3:0] sel_7;
wire [3:0] sel_8;
wire [3:0] sel_9;
wire [3:0] sel_10;
wire [3:0] sel_11;
wire [3:0] sel_12;
wire [3:0] sel_13;
reg [3:0] roll;
//找出0-9中的第一个1
tmp_encode tmp_encode_inst0(
.din (int_i[14:0] ),
.dout (sel_0 )
);
//找出1-9中的第一个1
tmp_encode tmp_encode_inst1(
.din ({int_i[14:1],1'b0} ),
.dout (sel_1 )
);
//找出2-9中的第一个1
tmp_encode tmp_encode_inst2(
.din ({int_i[14:2],2'b0} ),
.dout (sel_2 )
);
//找出3-9中的第一个1
tmp_encode tmp_encode_inst3(
.din ({int_i[14:3],3'b0} ),
.dout (sel_3 )
);
//找出4-9中的第一个1
tmp_encode tmp_encode_inst4(
.din ({int_i[14:4],4'b0} ),
.dout (sel_4 )
);
//找出5-9中的第一个1
tmp_encode tmp_encode_inst5(
.din ({int_i[14:5],5'b0} ),
.dout (sel_5 )
);
//找出6-9中的第一个1
tmp_encode tmp_encode_inst6(
.din ({int_i[14:6],6'b0} ),
.dout (sel_6 )
);
//找出7-9中的第一个1
tmp_encode tmp_encode_inst7(
.din ({int_i[14:7],7'b0} ),
.dout (sel_7 )
);
//找出8-9中的第一个1
tmp_encode tmp_encode_inst8(
.din ({int_i[14:8],8'b0} ),
.dout (sel_8 )
);
//找出8-9中的第一个1
tmp_encode tmp_encode_inst9(
.din ({int_i[14:9],9'b0} ),
.dout (sel_9 )
);
//找出8-9中的第一个1
tmp_encode tmp_encode_inst10(
.din ({int_i[14:10],10'b0} ),
.dout (sel_10 )
);
//找出8-9中的第一个1
tmp_encode tmp_encode_inst11(
.din ({int_i[14:11],11'b0} ),
.dout (sel_11 )
);
//找出8-9中的第一个1
tmp_encode tmp_encode_inst12(
.din ({int_i[14:12],12'b0} ),
.dout (sel_12 )
);
//找出8-9中的第一个1
tmp_encode tmp_encode_inst13(
.din ({int_i[14:13],13'b0} ),
.dout (sel_13 )
);
always@(posedge clk or negedge nrst)begin
if(!nrst)begin
roll <=0;
end
else if(clr && roll==4'd14)begin
roll <=0;
end
else if(clr && roll!=4'd14)begin
if(roll==4'd0 && empty_1_14==1'b1)begin
roll <=0;
end
else if(roll==4'd1 && empty_2_14==1'b1)begin
roll <=0;
end
else if(roll==4'd2 && empty_3_14==1'b1)begin
roll <=0;
end
else if(roll==4'd3 && empty_4_14==1'b1)begin
roll <=0;
end
else if(roll==4'd4 && empty_5_14==1'b1)begin
roll <=0;
end
else if(roll==4'd5 && empty_6_14==1'b1)begin
roll <=0;
end
else if(roll==4'd6 && empty_7_14==1'b1)begin
roll <=0;
end
else if(roll==4'd7 && empty_8_14==1'b1)begin
roll <=0;
end
else if(roll==4'd8 && empty_9_14==1'b1)begin
roll <=0;
end
else if(roll==4'd9 && empty_10_14==1'b1)begin
roll <=0;
end
else if(roll==4'd10 && empty_11_14==1'b1)begin
roll <=0;
end
else if(roll==4'd11 && empty_12_14==1'b1)begin
roll <=0;
end
else if(roll==4'd12 && empty_13_14==1'b1)begin
roll <=0;
end
else if(roll==4'd13 && empty_14_14==1'b1)begin
roll <=0;
end
else begin
roll <=roll+1;
end
end
else begin
roll <=roll;
end
end
//always@(*)begin
// case(roll)
// 4'd0: int_rslt =sel_0;
// 4'd1: int_rslt =sel_1;
// 4'd2: int_rslt =sel_2;
// 4'd3: int_rslt =sel_3;
// 4'd4: int_rslt =sel_4;
// 4'd5: int_rslt =sel_5;
// 4'd6: int_rslt =sel_6;
// 4'd7: int_rslt =sel_7;
// 4'd8: int_rslt =sel_8;
// 4'd9: int_rslt =4'd9;
// default:begin
// int_rslt=4'b1111;
// end
//
// endcase
//end
parameter wait_int =2'd0,
int_pro =2'd1,
wait_pro =2'd2;
reg [1:0] state;
//当发现int_i不为0时开始仲裁
always@(posedge clk or negedge nrst)begin
if(!nrst)begin
int_rslt <=4'hf;
state <=0;
end
else begin
case(state)
wait_int:begin
int_rslt <=4'hf;
if(int_i!=0)begin
state <=int_pro;
end
else begin
state <=wait_int;
end
end
int_pro:begin
if(clr)begin
state <=wait_int;
end
else begin
state <=int_pro;
case(roll)
4'd0: int_rslt <=sel_0;
4'd1: int_rslt <=sel_1;
4'd2: int_rslt <=sel_2;
4'd3: int_rslt <=sel_3;
4'd4: int_rslt <=sel_4;
4'd5: int_rslt <=sel_5;
4'd6: int_rslt <=sel_6;
4'd7: int_rslt <=sel_7;
4'd8: int_rslt <=sel_8;
4'd9: int_rslt <=sel_9;
4'd10: int_rslt <=sel_10;
4'd11: int_rslt <=sel_11;
4'd12: int_rslt <=sel_12;
4'd13: int_rslt <=sel_13;
4'd14: int_rslt <=4'd14;
default:begin
int_rslt<=4'hf;
end
endcase
end
end
// wait_pro:begin
// if(clr)begin
// state <=wait_int;
// end
// else begin
// state <=wait_pro;
// end
// end
default:begin
state <=wait_int;
end
endcase
end
end
endmodule

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@ -0,0 +1,253 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/11/07 15:37:14
// Design Name:
// Module Name: mux_dmux
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mux_dmux_l(
input clk ,
input reset ,
output slot ,
// input wr_rst,
// input rd_rst,
//**************rx interface********************** 下行的数是按照mux模块给的时钟给的所以时钟是不需要再转换
input s0_user_rx_tvalid ,
output s0_user_rx_tready ,
input [ 63: 0] s0_user_rx_tdata ,
input [ 7: 0] s0_user_rx_tkeep ,
input s0_user_rx_tlast ,
//**************tx interface********************** 上行的数是按照top模块的时钟给出去需要fifo转一下时钟
input fifo_tx_m_axis_clk ,
output fifo_tx_m_axis_tvalid ,
input fifo_tx_m_axis_tready ,
output [ 63: 0] fifo_tx_m_axis_tdata ,
output [ 7: 0] fifo_tx_m_axis_tkeep ,
output fifo_tx_m_axis_tlast ,
// 分接
// attenuator
input atten_rx_in_fifo_ready ,
output [ 31: 0] atten_rx_in_fifo_data ,
output atten_rx_in_fifo_valid ,
output [ 9: 0] atten_rx_axis_rd_data_count,
//spi
input c0_rx_in_fifo_ready ,
output [ 31: 0] c0_rx_in_fifo_data ,
output c0_rx_in_fifo_valid ,
output [ 9: 0] c0_rx_axis_rd_data_count ,
input c1_rx_in_fifo_ready ,
output [ 31: 0] c1_rx_in_fifo_data ,
output c1_rx_in_fifo_valid ,
output [ 9: 0] c1_rx_axis_rd_data_count ,
input c2_rx_in_fifo_ready ,
output [ 31: 0] c2_rx_in_fifo_data ,
output c2_rx_in_fifo_valid ,
output [ 9: 0] c2_rx_axis_rd_data_count ,
input c3_rx_in_fifo_ready ,
output [ 31: 0] c3_rx_in_fifo_data ,
output c3_rx_in_fifo_valid ,
output [ 9: 0] c3_rx_axis_rd_data_count ,
input c4_rx_in_fifo_ready ,
output [ 31: 0] c4_rx_in_fifo_data ,
output c4_rx_in_fifo_valid ,
output [ 9: 0] c4_rx_axis_rd_data_count ,
input c5_rx_in_fifo_ready ,
output [ 31: 0] c5_rx_in_fifo_data ,
output c5_rx_in_fifo_valid ,
output [ 9: 0] c5_rx_axis_rd_data_count ,
// 复接
input tx_fifo_0_tvalid ,
output tx_fifo_0_tready ,
input [ 31: 0] tx_fifo_0_indata ,
input [ 31: 0] tx_fifo_0_pkgcnt ,
input tx_fifo_1_tvalid ,
output tx_fifo_1_tready ,
input [ 31: 0] tx_fifo_1_indata ,
input [ 31: 0] tx_fifo_1_pkgcnt ,
input tx_fifo_2_tvalid ,
output tx_fifo_2_tready ,
input [ 31: 0] tx_fifo_2_indata ,
input [ 31: 0] tx_fifo_2_pkgcnt ,
input tx_fifo_3_tvalid ,
output tx_fifo_3_tready ,
input [ 31: 0] tx_fifo_3_indata ,
input [ 31: 0] tx_fifo_3_pkgcnt ,
input tx_fifo_4_tvalid ,
output tx_fifo_4_tready ,
input [ 31: 0] tx_fifo_4_indata ,
input [ 31: 0] tx_fifo_4_pkgcnt ,
input tx_fifo_5_tvalid ,
output tx_fifo_5_tready ,
input [ 31: 0] tx_fifo_5_indata ,
input [ 31: 0] tx_fifo_5_pkgcnt ,
input tx_fifo_6_tvalid ,
output tx_fifo_6_tready ,
input [ 31: 0] tx_fifo_6_indata ,
input [ 31: 0] tx_fifo_6_pkgcnt ,
input tx_fifo_7_tvalid ,
output tx_fifo_7_tready ,
input [ 31: 0] tx_fifo_7_indata ,
input [ 31: 0] tx_fifo_7_pkgcnt ,
input tx_fifo_8_tvalid ,
output tx_fifo_8_tready ,
input [ 31: 0] tx_fifo_8_indata ,
input [ 31: 0] tx_fifo_8_pkgcnt
);
// mux tx
wire tcpip_tx_fifo_full;
wire tcpip_tx_fifo_af;
wire [9 :0] tcpip_tx_fifo_wrcnt;
wire tcpip_tx_fifo_wren;
wire [31:0] tcpip_tx_fifo_wrdata;
wire [31:0] s0_user_tx_fifo_rddata_r;
reg [31:0] s0_user_tx_fifo_rddata_r1;
wire [11:0] s0_user_tx_fifo_rdcnt_r;
wire [11:0] s0_user_tx_fifo_wrcnt_r;
AddrCho_rx AddrCho_rx_u(
.clk_187m (clk ),// input
.reset (reset ),// input
.slot (slot ),// output
//**************aurora interface********************** 下行的数是按照mux模块给的时钟给的所以时钟是不需要再转换
.s0_user_rx_tvalid (s0_user_rx_tvalid ),// input
.s0_user_rx_tready (s0_user_rx_tready ),// output
.s0_user_rx_tdata (s0_user_rx_tdata ),// input [63:0]
.s0_user_rx_tkeep (s0_user_rx_tkeep ),// input [7:0]
.s0_user_rx_tlast (s0_user_rx_tlast ),// input
//**************cache spi interface**********************
// attenuator
.atten_rx_in_fifo_ready (atten_rx_in_fifo_ready ),// input
.atten_rx_in_fifo_data (atten_rx_in_fifo_data ),// output [31:0]
.atten_rx_in_fifo_valid (atten_rx_in_fifo_valid ),// output
.atten_rx_axis_rd_data_count (atten_rx_axis_rd_data_count),// output [10:0]
//spi
.c0_rx_in_fifo_ready (c0_rx_in_fifo_ready ),// input
.c0_rx_in_fifo_data (c0_rx_in_fifo_data ),// output [31:0]
.c0_rx_in_fifo_valid (c0_rx_in_fifo_valid ),// output
.c0_rx_axis_rd_data_count (c0_rx_axis_rd_data_count ),// output [10:0]
.c1_rx_in_fifo_ready (c1_rx_in_fifo_ready ),// input
.c1_rx_in_fifo_data (c1_rx_in_fifo_data ),// output [31:0]
.c1_rx_in_fifo_valid (c1_rx_in_fifo_valid ),// output
.c1_rx_axis_rd_data_count (c1_rx_axis_rd_data_count ),// output [10:0]
.c2_rx_in_fifo_ready (c2_rx_in_fifo_ready ),// input
.c2_rx_in_fifo_data (c2_rx_in_fifo_data ),// output [31:0]
.c2_rx_in_fifo_valid (c2_rx_in_fifo_valid ),// output
.c2_rx_axis_rd_data_count (c2_rx_axis_rd_data_count ),// output [10:0]
.c3_rx_in_fifo_ready (c3_rx_in_fifo_ready ),// input
.c3_rx_in_fifo_data (c3_rx_in_fifo_data ),// output [31:0]
.c3_rx_in_fifo_valid (c3_rx_in_fifo_valid ),// output
.c3_rx_axis_rd_data_count (c3_rx_axis_rd_data_count ),// output [10:0]
//ezq2p0---改为固件更新了
.c4_rx_in_fifo_ready (c4_rx_in_fifo_ready ),// input
.c4_rx_in_fifo_data (c4_rx_in_fifo_data ),// output [31:0]
.c4_rx_in_fifo_valid (c4_rx_in_fifo_valid ),// output
.c4_rx_axis_rd_data_count (c4_rx_axis_rd_data_count ),// output [10:0]
//寄存器操作固件更新命令或状态上报等寄存器
.c5_rx_in_fifo_ready (c5_rx_in_fifo_ready ),//input
.c5_rx_in_fifo_data (c5_rx_in_fifo_data ),//output [31:0]
.c5_rx_in_fifo_valid (c5_rx_in_fifo_valid ),//output
.c5_rx_axis_rd_data_count (c5_rx_axis_rd_data_count ) //output [9:0]
);
AddrCho_tx AddrCho_tx_u(
.clk (clk), // input
.reset (reset), // input
//***************cache rslt_push interface********************
.tx_fifo_0_tvalid (tx_fifo_0_tvalid), // input
.tx_fifo_0_tready (tx_fifo_0_tready), // output
.tx_fifo_0_indata (tx_fifo_0_indata), // input [31 : 0]
.tx_fifo_0_pkgcnt (tx_fifo_0_pkgcnt), // input [31 : 0]
.tx_fifo_1_tvalid (tx_fifo_1_tvalid), // input
.tx_fifo_1_tready (tx_fifo_1_tready), // output
.tx_fifo_1_indata (tx_fifo_1_indata) ,// input [31 : 0]
.tx_fifo_1_pkgcnt (tx_fifo_1_pkgcnt), // input [31 : 0]
.tx_fifo_2_tvalid (tx_fifo_2_tvalid), // input
.tx_fifo_2_tready (tx_fifo_2_tready), // output
.tx_fifo_2_indata (tx_fifo_2_indata) ,// input [31 : 0]
.tx_fifo_2_pkgcnt (tx_fifo_2_pkgcnt), // input [31 : 0]
.tx_fifo_3_tvalid (tx_fifo_3_tvalid), // input
.tx_fifo_3_tready (tx_fifo_3_tready), // output
.tx_fifo_3_indata (tx_fifo_3_indata) ,// input [31 : 0]
.tx_fifo_3_pkgcnt (tx_fifo_3_pkgcnt), // input [31 : 0]
//***************cache ezq2p0 interface********************
.tx_fifo_4_tvalid (tx_fifo_4_tvalid), // input
.tx_fifo_4_tready (tx_fifo_4_tready), // output
.tx_fifo_4_indata (tx_fifo_4_indata), // input [31 : 0]
.tx_fifo_4_pkgcnt (tx_fifo_4_pkgcnt), // input [31 : 0]
//***************cache spi interface********************
.tx_fifo_5_tvalid (tx_fifo_5_tvalid), // input
.tx_fifo_5_tready (tx_fifo_5_tready), // output
.tx_fifo_5_indata (tx_fifo_5_indata), // input [31 : 0]
.tx_fifo_5_pkgcnt (tx_fifo_5_pkgcnt), // input [31 : 0]
.tx_fifo_6_tvalid (tx_fifo_6_tvalid), // input
.tx_fifo_6_tready (tx_fifo_6_tready), // output
.tx_fifo_6_indata (tx_fifo_6_indata) ,// input [31 : 0]
.tx_fifo_6_pkgcnt (tx_fifo_6_pkgcnt), // input [31 : 0]
.tx_fifo_7_tvalid (tx_fifo_7_tvalid), // input
.tx_fifo_7_tready (tx_fifo_7_tready), // output
.tx_fifo_7_indata (tx_fifo_7_indata) ,// input [31 : 0]
.tx_fifo_7_pkgcnt (tx_fifo_7_pkgcnt), // input [31 : 0]
.tx_fifo_8_tvalid (tx_fifo_8_tvalid), // input
.tx_fifo_8_tready (tx_fifo_8_tready), // output
.tx_fifo_8_indata (tx_fifo_8_indata) ,// input [31 : 0]
.tx_fifo_8_pkgcnt (tx_fifo_8_pkgcnt), // input [31 : 0]
//****************aurora interface****************
.fifo_tx_m_axis_clk (fifo_tx_m_axis_clk ), // input
.fifo_tx_m_axis_tvalid(fifo_tx_m_axis_tvalid), // output
.fifo_tx_m_axis_tready(fifo_tx_m_axis_tready), // input
.fifo_tx_m_axis_tdata (fifo_tx_m_axis_tdata ), // output [63:0]
.fifo_tx_m_axis_tkeep (fifo_tx_m_axis_tkeep ), // output [7:0]
.fifo_tx_m_axis_tlast (fifo_tx_m_axis_tlast ) // output
);
//ila_mux_l ila_mux_l_u(
// .clk(clk_187m),
// .probe0({s0_user_tx_fifo_rden,s0_user_tx_fifo_rddata_r2,s0_user_tx_fifo_rdcnt_r,s0_tx_m_axis_tvalid,s0_user_tx_fifo_rddata_r1,s0_tx_m_axis_tvalid_r}) // 79
//);
endmodule

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//+FHDR--------------------------------------------------------------------------------------------------------
// Company: Quantum Communication Technology Co.,Ltd.,Anhui
//-----------------------------------------------------------------------------------------------------------------
// File Name : sdr_addr_ctrl.v
// Department : ASIC Group
// Author : PWY
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 1.0 2022-03-15 PWY
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device: Zynq-7 XC7Z100ffg900-2
// Tool versions: Vivado 2016.4
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module sdr_addr_ctrl (
// system signals
input clk // System clock 100MHZ
,input rst // System reset, hight active
,input [31:0] start_addr // Start addr
,input [31:0] end_addr // End addr
,input [31:0] rd_ptr // Read ptr
,input [31:0] wr_ptr // Write ptr
,input wr_round // Write round
,input rd_round // Read round
,output [31:0] use_cnt // DDR memory used space
,output [31:0] left_space // DDR memory left space
);
wire [31:0] ddr_space;
wire [31:0] use_cnt_w;
wire [31:0] left_space_w;
reg [31:0] ddr_space_r;
reg [31:0] use_cnt_r;
reg [31:0] left_space_r;
//ddr write and read ptr contrl
assign ddr_space = end_addr - start_addr + 1'b1;
// assign use_cnt = (wr_ptr >= rd_ptr) ? (wr_ptr - rd_ptr) : (ddr_space + wr_ptr - rd_ptr);
assign use_cnt_w = ((wr_round == rd_round) && (wr_ptr == rd_ptr)) ? 32'h0 : (wr_ptr > rd_ptr) ? (wr_ptr - rd_ptr) : (ddr_space_r + wr_ptr - rd_ptr);
assign left_space_w = ddr_space_r - use_cnt_w;
always @(posedge clk or posedge rst) begin
if(rst) begin
ddr_space_r <= 32'd0;
end
else begin
ddr_space_r <= ddr_space;
end
end
always @(posedge clk or posedge rst) begin
if(rst) begin
use_cnt_r <= 32'd0;
end
else begin
use_cnt_r <= use_cnt_w;
end
end
always @(posedge clk or posedge rst) begin
if(rst) begin
left_space_r <= 32'd0;
end
else begin
left_space_r <= left_space_w;
end
end
assign use_cnt = use_cnt_w;
assign left_space = left_space_r;
endmodule
/*
module sdr_addr_ctrl (
input [31:0] start_addr // Start addr
,input [31:0] end_addr // End addr
,input [31:0] rd_ptr // Read ptr
,input [31:0] wr_ptr // Write ptr
,input wr_round // Write round
,input rd_round // Read round
,output [31:0] use_cnt // DDR memory used space
,output [31:0] left_space // DDR memory left space
);
wire [31:0] ddr_space;
//ddr write and read ptr contrl
assign ddr_space = end_addr - start_addr + 1'b1;
// assign use_cnt = (wr_ptr >= rd_ptr) ? (wr_ptr - rd_ptr) : (ddr_space + wr_ptr - rd_ptr);
assign use_cnt = ((wr_round == rd_round) && (wr_ptr == rd_ptr)) ? 32'h0 : (wr_ptr > rd_ptr) ? (wr_ptr - rd_ptr) : (ddr_space + wr_ptr - rd_ptr);
assign left_space = ddr_space - use_cnt;
endmodule
*/

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/03/05 17:12:46
// Design Name:
// Module Name: send_int_gen_5ch
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module send_int_gen_5ch(
input clk,
input nrst,
input [31:0] int_mode,
input [31:0] ch0_thre,
input [31:0] ch1_thre,
input [31:0] ch2_thre,
input [31:0] ch3_thre,
input [31:0] ch4_thre,
input [31:0] ch5_thre,
input [31:0] ch6_thre,
input [31:0] ch7_thre,
input [31:0] ch8_thre,
input tx_fifo_0_empty,
input [31:0] tx_fifo_0_pkgcnt,
input tx_fifo_1_empty,
input [31:0] tx_fifo_1_pkgcnt,
input tx_fifo_2_empty,
input [31:0] tx_fifo_2_pkgcnt,
input tx_fifo_3_empty,
input [31:0] tx_fifo_3_pkgcnt,
input tx_fifo_4_empty,
input [31:0] tx_fifo_4_pkgcnt,
input tx_fifo_5_empty,
input [31:0] tx_fifo_5_pkgcnt,
input tx_fifo_6_empty,
input [31:0] tx_fifo_6_pkgcnt,
input tx_fifo_7_empty,
input [31:0] tx_fifo_7_pkgcnt,
input tx_fifo_8_empty,
input [31:0] tx_fifo_8_pkgcnt,
output [14:0] int_o
);
wire int_0;
wire int_1;
wire int_2;
wire int_3;
wire int_4;
wire int_5;
wire int_6;
wire int_7;
wire int_8;
assign int_o ={int_8,int_7,int_6,int_5,int_4,int_3,int_2,int_1,int_0};
stop_if # (
.CHx_CW (32)
)
stop_if_inst0(
.clk (clk ),
.nrst (nrst ),
.mode (int_mode[1:0] ),
.chx_thre (ch0_thre ),
.tx_fifo_x_empty (tx_fifo_0_empty ),
.tx_fifo_x_rdcnt (tx_fifo_0_pkgcnt ),
.int_x (int_0 )
);
stop_if # (
.CHx_CW (32)
)
stop_if_inst1(
.clk (clk ),
.nrst (nrst ),
.mode (int_mode[3:2] ),
.chx_thre (ch1_thre ),
.tx_fifo_x_empty (tx_fifo_1_empty ),
.tx_fifo_x_rdcnt (tx_fifo_1_pkgcnt ),
.int_x (int_1 )
);
stop_if # (
.CHx_CW (32)
)
stop_if_inst2(
.clk (clk ),
.nrst (nrst ),
.mode (int_mode[5:4] ),
.chx_thre (ch2_thre ),
.tx_fifo_x_empty (tx_fifo_2_empty ),
.tx_fifo_x_rdcnt (tx_fifo_2_pkgcnt ),
.int_x (int_2 )
);
stop_if # (
.CHx_CW (32)
)
stop_if_inst3(
.clk (clk ),
.nrst (nrst ),
.mode (int_mode[7:6] ),
.chx_thre (ch3_thre ),
.tx_fifo_x_empty (tx_fifo_3_empty ),
.tx_fifo_x_rdcnt (tx_fifo_3_pkgcnt ),
.int_x (int_3 )
);
stop_if # (
.CHx_CW (32)
)
stop_if_inst4(
.clk (clk ),
.nrst (nrst ),
.mode (int_mode[9:8] ),
.chx_thre (ch4_thre ),
.tx_fifo_x_empty (tx_fifo_4_empty ),
.tx_fifo_x_rdcnt (tx_fifo_4_pkgcnt ),
.int_x (int_4 )
);
stop_if # (
.CHx_CW (32)
)
stop_if_inst5(
.clk (clk ),
.nrst (nrst ),
.mode (int_mode[11:10] ),
.chx_thre (ch5_thre ),
.tx_fifo_x_empty (tx_fifo_5_empty ),
.tx_fifo_x_rdcnt (tx_fifo_5_pkgcnt ),
.int_x (int_5 )
);
stop_if # (
.CHx_CW (32)
)
stop_if_inst6(
.clk (clk ),
.nrst (nrst ),
.mode (int_mode[13:12] ),
.chx_thre (ch6_thre ),
.tx_fifo_x_empty (tx_fifo_6_empty ),
.tx_fifo_x_rdcnt (tx_fifo_6_pkgcnt ),
.int_x (int_6 )
);
stop_if # (
.CHx_CW (32)
)
stop_if_inst7(
.clk (clk ),
.nrst (nrst ),
.mode (int_mode[15:14] ),
.chx_thre (ch7_thre ),
.tx_fifo_x_empty (tx_fifo_7_empty ),
.tx_fifo_x_rdcnt (tx_fifo_7_pkgcnt ),
.int_x (int_7 )
);
stop_if # (
.CHx_CW (32)
)
stop_if_inst8(
.clk (clk ),
.nrst (nrst ),
.mode (int_mode[17:16] ),
.chx_thre (ch8_thre ),
.tx_fifo_x_empty (tx_fifo_8_empty ),
.tx_fifo_x_rdcnt (tx_fifo_8_pkgcnt ),
.int_x (int_8 )
);
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/12/09 17:10:32
// Design Name:
// Module Name: spi_m_1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spi_m_1#
(parameter DEBUG = 0
)(
input sys_clk,
input sys_rst_n,
// fifo trans
input [31 : 0] WDATA_spi,
input WVALID_spi,
output WREADY_spi,
output spi_busy, // ~ss
output tlast_o, // ss last
output tlast_zo, // read spi data last
output [31 : 0] cmd_length_o,
output cmd_wr_o,
// fifo read
input READY_spi,
output RVALID_spi_o,
output [32 : 0] RDATA_spi_o,
// spi slave
input spi_slave_bit,
output ss,
output spi_clk,
output spi_master_bit,
// 中断
input irq
);
// 4 分频
// localparam DIVIDE_CLK = 8'd4;
// localparam DIVIDE_CNT = 8'd7; // 2^7 = 4*32 = 128
// localparam DIVICE_CNT_2 = 32'd127; // 128 - 1 = 127
// //--------300m--10分频--30M-----------
// localparam DIVIDE_CLK = 8'd10;
// localparam DIVIDE_CNT = 8'd9; // 192=8'B1100_0000
// localparam DIVICE_CNT_2 = 32'd319; // 192 - 1 = 191
// ----------250M---8分频---31.25m---------------
// localparam DIVIDE_CLK = 8'd8;
// localparam DIVIDE_CNT = 8'd8; // 2^8 = 8*32 = 256
// localparam DIVICE_CNT_2 = 32'd255; // 256 - 1 = 255
// //--------300m--6分频--50M-----------
// localparam DIVIDE_CLK = 8'd6;
// localparam DIVIDE_CNT = 8'd8; // DIVICE_CNT_2的位宽
// localparam DIVICE_CNT_2 = 32'd191; // SPI_CS计数 div*32
// //--------300m--30分频--10M-----------
// localparam DIVIDE_CLK = 8'd30;
// localparam DIVIDE_CNT = 8'd10; // DIVICE_CNT_2的位宽
// localparam DIVICE_CNT_2 = 32'd959; // SPI_CS计数 div*32
// //--------300m--300分频--1M-----------
// localparam DIVIDE_CLK = 8'd200;
// localparam DIVIDE_CNT = 8'd14; // DIVICE_CNT_2的位宽
// localparam DIVICE_CNT_2 = 32'd6399; // SPI_CS计数 div*32
// STATE MACHINE
localparam [2:0]
ST_IDLE = 3'd0,
ST_HEAD = 3'd1,
ST_LENGTH = 3'd2,
ST_WR_DATA = 3'd3,
ST_RD_DATA = 3'd4,
ST_END = 3'd5;
localparam [24 : 0 ] IRQ_ADDR = 25'h00014;
wire [7:0] DIVIDE_CLK;// = 6; //时钟分频
wire [31:0] DIVICE_CNT2 = (DIVIDE_CLK<<5) - 1;// = 32'd191; //32位所需要的主时钟个数
reg [31 : 0] wready_spi_fifo_cnt;
wire wvalid_spi_fifo;
reg wready_spi_fifo;
reg wready_spi_fifo_flg; // control whether the wready is passed
wire [31 : 0] write_spi_fifo;
reg [31 : 0] write_spi_fifo_r;
reg [31 : 0] valid_wready_cnt;
reg cmd_wr;
reg [4 : 0] cmd_id; // cmd ID
reg [24 : 0] cmd_addr; // cmd ADDR
reg [31 : 0] cmd_length; // the length of this transaction
reg [31 : 0] wrdata_spi_fifo;
reg [2 : 0] state_current = ST_IDLE;
reg [2 : 0] state_next = ST_IDLE;
reg tlast_o_r;
reg tlast_zo_r;
reg tlast_zo_r1;
reg ss_r;
reg ss_rr; // for spi clk
reg spi_clk_r;
reg [7 : 0] spi_clk_cnt;
reg spi_clk_r1; // delay 1 clk
reg spi_clk_r2;
reg ss_r1; // ss_r delay 1 sys clk
reg ss_rr1; // ss_rr delay 1 sys clk
reg ss_rr2; // ss_rr delay 2 sys clk
reg ss_rr3;
wire ss_rr_falledge;
reg [4:0] slot;
reg [2:0] exaddr;
//
reg irq_get;
reg irq_state; // 中断状态此时不再接受外部的数据先发送中断查询信号
wire irq_valid;
wire tx_edge; // fall edge
wire rx_edge; // rise edge
assign tx_edge = spi_clk_r1 & (~spi_clk_r);
assign rx_edge = (~spi_clk_r1) & spi_clk_r;
reg [4 : 0] tx_edge_cnt; // 0~31
reg [4 : 0] rx_edge_cnt; // 0~31
reg spi_master_bit_r;
reg [31 : 0] rd_spi_data;
reg rd_spi_data_valid;
reg [31 : 0] rd_spi_data_fifo;
reg rd_spi_data_valid_fifo;
wire rd_spi_data_valid_edge;
reg [31 : 0] rd_spi_head_cnt;
wire wready_spi_fifo_flg_w;
assign wvalid_spi_fifo = (irq_state == 1'b1) ? irq_valid : WVALID_spi; // valid irq_state 选择是外部的valid 还是中断的 valid
assign WREADY_spi = (irq_state == 1'b1) ? 1'b0 : (wready_spi_fifo && wready_spi_fifo_flg); // wready irq_state 选择是输出 ready 接收外部数据还是输出0发送中断查询数据
assign write_spi_fifo = WDATA_spi;
assign tlast_o = tlast_o_r;
assign tlast_zo = (~tlast_zo_r1) & tlast_zo_r;
assign cmd_length_o = cmd_length;
assign cmd_wr_o = cmd_wr;
wire cmd_length_error;
assign cmd_length_error = (cmd_length > 32'd2) ? 1 : 0;
// spi interrupt
reg [1:0]irq_r;
wire irq_edge;
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(~sys_rst_n)
begin
irq_r <= 0;
end
else
begin
irq_r <= {irq_r[0],irq};
end
end
assign irq_edge = irq_r==2'b01;
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(~sys_rst_n)
begin
irq_get <= 1'b0;
end
else if(irq_edge)
begin
irq_get <= 1'b1;
end
else if((state_next == ST_END) && (state_current < ST_END) && irq_state && spi_busy) // 中断发送的最后一个bit((state_next == ST_END) && (state_current < ST_END) tlast_o_r 早一个系统clk)
begin
irq_get <= 1'b0;
end
end
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(~sys_rst_n)
begin
irq_state <= 1'b0;
end
// else if(irq_get && (~spi_busy))
// else if(irq_get && ((state_current == ST_WR_DATA) || (state_current == ST_RD_DATA))) // 此时不在发数状态里
else if(irq_get && ((state_current == ST_END) || (state_current == ST_IDLE))) // 此时不在发数状态里
begin
irq_state <= 1'b1;
end
else if(tlast_o_r && irq_state && spi_busy) // 中断发送的最后一个bit
begin
irq_state <= 1'b0;
end
end
assign irq_valid = (irq_state && (valid_wready_cnt <= 32'd4)) ? 1'b1 : 1'b0; // 固定长度的读命令
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge sys_clk) begin
state_current <= (!sys_rst_n) ? ST_IDLE : state_next;
end
always @(*)
begin
begin
case (state_current)
ST_IDLE: state_next = (valid_wready_cnt == 32'b0) && (wvalid_spi_fifo && wready_spi_fifo && wready_spi_fifo_flg) ? ST_HEAD : ST_IDLE;
ST_HEAD: state_next = (valid_wready_cnt == 32'b1) && (wvalid_spi_fifo && wready_spi_fifo && wready_spi_fifo_flg) ? ST_LENGTH : ST_HEAD ;
ST_LENGTH: state_next = (valid_wready_cnt == 32'd2) && ((cmd_wr || wvalid_spi_fifo) && wready_spi_fifo) ? (cmd_wr ? ST_RD_DATA : ST_WR_DATA) : ST_LENGTH;
ST_WR_DATA: state_next = (valid_wready_cnt == cmd_length + 32'd2) && wready_spi_fifo ? ST_END : ST_WR_DATA;
ST_RD_DATA: state_next = (valid_wready_cnt == cmd_length + 32'd3) ? ST_END : ST_RD_DATA;
ST_END: state_next = (wready_spi_fifo_cnt == 32'b1) ? ST_IDLE : ST_END; // for the last data
default: state_next = ST_IDLE;
endcase
end
end
always @(posedge sys_clk or negedge sys_rst_n)
begin
if(~sys_rst_n)
begin
cmd_wr <= 1'b0;
cmd_id <= 5'b0;
cmd_addr <= 25'b0;
cmd_length <= 32'b0;
wrdata_spi_fifo <= 32'b0;
end
else if(irq_state) // 中断状态下命令是读某一地址的一个数
begin
case (state_current)
ST_HEAD:
begin
cmd_wr <= 1'b1;
cmd_id <= 5'b0;
cmd_addr <= IRQ_ADDR;
end
ST_LENGTH:
begin
cmd_length <= 32'd1;
slot <= write_spi_fifo_r[27:23];
exaddr <= write_spi_fifo_r[22:20];
wrdata_spi_fifo <= {cmd_wr,cmd_addr,cmd_id,1'b0};
// wrdata_spi_fifo <= {cmd_wr,1'b0,cmd_id,cmd_addr}; // 上传与下发数据格式不同attention !!!!!!!!
end
ST_WR_DATA: wrdata_spi_fifo <= 32'ha5a55a5a;
ST_RD_DATA: wrdata_spi_fifo <= 32'b1;
// ST_END: cmd_wr <= 1'b0;
default: wrdata_spi_fifo <= wrdata_spi_fifo;
endcase
end
else
begin
case (state_current)
ST_HEAD:
begin
cmd_wr <= write_spi_fifo_r[31];
cmd_id <= write_spi_fifo_r[29 : 25];
cmd_addr <= write_spi_fifo_r[24 : 0];
end
ST_LENGTH:
begin
cmd_length <= write_spi_fifo_r[19:0] >> 2;
slot <= write_spi_fifo_r[27:23];
exaddr <= write_spi_fifo_r[22:20];
wrdata_spi_fifo <= {cmd_wr,cmd_addr,cmd_id,1'b0};
// wrdata_spi_fifo <= {cmd_wr,1'b0,cmd_id,cmd_addr}; // 上传与下发数据格式不同attention !!!!!!!!
end
ST_WR_DATA: wrdata_spi_fifo <= write_spi_fifo_r;
ST_RD_DATA: wrdata_spi_fifo <= 32'b1;
// ST_END: cmd_wr <= 1'b0;
default: wrdata_spi_fifo <= wrdata_spi_fifo;
endcase
end
end
always@(posedge sys_clk)
begin
if((valid_wready_cnt == cmd_length + 32'd2) && (state_current > ST_LENGTH)) // read the last data
begin
tlast_zo_r <= 1'b1;
end
else
begin
tlast_zo_r <= 1'b0;
end
end
always@(posedge sys_clk)
begin
if((state_next == ST_END) && (state_current < ST_END))
begin
tlast_o_r <= 1'b1;
end
else
begin
tlast_o_r <= 1'b0;
end
end
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(~sys_rst_n)
begin
valid_wready_cnt <= 32'h0;
write_spi_fifo_r <= 32'b0;
end
else if(state_next < ST_WR_DATA)
begin
if(wvalid_spi_fifo && wready_spi_fifo && wready_spi_fifo_flg)
begin
valid_wready_cnt <= valid_wready_cnt + 32'b1;
write_spi_fifo_r <= write_spi_fifo;
end
end
else if(state_next < ST_END)
begin
if(cmd_wr)
begin
if(wready_spi_fifo_cnt == 32'd2) // compare with wready_spi_fifo, delay 1 clk
begin
valid_wready_cnt <= valid_wready_cnt + 32'b1;
write_spi_fifo_r <= 32'b1;
end
end
else
begin
if(wvalid_spi_fifo && wready_spi_fifo && wready_spi_fifo_flg)
begin
valid_wready_cnt <= valid_wready_cnt + 32'b1;
write_spi_fifo_r <= write_spi_fifo;
end
end
end
else // ST_END
begin
valid_wready_cnt <= 32'b0;
end
end
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(~sys_rst_n)
begin
wready_spi_fifo_flg <= 1'b0;
end
else if(state_next < ST_WR_DATA)
begin
if(cmd_wr && (state_next == ST_LENGTH))
begin
wready_spi_fifo_flg <= 1'b0;
end
else
begin
wready_spi_fifo_flg <= 1'b1;
end
end
else if(state_next < ST_END)
begin
if(valid_wready_cnt == cmd_length + 32'd2)
begin
wready_spi_fifo_flg <= 1'b0;
end
end
end
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(~sys_rst_n)
begin
wready_spi_fifo_cnt <= 'd0;
end
else if(~wvalid_spi_fifo && (state_current == ST_IDLE))
begin
wready_spi_fifo_cnt <= 'd0;
end
else if((wready_spi_fifo_cnt == 'd20) && (state_current == ST_END)) // 缩短ST_END状态时间
begin
wready_spi_fifo_cnt <= 'd0;
end
else
begin
if(DIVICE_CNT2 == wready_spi_fifo_cnt) begin
wready_spi_fifo_cnt <= 'd0;
end
else begin
wready_spi_fifo_cnt <= wready_spi_fifo_cnt + 'd1;
end
end
end
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(~sys_rst_n)
begin
wready_spi_fifo <= 1'b0;
end
else if((wready_spi_fifo_cnt == 32'b1) && (~wready_spi_fifo))
begin
wready_spi_fifo <= 1'b1;
end
else
begin
wready_spi_fifo <= 1'b0;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(~sys_rst_n)
begin
ss_r <= 1'b1;
end
else if((state_current == ST_IDLE) || ((wready_spi_fifo_cnt == 32'd7) && (state_current == ST_END)))
begin
ss_r <= 1'b1;
end
else if((wready_spi_fifo_cnt == DIVICE_CNT2) && (state_current == ST_HEAD))
begin
ss_r <= 1'b0;
end
end
// compare with the ss_r, fall delay 3 sysclk and rise before 5 sysclk,for spi clk cnt (for 4 sys clk between ss and spi_clk)
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(~sys_rst_n) // (valid_wready_cnt == cmd_length + 32'd2) means the last data
begin
ss_rr <= 1'b1;
end
else if((state_current == ST_IDLE) || ((wready_spi_fifo_cnt == 32'd2) && ((state_current == ST_WR_DATA) || (state_current == ST_RD_DATA)) && (valid_wready_cnt == cmd_length + 32'd2)))
begin
ss_rr <= 1'b1;
end
else if((wready_spi_fifo_cnt == 32'd2) && (state_current == ST_HEAD))
begin
ss_rr <= 1'b0;
end
end
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
always@(posedge sys_clk)
begin
if(ss_rr)
begin
spi_clk_cnt <= 8'hff;
end
else
begin
if(spi_clk_cnt == DIVIDE_CLK - 1)
begin
spi_clk_cnt <= 8'b0;
end
else
begin
spi_clk_cnt <= spi_clk_cnt + 8'b1;
end
end
end
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(~sys_rst_n)
begin
spi_clk_r <= 1'b1;
end
else if(ss_rr)
begin
spi_clk_r <= 1'b1;
end
// else if(~ss_rr)
else
begin
if(spi_clk_cnt >= DIVIDE_CLK - 1)
begin
spi_clk_r <= 1'b0;
end
else if(spi_clk_cnt == (DIVIDE_CLK >> 1) - 1)
begin
spi_clk_r <= 1'b1;
end
end
end
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(~sys_rst_n)
begin
ss_r1 <= 1'b1;
spi_clk_r1 <= 1'b1;
spi_clk_r2 <= 1'b1;
ss_rr1 <= 1'b1;
ss_rr2 <= 1'b1;
ss_rr3 <= 1'b1;
tlast_zo_r1<= 1'b0;
end
else
begin
ss_r1 <= ss_r;
spi_clk_r1 <= spi_clk_r;
spi_clk_r2 <= spi_clk_r1;
ss_rr1 <= ss_rr;
ss_rr2 <= ss_rr1;
ss_rr3 <= ss_rr2;
tlast_zo_r1<= tlast_zo_r;
end
end
assign ss_rr_falledge = (ss_rr3) & (~ss_rr2); // ss_rr fall edge, means transfer start
// tx
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(~sys_rst_n)
begin
spi_master_bit_r <= 1'b0;
tx_edge_cnt <= 5'd31;
end
else if(ss_rr)
begin
spi_master_bit_r <= 1'b0;
tx_edge_cnt <= 5'd31;
end
else if(tx_edge)
begin
spi_master_bit_r <= wrdata_spi_fifo[tx_edge_cnt];
tx_edge_cnt <= tx_edge_cnt - 32'b1;
end
end
// ----------------------------------------rx------------------------------------
wire [ 2: 0] SPI_MISO_DELAY ;
reg [4 : 0] rx_edge_dly;
reg [4 : 0] rx_ss_rr;
reg [4 : 0] rx_ss_r;
reg [4 : 0] rx_ss_rr_falledge;
always @(posedge sys_clk) begin
rx_edge_dly <= {rx_edge_dly[3:0], rx_edge};
rx_ss_rr <= {rx_ss_rr[3:0], ss_rr};
rx_ss_r <= {rx_ss_r[3:0], ss_r};
rx_ss_rr_falledge <= {rx_ss_rr_falledge[3:0], ss_rr_falledge};
end
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(~sys_rst_n)
begin
rd_spi_data <= 32'b0;
rx_edge_cnt <= 5'd31;
end
else if(rx_ss_rr[SPI_MISO_DELAY]) //MISO延迟
begin
rd_spi_data <= 32'b0;
rx_edge_cnt <= 5'd31;
end
// else if(rx_edge)
else if(rx_edge_dly[SPI_MISO_DELAY]) //MISO延迟
begin
rd_spi_data[rx_edge_cnt] <= spi_slave_bit;
rx_edge_cnt <= rx_edge_cnt - 32'b1;
end
end
assign rd_spi_data_valid_edge = rd_spi_data_valid && (rx_edge_cnt != 32'b0); // valid only 1 sys clk
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(~sys_rst_n)
begin
rd_spi_data_valid <= 1'b0;
end
else if(rx_ss_rr[SPI_MISO_DELAY]) //MISO延迟
begin
rd_spi_data_valid <= 1'b0;
end
else if(rx_edge_cnt == 32'b0)
begin
rd_spi_data_valid <= 1'b1;
end
else
begin
rd_spi_data_valid <= 1'b0;
end
end
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(~sys_rst_n)
begin
rd_spi_head_cnt <= 32'h0;
end
else if(rx_ss_r[SPI_MISO_DELAY]) //MISO延迟
begin
rd_spi_head_cnt <= 32'h0;
end
else if(rx_ss_rr_falledge[SPI_MISO_DELAY] || rd_spi_data_valid_edge) //MISO延迟
begin
rd_spi_head_cnt <= rd_spi_head_cnt + 32'b1;
end
end
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(~sys_rst_n)
begin
rd_spi_data_fifo <= 32'b0;
rd_spi_data_valid_fifo <= 1'b0;
end
else if(rx_ss_r[SPI_MISO_DELAY]) //MISO延迟
begin
rd_spi_data_fifo <= 32'b0;
rd_spi_data_valid_fifo <= 1'b0;
end
else if(rd_spi_head_cnt == 32'b0) // head
begin
// rd_spi_data_fifo <= wrdata_spi_fifo;
rd_spi_data_fifo <= {cmd_wr,1'b0,cmd_id,cmd_addr}; // 上传与下发数据格式不同attention !!!!!!!!
rd_spi_data_valid_fifo <= rx_ss_rr_falledge[SPI_MISO_DELAY];//MISO延迟
end
else if(rd_spi_head_cnt == 32'b1) //length
begin
rd_spi_data_fifo <= {4'b0,slot,exaddr,cmd_length[17:0],2'b0};
// rd_spi_data_fifo <= cmd_length<<2;
rd_spi_data_valid_fifo <= rd_spi_data_valid_edge;
end
else
begin
rd_spi_data_fifo <= rd_spi_data; // data
rd_spi_data_valid_fifo <= rd_spi_data_valid_edge;
end
end
assign RDATA_spi_o = {tlast_o_r, rd_spi_data_fifo};
assign RVALID_spi_o = (cmd_wr) ? rd_spi_data_valid_fifo : 1'b0;
assign ss = ss_r1;
assign spi_busy = ~ss;
assign spi_clk = spi_clk_r1;
assign spi_master_bit = spi_master_bit_r;
generate
if (DEBUG == 1) begin: debug_gen
ila_spi_m1 ila_spi_m1_u(
.clk(sys_clk),
.probe0({ss,spi_clk,spi_master_bit,spi_slave_bit,cmd_wr,cmd_id,cmd_addr,cmd_length,wrdata_spi_fifo,rd_spi_data_valid_fifo,rd_spi_data_fifo,tlast_o_r,state_current,state_next}), // 139
.probe1({WDATA_spi, WVALID_spi, WREADY_spi, cmd_length_error}), // 35
.probe2({valid_wready_cnt,wready_spi_fifo_flg,wvalid_spi_fifo, wready_spi_fifo,write_spi_fifo,wready_spi_fifo_cnt,WREADY_spi_r,WVALID_spi_r,irq,irq_get,irq_state,irq_valid}) // 76
);
//接收延迟
vio_SPI_DELAY vio_SPI_DELAY_I (
.clk (sys_clk ),// input wire clk
.probe_out0 (SPI_MISO_DELAY ),// output wire [2 : 0] probe_out0
.probe_out1 (DIVIDE_CLK )// output wire [7 : 0] probe_out1
);
end
else begin
assign SPI_MISO_DELAY = 3'b000;
assign DIVIDE_CLK = 8'd8;
end
endgenerate
endmodule

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//`define FPGA_XIL
//`define SMIC_IC
//`ifndef FPGA_XIL
//`ifndef SMIC_IC
//`define BEHAVIOUR_SIM
//`endif
//`endif
//`ifdef FPGA_XIL
`define XINLINX_FPGA
//`endif
`undef BEHAVIOUR_SIM
`undef SMIC_IC
module spram #(
parameter width =16,
parameter depth =1024
)(
clka,
ena,
dina,
addra,
clkb,
enb,
doutb,
addrb
);
///////////////////////////////////////////////////////
//Function
///////////////////////////////////////////////////////
function integer clog2(input integer depth);
begin
for(clog2=0;depth>0;clog2=clog2+1)
depth =depth>>1;
end
endfunction
localparam aw = clog2(depth-1);
///////////////////////////////////////////////////////
//Input declaration
///////////////////////////////////////////////////////
input clka;
input ena;
input [width-1:0] dina;
input [aw-1:0] addra;
input clkb;
input enb;
output [width-1:0] doutb;
input [aw-1:0] addrb;
///////////////////////////////////////////////////////
//SRAM
///////////////////////////////////////////////////////
`ifdef BEHAVIOUR_SIM
bhv_spram #(
.width (width ),
.depth (depth )
)bhv_spram(
.clka (clka ),
.ena (ena ),
.dina (dina ),
.addra (addra ),
.clkb (clkb ),
.enb (enb ),
.doutb (doutb ),
.addrb (addrb )
);
`elsif XINLINX_FPGA
xil_spram #(
.dw (width ),
.depth (depth )
)xil_spram(
.wrclk (clka ),
.wren (ena ),
.wrdata (dina ),
.wraddr (addra ),
.rdclk (clkb ),
.rden (enb ),
.rddata (doutb ),
.rdaddr (addrb )
);
`elsif SMIC_IC
smic_spram #(
.width (width),
.depth (depth)
)smic_spram(
.CLKB (clka ),
.CENB (ena ),
.AB (addra ),
.DB (dina ),
.CLKA (clkb ),
.CENA (enb ),
.AA (addrb ),
.QA (doutb )
);
`endif
endmodule
//`undef FPGA_XIL

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//<EFBFBD>жϲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//(1)<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֮<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>û<EFBFBD>б仯
//(2)<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
//////////////////////////////////////////////////////////////////////////////////
module stop_if #(
parameter CHx_CW =10
)(
input clk,
input nrst,
input [1:0] mode,
input [31:0] chx_thre,
input tx_fifo_x_empty,
input [CHx_CW-1:0] tx_fifo_x_rdcnt,
output int_x
);
////////////////////////////////////////
//reg wire
////////////////////////////////////////
reg [CHx_CW-1:0] rdcnt_dly1;
reg [CHx_CW-1:0] rdcnt_dly2;
reg [CHx_CW-1:0] rdcnt_dly3;
reg [CHx_CW-1:0] rdcnt_dly4;
reg [CHx_CW-1:0] rdcnt_dly5;
reg [CHx_CW-1:0] rdcnt_dly6;
reg [CHx_CW-1:0] rdcnt_dly7;
reg [CHx_CW-1:0] rdcnt_dly8;
wire wr_stop;
wire over_thre;
always@(posedge clk or negedge nrst)begin
if(!nrst)begin
rdcnt_dly1 <=0;
rdcnt_dly2 <=0;
rdcnt_dly3 <=0;
rdcnt_dly4 <=0;
rdcnt_dly5 <=0;
rdcnt_dly6 <=0;
rdcnt_dly7 <=0;
rdcnt_dly8 <=0;
end
else begin
rdcnt_dly1 <=tx_fifo_x_rdcnt;
rdcnt_dly2 <=rdcnt_dly1;
rdcnt_dly3 <=rdcnt_dly2;
rdcnt_dly4 <=rdcnt_dly3;
rdcnt_dly5 <=rdcnt_dly4;
rdcnt_dly6 <=rdcnt_dly5;
rdcnt_dly7 <=rdcnt_dly6;
rdcnt_dly8 <=rdcnt_dly7;
end
end
assign wr_stop = tx_fifo_x_rdcnt==rdcnt_dly1 &&
tx_fifo_x_rdcnt==rdcnt_dly2 &&
tx_fifo_x_rdcnt==rdcnt_dly3 &&
tx_fifo_x_rdcnt==rdcnt_dly4 &&
tx_fifo_x_rdcnt==rdcnt_dly5 &&
tx_fifo_x_rdcnt==rdcnt_dly6 &&
tx_fifo_x_rdcnt==rdcnt_dly7 &&
tx_fifo_x_rdcnt==rdcnt_dly8 &&
!tx_fifo_x_empty && tx_fifo_x_rdcnt!=0;
assign over_thre = (tx_fifo_x_rdcnt>chx_thre) ? 1'b1 : 1'b0;
//assign int_x = wr_stop | over_thre;
assign int_x = mode==2'b00 ? (wr_stop | over_thre) :
mode==2'b01 ? over_thre :
mode==2'b10 ? wr_stop :
mode==2'b11 ? 1'b0 : 1'b0;
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//温度计编码
//寻找从第一个bit开始第一个不为0的bit的位置
//////////////////////////////////////////////////////////////////////////////////
module tmp_encode(
input [14:0] din,
output reg [3:0] dout
);
always@(*)begin
case(1'b1)
din[0]: dout =4'd0;
din[1]: dout =4'd1;
din[2]: dout =4'd2;
din[3]: dout =4'd3;
din[4]: dout =4'd4;
din[5]: dout =4'd5;
din[6]: dout =4'd6;
din[7]: dout =4'd7;
din[8]: dout =4'd8;
din[9]: dout =4'd9;
din[10]: dout =4'd10;
din[11]: dout =4'd11;
din[12]: dout =4'd12;
din[13]: dout =4'd13;
din[14]: dout =4'd14;
default:begin
dout =4'b1111;
end
endcase
end
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/07/03 13:29:31
// Design Name:
// Module Name: dpram
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//`define XINLINX_FPGA
module xil_spram #(
parameter dw=16,
parameter depth =256
)(
wrclk,
wren,
wrdata,
wraddr,
rdclk,
rden,
rddata,
rdaddr
);
////////////////////////////////////////////////////////////////////////////////
//Function
////////////////////////////////////////////////////////////////////////////////
function integer clog2(input integer bit_depth);
begin
for(clog2=0;bit_depth>0;clog2=clog2+1)
bit_depth =bit_depth>>1;
end
endfunction
localparam aw=clog2(depth-1);
localparam mb=dw*(32'h0000_0001<<aw);
////////////////////////////////////////////////////////////////////////////////
//Input declaration
////////////////////////////////////////////////////////////////////////////////
input wrclk;
input wren;
input [dw-1:0] wrdata;
input [aw-1:0] wraddr;
input rdclk;
input rden;
output [dw-1:0] rddata;
input [aw-1:0] rdaddr;
////////////////////////////////////////////////////////////////////////////////
//XPM
////////////////////////////////////////////////////////////////////////////////
xpm_memory_sdpram # (
// Common module parameters
.MEMORY_SIZE (mb), //positive integer
.MEMORY_PRIMITIVE ("block"), //string; "auto", "distributed", "block" or "ultra";
.CLOCKING_MODE ("independent_clock"),//string; "common_clock", "independent_clock"
.MEMORY_INIT_FILE ("none"), //string; "none" or "<filename>.mem"
.MEMORY_INIT_PARAM ("" ), //string;
.USE_MEM_INIT (1), //integer; 0,1
.WAKEUP_TIME ("disable_sleep"), //string; "disable_sleep" or "use_sleep_pin"
.MESSAGE_CONTROL (0), //integer; 0,1
.ECC_MODE ("no_ecc"), //string; "no_ecc", "encode_only", "decode_only" or "both_encode_and_decode"
.AUTO_SLEEP_TIME (0), //Do not Change
// Port A module parameters
.WRITE_DATA_WIDTH_A (dw), //positive integer
.BYTE_WRITE_WIDTH_A (dw), //integer; 8, 9, or WRITE_DATA_WIDTH_A value
.ADDR_WIDTH_A (aw), //positive integer
// Port B module parameters
.READ_DATA_WIDTH_B (dw), //positive integer
.ADDR_WIDTH_B (aw), //positive integer
.READ_RESET_VALUE_B ("0"), //string
.READ_LATENCY_B (1), //non-negative integer
.WRITE_MODE_B ("no_change") //string; "write_first", "read_first", "no_change"
) xpm_memory_sdpram_inst (
// Common module ports
.sleep (1'b0),
// Port A module ports
.clka (wrclk ),
.ena (1'b1 ),
.wea (wren ),
.addra (wraddr[aw-1:0] ),
.dina (wrdata ),
.injectsbiterra (1'b0 ),
.injectdbiterra (1'b0 ),
// Port B module ports
.clkb (rdclk ),
.rstb (0 ),
.enb (rden ),
.regceb (0 ),
.addrb (rdaddr[aw-1:0] ),
.doutb (rddata ),
.sbiterrb (),
.dbiterrb ()
);
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/07/08 15:58:25
// Design Name:
// Module Name: Eth_1G_Top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Eth_1G_Top
(
input reset,
// input gtrefclk1_p,
// input gtrefclk1_n,
input drp_clk,
input userclk2_o,
// input sfp_rx_p,
// input sfp_rx_n,
// output sfp_tx_p,
// output sfp_tx_n,
//RGMII S
input ETHA_RXD0 ,
input ETHA_RXD1 ,
input ETHA_RXD2 ,
input ETHA_RXD3 ,
input ETHA_RXCTL ,
input ETHA_RXCK ,
output ETHA_TXD0 ,
output ETHA_TXD1 ,
output ETHA_TXD2 ,
output ETHA_TXD3 ,
output ETHA_TXCTL ,
output ETHA_TXCK ,
inout ETHA_MDIO ,
output ETHA_MDC ,
output phy_resetn ,
input Clk_Sys300M ,
output inband_link_status ,
//RGMII E
output [15:0] PHY_status_vector,
output sfp_tx_disable,
output gt_powergood,
output [3:0] s0_tcp_state,
input dcm_locked,
//output s_axi_resetn,
// register
output reg_clk, // userclk2_o
input [31:0] reg_addr ,
input reg_wren ,
input [31:0] reg_wrdata,
input reg_rden ,
output [31:0] reg_rddata,
// UDP App Interface
output udp_app_recv_fifo_rdclk, // userclk2_o
output udp_app_recv_fifo_empty,
output [11:0] udp_app_recv_fifo_rdcnt,
input udp_app_recv_fifo_rden,
output [7:0] udp_app_recv_fifo_rddata,
output udp_app_send_fifo_rdclk, // userclk2_o
input udp_app_send_fifo_empty,
input [11:0] udp_app_send_fifo_rdcnt,
output udp_app_send_fifo_rden,
input [7:0] udp_app_send_fifo_rddata,
// TCP App Interface
output s0_user_tx_fifo_rdclk, // userclk2_o
input [11:0] s0_user_tx_fifo_rdcnt,
output s0_user_tx_fifo_rden,
input [7:0] s0_user_tx_fifo_rddata,
input s0_user_rx_fifo_rdclk, // userclk2_o
output s0_user_rx_fifo_empty,
input s0_user_rx_fifo_rden,
output [7:0] s0_user_rx_fifo_rddata
);
wire gtrefclk;
wire userclk;
wire rxuserclk;
wire rxuserclk2;
wire pma_reset;
wire resetdone;
wire [7:0] gmii_txd;
wire gmii_tx_en;
wire gmii_tx_er;
wire [7:0] gmii_rxd;
wire gmii_rx_dv;
wire gmii_rx_er;
wire gmii_isolate;
wire an_interrupt;
wire mmcm_locked;
//wire dcm_locked;
wire rx_reset;
wire tx_reset;
wire glbl_rst_intn;
wire gtx_resetn;
wire s_axi_resetn;
wire core_reset;
wire phy_resetn;
wire rx_mac_aclk; // MAC Rx clock
wire tx_mac_aclk; // MAC Tx clock
// MAC receiver client I/F
wire [7:0] rx_axis_mac_tdata;
wire rx_axis_mac_tvalid;
wire rx_axis_mac_tlast;
wire rx_axis_mac_tuser;
// MAC transmitter client I/F
wire [7:0] tx_axis_mac_tdata;
wire tx_axis_mac_tvalid;
wire tx_axis_mac_tready;
wire tx_axis_mac_tlast;
wire tx_axis_mac_tuser;
// AXI-Lite interface
wire [11:0] s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_awready;
wire [31:0] s_axi_wdata;
wire s_axi_wvalid;
wire s_axi_wready;
wire [1:0] s_axi_bresp;
wire s_axi_bvalid;
wire s_axi_bready;
wire [11:0] s_axi_araddr;
wire s_axi_arvalid;
wire s_axi_arready;
wire [31:0] s_axi_rdata;
wire [1:0] s_axi_rresp;
wire s_axi_rvalid;
wire s_axi_rready;
assign sfp_tx_disable = 1'b0;
wire mac_tx_valid;
wire [7:0] mac_tx_data;
wire [7:0] mac_tx_keep;
wire mac_tx_ready;
wire mac_tx_last;
wire mac_tx_user;
wire mac_rx_ready;
wire mac_rx_valid;
wire [7:0] mac_rx_data;
wire [7:0] mac_rx_keep;
wire mac_rx_last;
wire mac_rx_user;
// // Gigabytes Ethernet PHY core
// gig_ethernet_pcs_pma_1 gig_ethernet_pcs_pma_i_1(
// .gtrefclk_p (gtrefclk1_p), // input
// .gtrefclk_n (gtrefclk1_n), // input
// .gtrefclk_out (gtrefclk), // output /* synthesis syn_isclock = 1 */;
// // .gtrefclk_bufg_out (gtrefclk_bufg), // output /* synthesis syn_isclock = 1 */;
// .txp (sfp_tx_p), // output
// .txn (sfp_tx_n), // output
// .rxp (sfp_rx_p), // input
// .rxn (sfp_rx_n), // input
// .mmcm_locked_out (mmcm_locked), // output
// .userclk_out (userclk), // output /* synthesis syn_isclock = 1 */;
// .userclk2_out (userclk2_o), // output /* synthesis syn_isclock = 1 */;
// .rxuserclk_out (rxuserclk), // output /* synthesis syn_isclock = 1 */;
// .rxuserclk2_out (rxuserclk2), // output /* synthesis syn_isclock = 1 */;
// .independent_clock_bufg(drp_clk), // input /* synthesis syn_isclock = 1 */;
// .pma_reset_out (pma_reset), // output
// .resetdone (resetdone), // output
// .gmii_txd (gmii_txd), // input [7:0]
// .gmii_tx_en (gmii_tx_en), // input
// .gmii_tx_er (gmii_tx_er), // input
// .gmii_rxd (gmii_rxd), // output
// .gmii_rx_dv (gmii_rx_dv), // output
// .gmii_rx_er (gmii_rx_er), // output
// .gmii_isolate (gmii_isolate), // output
// .configuration_vector (5'b0), // input [4:0]
// .an_interrupt (an_interrupt), // output
// .an_adv_config_vector (16'b0000000000100001), // input [15:0]
// .an_restart_config (1'b0), // input
// .status_vector (PHY_status_vector), // output [15:0]
// .reset (reset), // input 1'b0
// .signal_detect (1'b1), // input
// .gtpowergood (gt_powergood) // output
// // .gt0_qplloutclk_out (gt0_qplloutclk), // output
// // .gt0_qplloutrefclk_out (gt0_qplloutrefclk) // output
// );
// Gigabytes Ethernet MAC reset
tri_mode_ethernet_mac_0_example_design_resets tri_mode_ethernet_mac_resets(
// clocks
.s_axi_aclk (userclk2_o),
.gtx_clk (userclk2_o),
.core_clk (drp_clk),
// asynchronous resets
.glbl_rst (reset),
.reset_error (1'b0),
.rx_reset (rx_reset),
.tx_reset (tx_reset),
.dcm_locked (dcm_locked),
// synchronous reset outputs
.glbl_rst_intn (glbl_rst_intn),
.gtx_resetn (gtx_resetn),
.s_axi_resetn (s_axi_resetn),
.phy_resetn (phy_resetn),
.chk_resetn (),
.core_reset (core_reset)
);
// Gigabytes Ethernet MAC core
tri_mode_ethernet_mac_0 tri_mode_ethernet_mac_0_u(
.gtx_clk (userclk2_o), // input
// asynchronous reset
.glbl_rstn (glbl_rst_intn), // input
.rx_axi_rstn (1'b1), // input
.tx_axi_rstn (1'b1), // input
// Receiver Interface
.rx_statistics_vector (), // output [27:0]
.rx_statistics_valid (), // output
.rx_mac_aclk (rx_mac_aclk), // output
.rx_reset (rx_reset), // output
.rx_axis_mac_tdata (rx_axis_mac_tdata ), // output [7:0]
.rx_axis_mac_tvalid (rx_axis_mac_tvalid), // output
.rx_axis_mac_tlast (rx_axis_mac_tlast ), // output
.rx_axis_mac_tuser (rx_axis_mac_tuser ), // output
// Transmitter Interface
.tx_ifg_delay (8'd0), // input [7:0]
.tx_statistics_vector (), // output [31:0]
.tx_statistics_valid (), // output
.tx_mac_aclk (tx_mac_aclk), // output
.tx_reset (tx_reset), // output
.tx_axis_mac_tdata (tx_axis_mac_tdata), // input [7:0]
.tx_axis_mac_tvalid (tx_axis_mac_tvalid), // input
.tx_axis_mac_tlast (tx_axis_mac_tlast ), // input
.tx_axis_mac_tuser (tx_axis_mac_tuser), // input
.tx_axis_mac_tready (tx_axis_mac_tready), // output
// MAC Control Interface
.pause_req (1'b0), // input
.pause_val (16'b0), // input [15:0]
.speedis100 (), // output
.speedis10100 (), // output
// GMII Interface
// .gmii_txd (gmii_txd ), // output [7:0]
// .gmii_tx_en (gmii_tx_en ), // output
// .gmii_tx_er (gmii_tx_er ), // output
// .gmii_rxd (gmii_rxd ), // input [7:0]
// .gmii_rx_dv (gmii_rx_dv ), // input
// .gmii_rx_er (gmii_rx_er ), // input
// RGMII Interface
.rgmii_txd ({ETHA_TXD3,ETHA_TXD2,ETHA_TXD1,ETHA_TXD0}),// output wire [3 : 0] rgmii_txd
.rgmii_tx_ctl (ETHA_TXCTL ),// output wire rgmii_tx_ctl
.rgmii_txc (ETHA_TXCK ),// output wire rgmii_txc
.rgmii_rxd ({ETHA_RXD3,ETHA_RXD2,ETHA_RXD1,ETHA_RXD0}),// input wire [3 : 0] rgmii_rxd
.rgmii_rx_ctl (ETHA_RXCTL ),// input wire rgmii_rx_ctl
.rgmii_rxc (ETHA_RXCK ),// input wire rgmii_rxc
.inband_link_status (inband_link_status ),// output wire inband_link_status
.inband_clock_speed ( ),// output wire [1 : 0] inband_clock_speed
.inband_duplex_status ( ),// output wire inband_duplex_status
// AXI-Lite Interface
.s_axi_aclk (userclk2_o), // input
.s_axi_resetn (s_axi_resetn), // input
.s_axi_awaddr (s_axi_awaddr), // input [11:0]
.s_axi_awvalid (s_axi_awvalid), // input
.s_axi_awready (s_axi_awready), // output
.s_axi_wdata (s_axi_wdata), // input [31:0]
.s_axi_wvalid (s_axi_wvalid), // input
.s_axi_wready (s_axi_wready), // output
.s_axi_bresp (s_axi_bresp), // output [1:0]
.s_axi_bvalid (s_axi_bvalid), // output
.s_axi_bready (s_axi_bready), // input
.s_axi_araddr (s_axi_araddr), // input [11:0]
.s_axi_arvalid (s_axi_arvalid), // input
.s_axi_arready (s_axi_arready), // output
.s_axi_rdata (s_axi_rdata), // output [31:0]
.s_axi_rresp (s_axi_rresp), // output [1:0]
.s_axi_rvalid (s_axi_rvalid), // output
.s_axi_rready (s_axi_rready), // input
.mac_irq () // output
);
// Tri-mode MAC AXI-Lite interface
tri_mode_ethernet_mac_0_axi_lite_sm axi_lite_controller_0 (
.s_axi_aclk (userclk2_o),
.s_axi_resetn (s_axi_resetn),
.mac_speed (2'b10),
.update_speed (1'b0), // may need glitch protection on this..
.serial_command (1'b0),
.serial_response (),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
.s_axi_wdata (s_axi_wdata),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
.s_axi_araddr (s_axi_araddr),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready)
);
// TOE
toe_top_s TOE_inst(
.clk (userclk2_o), // input
.rst (reset), // input
//host interface:apb bus
.reg_clk (userclk2_o), // input
.reg_rst (reset), // input
.reg_addr (reg_addr ), // input [31:0]
.reg_wren (reg_wren ), // input
.reg_wrdata (reg_wrdata), // input [31:0]
.reg_rden (reg_rden ), // input
.reg_rddata (reg_rddata), // output[31:0]
//interrupt
.intr (), // output
.ex_in (), // output
.s0_tcp_state (s0_tcp_state),
//gmac interface
//output [1:0] mac_speed,
//output update_speed,
.mac_rx_ready (mac_rx_ready), // output
.mac_rx_valid (mac_rx_valid), // input
.mac_rx_data (mac_rx_data ), // input [7:0]
.mac_rx_last (mac_rx_last ), // input
.mac_tx_ready (mac_tx_ready), // input
.mac_tx_valid (mac_tx_valid), // output
.mac_tx_data (mac_tx_data ), // output [7:0]
.mac_tx_last (mac_tx_last ), // output
//udp app interface
.udp_app_recv_fifo_rdclk (udp_app_recv_fifo_rdclk ), // input udp_app_recv_fifo_rdclk
.udp_app_recv_fifo_empty (udp_app_recv_fifo_empty ), // output
.udp_app_recv_fifo_rdcnt (udp_app_recv_fifo_rdcnt ), // output [11:0]
.udp_app_recv_fifo_rden (udp_app_recv_fifo_rden && (~udp_app_recv_fifo_empty)), // input
.udp_app_recv_fifo_rddata (udp_app_recv_fifo_rddata), // output [7:0]
.udp_app_send_fifo_rdclk (udp_app_send_fifo_rdclk ), // output
.udp_app_send_fifo_empty (udp_app_send_fifo_empty ), // input
.udp_app_send_fifo_rdcnt (udp_app_send_fifo_rdcnt ), // input [11:0]
.udp_app_send_fifo_rden (udp_app_send_fifo_rden ), // output
.udp_app_send_fifo_rddata (udp_app_send_fifo_rddata), // input [7:0]
//tcp app interface to mux_dmux
.s0_user_tx_fifo_rdclk (s0_user_tx_fifo_rdclk ), // output
.s0_user_tx_fifo_rdcnt (s0_user_tx_fifo_rdcnt ), // input [11:0]
.s0_user_tx_fifo_rden (s0_user_tx_fifo_rden ), // output
.s0_user_tx_fifo_rddata (s0_user_tx_fifo_rddata ), // input [7:0]
.s0_user_rx_fifo_rdclk (s0_user_rx_fifo_rdclk ), // input
.s0_user_rx_fifo_empty (s0_user_rx_fifo_empty ), // output
.s0_user_rx_fifo_rden (s0_user_rx_fifo_rden ), // input
.s0_user_rx_fifo_rddata (s0_user_rx_fifo_rddata ) // output [7:0]
);
// MAC RX FIFO
axis_data_fifo_1 rx_async_fifo0 (
.s_axis_aresetn (~core_reset), // input wire s_axis_aresetn
.s_axis_aclk (rx_mac_aclk), // input wire s_axis_aclk
.s_axis_tvalid (rx_axis_mac_tvalid), // input wire s_axis_tvalid
.s_axis_tready (), // output wire s_axis_tready
.s_axis_tdata (rx_axis_mac_tdata), // input wire [7 : 0] s_axis_tdata
.s_axis_tkeep (8'hff), // input wire [7 : 0] s_axis_tkeep
.s_axis_tlast (rx_axis_mac_tlast), // input wire s_axis_tlast
.s_axis_tuser (1'b0), // input wire [0 : 0] s_axis_tuser
.m_axis_aclk (userclk2_o), // input wire m_axis_aclk
.m_axis_tvalid (mac_rx_valid), // output wire m_axis_tvalid
.m_axis_tready (mac_rx_ready), // input wire m_axis_tready
.m_axis_tdata (mac_rx_data), // output wire [7 : 0] m_axis_tdata
.m_axis_tkeep (), // output wire [7 : 0] m_axis_tkeep
.m_axis_tlast (mac_rx_last), // output wire m_axis_tlast
.m_axis_tuser (), // output wire [0 : 0] m_axis_tuser
.axis_wr_data_count (), // output wire [31 : 0] axis_wr_data_count
.axis_rd_data_count () // output wire [31 : 0] axis_rd_data_count
);
// MAC TX FIFO
axis_data_fifo_1 tx_async_fifo0 (
.s_axis_aresetn (~core_reset), // input wire s_axis_aresetn
.s_axis_aclk (userclk2_o), // input wire s_axis_aclk
.s_axis_tvalid (mac_tx_valid), // input wire s_axis_tvalid
.s_axis_tready (mac_tx_ready), // output wire s_axis_tready
.s_axis_tdata (mac_tx_data), // input wire [7 : 0] s_axis_tdata
.s_axis_tkeep (8'hff), // input wire [7 : 0] s_axis_tkeep
.s_axis_tlast (mac_tx_last), // input wire s_axis_tlast
.s_axis_tuser (1'b0), // input wire [0 : 0] s_axis_tuser
.m_axis_aclk (tx_mac_aclk), // input wire m_axis_aclk
.m_axis_tvalid (tx_axis_mac_tvalid), // output wire m_axis_tvalid
.m_axis_tready (tx_axis_mac_tready), // input wire m_axis_tready
.m_axis_tdata (tx_axis_mac_tdata), // output wire [7 : 0] m_axis_tdata
.m_axis_tkeep (tx_axis_mac_tkeep), // output wire [7 : 0] m_axis_tkeep
.m_axis_tlast (tx_axis_mac_tlast), // output wire m_axis_tlast
.m_axis_tuser (tx_axis_mac_tuser), // output wire [0 : 0] m_axis_tuser
.axis_wr_data_count (), // output wire [31 : 0] axis_wr_data_count
.axis_rd_data_count () // output wire [31 : 0] axis_rd_data_count
);
assign udp_app_recv_fifo_rdclk = userclk2_o;
//assign s0_user_rx_fifo_rdclk = userclk2_o;
assign reg_clk = userclk2_o;
endmodule

View File

@ -0,0 +1,865 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/11/13 13:17:36
// Design Name:
// Module Name: Net_top_x1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Net_top_x1
(
input DelayCtrlCLK ,
input eth_userclk2 ,
input Clk_Sys300M ,
input drp_clk ,
input sys_clk_locked ,
//------------TX AXI-------------------
input [ 63: 0] i_NET_TX_S_AXIS_tdata ,
input [ 7: 0] i_NET_TX_S_AXIS_tkeep ,
input i_NET_TX_S_AXIS_tlast ,
output o_NET_TX_S_AXIS_tready ,
input i_NET_TX_S_AXIS_tvalid ,
//------------RX AXI-------------------
output [ 63: 0] o_NET_RX_m_axis_tdata ,
output [ 7: 0] o_NET_RX_m_axis_tkeep ,
output o_NET_RX_m_axis_tlast ,
input i_NET_RX_m_axis_tready ,
output o_NET_RX_m_axis_tvalid ,
//RGMII S
input ETHA_RXD0 ,
input ETHA_RXD1 ,
input ETHA_RXD2 ,
input ETHA_RXD3 ,
input ETHA_RXCTL ,
input ETHA_RXCK ,
output ETHA_TXD0 ,
output ETHA_TXD1 ,
output ETHA_TXD2 ,
output ETHA_TXD3 ,
output ETHA_TXCTL ,
output ETHA_TXCK ,
//RGMII E
inout ETHA_MDIO ,
output ETHA_MDC ,
output ETH_RST_n ,
//----------复位与状态指示-------------
output eth_linked ,
input Hard0_Rstn
);
wire drp_clk;
wire clk_200M;
wire clk_300M;
wire sys_clk_locked;
wire glb_reset;
wire eth_userclk2;
wire [15:0] PHY_status_vector;
wire sfp_tx_disable;
wire gt_powergood;
wire reg_clk ;
reg [31:0] reg_addr = 'b0;
reg reg_wren = 'b0;
reg [31:0] reg_wrdata = 'b0;
reg reg_rden = 'b0;
wire [31:0] reg_rddata ;
wire udp_app_recv_fifo_rdclk;
wire udp_app_recv_fifo_empty;
wire [11:0] udp_app_recv_fifo_rdcnt;
reg udp_app_recv_fifo_rden = 'b0;
wire [7:0] udp_app_recv_fifo_rddata;
wire udp_app_send_fifo_rdclk;
wire udp_app_send_fifo_empty;
wire [11:0] udp_app_send_fifo_rdcnt;
wire udp_app_send_fifo_rden;
wire [7:0] udp_app_send_fifo_rddata;
wire s0_user_tx_fifo_rdclk;
wire [11:0] s0_user_tx_fifo_rdcnt;
wire s0_user_tx_fifo_rden;
wire [7:0] s0_user_tx_fifo_rddata;
wire s0_user_rx_fifo_rdclk;
wire s0_user_rx_fifo_empty;
wire s0_user_rx_fifo_rden;
wire [7:0] s0_user_rx_fifo_rddata;
wire [3:0] s0_tcp_state;
wire [9:0] CMU_FPGA_temperature;
wire [9:0] CMU_Power_temperature;
wire inband_link_status ;
IDELAYCTRL #( // Instantiate input delay control block
.SIM_DEVICE ("ULTRASCALE") )
Eth_Ctrl (
.REFCLK (DelayCtrlCLK ),
.RST (glb_reset ),
.RDY ( )
);
assign glb_reset = (!Hard0_Rstn) | (!sys_clk_locked); //按键复位系统复位时钟未锁定IDELAYCTRL未准备好都将导致系统复位
// TCP UDP
Eth_1G_Top Eth_1G_inst
(
.reset (glb_reset ),
// .gtrefclk1_p (gtrefclk1_p ),
// .gtrefclk1_n (gtrefclk1_n ),
.drp_clk (drp_clk ),
.userclk2_o (eth_userclk2 ),
// .sfp_rx_p (sfp_rx_p ),
// .sfp_rx_n (sfp_rx_n ),
// .sfp_tx_p (sfp_tx_p ),
// .sfp_tx_n (sfp_tx_n ),
.ETHA_RXD0 (ETHA_RXD0 ),
.ETHA_RXD1 (ETHA_RXD1 ),
.ETHA_RXD2 (ETHA_RXD2 ),
.ETHA_RXD3 (ETHA_RXD3 ),
.ETHA_RXCTL (ETHA_RXCTL ),
.ETHA_RXCK (ETHA_RXCK ),
.ETHA_TXD0 (ETHA_TXD0 ),
.ETHA_TXD1 (ETHA_TXD1 ),
.ETHA_TXD2 (ETHA_TXD2 ),
.ETHA_TXD3 (ETHA_TXD3 ),
.ETHA_TXCTL (ETHA_TXCTL ),
.ETHA_TXCK (ETHA_TXCK ),
.ETHA_MDIO (ETHA_MDIO ),//inout
.ETHA_MDC (ETHA_MDC ),
.phy_resetn (ETH_RST_n ),
.Clk_Sys300M (Clk_Sys300M ),
.inband_link_status (inband_link_status ),
.PHY_status_vector (PHY_status_vector ),
.sfp_tx_disable (sfp_tx_disable ),
.gt_powergood (gt_powergood ),
.dcm_locked (sys_clk_locked ),
.s0_tcp_state (s0_tcp_state ),
.reg_clk (reg_clk ), // userclk2_o
.reg_addr (reg_addr ),
.reg_wren (reg_wren ),
.reg_wrdata (reg_wrdata ),
.reg_rden (reg_rden ),
.reg_rddata (reg_rddata ),
//------UDP Port--------
.udp_app_recv_fifo_rdclk (udp_app_recv_fifo_rdclk ), // userclk2_o
.udp_app_recv_fifo_empty (udp_app_recv_fifo_empty ),
.udp_app_recv_fifo_rdcnt (udp_app_recv_fifo_rdcnt ),
.udp_app_recv_fifo_rden (udp_app_recv_fifo_rden ),
.udp_app_recv_fifo_rddata (udp_app_recv_fifo_rddata),
.udp_app_send_fifo_rdclk (udp_app_send_fifo_rdclk ), // userclk2_o
.udp_app_send_fifo_empty (udp_app_send_fifo_empty ),
.udp_app_send_fifo_rdcnt (udp_app_send_fifo_rdcnt ),
.udp_app_send_fifo_rden (udp_app_send_fifo_rden ),
.udp_app_send_fifo_rddata (udp_app_send_fifo_rddata),
//------TCP Port--------
.s0_user_tx_fifo_rdclk (s0_user_tx_fifo_rdclk ), //output
.s0_user_tx_fifo_rdcnt (s0_user_tx_fifo_rdcnt ), //input [11:0]
.s0_user_tx_fifo_rden (s0_user_tx_fifo_rden ), //output
.s0_user_tx_fifo_rddata (s0_user_tx_fifo_rddata ), //input [7:0]
.s0_user_rx_fifo_rdclk (eth_userclk2 ), //input
.s0_user_rx_fifo_empty (s0_user_rx_fifo_empty ), //output
.s0_user_rx_fifo_rden (s0_user_rx_fifo_rden ), //input
.s0_user_rx_fifo_rddata (s0_user_rx_fifo_rddata ) //output [7:0]
);
// ethernet status
reg [11:0] eth_link_cnt = 'b0;
always @ (posedge eth_userclk2)
if(glb_reset)
eth_link_cnt <= 'b0;
else if(inband_link_status == 1'b1)
if(eth_link_cnt < 12'd4000)
eth_link_cnt <= eth_link_cnt + 1'b1;
else eth_link_cnt <= 12'd4090;
else eth_link_cnt <= 'b0;
wire eth_linked;
assign eth_linked = (eth_link_cnt >= 12'd4000);
// UDP RX
wire udp_app_recv_fifo_ready;
wire udp_app_recv_fifo_rden_r;
wire udp_recv_data_tvalid;
wire [63:0] udp_recv_data;
wire [63:0] udp_recv_data_con;
reg reg_rden_r = 'b0;
wire reg_rden_edge; // read data at rden fall edge
always@(posedge eth_userclk2)
begin
if((~udp_app_recv_fifo_empty) && udp_app_recv_fifo_ready)
begin
udp_app_recv_fifo_rden <= 1'b1;
end
else if(udp_app_recv_fifo_rdcnt == 12'b0)
begin
udp_app_recv_fifo_rden <= 1'b0;
end
// udp_app_recv_fifo_rden_r <= udp_app_recv_fifo_rden && (~udp_app_recv_fifo_empty);
end
assign udp_app_recv_fifo_rden_r = udp_app_recv_fifo_rden && (~udp_app_recv_fifo_empty); // udp recv data does not delay, so the en needn't delay
axis_dwidth_converter_2 axis_dwidth_converter_2_udprx(
.aclk (eth_userclk2), // input
.aresetn (~glb_reset), // input
.s_axis_tvalid(udp_app_recv_fifo_rden_r), // input
.s_axis_tready(udp_app_recv_fifo_ready), // output
.s_axis_tdata (udp_app_recv_fifo_rddata), // input [7:0]
.m_axis_tvalid(udp_recv_data_tvalid), // output
.m_axis_tready(1'b1), // input
.m_axis_tdata (udp_recv_data) // output [63:0]
);
assign udp_recv_data_con = {udp_recv_data[7:0], udp_recv_data[15:8], udp_recv_data[23:16], udp_recv_data[31:24], udp_recv_data[39:32], udp_recv_data[47:40], udp_recv_data[55:48], udp_recv_data[63:56]};
// write/read TOE reg by UDP
always@(posedge eth_userclk2)
begin
if(glb_reset)
begin
reg_wren <= 1'b0;
reg_rden <= 1'b0;
reg_addr <= 32'b0;
reg_wrdata <= 32'b0;
end
else if(udp_recv_data_tvalid && (udp_recv_data_con[63:56]==8'h1E))
begin
reg_wren <= ~udp_recv_data_con[48];
reg_rden <= udp_recv_data_con[48];
reg_addr <= {16'b0, udp_recv_data_con[47:32]};
reg_wrdata <= udp_recv_data_con[31:0];
end
else
begin
reg_wren <= 1'b0;
reg_rden <= 1'b0;
end
end
always @ (posedge eth_userclk2)
reg_rden_r <= reg_rden; // the latency between rden and read back data is 1 clk
// UDP TX
reg [63 : 0] udp_send_data;
reg udp_send_data_tvalid;
wire udp_send_data_tready;
wire [7 : 0] udp_send_data_8b;
wire udp_send_data_tvalid_8b;
wire udp_send_data_fifo_full;
reg [3:0] udp_send_state = 'b0;
always@(posedge eth_userclk2)
if(glb_reset)
begin
udp_send_data_tvalid <= 1'b0;
udp_send_data <= 64'b0;
udp_send_state <= 'b0;
end
else
case(udp_send_state)
0: begin
udp_send_data_tvalid <= 1'b0;
udp_send_data <= 64'b0;
if(reg_rden_r)
begin
udp_send_data_tvalid <= 1'b1;
udp_send_data <= {8'h1E,8'h01,reg_addr[15:0],reg_rddata};
udp_send_state <= 4'd1;
end
else udp_send_state <= 4'd0;
end
1: begin
if(udp_send_data_tready)
begin
udp_send_data_tvalid <= 1'b0;
udp_send_state <= 4'd0;
end
else
begin
udp_send_data_tvalid <= 1'b1;
udp_send_state <= 4'd1;
end
end
default: udp_send_state <= 4'd0;
endcase
wire [63 : 0] udp_send_data_con;
assign udp_send_data_con = {udp_send_data[7:0], udp_send_data[15:8], udp_send_data[23:16], udp_send_data[31:24], udp_send_data[39:32], udp_send_data[47:40], udp_send_data[55:48], udp_send_data[63:56]};
axis_dwidth_converter_3 axis_dwidth_converter_3_udptx(
.aclk (eth_userclk2), // input
.aresetn (~glb_reset ), // input
.s_axis_tvalid(udp_send_data_tvalid), // input
.s_axis_tready(udp_send_data_tready), // output
.s_axis_tdata (udp_send_data_con), // input [63:0]
.m_axis_tvalid(udp_send_data_tvalid_8b), // output
.m_axis_tready(~udp_send_data_fifo_full), // input
.m_axis_tdata (udp_send_data_8b) // output [7:0]
);
fifo_generator_1 fifo_generator_1_udptx(
.clk (eth_userclk2), // input
.srst (glb_reset), // input
.din (udp_send_data_8b), // input [7:0]
.wr_en(udp_send_data_tvalid_8b & (~udp_send_data_fifo_full)), // input
.rd_en(udp_app_send_fifo_rden), // input
.dout (udp_app_send_fifo_rddata), // output [7:0]
.full (udp_send_data_fifo_full), // output
.prog_full(), // output wire prog_full
.empty(udp_app_send_fifo_empty), // output
.data_count(udp_app_send_fifo_rdcnt), // output [11:0]
.wr_rst_busy(),
.rd_rst_busy()
);
//****************************************************TCP RX/TX Start*********************************************************
//----------RX----------
wire TCP_RX_s_axis_tvalid ;
wire TCP_RX_s_axis_tready ;
wire [ 7: 0] TCP_RX_s_axis_tdata ;
wire TCP_RX_s_axis_tlast ;
wire [ 63: 0] DataNI ;
wire [ 7: 0] KeepNI ;
axis_dwidth_8bTo64b axis_dwidth_8bTo64b_TCP_RX (
.aclk (eth_userclk2 ),// input wire aclk
.aresetn (~glb_reset ),// input wire aresetn
.s_axis_tvalid (s0_user_rx_fifo_rden ),// input wire s_axis_tvalid
.s_axis_tready (TCP_RX_s_axis_tready ),// output wire s_axis_tready
.s_axis_tdata (s0_user_rx_fifo_rddata ),// input wire [7 : 0] s_axis_tdata
.s_axis_tkeep (s0_user_rx_fifo_rden ),// input wire [0 : 0] s_axis_tkeep
.s_axis_tlast (TCP_RX_s_axis_tlast ),// input wire s_axis_tlast
.m_axis_tvalid (NET_RX_m_axis_tvalid ),// output wire m_axis_tvalid
.m_axis_tready (NET_RX_m_axis_tready ),// input wire m_axis_tready
.m_axis_tdata ({DataNI[7:0],DataNI[15:8],DataNI[23:16],DataNI[31:24],DataNI[39:32],DataNI[47:40],DataNI[55:48],DataNI[63:56]}),// output wire [63 : 0] m_axis_tdata
.m_axis_tkeep ({KeepNI[0],KeepNI[1],KeepNI[2],KeepNI[3],KeepNI[4],KeepNI[5],KeepNI[6],KeepNI[7]}),// output wire [7 : 0] m_axis_tkeep
.m_axis_tlast (NET_RX_m_axis_tlast ) // output wire m_axis_tlast
);
assign NET_RX_m_axis_tdata = DataNI;
assign NET_RX_m_axis_tkeep = KeepNI;
assign TCP_RX_s_axis_tlast = ((clen_cnt == clen - 1'b1) && s0_user_rx_fifo_rden) ? 1'b1 : 1'b0; //本包最后一个数据
assign s0_user_rx_fifo_rden = (!s0_user_rx_fifo_empty) & TCP_RX_s_axis_tready;
//---转时钟域---
wire [ 63: 0] NET_RX_m_axis_tdata ;
wire [ 7: 0] NET_RX_m_axis_tkeep ;
wire NET_RX_m_axis_tlast ;
wire NET_RX_m_axis_tready ;
wire NET_RX_m_axis_tvalid ;
axis_data_fifo_TCP_RX axis_data_fifo_TCP_RX (
.s_axis_aresetn (~glb_reset ),// input wire s_axis_aresetn
.s_axis_aclk (eth_userclk2 ),// input wire s_axis_aclk
.s_axis_tvalid (NET_RX_m_axis_tvalid ),// input wire s_axis_tvalid
.s_axis_tready (NET_RX_m_axis_tready ),// output wire s_axis_tready
.s_axis_tdata (NET_RX_m_axis_tdata ),// input wire [63 : 0] s_axis_tdata
.s_axis_tkeep (NET_RX_m_axis_tkeep ),// input wire [7 : 0] s_axis_tkeep
.s_axis_tlast (NET_RX_m_axis_tlast ),// input wire s_axis_tlast
.m_axis_aclk (Clk_Sys300M ),// input wire m_axis_aclk
.m_axis_tvalid (o_NET_RX_m_axis_tvalid ),// output wire m_axis_tvalid
.m_axis_tready (i_NET_RX_m_axis_tready ),// input wire m_axis_tready
.m_axis_tdata (o_NET_RX_m_axis_tdata ),// output wire [63 : 0] m_axis_tdata
.m_axis_tkeep (o_NET_RX_m_axis_tkeep ),// output wire [7 : 0] m_axis_tkeep
.m_axis_tlast (o_NET_RX_m_axis_tlast ) // output wire m_axis_tlast
);
//----------TX----------
wire w64To8_m_axis_tvalid ;
wire w64To8_m_axis_tready ;
wire [ 7: 0] w64To8_m_axis_tdata ;
wire [ 0: 0] w64To8_m_axis_tkeep ;
wire w64To8_m_axis_tlast ;
axis_dwidth_64bTo8b axis_dwidth_64bTo8b_TCP_TX (
.aclk (Clk_Sys300M ),// input wire aclk
.aresetn (~glb_reset ),// input wire aresetn
.s_axis_tvalid (i_NET_TX_S_AXIS_tvalid ),// input wire s_axis_tvalid
.s_axis_tready (o_NET_TX_S_AXIS_tready ),// output wire s_axis_tready
.s_axis_tdata ({i_NET_TX_S_AXIS_tdata[7:0],i_NET_TX_S_AXIS_tdata[15:8],i_NET_TX_S_AXIS_tdata[23:16],i_NET_TX_S_AXIS_tdata[31:24],i_NET_TX_S_AXIS_tdata[39:32],i_NET_TX_S_AXIS_tdata[47:40],i_NET_TX_S_AXIS_tdata[55:48],i_NET_TX_S_AXIS_tdata[63:56]}),// input wire [63 : 0] s_axis_tdata
.s_axis_tkeep ({i_NET_TX_S_AXIS_tkeep[0],i_NET_TX_S_AXIS_tkeep[1],i_NET_TX_S_AXIS_tkeep[2],i_NET_TX_S_AXIS_tkeep[3],i_NET_TX_S_AXIS_tkeep[4],i_NET_TX_S_AXIS_tkeep[5],i_NET_TX_S_AXIS_tkeep[6],i_NET_TX_S_AXIS_tkeep[7]}),// input wire [7 : 0] s_axis_tkeep
.s_axis_tlast (i_NET_TX_S_AXIS_tlast ),// input wire s_axis_tlast
.m_axis_tvalid (w64To8_m_axis_tvalid ),// output wire m_axis_tvalid
.m_axis_tready (w64To8_m_axis_tready ),// input wire m_axis_tready
.m_axis_tdata (w64To8_m_axis_tdata ),// output wire [7 : 0] m_axis_tdata
.m_axis_tkeep (w64To8_m_axis_tkeep ),// output wire [0 : 0] m_axis_tkeep
.m_axis_tlast (w64To8_m_axis_tlast ) // output wire m_axis_tlast
);
wire TCP_TX_prog_full ;
wire fifo_TCP_TX_wr_en ;
assign w64To8_m_axis_tready = ~TCP_TX_prog_full ;
assign fifo_TCP_TX_wr_en = w64To8_m_axis_tvalid & w64To8_m_axis_tready & w64To8_m_axis_tkeep;
fifo_generator_TCP_TX fifo_generator_TCP_TX_i (
.rst (glb_reset ),// input wire rst
.wr_clk (Clk_Sys300M ),// input wire wr_clk
.din (w64To8_m_axis_tdata ),// input wire [7 : 0] din
.wr_en (fifo_TCP_TX_wr_en ),// input wire wr_en
.rd_clk (s0_user_tx_fifo_rdclk ),// input wire rd_clk
.rd_en (s0_user_tx_fifo_rden ),// input wire rd_en
.dout (s0_user_tx_fifo_rddata ),// output wire [7 : 0] dout
.rd_data_count (s0_user_tx_fifo_rdcnt ),// output wire [11 : 0] rd_data_count
.full ( ),// output wire full
.empty (empty ),// output wire empty
.prog_full (TCP_TX_prog_full ) // output wire prog_full
);
//*******************************************************TCP RX/TX END*******************************************************
// TCP rx deal
reg [3:0] tcp_rx_state = 'b0;
reg [4:0] CID = 'b0;
reg [24:0] caddr = 'b0;
reg [11:0] cexaddr = 'b0;
reg [19:0] clen = 'b0;
reg c_wor = 'b0;
reg [19:0] clen_cnt = 'b0;
reg [63:0] trans_header= 'b0;
reg trans_header_vld = 'b0;
reg ram_ena = 'b0;
reg ram_wea = 'b0;
reg [13:0] ram_addra = 'b0;
reg [7:0] ram_dina = 'b0;
reg [13:0] ram_addrb = 'b0;
reg ram_enb = 'b0;
wire [7:0] ram_doutb;
always @ (posedge eth_userclk2)
if(glb_reset)
begin
tcp_rx_state <= 'b0;
CID <= 'b0;
caddr <= 'b0;
cexaddr <= 'b0;
clen <= 'b0;
c_wor <= 'b0;
trans_header <= 'b0;
trans_header_vld<= 'b0;
ram_ena <= 'b0;
ram_wea <= 'b0;
end
else
case(tcp_rx_state)
0: begin
trans_header_vld<= 'b0;
ram_ena <= 'b0;
ram_wea <= 'b0;
if(eth_linked && s0_user_rx_fifo_rden)
begin
tcp_rx_state <= 4'd1;
c_wor <= s0_user_rx_fifo_rddata[7];
CID <= s0_user_rx_fifo_rddata[5:1];
caddr[24] <= s0_user_rx_fifo_rddata[0];
end
else begin
tcp_rx_state <= 4'd0;
end
end
1: begin
trans_header_vld <= 1'b0;
ram_ena <= 'b0;
ram_wea <= 'b0;
if(s0_user_rx_fifo_rden)
begin
tcp_rx_state <= 4'd2;
caddr[23:16] <= s0_user_rx_fifo_rddata;
end
else tcp_rx_state <= 4'd1;
end
2: begin
if(s0_user_rx_fifo_rden)
begin
tcp_rx_state <= 4'd3;
caddr[15:8] <= s0_user_rx_fifo_rddata;
end
else tcp_rx_state <= 4'd2;
end
3: begin
if(s0_user_rx_fifo_rden)
begin
tcp_rx_state <= 4'd4;
caddr[7:0] <= s0_user_rx_fifo_rddata;
end
else tcp_rx_state <= 4'd3;
end
4: begin
if(s0_user_rx_fifo_rden)
begin
tcp_rx_state <= 4'd5;
cexaddr[11:4] <= s0_user_rx_fifo_rddata;
end
else tcp_rx_state <= 4'd4;
end
5: begin
if(s0_user_rx_fifo_rden)
begin
tcp_rx_state <= 4'd6;
cexaddr[3:0] <= s0_user_rx_fifo_rddata[7:4];
clen[19:16] <= s0_user_rx_fifo_rddata[3:0];
end
else tcp_rx_state <= 4'd5;
end
6: begin
if(s0_user_rx_fifo_rden)
begin
tcp_rx_state <= 4'd7;
clen[15:8] <= s0_user_rx_fifo_rddata;
end
else tcp_rx_state <= 4'd6;
end
7: begin
clen_cnt <= 'b0;
if(s0_user_rx_fifo_rden)
begin
clen[7:0] <= s0_user_rx_fifo_rddata;
if(c_wor) tcp_rx_state <= 4'd9;
else tcp_rx_state <= 4'd8;
end
else tcp_rx_state <= 4'd7;
end
8: begin // write ram
ram_ena <= 1'b0;
ram_wea <= 1'b0;
if(clen_cnt < clen)
begin
if(s0_user_rx_fifo_rden)
begin
ram_ena <= 1'b1;
ram_wea <= 1'b1;
ram_dina <= s0_user_rx_fifo_rddata;
ram_addra <= caddr[13:0] + clen_cnt;
clen_cnt <= clen_cnt + 1'b1;
end
tcp_rx_state <= 4'd8;
end
else if(eth_linked && s0_user_rx_fifo_rden)
begin
tcp_rx_state <= 4'd1;
c_wor <= s0_user_rx_fifo_rddata[7];
CID <= s0_user_rx_fifo_rddata[5:1];
caddr[24] <= s0_user_rx_fifo_rddata[0];
end
else
begin
tcp_rx_state <= 4'd0;
end
end
9: begin
trans_header <= {c_wor,1'b0,CID,caddr,cexaddr,clen};
trans_header_vld<= 1'b1;
if(eth_linked && s0_user_rx_fifo_rden)
begin
tcp_rx_state <= 4'd1;
c_wor <= s0_user_rx_fifo_rddata[7];
CID <= s0_user_rx_fifo_rddata[5:1];
caddr[24] <= s0_user_rx_fifo_rddata[0];
end
else tcp_rx_state <= 4'd0;
end
default: tcp_rx_state <= 4'd0;
endcase
wire fifo_header_full,fifo_header_empty,fifo_header_wr_rst_busy,fifo_header_rd_rst_busy;
wire [63:0] fifo_header_dout;
reg fifo_header_rden = 'b0;
fifo_header fifo_trans_header_inst (
.clk(eth_userclk2), // input wire clk
.srst(glb_reset), // input wire srst
.din(trans_header), // input wire [63 : 0] din
.wr_en(trans_header_vld), // input wire wr_en
.rd_en(fifo_header_rden), // input wire rd_en
.dout(fifo_header_dout), // output wire [63 : 0] dout
.full(fifo_header_full), // output wire full
.empty(fifo_header_empty), // output wire empty
.wr_rst_busy(fifo_header_wr_rst_busy), // output wire wr_rst_busy
.rd_rst_busy(fifo_header_rd_rst_busy) // output wire rd_rst_busy
);
reg [3:0] ram_rd_state = 'b0;
reg [13:0] ram_rd_len = 'b0;
reg [13:0] ram_rd_cnt = 'b0;
reg [13:0] ram_rd_addr = 'b0;
reg [7:0] tcp_send_data_8b = 'b0;
reg tcp_send_data_tvalid_8b = 'b0;
wire s0_user_tx_data_fifo_full,s0_user_tx_fifo_empty;
always @ (posedge eth_userclk2)
if(glb_reset)
begin
fifo_header_rden <= 'b0;
ram_rd_state <= 'b0;
ram_rd_len <= 'b0;
ram_rd_cnt <= 'b0;
tcp_send_data_8b <= 'b0;
tcp_send_data_tvalid_8b <= 'b0;
ram_enb <= 'b0;
end
else
case(ram_rd_state)
0: begin
ram_rd_len <= 'b0;
ram_rd_cnt <= 'b0;
tcp_send_data_tvalid_8b <= 'b0;
ram_enb <= 'b0;
if(!fifo_header_empty)
begin
fifo_header_rden <= 1'b1;
ram_rd_state <= 4'd1;
end
else
begin
fifo_header_rden <= 1'b0;
ram_rd_state <= 4'd0;
end
end
1: begin
fifo_header_rden <= 1'b0;
ram_rd_cnt <= 'b0;
ram_rd_len <= fifo_header_dout[13:0];
ram_rd_addr <= fifo_header_dout[45:32];
ram_rd_state <= 4'd2;
end
2: begin
if(!s0_user_tx_data_fifo_full)
begin
tcp_send_data_8b <= fifo_header_dout[63:56];
tcp_send_data_tvalid_8b <= 1'b1;
ram_rd_state <= 4'd3;
end
else
begin
tcp_send_data_tvalid_8b <= 1'b0;
ram_rd_state <= 4'd2;
end
end
3: begin
if(!s0_user_tx_data_fifo_full)
begin
tcp_send_data_8b <= fifo_header_dout[55:48];
tcp_send_data_tvalid_8b <= 1'b1;
ram_rd_state <= 4'd4;
end
else
begin
tcp_send_data_tvalid_8b <= 1'b0;
ram_rd_state <= 4'd3;
end
end
4: begin
if(!s0_user_tx_data_fifo_full)
begin
tcp_send_data_8b <= fifo_header_dout[47:40];
tcp_send_data_tvalid_8b <= 1'b1;
ram_rd_state <= 4'd5;
end
else
begin
tcp_send_data_tvalid_8b <= 1'b0;
ram_rd_state <= 4'd4;
end
end
5: begin
if(!s0_user_tx_data_fifo_full)
begin
tcp_send_data_8b <= fifo_header_dout[39:32];
tcp_send_data_tvalid_8b <= 1'b1;
ram_rd_state <= 4'd6;
end
else
begin
tcp_send_data_tvalid_8b <= 1'b0;
ram_rd_state <= 4'd5;
end
end
6: begin
if(!s0_user_tx_data_fifo_full)
begin
tcp_send_data_8b <= fifo_header_dout[31:24];
tcp_send_data_tvalid_8b <= 1'b1;
ram_rd_state <= 4'd7;
end
else
begin
tcp_send_data_tvalid_8b <= 1'b0;
ram_rd_state <= 4'd6;
end
end
7: begin
if(!s0_user_tx_data_fifo_full)
begin
tcp_send_data_8b <= fifo_header_dout[23:16];
tcp_send_data_tvalid_8b <= 1'b1;
ram_rd_state <= 4'd8;
end
else
begin
tcp_send_data_tvalid_8b <= 1'b0;
ram_rd_state <= 4'd7;
end
end
8: begin
if(!s0_user_tx_data_fifo_full)
begin
tcp_send_data_8b <= fifo_header_dout[15:8];
tcp_send_data_tvalid_8b <= 1'b1;
ram_rd_state <= 4'd9;
end
else
begin
tcp_send_data_tvalid_8b <= 1'b0;
ram_rd_state <= 4'd8;
end
end
9: begin
if(!s0_user_tx_data_fifo_full)
begin
tcp_send_data_8b <= fifo_header_dout[7:0];
tcp_send_data_tvalid_8b <= 1'b1;
ram_rd_state <= 4'd10;
end
else
begin
tcp_send_data_tvalid_8b <= 1'b0;
ram_rd_state <= 4'd9;
end
end
10: begin
tcp_send_data_tvalid_8b <= 'b0;
ram_enb <= 'b0;
if(ram_rd_cnt < ram_rd_len)
if(!s0_user_tx_data_fifo_full)
begin
ram_enb <= 1'b1;
ram_addrb <= ram_rd_addr + ram_rd_cnt;
ram_rd_cnt <= ram_rd_cnt + 1'b1;
ram_rd_state <= 4'd10;
end
else
begin
ram_enb <= 1'b0;
ram_rd_state <= 4'd10;
end
else
begin
ram_enb <= 1'b0;
ram_rd_state <= 4'd0;
end
end
default: ram_rd_state <= 4'd0;
endcase
reg ram_enb_r1 = 'b0;
reg ram_enb_r2 = 'b0;
wire ram_enb_w = ram_enb || ram_enb_r1;
reg [13:0] ram_addrb_r1,ram_addrb_r2;
wire [13:0] ram_addrb_add = ram_addrb_r1 - ram_addrb_r2;
always @ (posedge eth_userclk2)
begin
ram_enb_r1 <= ram_enb;
ram_enb_r2 <= ram_enb_r1;
ram_addrb_r1<= ram_addrb;
ram_addrb_r2<= ram_addrb_r1;
end
// blk_mem_gen_0 trans_ram_inst (
// .clka(eth_userclk2), // input wire clka
// .ena(ram_ena), // input wire ena
// .wea(ram_wea), // input wire [0 : 0] wea
// .addra(ram_addra), // input wire [13 : 0] addra
// .dina(ram_dina), // input wire [7 : 0] dina
// .clkb(eth_userclk2), // input wire clkb
// .enb(ram_enb_w), // input wire enb
// .addrb(ram_addrb), // input wire [13 : 0] addrb
// .doutb(ram_doutb) // output wire [7 : 0] doutb
// );
reg tcp_tx_wren = 'b0;
reg [7:0] txp_tx_data = 'b0;
wire tcp_tx_fifo_full;
always @ (posedge eth_userclk2)
if(glb_reset)
begin
tcp_tx_wren <= 'b0;
txp_tx_data <= 'b0;
end
else if(tcp_send_data_tvalid_8b)
begin
tcp_tx_wren <= 1'b1;
txp_tx_data <= tcp_send_data_8b;
end
else if(ram_enb_r2)
begin
tcp_tx_wren <= 1'b1;
txp_tx_data <= ram_doutb;
end
else
begin
tcp_tx_wren <= 'b0;
end
ila_tcp_125M ila_tcp_125M_i (
.clk(eth_userclk2), // input wire clk
.probe0({
NET_RX_m_axis_tdata ,
NET_RX_m_axis_tkeep ,
NET_RX_m_axis_tlast ,
NET_RX_m_axis_tready ,
NET_RX_m_axis_tvalid ,
s0_user_rx_fifo_rden ,
TCP_RX_s_axis_tready ,
s0_user_rx_fifo_rddata ,
TCP_RX_s_axis_tlast ,
clen_cnt,
clen,
tcp_rx_state,
inband_link_status,
eth_linked,
ETH_RST_n
}) // input wire [95:0] probe0
);
endmodule

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@ -0,0 +1,542 @@
/////////////////////////////////////////////////////////////
//Engineer : Xiaodng Zhong
//Date : 2019.7.17
//Description:arp表项的管理
/************************************************************
//表项8个
// ----------------------------------------------------
//| state | ip | mac | time | try_number |
// ----------------------------------------------------
//| 2'b00:empty | 32 | 48 | 32 | |
//| 2'b01:wait_rslv | | | (ms) | |
//| 2'b10:rslvd | | | | |
// ----------------------------------------------------
//静态表项4个
//功能:(1)表项添加防止重复,(2)表项查询
// (3)生存时间到,解析请求(3)wait_rslv->rslvd上报
(4)wait_rslvd:time-out,
尝试解析3次隔1ms,2ms,4ms,失败上报->empty
//到时间直接删除不应该再主动解析
************************************************************/
/////////////////////////////////////////////////////////////
module arp_cache(
input clk,
input rst,
input [31:0] live_time,
input [3:0] retry_time,
input [80:0] static_table0, //type:valid(1)+ip+mac
input [80:0] static_table1,
input [80:0] static_table2,
input [80:0] static_table3,
output reg error,
input arp_addlook_req, //添加查询
output reg arp_addlook_grant,
input [80:0] arp_addlook_ipmac, //type:add(0),look(1)+ip(32)+mac(48)
output reg [48:0] arp_look_rslt, //type:found(1),notfound(0)+mac(48)
output reg arp_rslv_report_req, //解析上报
input arp_rslv_report_grant,
output reg [81:0] arp_rslv_ip //type:(1):resolve(0),report(1)+(2):found(1),not(0)+ip+mac
);
/////////////////////////////////////////////
//ms timer
/////////////////////////////////////////////
localparam ms=17'd125000;
reg [16:0] ms_cnt;
reg ms_en;
always@(posedge clk or posedge rst)begin
if(rst)begin
ms_cnt <=0;
ms_en <=0;
end
else if(ms_cnt==(ms-1))begin
ms_cnt <=0;
ms_en <=1;
end
else begin
ms_cnt <=ms_cnt+1;
ms_en <=0;
end
end
/////////////////////////////////////////////
//table
/////////////////////////////////////////////
//-------------------------------------------
//表项维护逻辑
localparam idle = 4'd0,
arp_add = 4'd1,
arp_look_p1 = 4'd2,
arp_look_p2 = 4'd3,
arp_rslv = 4'd4,
arp_report = 4'd5,
check_retry = 4'd6,
check_tryout = 4'd7,
check_liveout = 4'd8;
localparam t_null = 2'b00,
t_wait = 2'b01,
t_rslvd = 2'b10;
reg [3:0] state;
reg [3:0] i;
reg [1:0] table_state [0:7];
reg [79:0] dynamic_table[0:7];
reg [3:0] try_number [0:7];
wire [31:0] timer [0:7];
wire [7:0] retry;
wire [7:0] try_out;
wire [7:0] live_out;
reg [31:0] ip_reg;
reg [47:0] mac_reg;
wire [7:0] ena;
wire [7:0] hold;
reg [7:0] clr;
wire [7:0] ena_ms;
//-------------------------------------------
//计数器
genvar j;
generate
for(j=0;j<8;j=j+1) begin:timer_loop
assign ena_ms[j] = ena[j] & ms_en;
counter #(.q_width(32))counter_i(
.clk (clk ),
.rst (rst ),
.clr (clr[j] ),
.ena (ena_ms[j] ),
.hold (hold[j] ),
.q (timer[j] )
);
assign ena[j] = table_state[j]!=t_null;
assign hold[j] = (table_state[j]==t_wait) ? timer[j]==(32'd1000<<try_number[j]):
(table_state[j]==t_rslvd) ? (timer[j]==live_time) : 0;
end
endgenerate
//
//重新询问
//
genvar loop_retry;
generate
for(loop_retry=0;loop_retry<8;loop_retry=loop_retry+1)begin:loop_retry_inst
assign retry[loop_retry] = table_state[loop_retry]==t_wait && timer[loop_retry]==(32'd1000<<try_number[loop_retry]);
end
endgenerate
//
//尝试3次
//
genvar try_loop;
generate
for(try_loop=0;try_loop<8;try_loop=try_loop+1)begin:try_loop_inst
assign try_out[try_loop] = (table_state[try_loop]==t_wait) && (try_number[try_loop]==retry_time);
end
endgenerate
//
//生存时间到了
//
genvar loop_live;
generate
for(loop_live=0;loop_live<8;loop_live=loop_live+1)begin:loop_live_inst
assign live_out[loop_live] = table_state[loop_live]==t_rslvd && timer[loop_live]==(live_time-1);
end
endgenerate
always@(posedge clk or posedge rst)begin
if(rst)begin
table_state[0] <=0;
table_state[1] <=0;
table_state[2] <=0;
table_state[3] <=0;
table_state[4] <=0;
table_state[5] <=0;
table_state[6] <=0;
table_state[7] <=0;
dynamic_table[0] <=0;
dynamic_table[1] <=0;
dynamic_table[2] <=0;
dynamic_table[3] <=0;
dynamic_table[4] <=0;
dynamic_table[5] <=0;
dynamic_table[6] <=0;
dynamic_table[7] <=0;
try_number[0] <=0;
try_number[1] <=0;
try_number[2] <=0;
try_number[3] <=0;
try_number[4] <=0;
try_number[5] <=0;
try_number[6] <=0;
try_number[7] <=0;
i <=0;
state <=0;
clr <=0;
error <=0;
arp_addlook_grant <=0;
arp_look_rslt <=0;
arp_rslv_ip<=0;
arp_rslv_report_req <=0;
ip_reg <=0;
mac_reg <=0;
end
else begin
case(state)
idle:begin //更新时间到了尝试次数到了生存时间到了添加/查询上报成功或失败
arp_addlook_grant <=0;
if(arp_addlook_req && arp_addlook_ipmac[80]==1'b0)begin //add
arp_addlook_grant <=1;
ip_reg <=arp_addlook_ipmac[79:48];
mac_reg <=arp_addlook_ipmac[47:0];
state <=arp_add;
end
else if(arp_addlook_req && arp_addlook_ipmac[80]==1'b1)begin //look
ip_reg <=arp_addlook_ipmac[79:48];
mac_reg <=arp_addlook_ipmac[47:0];
state <=arp_look_p1;
end
else if(retry!=8'h00)begin
state <=check_retry;
end
else if(try_out!=8'h00)begin
state <=check_tryout;
end
else if(live_out!=8'h00)begin
state <=check_liveout;
end
end
arp_add:begin
arp_addlook_grant <=0;
if(i==8)begin
i <=0;
state <=idle;
end
else if(table_state[i[2:0]]==t_wait && dynamic_table[i[2:0]][79:48]==ip_reg)begin
i <=0;
state <=arp_report;
dynamic_table[i[2:0]][47:0] <=mac_reg;
table_state[i[2:0]] <=t_rslvd;
arp_rslv_ip <={1'b1,1'b1,ip_reg,mac_reg};
end
else begin
i <=i+1;
end
end
arp_report:begin
if(i==0)begin
arp_rslv_report_req <=1'b1;
i <=1;
end
else if(i==1)begin
if(arp_rslv_report_grant)begin
i <=0;
arp_rslv_report_req <=1'b0;
if(arp_rslv_ip[80]==1'b1)begin
state <=idle;
end
else begin
state <=check_tryout;
end
end
else begin
i <=i;
state <=arp_report;
end
end
end
arp_look_p1:begin //查找有无该表项,要求t_valid
arp_addlook_grant <=1;
if(table_state[0]==t_rslvd && ip_reg==dynamic_table[0][79:48])begin
state <=idle;
arp_look_rslt <={1'b1,dynamic_table[0][47:0]};
end
else if(table_state[1]==t_rslvd && ip_reg==dynamic_table[1][79:48])begin
state <=idle;
arp_look_rslt <={1'b1,dynamic_table[1][47:0]};
end
else if(table_state[2]==t_rslvd && ip_reg==dynamic_table[2][79:48])begin
state <=idle;
arp_look_rslt <={1'b1,dynamic_table[2][47:0]};
end
else if(table_state[3]==t_rslvd && ip_reg==dynamic_table[3][79:48])begin
state <=idle;
arp_look_rslt <={1'b1,dynamic_table[3][47:0]};
end
else if(table_state[4]==t_rslvd && ip_reg==dynamic_table[4][79:48])begin
state <=idle;
arp_look_rslt <={1'b1,dynamic_table[4][47:0]};
end
else if(table_state[5]==t_rslvd && ip_reg==dynamic_table[5][79:48])begin
state <=idle;
arp_look_rslt <={1'b1,dynamic_table[5][47:0]};
end
else if(table_state[6]==t_rslvd && ip_reg==dynamic_table[6][79:48])begin
state <=idle;
arp_look_rslt <={1'b1,dynamic_table[1][47:0]};
end
else if(table_state[7]==t_rslvd && ip_reg==dynamic_table[7][79:48])begin
state <=idle;
arp_look_rslt <={1'b1,dynamic_table[7][47:0]};
end
else if(static_table0[80]==1'b1 && ip_reg==static_table0[79:48])begin
state <=idle;
arp_look_rslt <={1'b1,static_table0[47:0]};
end
else if(static_table1[80]==1'b1 && ip_reg==static_table1[79:48])begin
state <=idle;
arp_look_rslt <={1'b1,static_table1[47:0]};
end
else if(static_table2[80]==1'b1 && ip_reg==static_table2[79:48])begin
state <=idle;
arp_look_rslt <={1'b1,static_table2[47:0]};
end
else if(static_table3[80]==1'b1 && ip_reg==static_table3[79:48])begin
state <=idle;
arp_look_rslt <={1'b1,static_table3[47:0]};
end
else begin
state <=arp_look_p2;
arp_look_rslt <={1'b0,48'h0};
end
end
arp_look_p2:begin //如果没有添加表项t_null->t_wait
arp_addlook_grant <=0;
if(i==8)begin
i <=0;
state <=idle;
error <=1;
end
else if(table_state[i[2:0]]==t_null)begin
i <=0;
table_state[i[2:0]] <=t_wait;
dynamic_table[i[2:0]][79:48] <=ip_reg;
state <=idle;
end
else begin
i <=i+1;
end
end
arp_rslv:begin
if(i==0)begin
arp_rslv_report_req <=1;
i <=1;
end
else if(i==1)begin
if(arp_rslv_report_grant)begin
i <=0;
arp_rslv_report_req <=0;
state <=check_retry;
end
else begin
i <=i;
state <=arp_rslv;
end
end
end
check_retry:begin //1ms2ms,4ms
if(retry==8'h00)begin
clr <=8'h00;
state <=idle;
end
else if(retry[0])begin
clr[0] <=1;
try_number[0] <=try_number[0]+1;
arp_rslv_ip <={1'b0,1'b0,dynamic_table[0][79:48],48'h0};
state <=try_number[0] ==(retry_time-1) ? idle: arp_rslv;
end
else if(retry[1])begin
clr[1] <=1;
try_number[1] <=try_number[1]+1;
arp_rslv_ip <={1'b0,1'b0,dynamic_table[1][79:48],48'h0};
state <=try_number[1] ==(retry_time-1) ? idle: arp_rslv;
end
else if(retry[2])begin
clr[2] <=1;
try_number[2] <=try_number[2]+1;
arp_rslv_ip <={1'b0,1'b0,dynamic_table[2][79:48],48'h0};
state <=try_number[2] ==(retry_time-1) ? idle: arp_rslv;
end
else if(retry[3])begin
clr[3] <=1;
try_number[3] <=try_number[3]+1;
arp_rslv_ip <={1'b0,1'b0,dynamic_table[3][79:48],48'h0};
state <=try_number[3] ==(retry_time-1) ? idle: arp_rslv;
end
else if(retry[4])begin
clr[4] <=1;
try_number[4] <=try_number[4]+1;
arp_rslv_ip <={1'b0,1'b0,dynamic_table[4][79:48],48'h0};
state <=try_number[4] ==(retry_time-1) ? idle: arp_rslv;
end
else if(retry[5])begin
clr[5] <=1;
try_number[5] <=try_number[5]+1;
arp_rslv_ip <={1'b0,1'b0,dynamic_table[5][79:48],48'h0};
state <=try_number[5] ==(retry_time-1) ? idle: arp_rslv;
end
else if(retry[6])begin
clr[6] <=1;
try_number[6] <=try_number[6]+1;
arp_rslv_ip <={1'b0,1'b0,dynamic_table[6][79:48],48'h0};
state <=try_number[6] ==(retry_time-1) ? idle: arp_rslv;
end
else if(retry[7])begin
clr[7] <=1;
try_number[7] <=try_number[7]+1;
arp_rslv_ip <={1'b0,1'b0,dynamic_table[7][79:48],48'h0};
state <=try_number[7] ==(retry_time-1) ? idle: arp_rslv;
end
end
check_tryout:begin
if(try_out==8'h00)begin
state <=idle;
clr <=8'h00;
end
else if(try_out[0])begin
error <=1;
clr[0] <=1;
try_number[0] <=0;
state <=arp_report;
table_state[0] <=t_null;
arp_rslv_ip <={1'b1,1'b0,dynamic_table[0][79:48],48'h0};
end
else if(try_out[1])begin
error <=1;
clr[1] <=1;
try_number[1] <=0;
table_state[1] <=t_null;
state <=arp_report;
arp_rslv_ip <={1'b1,1'b0,dynamic_table[1][79:48],48'h0};
end
else if(try_out[2])begin
error <=1;
clr[2] <=1;
try_number[2] <=0;
table_state[2] <=t_null;
state <=arp_report;
arp_rslv_ip <={1'b1,1'b0,dynamic_table[2][79:48],48'h0};
end
else if(try_out[3])begin
error <=1;
clr[3] <=1;
try_number[3] <=0;
table_state[3] <=t_null;
state <=arp_report;
arp_rslv_ip <={1'b1,1'b0,dynamic_table[3][79:48],48'h0};
end
else if(try_out[4])begin
error <=1;
clr[4] <=1;
try_number[4] <=0;
table_state[4] <=t_null;
state <=arp_report;
arp_rslv_ip <={1'b1,1'b0,dynamic_table[4][79:48],48'h0};
end
else if(try_out[5])begin
error <=1;
clr[5] <=1;
try_number[5] <=0;
table_state[5] <=t_null;
state <=arp_report;
arp_rslv_ip <={1'b1,1'b0,dynamic_table[5][79:48],48'h0};
end
else if(try_out[6])begin
error <=1;
clr[6] <=1;
try_number[6] <=0;
table_state[6] <=t_null;
state <=arp_report;
arp_rslv_ip <={1'b1,1'b0,dynamic_table[6][79:48],48'h0};
end
else if(try_out[7])begin
error <=1;
clr[7] <=1;
try_number[7] <=0;
table_state[7] <=t_null;
state <=arp_report;
arp_rslv_ip <={1'b1,1'b0,dynamic_table[0][79:48],48'h0};
end
end
check_liveout:begin
if(live_out==8'h00)begin
clr <=8'h00;
state <=idle;
end
else if(live_out[0])begin
clr[0] <=1;
table_state[0] <=t_null;
end
else if(live_out[1])begin
clr[1] <=1;
table_state[1] <=t_null;
end
else if(live_out[2])begin
clr[2] <=1;
table_state[2] <=t_null;
end
else if(live_out[3])begin
clr[3] <=1;
table_state[3] <=t_null;
end
else if(live_out[4])begin
clr[4] <=1;
table_state[4] <=t_null;
end
else if(live_out[5])begin
clr[5] <=1;
table_state[5] <=t_null;
end
else if(live_out[6])begin
clr[6] <=1;
table_state[6] <=t_null;
end
else if(live_out[7])begin
clr[7] <=1;
table_state[7] <=t_null;
end
end
default:begin
state <=idle;
end
endcase
end
end
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: USTC
// Engineer: Xiaodong Zhong
//
// Create Date: 2019/07/17 20:02:11
// Design Name:
// Module Name: arp_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description: arp层包含arp事务处理arp高速缓存8个动态表项4个静态表项
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module arp_manage_top(
input clk,
input rst,
input [3:0] retry_time,
input [31:0] live_time,
input [80:0] static_table0,
input [80:0] static_table1,
input [80:0] static_table2,
input [80:0] static_table3,
output error,
input arp_recv_fifo_empty,
output arp_recv_fifo_rden,
input [81:0] arp_recv_fifo_rddata,
input arp_send_fifo_af,
output arp_send_fifo_wren,
output [80:0] arp_send_fifo_wrdata,
input ip_rslv_req,
output ip_rslv_grant,
input [31:0] ip_rslv_ip,
output ip_rslvd_req,
input ip_rslvd_grant,
output [80:0] ip_rslvd_ipmac,
input want_arp
);
//////////////////////////////////////////////
//reg & wire
//////////////////////////////////////////////
wire arp_addlook_req;
wire arp_addlook_grant;
wire [80:0] arp_addlook_ipmac;
wire [48:0] arp_look_rslt;
wire arp_rslv_report_req;
wire arp_rslv_report_grant;
wire [81:0] arp_rslv_ip;
////////////////////////////////////////////////////////
//arp cache
////////////////////////////////////////////////////////
arp_cache U_arp_cache(
.clk (clk ),
.rst (rst ),
.retry_time (retry_time ),
.live_time (live_time ),
.static_table0 (static_table0 ),
.static_table1 (static_table1 ),
.static_table2 (static_table2 ),
.static_table3 (static_table3 ),
.error (error ),
.arp_addlook_req (arp_addlook_req ),
.arp_addlook_grant (arp_addlook_grant ),
.arp_addlook_ipmac (arp_addlook_ipmac ),
.arp_look_rslt (arp_look_rslt ),
.arp_rslv_report_req (arp_rslv_report_req ),
.arp_rslv_report_grant (arp_rslv_report_grant ),
.arp_rslv_ip (arp_rslv_ip )
);
/////////////////////////////////////////////////////////
//arp processor
/////////////////////////////////////////////////////////
arp_processor U_arp_processor(
.clk (clk ),
.rst (rst ),
.arp_recv_fifo_empty (arp_recv_fifo_empty ),
.arp_recv_fifo_rden (arp_recv_fifo_rden ),
.arp_recv_fifo_rddata (arp_recv_fifo_rddata ),
.arp_send_fifo_af (arp_send_fifo_af ),
.arp_send_fifo_wren (arp_send_fifo_wren ),
.arp_send_fifo_wrdata (arp_send_fifo_wrdata ),
.ip_rslv_req (ip_rslv_req ),
.ip_rslv_grant (ip_rslv_grant ),
.ip_rslv_ip (ip_rslv_ip ),
.ip_rslvd_req (ip_rslvd_req ),
.ip_rslvd_grant (ip_rslvd_grant ),
.ip_rslvd_ipmac (ip_rslvd_ipmac ),
.want_arp (want_arp ),
.arp_addlook_req (arp_addlook_req ),
.arp_addlook_grant (arp_addlook_grant ),
.arp_addlook_ipmac (arp_addlook_ipmac ),
.arp_look_rslt (arp_look_rslt ),
.arp_rslv_report_req (arp_rslv_report_req ),
.arp_rslv_report_grant (arp_rslv_report_grant ),
.arp_rslv_ip (arp_rslv_ip )
);
endmodule

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///////////////////////////////////////////1////////////////
//Engineer : Xiaodong Zhong
//Date : 2019.7.16
//Description: arp事务处理
/**********************************************************
//a接收IP层的IP解析请求
//barp_recv的请求?回夿
//carp_send的请求?回夿
//darp_cache的表项添势
//earp的解析请汿
**********************************************************/
///////////////////////////////////////////////////////////
module arp_processor(
input clk,
input rst,
input arp_recv_fifo_empty,
output reg arp_recv_fifo_rden,
input [81:0] arp_recv_fifo_rddata, //type(1):0请求_1回复dst_ip:_0不是_1本地 src_ip(32),src_mac(48)
input arp_send_fifo_af,
output reg arp_send_fifo_wren,
output reg [80:0] arp_send_fifo_wrdata, //type(1):0请求_1回复dst_ip(32),dst_mac(48)
input ip_rslv_req,
output reg ip_rslv_grant,
input [31:0] ip_rslv_ip, //ip to resolve
output reg ip_rslvd_req,
input ip_rslvd_grant,
output reg [80:0] ip_rslvd_ipmac, //yes(1)/no(0)+ip+mac reply
input want_arp,
output reg arp_addlook_req, //添加查诿
input arp_addlook_grant,
output reg [80:0] arp_addlook_ipmac, //type:add(0),look(1)+ip(32)+mac(48)
input [48:0] arp_look_rslt, //type:found(1),notfound(0)+mac(48)
input arp_rslv_report_req, //解析上抿
output reg arp_rslv_report_grant,
input [81:0] arp_rslv_ip //type:(1)[resolve(0),report(1)]+(2):[found(1),not(0)]+ip+mac(48)
);
localparam idle = 4'd0,
check_arp_recv = 4'd1,
check_ip_rslv = 4'd2,
check_arp_rslv_report = 4'd3,
use_arp_send_ask = 4'd4,
use_arp_send_reply = 4'd5,
use_ip_rslvd = 4'd6,
use_arp_add = 4'd7,
use_arp_look = 4'd8;
///////////////////////////////////////////////////
//reg & wire
///////////////////////////////////////////////////
reg [3:0] state;
reg [1:0] round;
reg [81:0] arp_recv_fifo_rddata_reg;
reg [31:0] ip_reg;
reg [81:0] arp_rslv_ip_reg;
reg [1:0] i;
///////////////////////////////////////////////////
//fsm
///////////////////////////////////////////////////
always@(posedge clk or posedge rst)begin
if(rst)begin
state <=0;
arp_recv_fifo_rden <=0;
arp_send_fifo_wren <=0;
arp_send_fifo_wrdata <=0;
ip_rslv_grant <=0;
ip_rslvd_req <=0;
ip_rslvd_ipmac <=0;
arp_addlook_req <=0;
arp_addlook_ipmac <=0;
arp_rslv_report_grant <=0;
round <=0;
i <=0;
arp_recv_fifo_rddata_reg <=0;
ip_reg <=0;
arp_rslv_ip_reg <=0;
end
else begin
case(state)
idle:begin
arp_send_fifo_wren <=0;
if(!arp_recv_fifo_empty)begin
round <=2'b00;
arp_recv_fifo_rden <=1'b1;
state <=check_arp_recv;
end
else if(ip_rslv_req)begin
round <=2'b01;
ip_rslv_grant <=1'b1;
ip_reg <=ip_rslv_ip;
state <=use_arp_look;
end
else if(arp_rslv_report_req)begin
round <=2'b10;
arp_rslv_report_grant <=1'b1;
arp_rslv_ip_reg <=arp_rslv_ip;
if(arp_rslv_ip[81]==1'b0)begin //arp_cache解析请求
state <=use_arp_send_ask;
ip_reg <=arp_rslv_ip[79:48];
end
else if(arp_rslv_ip[81]==1'b1)begin //report
state <=use_ip_rslvd;
ip_rslvd_ipmac <={arp_rslv_ip[80],arp_rslv_ip[79:48],arp_rslv_ip[47:0]};
end
end
end
check_arp_recv:begin
arp_recv_fifo_rden <=1'b0;
arp_recv_fifo_rddata_reg <=arp_recv_fifo_rddata;
if(arp_recv_fifo_rddata[81:80]==2'b01)begin //请求,目的ip是本地ip
state <=use_arp_send_reply;
end
else if(arp_recv_fifo_rddata[81:80]==2'b00)begin //请求目的ip不是本地ip
state <=idle;
end
else if(arp_recv_fifo_rddata[81:80]==2'b11)begin //回复目的ip是本地ip
state <=use_arp_add;
arp_addlook_req <=1'b1;
arp_addlook_ipmac <={1'b0,arp_recv_fifo_rddata[79:0]};
end
else if(arp_recv_fifo_rddata[81:80]==2'b10)begin //回复目的ip不是本地ip
state <=idle;
end
end
use_arp_send_reply:begin
if(!arp_send_fifo_af)begin
arp_send_fifo_wren <=1'b1;
arp_send_fifo_wrdata <={1'b1,arp_recv_fifo_rddata_reg[79:0]};
state <=idle;
end
else begin
state <=use_arp_send_reply;
end
end
use_arp_add:begin
if(arp_addlook_grant)begin
arp_addlook_req <=1'b0;
state <=idle;
end
else begin
state <=use_arp_add;
end
end
use_arp_look:begin
ip_rslv_grant <=1'b0;
if(i==0)begin
arp_addlook_req <=1'b1;
arp_addlook_ipmac <={1'b1,ip_reg[31:0],48'h0};
i <=1'b1;
end
else if(i==1 && arp_addlook_grant)begin
i <=0;
arp_addlook_req <=0;
if(arp_look_rslt[48]==1'b1)begin //查询到回复ip
ip_rslvd_ipmac <={1'b1,ip_reg[31:0],arp_look_rslt[47:0]};
state <=use_ip_rslvd;
end
else if(arp_look_rslt[48]==1'b0)begin //没有查询刿
state <=use_arp_send_ask;
end
end
else begin
i <=i;
state <=use_arp_look;
end
end
use_ip_rslvd:begin
arp_rslv_report_grant <=1'b0;
if(i==0)begin
if(want_arp)begin
ip_rslvd_req <=1'b1;
i <=1'b1;
end
else begin
i <=0;
state <=idle;
end
end
else if(i==1)begin
if(ip_rslvd_grant)begin
ip_rslvd_req <=0;
i <=0;
state <=idle;
end
else begin
i <=i;
state <=use_ip_rslvd;
end
end
end
use_arp_send_ask:begin
arp_rslv_report_grant <=1'b0;
if(!arp_send_fifo_af)begin
arp_send_fifo_wren <=1'b1;
arp_send_fifo_wrdata <={1'b0,ip_reg[31:0],48'hFFFF_FFFF_FFFF};
state <=idle;
end
else begin
state <=use_arp_send_ask;
end
end
default:begin
state <=idle;
end
endcase
end
end
endmodule

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@ -0,0 +1,321 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/08/14 16:33:30
// Design Name:
// Module Name: arp_recv
// Description:
//
// +-----------------------------------------------------------------------------+
// |dst_mac(6) | src_mac(6) | type/len(2) | hard_type(2) | protocal_type(2) |
// +-----------------------------------------------------------------------------+
// |hard_addr_len(1) | protocol_addr_len(1) | op(2) |
// +-----------------------------------------------------------------------------+
// | sender_mac(6) | sender_ip(4) | dst_mac(6) | dst_ip(4) |
// +-----------------------------------------------------------------------------+
//type:0x0806 for arp
//hard_type:0x0001 for ethernet
//protocol:0x0800 for ip
//hard_addr_len:0x06
//protocol_len:0x04
//op:0x0001:who_has(request);0x0002:I have(answer)
//////////////////////////////////////////////////////////////////////////////////
module arp_recv(
input clk,
input rst,
input [47:0] local_mac,
input [31:0] local_ip,
input arp_recv_fifo_empty,
output arp_recv_fifo_rden,
input [8:0] arp_recv_fifo_rddata,
input arp_recv_info_fifo_af,
output reg arp_recv_info_fifo_wren,
output reg [81:0]arp_recv_info_fifo_wrdata //type(1):0请求_1回复dst_ip:_0不是_1本地 src_ip(32),src_mac(48)
);
///////////////////////////////////////////////
//parameter
///////////////////////////////////////////////
localparam idle = 4'd0,
recv_hrd_type = 4'd1,
recv_proc_type = 4'd2,
recv_hrd_len = 4'd3,
recv_proc_len = 4'd4,
recv_op = 4'd5,
recv_src_mac = 4'd6,
recv_src_ip = 4'd7,
recv_dst_mac = 4'd8,
recv_dst_ip = 4'd9,
wait_end = 4'd10,
send_info = 4'd11;
///////////////////////////////////////////////
//reg & wire
///////////////////////////////////////////////
reg [3:0] state;
reg ready;
reg [2:0] i;
reg [15:0] op;
reg [47:0] src_mac_reg;
reg [31:0] src_ip_reg;
reg [47:0] dst_mac_reg;
reg [31:0] dst_ip_reg;
///////////////////////////////////////////////
//combinational logic
///////////////////////////////////////////////
//read out a frame
assign arp_recv_fifo_rden = ~arp_recv_fifo_empty & ready;
///////////////////////////////////////////////
//fsm
///////////////////////////////////////////////
always@(posedge clk or posedge rst)begin
if(rst)begin
state <=0;
ready <=0;
i <=0;
op <=0;
src_mac_reg <=0;
src_ip_reg <=0;
dst_mac_reg <=0;
dst_ip_reg <=0;
arp_recv_info_fifo_wren <=0;
arp_recv_info_fifo_wrdata <=0;
end
else begin
case(state)
idle:begin
arp_recv_info_fifo_wren <=0;
arp_recv_info_fifo_wrdata <=0;
if(!arp_recv_fifo_empty)begin
state <=recv_hrd_type;
ready <=1;
end
end
//hard type: 0x0001 for Ethernet
recv_hrd_type:begin
if(arp_recv_fifo_rden)begin
if(i==0 && arp_recv_fifo_rddata[7:0]==8'h00)begin
i <=i+1;
end
else if(i==1 && arp_recv_fifo_rddata[7:0]==8'h01)begin
i <=0;
state <=recv_proc_type;
end
else begin
i <=0;
state <=wait_end;
end
end
else begin
state <=recv_hrd_type;
end
end
//protocol type: 0x0800 for IP
recv_proc_type:begin
if(arp_recv_fifo_rden)begin
if(i==0 && arp_recv_fifo_rddata[7:0]==8'h08)begin
i <=i+1;
end
else if(i==1 && arp_recv_fifo_rddata[7:0]==8'h00)begin
i <=0;
state <=recv_hrd_len;
end
else begin
i <=0;
state <=wait_end;
end
end
else begin
state <=recv_proc_type;
end
end
//hard_len :0x06 for mac_addr length
recv_hrd_len:begin
if(arp_recv_fifo_rden)begin
if(arp_recv_fifo_rddata[7:0]==8'h06)begin
state <=recv_proc_len;
end
else begin
state <=wait_end;
end
end
else begin
state <=recv_hrd_len;
end
end
//protocol len: 0x04 for ip addr
recv_proc_len:begin
if(arp_recv_fifo_rden)begin
if(arp_recv_fifo_rddata[7:0]==8'h04)begin
state <=recv_op;
end
else begin
state <=wait_end;
end
end
else begin
state <=recv_proc_len;
end
end
//op:0x0001 for who has...;0x0002 for ... is at xxx
recv_op:begin
if(arp_recv_fifo_rden)begin
if(i==0 && arp_recv_fifo_rddata[7:0]==8'h00)begin
i <=i+1;
end
else if(i==1 && arp_recv_fifo_rddata[7:0]==8'h01)begin
op <=16'h0001;
i <=0;
state <=recv_src_mac;
end
else if(i==1 && arp_recv_fifo_rddata[7:0]==8'h02)begin
op <=16'h0002;
i <=0;
state <=recv_src_mac;
end
else begin
state <=wait_end;
end
end
else begin
state <=recv_op;
end
end
recv_src_mac:begin
if(arp_recv_fifo_rden)begin
src_mac_reg <={src_mac_reg[39:0],arp_recv_fifo_rddata[7:0]};
if(i==5)begin
i <=0;
state <=recv_src_ip;
end
else begin
i <=i+1;
end
end
else begin
state <=recv_src_mac;
end
end
recv_src_ip:begin
if(arp_recv_fifo_rden)begin
src_ip_reg <={src_ip_reg[23:0],arp_recv_fifo_rddata[7:0]};
if(i==3)begin
i <=0;
state <=recv_dst_mac;
end
else begin
i <=i+1;
end
end
else begin
state <=recv_src_ip;
end
end
recv_dst_mac:begin
if(arp_recv_fifo_rden)begin
dst_mac_reg <={dst_mac_reg[39:0],arp_recv_fifo_rddata[7:0]};
if(i==5)begin
i <=0;
//if({dst_mac_reg[39:0],arp_recv_fifo_rddata[7:0]}==local_mac || {dst_mac_reg[39:0],arp_recv_fifo_rddata[7:0]}==48'hffff_ffff_ffff)begin
state <=recv_dst_ip;
//end
//else begin
// state <=wait_end;
//end
end
else begin
i <=i+1;
end
end
else begin
state <=recv_dst_mac;
end
end
recv_dst_ip:begin
if(arp_recv_fifo_rden)begin
dst_ip_reg <={dst_ip_reg[23:0],arp_recv_fifo_rddata[7:0]};
if(i==3)begin
i <=0;
if({dst_ip_reg[23:0],arp_recv_fifo_rddata[7:0]}==local_ip)begin
if(arp_recv_fifo_rddata[8])begin
ready <=0;
state <=send_info;
end
else begin
state <=send_info;
end
end
else begin
if(arp_recv_fifo_rddata[8])begin
ready <=0;
state <=idle;
end
else begin
state <=wait_end;
end
end
end
else begin
i <=i+1;
end
end
else begin
state <=recv_dst_ip;
end
end
send_info:begin
if(ready==0)begin
if(!arp_recv_info_fifo_af)begin
state <=idle;
arp_recv_info_fifo_wren <=1;
arp_recv_info_fifo_wrdata <={op[1],1'b1,src_ip_reg[31:0],src_mac_reg[47:0]};
end
else begin
arp_recv_info_fifo_wren <=0;
arp_recv_info_fifo_wrdata <=arp_recv_info_fifo_wrdata;
end
end
else begin
if(arp_recv_fifo_rddata[8])begin
ready <=0;
end
else begin
ready <=1;
end
end
end
wait_end:begin
if(arp_recv_fifo_rddata[8])begin
ready <=0;
state <=idle;
end
else begin
ready <=1;
state <=wait_end;
end
end
default:begin
state <=idle;
end
endcase
end
end
endmodule

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@ -0,0 +1,314 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/08/14 16:33:51
// Design Name:
// Module Name: arp_send
// Description:
//
// +-----------------------------------------------------------------------------+
// |dst_mac(6) | src_mac(6) | type/len(2) | hard_type(2) | protocal_type(2) |
// +-----------------------------------------------------------------------------+
// |hard_addr_len(1) | protocol_addr_len(1) | op(2) |
// +-----------------------------------------------------------------------------+
// | sender_mac(6) | sender_ip(4) | dst_mac(6) | dst_ip(4) |
// +-----------------------------------------------------------------------------+
//type:0x0806 for arp
//hard_type:0x0001 for ethernet
//protocol:0x0800 for ip
//hard_addr_len:0x06
//protocol_len:0x04
//op:0x0001:who_has(request);0x0002:I have(answer)
//////////////////////////////////////////////////////////////////////////////////
module arp_send(
input clk,
input rst,
input [47:0] local_mac,
input [31:0] local_ip,
input arp_send_info_fifo_empty,
output reg arp_send_info_fifo_rden,
input [80:0] arp_send_info_fifo_rddata,//type(1):0ÇëÇó£ß1»Ø¸´£¬dst_ip(32),dst_mac(48)
input arp_send_fifo_af,
output reg arp_send_fifo_wren,
output reg [8:0] arp_send_fifo_wrdata
);
///////////////////////////////////////////////////
//parameter
///////////////////////////////////////////////////
localparam idle = 4'd0,
latch_info = 4'd1,
send_dmac = 4'd2,
send_hrd_type = 4'd3,
send_proc_type = 4'd4,
send_hrd_len = 4'd5,
send_proc_len = 4'd6,
send_op = 4'd7,
send_src_mac = 4'd8,
send_src_ip = 4'd9,
send_dst_mac = 4'd10,
send_dst_ip = 4'd11;
///////////////////////////////////////////////////
//reg & wire
///////////////////////////////////////////////////
reg [3:0] state;
reg [47:0] src_mac_reg;
reg [31:0] src_ip_reg;
reg [47:0] dst_mac_reg;
reg [31:0] dst_ip_reg;
reg [15:0] op_reg;
reg [2:0] i;
///////////////////////////////////////////////////
//combinational logic
///////////////////////////////////////////////////
///////////////////////////////////////////////////
//fsm
///////////////////////////////////////////////////
always@(posedge clk or posedge rst)begin
if(rst)begin
state <=0;
arp_send_info_fifo_rden <=0;
arp_send_fifo_wren <=0;
arp_send_fifo_wrdata <=0;
i <=0;
src_mac_reg <=0;
src_ip_reg <=0;
dst_mac_reg <=0;
dst_ip_reg <=0;
op_reg <=0;
end
else begin
case(state)
idle:begin
arp_send_fifo_wren <=0;
arp_send_fifo_wrdata <=0;
if(!arp_send_info_fifo_empty)begin
arp_send_info_fifo_rden <=1;
state <=latch_info;
end
else begin
state<=idle;
end
end
latch_info:begin
arp_send_info_fifo_rden <=0;
src_mac_reg <=local_mac;
src_ip_reg <=local_ip;
op_reg <=arp_send_info_fifo_rddata[80]==1'b0 ? 16'h0001 : 16'h0002;
dst_ip_reg <=arp_send_info_fifo_rddata[79:48];
dst_mac_reg <=arp_send_info_fifo_rddata[47:0];
state <=send_dmac;
end
send_dmac:begin
if(!arp_send_fifo_af)begin
arp_send_fifo_wren <=1;
if(i==0)begin
arp_send_fifo_wrdata <={1'b0,dst_mac_reg[47:40]};
i <=i+1;
end
else if(i==1)begin
arp_send_fifo_wrdata <={1'b0,dst_mac_reg[39:32]};
i <=i+1;
end
else if(i==2)begin
arp_send_fifo_wrdata <={1'b0,dst_mac_reg[31:24]};
i <=i+1;
end
else if(i==3)begin
arp_send_fifo_wrdata <={1'b0,dst_mac_reg[23:16]};
i <=i+1;
end
else if(i==4)begin
arp_send_fifo_wrdata <={1'b0,dst_mac_reg[15:8]};
i <=i+1;
end
else if(i==5)begin
arp_send_fifo_wrdata <={1'b0,dst_mac_reg[7:0]};
i <=0;
state <=send_hrd_type;
end
end
else begin
arp_send_fifo_wren <=0;
end
end
send_hrd_type:begin
if(!arp_send_fifo_af)begin
if(i==0)begin
i <=i+1;
arp_send_fifo_wren <=1;
arp_send_fifo_wrdata <={1'b0,8'h00};
end
else if(i==1)begin
i <=0;
state <=send_proc_type;
arp_send_fifo_wren <=1;
arp_send_fifo_wrdata <={1'b0,8'h01};
end
end
else begin
arp_send_fifo_wren <=0;
arp_send_fifo_wrdata <=arp_send_fifo_wrdata;
end
end
send_proc_type:begin
if(!arp_send_fifo_af)begin
if(i==0)begin
i <=i+1;
arp_send_fifo_wren <=1;
arp_send_fifo_wrdata <={1'b0,8'h08};
end
else if(i==1)begin
i <=0;
state <=send_hrd_len;
arp_send_fifo_wren <=1;
arp_send_fifo_wrdata <={1'b0,8'h00};
end
end
else begin
arp_send_fifo_wren <=0;
arp_send_fifo_wrdata <=arp_send_fifo_wrdata;
end
end
send_hrd_len:begin
if(!arp_send_fifo_af)begin
state <=send_proc_len;
arp_send_fifo_wren <=1;
arp_send_fifo_wrdata <={1'b0,8'h06};
end
else begin
arp_send_fifo_wren <=0;
arp_send_fifo_wrdata <=arp_send_fifo_wrdata;
end
end
send_proc_len:begin
if(!arp_send_fifo_af)begin
state <=send_op;
arp_send_fifo_wren <=1;
arp_send_fifo_wrdata <={1'b0,8'h04};
end
else begin
arp_send_fifo_wren <=0;
arp_send_fifo_wrdata <=arp_send_fifo_wrdata;
end
end
send_op:begin
if(!arp_send_fifo_af)begin
arp_send_fifo_wren <=1;
arp_send_fifo_wrdata <={1'b0,op_reg[15:8]};
op_reg <=op_reg<<8;
if(i==1)begin
i <=0;
state <=send_src_mac;
end
else begin
i <=i+1;
end
end
else begin
arp_send_fifo_wren <=0;
arp_send_fifo_wrdata <=arp_send_fifo_wrdata;
end
end
send_src_mac:begin
if(!arp_send_fifo_af)begin
arp_send_fifo_wren <=1;
arp_send_fifo_wrdata <={1'b0,src_mac_reg[47:40]};
src_mac_reg <=src_mac_reg<<8;
if(i==5)begin
i <=0;
state <=send_src_ip;
end
else begin
i <=i+1;
end
end
else begin
arp_send_fifo_wren <=0;
arp_send_fifo_wrdata <=arp_send_fifo_wrdata;
end
end
send_src_ip:begin
if(!arp_send_fifo_af)begin
arp_send_fifo_wren <=1;
arp_send_fifo_wrdata <={1'b0,src_ip_reg[31:24]};
src_ip_reg <=src_ip_reg<<8;
if(i==3)begin
i <=0;
state <=send_dst_mac;
end
else begin
i <=i+1;
end
end
else begin
arp_send_fifo_wren <=0;
arp_send_fifo_wrdata <=arp_send_fifo_wrdata;
end
end
send_dst_mac:begin
if(!arp_send_fifo_af)begin
arp_send_fifo_wren <=1;
arp_send_fifo_wrdata <={1'b0,dst_mac_reg[47:40]};
dst_mac_reg <=dst_mac_reg<<8;
if(i==5)begin
i <=0;
state <=send_dst_ip;
end
else begin
i <=i+1;
end
end
else begin
arp_send_fifo_wren <=0;
arp_send_fifo_wrdata <=arp_send_fifo_wrdata;
end
end
send_dst_ip:begin
if(!arp_send_fifo_af)begin
arp_send_fifo_wren <=1;
//arp_send_fifo_wrdata <=dst_ip_reg[31:24];
dst_ip_reg <=dst_ip_reg<<8;
if(i==3)begin
arp_send_fifo_wrdata <={1'b1,dst_ip_reg[31:24]};
i <=0;
state <=idle;
end
else begin
arp_send_fifo_wrdata <={1'b0,dst_ip_reg[31:24]};
i <=i+1;
end
end
else begin
arp_send_fifo_wren <=0;
arp_send_fifo_wrdata <=arp_send_fifo_wrdata;
end
end
default:begin
state <=idle;
end
endcase
end
end
endmodule

View File

@ -0,0 +1,221 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/08/15 10:23:29
// Design Name:
// Module Name: arp_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module arp_top(
input clk,
input rst,
input [47:0] local_mac,
input [31:0] local_ip,
input [3:0] retry_time,
input [31:0] live_time,
input [80:0] static_table0,
input [80:0] static_table1,
input [80:0] static_table2,
input [80:0] static_table3,
output arp_error,
input ip_rslv_req,
output ip_rslv_grant,
input [31:0] ip_rslv_ip,
output ip_rslvd_req,
input ip_rslvd_grant,
output [80:0] ip_rslvd_ipmac,
input want_arp,
//mac interface
input arp_recv_fifo_empty,
output arp_recv_fifo_rden,
input [8:0] arp_recv_fifo_rddata,
output arp_send_fifo_empty,
input arp_send_fifo_rden,
output [8:0] arp_send_fifo_rddata
);
//
wire arp_recv_info_fifo_wren;
wire [81:0] arp_recv_info_fifo_wrdata;
wire arp_recv_info_fifo_af;
wire arp_recv_info_fifo_rden;
wire [81:0] arp_recv_info_fifo_rddata;
wire arp_recv_info_fifo_empty;
//
wire arp_send_info_fifo_wren;
wire [80:0] arp_send_info_fifo_wrdata;
wire arp_send_info_fifo_af;
wire arp_send_info_fifo_rden;
wire [80:0] arp_send_info_fifo_rddata;
wire arp_send_info_fifo_empty;
//
wire arp_send_fifo_af;
wire arp_send_fifo_wren;
wire [8:0] arp_send_fifo_wrdata;
/////////////////////////////////////////////////////////
//arp issue manager
/////////////////////////////////////////////////////////
arp_manage_top U_arp_manage_top(
.clk (clk ),
.rst (rst ),
.retry_time (retry_time ),
.live_time (live_time ),
.static_table0 (static_table0 ),
.static_table1 (static_table1 ),
.static_table2 (static_table2 ),
.static_table3 (static_table3 ),
.error (arp_error ),
.arp_recv_fifo_empty (arp_recv_info_fifo_empty ),
.arp_recv_fifo_rden (arp_recv_info_fifo_rden ),
.arp_recv_fifo_rddata (arp_recv_info_fifo_rddata ),
.arp_send_fifo_af (arp_send_info_fifo_af ),
.arp_send_fifo_wren (arp_send_info_fifo_wren ),
.arp_send_fifo_wrdata (arp_send_info_fifo_wrdata ),
.ip_rslv_req (ip_rslv_req ),
.ip_rslv_grant (ip_rslv_grant ),
.ip_rslv_ip (ip_rslv_ip ),
.ip_rslvd_req (ip_rslvd_req ),
.ip_rslvd_grant (ip_rslvd_grant ),
.ip_rslvd_ipmac (ip_rslvd_ipmac ),
.want_arp (want_arp )
);
/////////////////////////////////////////////////////////
//arp receive
/////////////////////////////////////////////////////////
arp_recv U_arp_recv(
.clk (clk ),
.rst (rst ),
.local_mac (local_mac ),
.local_ip (local_ip ),
.arp_recv_fifo_empty (arp_recv_fifo_empty ),
.arp_recv_fifo_rden (arp_recv_fifo_rden ),
.arp_recv_fifo_rddata (arp_recv_fifo_rddata ),
.arp_recv_info_fifo_af (arp_recv_info_fifo_af ),
.arp_recv_info_fifo_wren (arp_recv_info_fifo_wren ),
.arp_recv_info_fifo_wrdata (arp_recv_info_fifo_wrdata )//type(1):0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD>ظ<EFBFBD><EFBFBD><EFBFBD>dst_ip:<EFBFBD><EFBFBD>0<EFBFBD><EFBFBD><EFBFBD>ǣ<EFBFBD>1<EFBFBD><EFBFBD><EFBFBD><EFBFBD> src_ip(32),src_mac(48)
);
//ila_100 ila_arp_info_recv(
// .clk (clk),
// .probe0 (
// {
// arp_recv_info_fifo_wren, //1
// arp_recv_info_fifo_wrdata,//82
// 17'b0
// }
// )
//);
//------------------------------------------------------
//arp recv info fifo
//------------------------------------------------------
syn_fwft_fifo #(
.width (82),
.depth (8))
U_arp_recv_info_fifo(
.clk (clk ),
.rst (rst ),
.clr (1'b0 ),
.wr_en (arp_recv_info_fifo_wren ),
.din (arp_recv_info_fifo_wrdata),
.full (),
.almost_full (arp_recv_info_fifo_af ),
.rd_en (arp_recv_info_fifo_rden ),
.dout (arp_recv_info_fifo_rddata),
.empty (arp_recv_info_fifo_empty )
);
/////////////////////////////////////////////////////////
//arp send
/////////////////////////////////////////////////////////
arp_send U_arp_send(
.clk (clk ),
.rst (rst ),
.local_mac (local_mac ),
.local_ip (local_ip ),
.arp_send_info_fifo_empty (arp_send_info_fifo_empty ),
.arp_send_info_fifo_rden (arp_send_info_fifo_rden ),
.arp_send_info_fifo_rddata (arp_send_info_fifo_rddata ),//type(1):0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD>ظ<EFBFBD><EFBFBD><EFBFBD>dst_ip(32),dst_mac(48)
.arp_send_fifo_af (arp_send_fifo_af ),
.arp_send_fifo_wren (arp_send_fifo_wren ),
.arp_send_fifo_wrdata (arp_send_fifo_wrdata )
);
//===============================================================
//ila_100 ila_arp_info_send(
// .clk (clk),
// .probe0 (
// {
// arp_send_info_fifo_wren, //1
// arp_send_info_fifo_wrdata,//81
// arp_send_fifo_wren, //1
// arp_send_fifo_wrdata, //9
// 8'b0
// }
// )
// );
//===============================================================
//------------------------------------------------------
//arp send info fifo
//------------------------------------------------------
syn_fwft_fifo #(
.width (81),
.depth (8))
U_arp_send_info_fifo(
.clk (clk ),
.rst (rst ),
.clr (1'b0 ),
.wr_en (arp_send_info_fifo_wren ),
.din (arp_send_info_fifo_wrdata),
.full (),
.almost_full (arp_send_info_fifo_af ),
.rd_en (arp_send_info_fifo_rden ),
.dout (arp_send_info_fifo_rddata),
.empty (arp_send_info_fifo_empty )
);
//------------------------------------------------------
//arp send info fifo
//------------------------------------------------------
syn_fwft_fifo #(
.width (9),
.depth (32))
U_arp_send_fifo(
.clk (clk ),
.rst (rst ),
.clr (1'b0 ),
.wr_en (arp_send_fifo_wren ),
.din (arp_send_fifo_wrdata ),
.full (),
.almost_full (arp_send_fifo_af ),
.rd_en (arp_send_fifo_rden ),
.dout (arp_send_fifo_rddata ),
.empty (arp_send_fifo_empty )
);
endmodule

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@ -0,0 +1,619 @@
// ------------------------------------------------------------------------
//
// (C) COPYRIGHT 2005 - 2013 SYNOPSYS, INC.
// ALL RIGHTS RESERVED
//
// This software and the associated documentation are confidential and
// proprietary to Synopsys, Inc. Your use or disclosure of this
// software is subject to the terms and conditions of a written
// license agreement between you, or your company, and Synopsys, Inc.
//
// The entire notice above must be reproduced on all authorized copies.
//
// ------------------------------------------------------------------------
//
// Filename : DWC_gmac_bcm21.v
// Revision : $Id: //dwh/ethernet_iip/main/GMAC_AHB_3_70A/src/common/DWC_gmac_bcm21.v#7 $
// Author : Doug Lee 2/20/05
// Description : DWC_gmac_bcm21.v Verilog module for DWbb
//
// DesignWare IP ID: 8cba72d0
//
////////////////////////////////////////////////////////////////////////////////
`define DWC_NO_CDC_INIT
`define DWC_NO_TST_MODE
module DWC_gmac_bcm21 (
clk_d,
rst_d_n,
`ifndef DWC_NO_CDC_INIT
init_d_n,
`endif
data_s,
`ifndef DWC_NO_TST_MODE
test,
`endif
data_d
);
parameter WIDTH = 1; // RANGE 1 to 1024
parameter F_SYNC_TYPE = 2; // RANGE 0 to 4
`ifndef DWC_NO_TST_MODE
parameter TST_MODE = 0; // RANGE 0 to 2
`endif
// leda W175 off
// LMD: Parameter is defined but not used
// LJ: This parameter is known to be unused for the synthesizable code. So, disable LEDA from reporting warning.
parameter VERIF_EN = 1; // RANGE 0 to 5
// leda W175 on
input clk_d; // clock input from destination domain
input rst_d_n; // active low asynchronous reset from destination domain
`ifndef DWC_NO_CDC_INIT
input init_d_n; // active low synchronous reset from destination domain
`endif
input [WIDTH-1:0] data_s; // data to be synchronized from source domain
`ifndef DWC_NO_TST_MODE
input test; // test input
`endif
output [WIDTH-1:0] data_d; // data synchronized to destination domain
reg [WIDTH-1:0] sample_meta_n;
reg [WIDTH-1:0] sample_meta;
reg [WIDTH-1:0] sample_syncm1;
reg [WIDTH-1:0] sample_syncm2;
reg [WIDTH-1:0] sample_syncl;
`ifndef DWC_NO_TST_MODE
reg [WIDTH-1:0] test_hold;
`endif
wire [WIDTH-1:0] next_sample_meta;
wire [WIDTH-1:0] next_sample_syncm1;
wire [WIDTH-1:0] next_sample_syncm2;
wire [WIDTH-1:0] next_sample_syncl;
// leda off
// verpp-pragma processing_off
`ifdef SYNTHESIS `else
initial begin
if ((F_SYNC_TYPE > 0)&&(F_SYNC_TYPE < 8))
$display("Information: *** Instance %m module is using the <Double Register Synchronizer (1)> Clock Domain Crossing Method ***");
end
`ifdef DW_REPORT_SYNC_PARAMS
initial begin
if ((F_SYNC_TYPE & 7) > 0)
// verpp-pragma processing_on
`ifndef DWC_NO_TST_MODE
$display("Information: *** Instance %m is configured as follows: WIDTH is: %0d, F_SYNC_TYPE is: %0d, TST_MODE is: %0d ***", WIDTH, (F_SYNC_TYPE & 7), TST_MODE);
`else
$display("Information: *** Instance %m is configured as follows: WIDTH is: %0d, F_SYNC_TYPE is: %0d ***", WIDTH, (F_SYNC_TYPE & 7));
`endif
// verpp-pragma processing_off
end
`endif
`endif
// verpp-pragma processing_on
// leda on
`ifndef DWC_NO_TST_MODE
`endif
// verpp-pragma processing_off
`ifdef SYNTHESIS
`define DW_data_s_int data_s
generate
if ((F_SYNC_TYPE & 7) == 1) begin : GEN_MS_NEXT_SYNCM1_FST1
assign next_sample_syncm1 = sample_meta_n;
end
if ((F_SYNC_TYPE & 7) > 1) begin : GEN_MS_NEXT_SYNCM1_FST_GT_1
assign next_sample_syncm1 = sample_meta;
end
endgenerate
`else
`ifdef DW_MODEL_MISSAMPLES
// leda off
initial begin
$display("Information: %m: *** Running with DW_MODEL_MISSAMPLES defined, VERIF_EN is: %0d ***",
VERIF_EN);
end
wire hclk_odd;
reg [WIDTH-1:0] last_data_dyn, data_s_delta_t;
reg [WIDTH-1:0] last_data_s, last_data_s_q, last_data_s_qq;
wire [WIDTH-1:0] data_s_sel_0, data_s_sel_1;
reg [WIDTH-1:0] data_select; initial data_select = 0;
reg [WIDTH-1:0] data_select_2; initial data_select_2 = 0;
// verpp-pragma processing_on
`ifndef DWC_NO_CDC_INIT
reg init_dly_n;
`endif
// verpp-pragma processing_off
always @ (posedge hclk_odd or data_s or rst_d_n) begin : PROC_catch_last_data
// verpp-pragma processing_on
`ifndef DWC_NO_CDC_INIT
data_s_delta_t <= data_s & {WIDTH{rst_d_n}} & {WIDTH{init_dly_n}};
last_data_dyn <= data_s_delta_t & {WIDTH{rst_d_n}} & {WIDTH{init_dly_n}};
`else
data_s_delta_t <= data_s & {WIDTH{rst_d_n}};
last_data_dyn <= data_s_delta_t & {WIDTH{rst_d_n}};
`endif
// verpp-pragma processing_off
end // PROC_catch_last_data
generate if ((VERIF_EN % 2) == 1) begin : GEN_HO_VE_EVEN
assign hclk_odd = clk_d;
end else begin : GEN_HO_VE_ODD
assign hclk_odd = ~clk_d;
end
endgenerate
always @ (posedge clk_d or negedge rst_d_n) begin : PROC_missample_hist_even
if (rst_d_n == 1'b0) begin
last_data_s_q <= {WIDTH{1'b0}};
// verpp-pragma processing_on
`ifndef DWC_NO_CDC_INIT
init_dly_n <= 1'b1;
end else if (init_d_n == 1'b0) begin
last_data_s_q <= {WIDTH{1'b0}};
init_dly_n <= 1'b0;
`endif
// verpp-pragma processing_off
end else begin
last_data_s_q <= last_data_s;
// verpp-pragma processing_on
`ifndef DWC_NO_CDC_INIT
init_dly_n <= 1'b1;
`endif
// verpp-pragma processing_off
end
end // PROC_missample_hist_even
always @ (posedge hclk_odd or negedge rst_d_n) begin : PROC_missample_hist_odd
if (rst_d_n == 1'b0) begin
last_data_s <= {WIDTH{1'b0}};
last_data_s_qq <= {WIDTH{1'b0}};
// verpp-pragma processing_on
`ifndef DWC_NO_CDC_INIT
end else if (init_d_n == 1'b0) begin
last_data_s <= {WIDTH{1'b0}};
last_data_s_qq <= {WIDTH{1'b0}};
`endif
// verpp-pragma processing_off
end else begin
last_data_s <= data_s;
last_data_s_qq <= last_data_s_q;
end
end // PROC_missample_hist_odd
always @ (data_s or last_data_s) begin : PROC_mk_next_data_select
if (data_s != last_data_s) begin
data_select = wide_random(WIDTH);
if ((VERIF_EN == 2) || (VERIF_EN == 3))
data_select_2 = wide_random(WIDTH);
else
data_select_2 = {WIDTH{1'b0}};
end
end // PROC_mk_next_data_select
assign data_s_sel_0 = (VERIF_EN < 1)? data_s : ((data_s & ~data_select) | (last_data_dyn & data_select));
assign data_s_sel_1 = (VERIF_EN < 2)? {WIDTH{1'b0}} : ((last_data_s_q & ~data_select) | (last_data_s_qq & data_select));
`define DW_data_s_int ((data_s_sel_0 & ~data_select_2) | (data_s_sel_1 & data_select_2))
// { START Latency Accurate modeling
initial begin : set_setup_hold_delay_PROC
`ifdef DW_HOLD_MUX_DELAY
`else
`define DW_HOLD_MUX_DELAY 1
if (((F_SYNC_TYPE & 7) == 2) && (VERIF_EN == 5))
$display("Information: %m: *** Warning: `DW_HOLD_MUX_DELAY is not defined so it is being set to: %0d ***", `DW_HOLD_MUX_DELAY);
`endif
`ifdef DW_SETUP_MUX_DELAY
`else
`define DW_SETUP_MUX_DELAY 1
if (((F_SYNC_TYPE & 7) == 2) && (VERIF_EN == 5))
$display("Information: %m: *** Warning: `DW_SETUP_MUX_DELAY is not defined so it is being set to: %0d ***", `DW_SETUP_MUX_DELAY);
`endif
end // set_setup_hold_delay_PROC
initial begin
if (((F_SYNC_TYPE & 7) == 2) && (VERIF_EN == 5))
$display("Information: %m: *** Running with Latency Accurate MISSAMPLES defined, VERIF_EN is: %0d ***", VERIF_EN);
end
reg [WIDTH-1:0] setup_mux_ctrl, hold_mux_ctrl;
initial setup_mux_ctrl = {WIDTH{1'b0}};
initial hold_mux_ctrl = {WIDTH{1'b0}};
wire [WIDTH-1:0] data_s_q;
reg clk_d_q;
initial clk_d_q = 1'b0;
reg [WIDTH-1:0] setup_mux_out, d_muxout;
reg [WIDTH-1:0] d_ff1, d_ff2;
integer i,j,k;
//Delay the destination clock
always @ (posedge clk_d)
#`DW_HOLD_MUX_DELAY clk_d_q = 1'b1;
always @ (negedge clk_d)
#`DW_HOLD_MUX_DELAY clk_d_q = 1'b0;
//Delay the source data
assign #`DW_SETUP_MUX_DELAY data_s_q = (!rst_d_n) ? {WIDTH{1'b0}}:data_s;
//setup_mux_ctrl controls the data entering the flip flop
always @ (data_s or data_s_q or setup_mux_ctrl)
begin
for (i=0;i<=WIDTH-1;i=i+1) begin
if (setup_mux_ctrl[i])
setup_mux_out[i] = data_s_q[i];
else
setup_mux_out[i] = data_s[i];
end
end
always @ (posedge clk_d_q or negedge rst_d_n)
begin
if (rst_d_n == 1'b0)
d_ff2 <= {WIDTH{1'b0}};
// verpp-pragma processing_on
`ifndef DWC_NO_CDC_INIT
else if (init_d_n == 1'b0)
d_ff2 <= {WIDTH{1'b0}};
`endif
// verpp-pragma processing_off
// verpp-pragma processing_on
`ifndef DWC_NO_TST_MODE
else if (test == 1'b1)
d_ff2 <= (TST_MODE == 1) ? test_hold : data_s;
else
`endif
// verpp-pragma processing_off
d_ff2 <= setup_mux_out;
end
always @ (posedge clk_d or negedge rst_d_n)
begin
if (rst_d_n == 1'b0) begin
d_ff1 <= {WIDTH{1'b0}};
setup_mux_ctrl <= {WIDTH{1'b0}};
hold_mux_ctrl <= {WIDTH{1'b0}};
end
// verpp-pragma processing_on
`ifndef DWC_NO_CDC_INIT
else if (init_d_n == 1'b0) begin
d_ff1 <= {WIDTH{1'b0}};
setup_mux_ctrl <= {WIDTH{1'b0}};
hold_mux_ctrl <= {WIDTH{1'b0}};
end
`endif
// verpp-pragma processing_off
else begin
// verpp-pragma processing_on
`ifndef DWC_NO_TST_MODE
if (test == 1'b1)
d_ff1 <= (TST_MODE == 1) ? test_hold : data_s;
else
`endif
// verpp-pragma processing_off
d_ff1 <= setup_mux_out;
setup_mux_ctrl <= wide_random(WIDTH); //randomize mux_ctrl
hold_mux_ctrl <= wide_random(WIDTH); //randomize mux_ctrl
end
end
//hold_mux_ctrl decides the clock triggering the flip-flop
always @(hold_mux_ctrl or d_ff2 or d_ff1) begin
for (k=0;k<=WIDTH-1;k=k+1) begin
if (hold_mux_ctrl[k])
d_muxout[k] = d_ff2[k];
else
d_muxout[k] = d_ff1[k];
end
end
// END Latency Accurate modeling }
//Assertions
//static logic [WIDTH-1:0]cnt_hmux = {WIDTH{1'b0}};
// leda FM_2_34A off
`ifdef SYNTHESIS `else
// Only use assertions for simulation
`ifdef SYSTEMVERILOG
`ifdef DW_SVA_MODE
`define DW_LOCAL_SVA_MODE `DW_SVA_MODE
`else
// Default to 'error' message reporting
`define DW_LOCAL_SVA_MODE 2
`endif // DW_SVA_MODE
generate if ((F_SYNC_TYPE == 2) && (VERIF_EN == 5)) begin : GEN_ASSERT_FST2_VE5
sequence p_num_d_chng;
@ (posedge clk_d) 1'b1 ##0 (data_s != d_ff1); //Number of times input data changed
endsequence
sequence p_num_d_chng_hmux1;
@ (posedge clk_d) 1'b1 ##0 ((data_s != d_ff1) && (|(hold_mux_ctrl & (data_s ^ d_ff1)))); //Number of times hold_mux_ctrl was asserted when the input data changed
endsequence
sequence p_num_d_chng_smux1;
@ (posedge clk_d) 1'b1 ##0 ((data_s != d_ff1) && (|(setup_mux_ctrl & (data_s ^ d_ff1)))); //Number of times setup_mux_ctrl was asserted when the input data changed
endsequence
sequence p_hold_vio;
reg [WIDTH-1:0]temp_var, temp_var1;
@ (posedge clk_d) (((data_s != d_ff1) && (|(hold_mux_ctrl & (data_s ^ d_ff1)))), temp_var = data_s, temp_var1 =(hold_mux_ctrl & (data_s ^ d_ff1))) ##1 ((data_d & temp_var1) == (temp_var & temp_var1));
//Number of times output data was advanced due to hold violation
endsequence
sequence p_setup_vio;
reg [WIDTH-1:0]temp_var, temp_var1;
@ (posedge clk_d) (((data_s != d_ff1) && (|(setup_mux_ctrl & (data_s ^ d_ff1)))), temp_var = data_s, temp_var1 =(setup_mux_ctrl & (data_s ^ d_ff1))) ##2 ((data_d & temp_var1) != (temp_var & temp_var1));
//Number of times output data was delayed due to setup violation
endsequence
cp_num_d_chng :
cover property (p_num_d_chng);
cp_num_d_chng_hld_mux1 :
cover property (p_num_d_chng_hmux1);
cp_num_d_chng_set_mux1 :
cover property (p_num_d_chng_smux1);
cp_hold_vio :
cover property (p_hold_vio);
cp_setup_vio :
cover property (p_setup_vio);
end
endgenerate
`undef DW_LOCAL_SVA_MODE
`endif // SYSTEMVERILOG
`endif // SYNTHESIS
// leda FM_2_34A on
generate
if ((F_SYNC_TYPE & 7) == 1) begin : GEN_NXT_SMPL_SM1_FST1
assign next_sample_syncm1 = sample_meta_n;
end else begin : GEN_NXT_SMPL_SM1_NOT_FST1
if (((F_SYNC_TYPE & 7) == 2) && (VERIF_EN == 5)) begin : GEN_NXT_SMPL_SM1_FST2_VE5
assign next_sample_syncm1 = d_muxout;
end else begin : GEN_NXT_SMPL_SM1_ELSE
assign next_sample_syncm1 = sample_meta;
end
end
endgenerate
function [WIDTH-1:0] wide_random;
input [31:0] in_width; // should match "WIDTH" parameter -- need one input to satisfy Verilog function requirement
reg [WIDTH-1:0] temp_result;
reg [31:0] rand_slice;
integer i, j, base;
begin
temp_result = $random;
if (((WIDTH / 32) + 1) > 1) begin
for (i=1 ; i < ((WIDTH / 32) + 1) ; i=i+1) begin
base = i << 5;
rand_slice = $random;
for (j=0 ; ((j < 32) && (base+j < in_width)) ; j=j+1) begin
temp_result[base+j] = rand_slice[j];
end
end
end
wide_random = temp_result;
end
endfunction // wide_random
initial begin : seed_random_PROC
integer seed, init_rand;
`ifdef DW_MISSAMPLE_SEED
seed = `DW_MISSAMPLE_SEED;
`else
seed = 32'h0badbeef;
`endif
init_rand = $random(seed);
end // seed_random_PROC
// leda on
`else
`define DW_data_s_int data_s
generate
if ((F_SYNC_TYPE & 7) == 1) begin : GEN_NXT_SMPL_SM1_FST_EQUAL1
assign next_sample_syncm1 = sample_meta_n;
end
if ((F_SYNC_TYPE & 7) > 1) begin : GEN_NXT_SMPL_SM1_FST_GRTH1
assign next_sample_syncm1 = sample_meta;
end
endgenerate
`endif
`endif
// verpp-pragma processing_on
`ifdef DWC_NO_TST_MODE
assign next_sample_meta = `DW_data_s_int;
`else
generate
if (TST_MODE == 1) begin : GEN_TST_MODE1
assign next_sample_meta = (test == 1'b0) ? `DW_data_s_int : test_hold;
always @ (negedge clk_d or negedge rst_d_n) begin : PROC_test_hold_registers
if (rst_d_n == 1'b0) begin
// spyglass disable STARC-1.3.1.3
// spyglass disable STARC05-1.3.1.3
// SJ: Synchronizer FFs required to have reset to initialize system
test_hold <= {WIDTH{1'b0}};
// spyglass enable STARC05-1.3.1.3
// spyglass enable STARC-1.3.1.3
`ifndef DWC_NO_CDC_INIT
end else if (init_d_n == 1'b0) begin
test_hold <= {WIDTH{1'b0}};
`endif
end else begin
test_hold <= data_s;
end
end
end else begin : GEN_TST_MODE0
assign next_sample_meta = (test == 1'b0) ? `DW_data_s_int : data_s;
end
endgenerate
`endif
generate
if ((F_SYNC_TYPE & 7) == 0) begin : GEN_FST0
`ifndef DWC_NO_TST_MODE
if (TST_MODE == 1) begin : GEN_DATAD_FST0_TM1
assign data_d = (test == 1'b1) ? test_hold : data_s;
end else begin : GEN_DATAD_FST0_TM_NE_1
assign data_d = data_s;
end
`else
assign data_d = data_s;
`endif
end
if ((F_SYNC_TYPE & 7) == 1) begin : GEN_FST1
always @ (negedge clk_d or negedge rst_d_n) begin : PROC_negedge_registers
// spyglass disable STARC-1.3.1.3
// spyglass disable STARC05-1.3.1.3
// SJ: Synchronizer FFs required to have reset to initialize system
if (rst_d_n == 1'b0) begin
// spyglass enable STARC05-1.3.1.3
// spyglass enable STARC-1.3.1.3
sample_meta_n <= {WIDTH{1'b0}};
`ifndef DWC_NO_CDC_INIT
end else if (init_d_n == 1'b0) begin
sample_meta_n <= {WIDTH{1'b0}};
`endif
end else begin
sample_meta_n <= `DW_data_s_int;
end
end
assign next_sample_syncl = next_sample_syncm1;
always @ (posedge clk_d or negedge rst_d_n) begin : PROC_posedge_registers
// spyglass disable STARC-1.3.1.3
// spyglass disable STARC05-1.3.1.3
// SJ: Synchronizer FFs required to have reset to initialize system
if (rst_d_n == 1'b0) begin
// spyglass enable STARC05-1.3.1.3
// spyglass enable STARC-1.3.1.3
sample_syncl <= {WIDTH{1'b0}};
`ifndef DWC_NO_CDC_INIT
end else if (init_d_n == 1'b0) begin
sample_syncl <= {WIDTH{1'b0}};
`endif
end else begin
sample_syncl <= next_sample_syncl;
end
end
assign data_d = sample_syncl;
end
if ((F_SYNC_TYPE & 7) == 2) begin : GEN_FST2
assign next_sample_syncl = next_sample_syncm1;
always @ (posedge clk_d or negedge rst_d_n) begin : PROC_posedge_registers
// spyglass disable STARC-1.3.1.3
// spyglass disable STARC05-1.3.1.3
// SJ: Synchronizer FFs required to have reset to initialize system
if (rst_d_n == 1'b0) begin
// spyglass enable STARC05-1.3.1.3
// spyglass enable STARC-1.3.1.3
sample_meta <= {WIDTH{1'b0}};
sample_syncl <= {WIDTH{1'b0}};
`ifndef DWC_NO_CDC_INIT
end else if (init_d_n == 1'b0) begin
sample_meta <= {WIDTH{1'b0}};
sample_syncl <= {WIDTH{1'b0}};
`endif
end else begin
sample_meta <= next_sample_meta;
sample_syncl <= next_sample_syncl;
end
end
assign data_d = sample_syncl;
end
if ((F_SYNC_TYPE & 7) == 3) begin : GEN_FST3
assign next_sample_syncl = sample_syncm1;
always @ (posedge clk_d or negedge rst_d_n) begin : PROC_posedge_registers
// spyglass disable STARC-1.3.1.3
// spyglass disable STARC05-1.3.1.3
// SJ: Synchronizer FFs required to have reset to initialize system
if (rst_d_n == 1'b0) begin
// spyglass enable STARC05-1.3.1.3
// spyglass enable STARC-1.3.1.3
sample_meta <= {WIDTH{1'b0}};
sample_syncm1 <= {WIDTH{1'b0}};
sample_syncl <= {WIDTH{1'b0}};
`ifndef DWC_NO_CDC_INIT
end else if (init_d_n == 1'b0) begin
sample_meta <= {WIDTH{1'b0}};
sample_syncm1 <= {WIDTH{1'b0}};
sample_syncl <= {WIDTH{1'b0}};
`endif
end else begin
sample_meta <= next_sample_meta;
sample_syncm1 <= next_sample_syncm1;
sample_syncl <= next_sample_syncl;
end
end
assign data_d = sample_syncl;
end
if ((F_SYNC_TYPE & 7) == 4) begin : GEN_FST4
assign next_sample_syncm2 = sample_syncm1;
assign next_sample_syncl = sample_syncm2;
always @ (posedge clk_d or negedge rst_d_n) begin : PROC_posedge_registers
// spyglass disable STARC-1.3.1.3
// spyglass disable STARC05-1.3.1.3
// SJ: Synchronizer FFs required to have reset to initialize system
if (rst_d_n == 1'b0) begin
// spyglass enable STARC05-1.3.1.3
// spyglass enable STARC-1.3.1.3
sample_meta <= {WIDTH{1'b0}};
sample_syncm1 <= {WIDTH{1'b0}};
sample_syncm2 <= {WIDTH{1'b0}};
sample_syncl <= {WIDTH{1'b0}};
`ifndef DWC_NO_CDC_INIT
end else if (init_d_n == 1'b0) begin
sample_meta <= {WIDTH{1'b0}};
sample_syncm1 <= {WIDTH{1'b0}};
sample_syncm2 <= {WIDTH{1'b0}};
sample_syncl <= {WIDTH{1'b0}};
`endif
end else begin
sample_meta <= next_sample_meta;
sample_syncm1 <= next_sample_syncm1;
sample_syncm2 <= next_sample_syncm2;
sample_syncl <= next_sample_syncl;
end
end
assign data_d = sample_syncl;
end
endgenerate
`undef DW_data_s_int
endmodule

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////////////////////////////////////////////////////////
//description: real_win_size= min{rwnd,cwnd};
//designed by Xiaodong Zhong
//2018.12.27
////////////////////////////////////////////////////////
module congestion_control(
input clk,
input rst,
input tcp_connected, //tcp连接建立标志
input [15:0] MSS, //tcp一次能够传输的最大载荷
input [31:0] real_win_size,
input [31:0] win_block,
input rtt_over_vld, //RTT计数器发生超时
input dup_over_vld, //收到三个重复的ACK
input paper_send_req, //发生报文信息
input [31:0] tx_seqNo, //报文序号
input [15:0] tx_data_len, //报文数据长度
input paper_rcvd_req, //接收报文信息
input [31:0] rx_ackNo, //接收报文确认号
output cwnd_set,
output [31:0] cwnd //拥塞窗口打大小
);
///////////////////////////////////////////////////////
//慢开始 指数增大
//拥塞避免加法增大
//拥塞检测乘法减小
//1拥塞窗口从1个MMS开始当第一个ACK到达以后cwnd=cwnd+1
//2慢开始后cwnd增大到门限以后慢开始阶段停止
//3在拥塞避免阶段只有当一整个窗口中的报文段都被确认以后cwnd才加1
//4拥塞检测
//1如果是计时器超时
// 把门限值设为当前窗口的一半
// cwnd=1MMS
// 再次从慢开始阶段开始
//2如果是收到了三个ack,导致重传
// 把门限值设为当前窗口的一半
// cwnd=门限值
// 启动拥塞避免阶段
///////////////////////////////////////////////////////
parameter IDLE =2'd0,
SS =2'd1,
AI =2'd2,
MD =2'd3;
reg [1:0] current_state;
reg [1:0] next_state;
reg [15:0] cwnd_mms;
reg [15:0] cwnd_mms_thre;
reg event_type; //0:rtt_over;1:dup_over
wire [15:0] cwnd_mss_max;
reg [1:0] i;
reg cwnd_set_reg;
assign cwnd = (cwnd_mms ==0) ? MSS : MSS*cwnd_mms;
assign cwnd_set = cwnd_set_reg;
assign cwnd_mss_max = (win_block+1)>>10;
///////////////////////////////////////////////////////
//描述状态迁移
///////////////////////////////////////////////////////
always@(posedge clk or posedge rst) begin
if(rst) begin
current_state <=0;
end
else begin
current_state <=next_state;
end
end
///////////////////////////////////////////////////////
//描述状态迁移条件
///////////////////////////////////////////////////////
always@(*) begin
case(current_state)
IDLE:begin
if(tcp_connected) begin
next_state =SS;
end
else begin
next_state =IDLE;
end
end
SS:begin //Slow Start
if(tcp_connected) begin
if(cwnd_mms==cwnd_mms_thre) begin
next_state =AI;
end
else begin
next_state =SS;
end
end
else begin
next_state =IDLE;
end
end
AI:begin //Congestion avoid
if(tcp_connected) begin
if(rtt_over_vld || dup_over_vld) begin
next_state =MD;
end
else begin
next_state =AI;
end
end
else begin
next_state =IDLE;
end
end
MD:begin
if(tcp_connected) begin
if(event_type==1'b0) begin
next_state =SS;
end
//else if(event_type==1'b1) begin
else begin
next_state =AI;
end
end
else begin
next_state =IDLE;
end
end
default:begin
next_state =IDLE;
end
endcase
end
///////////////////////////////////////////////////////
//将paper_send_req和paper_rcvd_req同步为1个时钟周期
///////////////////////////////////////////////////////
reg paper_rcvd_req_dly;
reg paper_send_req_dly;
wire paper_rcvd_req_sync;
wire paper_send_req_sync;
always@(posedge clk or posedge rst) begin
if(rst) begin
paper_rcvd_req_dly <=0;
paper_send_req_dly <=0;
end
else begin
paper_rcvd_req_dly <=paper_rcvd_req;
paper_send_req_dly <=paper_send_req;
end
end
assign paper_rcvd_req_sync = paper_rcvd_req & (~paper_rcvd_req_dly);
assign paper_send_req_sync = paper_send_req & (~paper_send_req_dly);
///////////////////////////////////////////////////////
//描述输出寄存器状态
///////////////////////////////////////////////////////
reg [31:0] last_ack;
reg [31:0] current_ack;
reg [31:0] measure_seqNo;
wire [31:0] ack_size;
assign ack_size = (rx_ackNo>measure_seqNo) ? rx_ackNo-measure_seqNo : rx_ackNo+33'h1_0000_0000-measure_seqNo;
always@(posedge clk or posedge rst) begin
if(rst) begin
cwnd_mms <=0;
event_type <=0;
last_ack <=0;
current_ack <=0;
i <=0;
measure_seqNo <=0;
cwnd_set_reg <=0;
cwnd_mms_thre <=0;
end
else begin
case(next_state)
IDLE:begin
cwnd_mms <=1;
cwnd_mms_thre <=cwnd_mss_max>>1;//16'd16;
event_type <=0;
end
SS:begin
if(paper_rcvd_req_sync) begin //慢启动阶段每收到一个ack(没有到门限没有重复ack)
current_ack <=rx_ackNo;
last_ack <=current_ack;
if(rx_ackNo!=last_ack) begin
cwnd_mms <=cwnd_mms+1'b1;
cwnd_set_reg <=1'b1;
end
end
else begin
current_ack <=current_ack;
last_ack <=last_ack;
cwnd_mms <=cwnd_mms;
cwnd_set_reg <=1'b0;
end
end
AI:begin //发送数据MMS要收到确认后才能增大1
if(i==0) begin
cwnd_set_reg <=1'b0;
if(paper_send_req_sync) begin
i <=i+1;
measure_seqNo <=tx_seqNo;
end
end
else if(i==1) begin
if(paper_rcvd_req_sync) begin
current_ack <=rx_ackNo;
last_ack <=current_ack;
if(ack_size>=real_win_size) begin //收到的确认
i <=0;
if(cwnd_mms <cwnd_mss_max) begin
cwnd_mms <=cwnd_mms+1;
cwnd_set_reg <=1'b1;
end
else begin
cwnd_mms <=cwnd_mms;
cwnd_set_reg <=1'b0;
end
end
end
else begin
cwnd_set_reg <=1'b0;
end
end
end
MD:begin
i <=0; //需要重新更新measure_seqNo
if(rtt_over_vld) begin
event_type <=1'b0;
cwnd_mms_thre <=cwnd_mms>>1;
cwnd_mms <=1;
cwnd_set_reg <=1'b1;
end
else if(dup_over_vld) begin
event_type <=1'b1;
cwnd_mms_thre <=cwnd_mms>>1;
cwnd_mms <=cwnd_mms>>1;
cwnd_set_reg <=1'b1;
end
else begin
cwnd_set_reg <=1'b0;
end
end
default:begin
end
endcase
end
end
endmodule

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/////// /// ///////////////////////////////////////////////////
//Engineer : Xiaodng Zhong
//Date : 2019.7.17
//Description: 计æ°å?
/////////////////////////////////////////////////////////////
module counter #(
parameter q_width=32
)
(
input clk,
input rst,
input clr,
input ena,
input hold,
output [q_width-1:0]q
);
reg [q_width-1:0] cnt;
assign q = cnt;
always@(posedge clk or posedge rst)begin
if(rst)begin
cnt <=0;
end
else if(clr)begin
cnt <=0;
end
else if(hold)begin
cnt <=cnt;
end
else if(ena)begin
cnt <=cnt+1;
end
end
endmodule

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///////////////////////////////////////////////////////
//Engineer : Xiaodong Zhong
//Date : 2019.6.5
//Description: monitor data of mux_demux
///////////////////////////////////////////////////////
module data_monitor(
input clk,
input nrst,
input data_en,
output reg [31:0] rate //bps
);
parameter clk_fre = 100;
localparam ms = clk_fre*1000*1000;
localparam idle = 2'd0,
cnt_data= 2'd1,
delay = 2'd2;
///////////////////////////////////////////////////////
//ms counter
///////////////////////////////////////////////////////
reg [31:0] ms_cnt;
reg [31:0] d_cnt;
reg [1:0] state;
wire start;
wire over;
///////////////////////////////////////////////////////
//ms counter
///////////////////////////////////////////////////////
always@(posedge clk or negedge nrst)begin
if(!nrst)begin
ms_cnt <=0;
end
else if(ms_cnt==(ms-1))begin
ms_cnt <=0;
end
else begin
ms_cnt <=ms_cnt+1;
end
end
assign start = (ms_cnt==3);
assign over = (ms_cnt==1);
///////////////////////////////////////////////////////
//data counter
///////////////////////////////////////////////////////
always@(posedge clk or negedge nrst)begin
if(!nrst)begin
d_cnt <=0;
state <=0;
rate <=0;
end
else begin
case(state)
idle:begin
if(start)begin
state <=cnt_data;
end
else begin
state <=idle;
end
end
cnt_data:begin
if(over && !data_en)begin
state <=delay;
d_cnt <=d_cnt;
end
else if(over && data_en)begin
state <=delay;
d_cnt <=d_cnt+1;
end
else if(!over && data_en)begin
state <=cnt_data;
d_cnt <=d_cnt+1;
end
end
delay:begin
rate <=d_cnt<<5;
d_cnt <=0;
state <=idle;
end
default:begin
state <=idle;
end
endcase
end
end
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/08/27 21:17:00
// Design Name:
// Module Name: disorder_table
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module disorder_table21(
input clk,
input rst,
input [15:0] rx_win_block,
input add,
input [31:0] sof,
input [31:0] eof,
input check,
input [31:0] ackNo_i,
output reg [31:0] ackNo_o,
output reg update,
output table_busy,
output table_full,
output table_empty
);
//========================================================
//parameter
//========================================================
localparam idle = 4'd0,
next_latch = 4'd1,
check_next = 4'd2,
part_latch = 4'd3,
check_part = 4'd4,
abort_latch = 4'd5,
check_abort = 4'd6,
check_keep = 4'd7,
check_update= 4'd8;
//========================================================
//reg & wire
//========================================================
reg [0:0] flag_mem [0:47];
reg [31:0] sof_mem [0:47];
reg [31:0] eof_mem [0:47];
reg [3:0] state;
reg [5:0] i;
wire [5:0] addr;
wire [47:0] flag;
//=======================================================
//combinational logic
//=======================================================
assign table_full = flag==48'hffff_ffff_ffff;
assign table_empty = flag==48'h0000_0000_0000;
assign table_busy = (state==idle | state==check_update) ? 1'b0 : 1'b1;
assign flag ={flag_mem[47],flag_mem[46],flag_mem[45],flag_mem[44],
flag_mem[43],flag_mem[42],flag_mem[41],flag_mem[40],
flag_mem[39],flag_mem[38],flag_mem[37],flag_mem[36],
flag_mem[35],flag_mem[34],flag_mem[33],flag_mem[32],
flag_mem[31],flag_mem[30],flag_mem[29],flag_mem[28],
flag_mem[27],flag_mem[26],flag_mem[25],flag_mem[24],
flag_mem[23],flag_mem[22],flag_mem[21],flag_mem[20],
flag_mem[19],flag_mem[18],flag_mem[17],flag_mem[16],
flag_mem[15],flag_mem[14],flag_mem[13],flag_mem[12],
flag_mem[11],flag_mem[10],flag_mem[9],flag_mem[8],
flag_mem[7],flag_mem[6],flag_mem[5],flag_mem[4],
flag_mem[3],flag_mem[2],flag_mem[1],flag_mem[0]
};
wire [47:0] next_seg;
wire [47:0] abort_seg;
wire [47:0] part_seg;
wire [47:0] keep_seg;
reg [5:0] next_addr_l;
reg [5:0] part_addr_l;
reg [5:0] abort_addr_l;
wire [5:0] next_addr;
wire [5:0] abort_addr;
wire [5:0] part_addr;
//wire [5:0] keep_addr;
genvar j;
generate
for(j=0;j<48;j=j+1)begin:seg_type_loop
assign next_seg[j] = flag_mem[j]==0 ? 1'b0 : (sof_mem[j]==ackNo_o);
assign part_seg[j] = flag_mem[j]==0 ? 1'b0 : ((eof_mem[j]-sof_mem[j])>(ackNo_o-sof_mem[j]) && ackNo_o!=sof_mem[j]);
assign abort_seg[j] = flag_mem[j]==0 ? 1'b0 : ((ackNo_o-sof_mem[j])>(ackNo_o-eof_mem[j]) && (ackNo_o-sof_mem[j]) <=rx_win_block);
assign keep_seg[j] = flag_mem[j]==0 ? 1'b0 : ((eof_mem[j]-ackNo_o)>(sof_mem[j]-ackNo_o) && (eof_mem[j]-ackNo_o)<=rx_win_block && ackNo_o!=sof_mem[j]);
end
endgenerate
//
tmp_decode U_add_tmp(
.din (flag ),
.tmp_code (addr )
);
//
tmp_decode U_next_tmp(
.din (~next_seg ),
.tmp_code (next_addr )
);
//
tmp_decode U_part_tmp(
.din (~part_seg ),
.tmp_code (part_addr )
);
//
tmp_decode U_abort_tmp(
.din (~abort_seg ),
.tmp_code (abort_addr )
);
//
/*
tmp_decode U_keep_tmp(
.din (keep_seg ),
.tmp_code (keep_addr )
);*/
//=======================================================
//fsm
//=======================================================
always@(posedge clk or posedge rst)begin
if(rst)begin
state <=0;
i<=0;
ackNo_o <=0;
update <=0;
next_addr_l <=0;
part_addr_l <=0;
abort_addr_l<=0;
flag_mem[0] <=0;
flag_mem[1] <=0;
flag_mem[2] <=0;
flag_mem[3] <=0;
flag_mem[4] <=0;
flag_mem[5] <=0;
flag_mem[6] <=0;
flag_mem[7] <=0;
flag_mem[8] <=0;
flag_mem[9] <=0;
flag_mem[10] <=0;
flag_mem[11] <=0;
flag_mem[12] <=0;
flag_mem[13] <=0;
flag_mem[14] <=0;
flag_mem[15] <=0;
flag_mem[16] <=0;
flag_mem[17] <=0;
flag_mem[18] <=0;
flag_mem[19] <=0;
flag_mem[20] <=0;
flag_mem[21] <=0;
flag_mem[22] <=0;
flag_mem[23] <=0;
flag_mem[24] <=0;
flag_mem[25] <=0;
flag_mem[26] <=0;
flag_mem[27] <=0;
flag_mem[28] <=0;
flag_mem[29] <=0;
flag_mem[30] <=0;
flag_mem[31] <=0;
flag_mem[32] <=0;
flag_mem[33] <=0;
flag_mem[34] <=0;
flag_mem[35] <=0;
flag_mem[36] <=0;
flag_mem[37] <=0;
flag_mem[38] <=0;
flag_mem[39] <=0;
flag_mem[40] <=0;
flag_mem[41] <=0;
flag_mem[42] <=0;
flag_mem[43] <=0;
flag_mem[44] <=0;
flag_mem[45] <=0;
flag_mem[46] <=0;
flag_mem[47] <=0;
end
else begin
case(state)
idle:begin
ackNo_o <=ackNo_i;
update <=0;
if(add)begin
flag_mem[addr] <=1'b1;
sof_mem[addr] <=sof;
eof_mem[addr] <=eof;
end
else if(check)begin
state <=next_latch;
end
end
next_latch:begin
next_addr_l <=next_addr;
state <=check_next;
end
check_next:begin
if(next_seg==48'b0)begin
state <=part_latch;
end
else begin
flag_mem[next_addr_l] <=1'b0;
ackNo_o <=eof_mem[next_addr_l]==32'hffff_ffff ? 32'h0 : eof_mem[next_addr_l]+1;
state <=next_latch;
end
end
part_latch:begin
part_addr_l <=part_addr;
state <=check_part;
end
check_part:begin
if(next_seg!=0)begin
state <=next_latch;
end
else if(part_seg==48'b0)begin
//state <=check_abort;
state <=abort_latch;
end
else begin
flag_mem[part_addr_l] <=1'b0;
ackNo_o <=eof_mem[part_addr_l]==32'hffff_ffff ? 32'h0 : eof_mem[part_addr_l]+1;
state <=part_latch;
end
end
abort_latch:begin
abort_addr_l <=abort_addr;
state <=check_abort;
end
check_abort:begin
if(abort_seg==48'b0)begin
state <=check_keep;
end
else begin
flag_mem[abort_addr_l] <=1'b0;
state <=abort_latch;
end
end
check_keep:begin
if(i==48 || table_empty)begin
i <=0;
state <=check_update;
end
else begin
i <=i+1;
flag_mem[i] <= keep_seg[i] ? 1'b1 : 1'b0;
end
end
check_update:begin
state <=idle;
end
default:begin
state <=idle;
end
endcase
end
end
//=============================================================
//ila_200 ila_disorder(
// .clk (clk ),
// .probe0 ({
// wr_state, //3
// send_type, //2
// tw_seq_num, //32
// Sf, //32
// Sn, //32
// Sw, //32
// isn_set, //1
// isn, //32
// rwnd_set, //1
// rwnd, //16
// 17'd0
// })
//);
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/09/29 16:21:43
// Design Name:
// Module Name: icmp_processor
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`define echo_request 16'h0800
`define echo_reply 16'h0000
`define time_request 16'h0d00
`define time_reply 16'h0e00
module icmp_processor(
input clk,
input rst,
input [31:0] local_time,
////host issue
input host_req,
output reg host_grant,
input [31:0] host_dst_ip,
input [15:0] host_type_code,
input [11:0] host_tx_len,
input [31:0] host_time,
output host_intr,
output [31:0] host_remote_time,
output reg host_error,
//icmp recv issue
input icmp_recv_req,
output reg icmp_recv_grant,
input [31:0] rx_src_ip,
input [11:0] rx_len,
input [15:0] rx_type_code,
input [31:0] rx_id_seq,
input [31:0] rx_tx_timestamp,
input [31:0] rx_rx_timestamp,
input [31:0] rx_data_chksum,
input info_fifo_empty,
output info_fifo_rden,
input [7:0] info_fifo_rddata,
//icmp send issue
output reg icmp_send_req,
input icmp_send_grant,
output reg [31:0] tx_data_chksum,
output reg [31:0] tx_dst_ip,
output reg [15:0] tx_type_code,
output reg [11:0] tx_len,
output reg [31:0] tx_id_seq,
output reg [31:0] tx_local_timestamp,
output reg [31:0] tx_remote_timestamp,
output info_sel
);
//////////////////////////////////////////////////////////////////////////////////////
//parameter
//////////////////////////////////////////////////////////////////////////////////////
localparam idle = 3'd0,
host_issue = 3'd1,
recv_issue = 3'd2,
send_issue = 3'd3,
data_check = 3'd4;
//////////////////////////////////////////////////////////////////////////////////////
//wire
//////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////
//reg
//////////////////////////////////////////////////////////////////////////////////////
reg [2:0] state;
reg [31:0] host_dst_ip_reg;
reg [15:0] host_type_code_reg;
reg [11:0] host_tx_len_reg;
reg [31:0] host_time_reg;
reg [15:0] seq;
reg [11:0] i;
reg rd_ready;
//////////////////////////////////////////////////////////////////////////////////////
//combinational logic
//////////////////////////////////////////////////////////////////////////////////////
assign info_fifo_rden = ~info_fifo_empty & rd_ready;
assign info_sel = state == data_check ? 1'b1 : 1'b0;
assign host_intr =1'b0;
assign host_remote_time = 32'b0;
//////////////////////////////////////////////////////////////////////////////////////
//fsm
//////////////////////////////////////////////////////////////////////////////////////
always@(posedge clk or posedge rst)begin
if(rst)begin
state <=0;
host_dst_ip_reg <=0;
host_type_code_reg <=0;
host_tx_len_reg <=0;
host_time_reg <=0;
icmp_recv_grant <=0;
i <=0;
rd_ready <=0;
host_error <=0;
host_grant <=0;
seq <=0;
//seq <=16'hff06;
tx_data_chksum <=0;
tx_dst_ip <=0;;
tx_type_code <=0;
tx_len <=0;
tx_id_seq <=0;
tx_local_timestamp <=0;
tx_remote_timestamp <=0;
icmp_send_req <=0;
end
else begin
case(state)
idle:begin
icmp_recv_grant <=1'b0;
if(host_req)begin
host_error <=0;
host_grant <=1'b1;
state <=host_issue;
tx_dst_ip <=host_dst_ip;;
tx_type_code <=host_type_code;
tx_len <=host_tx_len;
tx_id_seq <={16'h0001,seq};
tx_local_timestamp <=local_time;
tx_remote_timestamp<=rx_tx_timestamp;
seq <=seq+1;
end
else if(icmp_recv_req & ~icmp_recv_grant)begin
state <=recv_issue;
//tx_local_timestamp <=local_time;
//tx_remote_timestamp <=rx_tx_timestamp;
end
end
host_issue:begin
host_grant <=1'b0;
state <=send_issue;
if(tx_type_code==`echo_request)begin //(0+255)*256/2=32640
if(tx_len[0]==0)begin
tx_data_chksum <=16'habab*(tx_len>>1);
// tx_data_chksum <=16'hf8f8*(tx_len>>1);
end
else begin
tx_data_chksum <=(16'habab*(tx_len-1)>>1)+16'hab00;
//tx_data_chksum <=(16'hf7f7*(tx_len-1)>>1)+16'hf700;
end
end
else if(tx_type_code==`time_request)begin
tx_data_chksum <=tx_local_timestamp[15:0]+tx_local_timestamp[31:16];
end
end
recv_issue:begin
icmp_recv_grant <=1'b1;
if(rx_type_code==`echo_request)begin
tx_data_chksum <=rx_data_chksum;
tx_dst_ip <=rx_src_ip;
tx_type_code <=`echo_reply;
tx_len <=rx_len;
tx_id_seq <=rx_id_seq;
state <=send_issue;
end
else if(rx_type_code==`echo_reply)begin
rd_ready <=1;
state <=data_check;
end
else if(rx_type_code==`time_request)begin
tx_data_chksum <=rx_tx_timestamp[31:16]+rx_tx_timestamp[15:0]+((local_time[31:16]+local_time[15:0])<<1);
tx_dst_ip <=rx_src_ip;
tx_type_code <=`time_reply;
tx_len <=12;
tx_id_seq <=rx_id_seq;
tx_local_timestamp <=local_time;
tx_remote_timestamp <=rx_tx_timestamp;
state <=send_issue;
end
else if(rx_type_code==`time_reply)begin
state <=idle;
end
end
send_issue:begin
icmp_recv_grant <=1'b0;
if(i==0)begin
icmp_send_req <=1;
i <=i+1;
end
else if(i==1)begin
if(icmp_send_grant)begin
icmp_send_req <=0;
i <=0;
state <=idle;
end
else begin
i <=i;
end
end
end
data_check:begin
icmp_recv_grant <=1'b0;
if(info_fifo_rden)begin
host_error <=info_fifo_rddata!=8'hab ? 1'b1 : host_error;
if(i==(rx_len-1))begin
i <=0;
rd_ready <=0;
state<=idle;
end
else begin
i <=i+1;
end
end
end
default:begin
state <=idle;
end
endcase
end
end
endmodule

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@ -0,0 +1,469 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/08/20 11:19:56
// Design Name:
// Module Name: icmp_recv
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
//format
//+---------------------------------------------------------------------+
//| type(8) | code(8) | checksum(16) |
//+---------------------------------------------------------------------+
//| content |
//+---------------------------------------------------------------------+
//
//时间戳
//+---------------------------------------------------------------------+
//|标识符(16) | 序列号(16) |
//+---------------------------------------------------------------------+
//| 发送时间戳 |
//+---------------------------------------------------------------------+
//| 接收时间戳 |
//+---------------------------------------------------------------------+
//| 传送时间戳 |
//+---------------------------------------------------------------------+
//回显
//+---------------------------------------------------------------------+
//|标识符(16) | 序列号(16) |
//+---------------------------------------------------------------------+
//| 选项数据 |
//+---------------------------------------------------------------------+
//+---------------------------------------------------------------------+
//| type | code | description |
//+---------------------------------------------------------------------+
//| 0 | 0 | 回显应答 |
//+----------------------------------------------------------------------
//| 8 | 0 | 回显请求 |
//+---------------------------------------------------------------------+
//| 13 | 0 | 时间戳请求 |
//+---------------------------------------------------------------------+
//| 14 | 0 | 时间戳应答 |
//+--------------------------------------------------------------------+
//icmp_paper+src_ip
//////////////////////////////////////////////////////////////////////////////////
module icmp_recv(
input clk,
input rst,
output reg req,
input grant,
output reg [31:0] src_ip,
output reg [11:0] rx_len,
output reg [31:0] rx_data_chksum,
output reg [15:0] type_code,
output reg [31:0] logo_seq,
output reg [31:0] tx_timestamp,
output reg [31:0] rx_timestamp,
input info_fifo_af,
output reg info_fifo_clr,
output reg info_fifo_wren,
output reg [7:0] info_fifo_wrdata,
input icmp_recv_fifo_empty,
output icmp_recv_fifo_rden,
input [8:0] icmp_recv_fifo_rddata
);
//////////////////////////////////////////////
//参数
//////////////////////////////////////////////
localparam rd_idle = 2'd0,
rd_frame = 2'd1,
rd_srcip = 2'd2,
rd_handle = 2'd3;
localparam dfm_type_code = 3'd0,
dfm_chk = 3'd1,
dfm_logo_seq = 3'd2,
dfm_echo_req = 3'd3,
dfm_echo_rep = 3'd4,
dfm_time_req = 3'd5,
dfm_time_rep = 3'd6,
dfm_error = 3'd7;
localparam H = 1'b0,
L = 1'b1;
//////////////////////////////////////////////
//reg & wire
//////////////////////////////////////////////
reg [2:0] rd_state;
reg [1:0] rd_cnt;
reg rd_ready;
reg frm_vld;
wire [7:0] frm_data;
reg [3:0] dfm_state;
reg [15:0] i;
reg [15:0] check_buffer;
reg [31:0] check_sum;
wire [31:0] ncheck_sum;
reg HL;
//reg [15:0] data_buffer ;
wire chk_right;
//reg [11:0] rx_len;
assign icmp_recv_fifo_rden = ~icmp_recv_fifo_empty & rd_ready;
//////////////////////////////////////////////////////////////////////////////////////////////
//读出一帧icmp数据
//////////////////////////////////////////////////////////////////////////////////////////////
always@(posedge clk or posedge rst)begin
if(rst)begin
rd_state <=0;
rd_cnt <=0;
rd_ready <=0;
src_ip <=0;
frm_vld <=0;
info_fifo_clr <=0;
req <=0;
//rx_len <=0;
end
else begin
case(rd_state)
rd_idle:begin
info_fifo_clr <=0;
if(!icmp_recv_fifo_empty && dfm_state==dfm_type_code)begin //接收缓冲区有数据解帧能工作
frm_vld <=1;
rd_ready <=1;
rd_state <=rd_frame;
end
else begin
end
end
rd_frame:begin
if(icmp_recv_fifo_rden)begin
if(!icmp_recv_fifo_rddata[8])begin
rd_state <=rd_frame;
frm_vld <=1'b1;
end
else if(icmp_recv_fifo_rddata[8])begin
rd_state <=rd_srcip;
frm_vld <=1'b0;
end
else begin
rd_state <=rd_frame;
end
end
else begin
frm_vld <=0;
end
end
rd_srcip:begin
if(icmp_recv_fifo_rden)begin
src_ip <={src_ip[23:0],icmp_recv_fifo_rddata[7:0]};
if(rd_cnt==2'd3)begin
rd_ready <=0;
rd_cnt <=0;
rd_state <=rd_handle;
end
else begin
rd_cnt <=rd_cnt+1;
rd_state <=rd_srcip;
end
end
else begin
src_ip <=src_ip;
rd_cnt <=rd_cnt;
end
end
rd_handle:begin
if(rd_cnt==0)begin
if(dfm_state==dfm_error)begin
rd_cnt <=0;
info_fifo_clr <=1;
rd_state <=rd_idle;
end
else if(chk_right)begin
rd_cnt <=rd_cnt+1;
req <=1;
end
else begin
rd_cnt <=0;
info_fifo_clr <=1;
rd_state <=rd_idle;
end
end
else if(rd_cnt==1)begin
if(grant)begin
req <=0;
rd_cnt <=0;
rd_state <=rd_idle;
end
else begin
rd_cnt <=rd_cnt;
rd_state <=rd_handle;
end
end
end
default:begin
rd_state <=rd_idle;
end
endcase
end
end
assign frm_data = icmp_recv_fifo_rddata[7:0];
//assign frm_vld = icmp_recv_fifo_rden & rd_state!=rd_srcip;
//////////////////////////////////////////////////////////////////////////////////////////////
//计算校验和
//////////////////////////////////////////////////////////////////////////////////////////////
always@(posedge clk or posedge rst)begin
if(rst)begin
check_buffer <=0;
check_sum <=0;
HL <=0;
rx_data_chksum <=0;
end
else if(frm_vld) begin
check_buffer <={check_buffer[7:0],frm_data};
case(HL)
H:begin
HL <=~HL;
end
L:begin
check_sum <=check_sum+{check_buffer[7:0],frm_data};
if(dfm_state==dfm_echo_req)begin
rx_data_chksum <=rx_data_chksum+{check_buffer[7:0],frm_data};
end
else begin
rx_data_chksum <=rx_data_chksum;
end
HL <=~HL;
end
default:begin
HL <=H;
end
endcase
end
else if(rd_state==rd_srcip && frm_vld==1'b0 && rd_cnt==2'd0)begin
if(HL==H)begin
check_sum <=check_sum;
end
else begin
check_sum <=check_sum+{check_buffer[7:0],8'h00};
rx_data_chksum <=rx_data_chksum+{check_buffer[7:0],8'h00};
end
end
else if(rd_state==rd_handle && grant)begin
check_buffer <=0;
check_sum <=0;
HL <=0;
rx_data_chksum <=0;
end
end
assign ncheck_sum =~(check_sum[31:16]+check_sum[15:0]);
assign chk_right =ncheck_sum[15:0] == 16'h0000;
//////////////////////////////////////////////////////////////////////////////////////////////
//解帧
//////////////////////////////////////////////////////////////////////////////////////////////
always@(posedge clk or posedge rst)begin
if(rst)begin
dfm_state <=0;
i <=0;
type_code <=0;
logo_seq <=0;
tx_timestamp <=0;
rx_timestamp <=0;
info_fifo_wren <=0;
info_fifo_wrdata <=0;
rx_len <=0;
end
else begin
case(dfm_state)
dfm_type_code:begin
info_fifo_wren <=0;
if(frm_vld )begin
type_code <={type_code[7:0],frm_data[7:0]};
if(i==0)begin
//if(frm_data== 8'd0 || frm_data == 8'd8 || frm_data == 8'd13 || frm_data == 8'd14)begin
if(frm_data== 8'd0 || frm_data == 8'd8 )begin
i <=i+1;
end
else begin
i <=0;
dfm_state <=dfm_error;
end
end
else if(i==1)begin
if(frm_data == 8'd0)begin
i <=0;
dfm_state <=dfm_chk;
end
else begin
i <=0;
dfm_state <=dfm_error;
end
end
end
else begin
dfm_state <=dfm_type_code;
end
end
dfm_chk:begin
rx_len <=0;
if(frm_vld)begin
if(i==1)begin
i <=0;
dfm_state <=dfm_logo_seq;
end
else begin
i <=i+1;
end
end
else begin
i <=i;
dfm_state <=dfm_chk;
end
end
dfm_logo_seq:begin
if(frm_vld)begin
logo_seq <={logo_seq[23:0],frm_data[7:0]};
if(i==3)begin
i <=0;
dfm_state <= type_code == {8'd0,8'd0} ? dfm_echo_rep :
type_code == {8'd8,8'd0} ? dfm_echo_req :
type_code == {8'd13,8'd0} ? dfm_time_req :
type_code == {8'd14,8'd0} ? dfm_time_rep : dfm_error;
end
else begin
i <=i+1;
end
end
else begin
i <=i;
dfm_state <=dfm_logo_seq;
end
end
dfm_echo_req:begin
if(frm_vld & !icmp_recv_fifo_rddata[8])begin
rx_len <=rx_len+1;
info_fifo_wren <=1;
info_fifo_wrdata <=frm_data;
end
else if(frm_vld & icmp_recv_fifo_rddata[8])begin
rx_len <=rx_len+1;
info_fifo_wren <=1;
info_fifo_wrdata <=frm_data;
dfm_state <=dfm_type_code;
end
else begin
rx_len <=rx_len;
info_fifo_wren <=0;
info_fifo_wrdata <=info_fifo_wrdata;
dfm_state <=dfm_echo_req;
end
end
dfm_echo_rep:begin
if(frm_vld & !icmp_recv_fifo_rddata[8])begin
rx_len <=rx_len+1;
info_fifo_wren <=1;
info_fifo_wrdata <=frm_data;
end
else if(frm_vld & icmp_recv_fifo_rddata[8])begin
rx_len <=rx_len+1;
info_fifo_wren <=1;
info_fifo_wrdata <=frm_data;
dfm_state <=dfm_type_code;
end
else begin
rx_len <=rx_len;
info_fifo_wren <=0;
info_fifo_wrdata <=info_fifo_wrdata;
dfm_state <=dfm_echo_rep;
end
end
dfm_time_req:begin
if(frm_vld)begin
if(i<=3)begin
i <=i+1;
tx_timestamp <={tx_timestamp[23:0],frm_data[7:0]};
end
else if(i<=7)begin
i <=i+1;
rx_timestamp <={rx_timestamp[23:0],frm_data[7:0]};
end
else if(i==11)begin
i <=0;
dfm_state <=dfm_type_code;
end
else begin
i <=i+1;
end
end
else begin
i <=i;
end
end
dfm_time_rep:begin
if(frm_vld)begin
if(i<=3)begin
i <=i+1;
tx_timestamp <={tx_timestamp[23:0],frm_data[7:0]};
end
else if(i<=7)begin
i <=i+1;
rx_timestamp <={rx_timestamp[23:0],frm_data[7:0]};
end
else if(i==11)begin
i <=0;
dfm_state <=dfm_type_code;
end
else begin
i <=i+1;
end
end
else begin
i <=i;
end
end
dfm_error:begin
if(!icmp_recv_fifo_rden)begin
dfm_state <=dfm_type_code;
end
else begin
dfm_state <=dfm_error;
end
end
default:begin
dfm_state <=dfm_type_code;
end
endcase
end
end
endmodule

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@ -0,0 +1,307 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/09/29 12:02:32
// Design Name:
// Module Name: icmp_send
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module icmp_send(
input clk,
input rst,
input req,
output reg grant,
input [31:0] data_chksum,
input [31:0] dst_ip,
input [15:0] type_code,
input [11:0] tx_len,
input [31:0] id_seq,
input [31:0] local_timestamp,
input [31:0] remote_timestamp,
input info_fifo_empty,
output info_fifo_rden,
input [7:0] info_fifo_rddata,
output reg icmp_send_req,
input icmp_send_grant,
output reg [31:0] icmp_send_dst_ip,
output reg [15:0] icmp_send_len,
input icmp_send_fifo_af,
output reg icmp_send_fifo_wren,
output reg [7:0] icmp_send_fifo_wrdata
);
/////////////////////////////////////////////////////////////////////////////////////
//parameter
/////////////////////////////////////////////////////////////////////////////////////
localparam idle = 4'd0,
send_type_code_sum = 4'd1,
send_id_seq = 4'd2,
send_echo_req = 4'd3,
send_echo_rep = 4'd4,
send_time_req = 4'd5,
send_time_rep = 4'd6,
send_launch = 4'd7;
/////////////////////////////////////////////////////////////////////////////////////
//wire
/////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////
//reg
/////////////////////////////////////////////////////////////////////////////////////
reg [3:0] state;
reg [11:0] i;
reg [31:0] data_chksum_reg;
reg [31:0] dst_ip_reg;
reg [15:0] type_code_reg;
reg [11:0] tx_len_reg;
reg [31:0] id_seq_reg;
reg [31:0] local_timestamp1_reg;
reg [31:0] local_timestamp2_reg;
reg [31:0] remote_timestamp_reg;
reg [31:0] icmp_chksum;
reg info_rd_ready;
/////////////////////////////////////////////////////////////////////////////////////
//combinational logic
/////////////////////////////////////////////////////////////////////////////////////
assign info_fifo_rden = ~info_fifo_empty & info_rd_ready & ~icmp_send_fifo_af;
/////////////////////////////////////////////////////////////////////////////////////
//fsm
/////////////////////////////////////////////////////////////////////////////////////
always@(posedge clk or posedge rst)begin
if(rst)begin
state <=0;
data_chksum_reg <=0;
dst_ip_reg <=0;
type_code_reg <=0;
tx_len_reg <=0;
id_seq_reg <=0;
local_timestamp1_reg <=0;
local_timestamp2_reg <=0;
remote_timestamp_reg <=0;
grant <=0;
icmp_chksum <=0;
info_rd_ready <=0;
icmp_send_req <=0;
icmp_send_dst_ip <=0;
icmp_send_len <=0;
icmp_send_fifo_wren <=0;
icmp_send_fifo_wrdata <=0;
i <=0;
end
else begin
case(state)
idle:begin
if(req)begin
state <=send_type_code_sum;
grant <=1'b1;
data_chksum_reg <=data_chksum;
dst_ip_reg <=dst_ip;
type_code_reg <=type_code;
tx_len_reg <=tx_len;
id_seq_reg <=id_seq;
local_timestamp1_reg <=local_timestamp;
local_timestamp2_reg <=local_timestamp;
remote_timestamp_reg <=remote_timestamp;
icmp_chksum <=type_code+id_seq[31:16]+id_seq[15:0]+data_chksum;
end
else begin
state <=idle;
end
end
send_type_code_sum:begin
grant <=1'b0;
if(!icmp_send_fifo_af)begin
if(i==0)begin
icmp_chksum <=icmp_chksum[31:16]+icmp_chksum[15:0];
i <=i+1;
icmp_send_fifo_wren <=1;
icmp_send_fifo_wrdata <=type_code_reg[15:8];
end
else if(i==1)begin
icmp_chksum <=icmp_chksum[31:16]+icmp_chksum[15:0];
i <=i+1;
icmp_send_fifo_wren <=1;
icmp_send_fifo_wrdata <=type_code_reg[7:0];
end
else if(i==2)begin
i <=i+1;
icmp_send_fifo_wren <=1;
icmp_send_fifo_wrdata <=~icmp_chksum[15:8];
end
else if(i==3)begin
i <=0;
state <=send_id_seq;
icmp_send_fifo_wren <=1;
icmp_send_fifo_wrdata <=~icmp_chksum[7:0];
end
end
else begin
icmp_send_fifo_wren <=0;
end
end
send_id_seq:begin
if(!icmp_send_fifo_af)begin
icmp_send_fifo_wren <=1;
icmp_send_fifo_wrdata <=id_seq_reg[31:24];
id_seq_reg <=id_seq_reg <<8;
if(i==3)begin
i <=0;
state <=type_code == {8'd0,8'd0} ? send_echo_rep :
type_code == {8'd8,8'd0} ? send_echo_req :
type_code == {8'd13,8'd0} ? send_time_req :
type_code == {8'd14,8'd0} ? send_time_rep : 0;
info_rd_ready <=type_code == {8'd0,8'd0} ? 1'b1 : 1'b0;
end
else begin
i <=i+1;
end
end
else begin
icmp_send_fifo_wren <=0;
end
end
send_echo_rep:begin
if(info_fifo_rden)begin
icmp_send_fifo_wren <=1;
icmp_send_fifo_wrdata <=info_fifo_rddata;
if(i==(tx_len-1))begin
i <=0;
info_rd_ready <=0;
state <=send_launch;
end
else begin
i <=i+1;
end
end
else begin
icmp_send_fifo_wren <=0;
icmp_send_fifo_wrdata <=icmp_send_fifo_wrdata;
end
end
send_echo_req:begin
if(!icmp_send_fifo_af)begin
icmp_send_fifo_wren <=1;
icmp_send_fifo_wrdata <=8'hab;
//icmp_send_fifo_wrdata <=8'hf8;
if(i==(tx_len-1))begin
i <=0;
state <=send_launch;
end
else begin
i <=i+1;
end
end
else begin
icmp_send_fifo_wren <=0;
end
end
send_time_req:begin
if(!icmp_send_fifo_af)begin
icmp_send_fifo_wren <=1;
if(i<=3)begin
i <=i+1;
icmp_send_fifo_wrdata <=local_timestamp1_reg[31:24];
local_timestamp1_reg <=local_timestamp1_reg<<8;
end
else if(i==11)begin
i <=0;
state <=send_launch;
icmp_send_fifo_wrdata <=8'h00;
end
else begin
i <=i+1;
icmp_send_fifo_wrdata <=8'h00;
end
end
else begin
icmp_send_fifo_wren <=0;
end
end
send_time_rep:begin
if(!icmp_send_fifo_af)begin
icmp_send_fifo_wren <=1;
if(i<=3)begin
i <=i+1;
icmp_send_fifo_wrdata <=remote_timestamp_reg[31:24];
remote_timestamp_reg <=remote_timestamp_reg<<8;
end
else if(i<=7)begin
i <=i+1;
icmp_send_fifo_wrdata <=local_timestamp1_reg[31:24];
local_timestamp1_reg <=local_timestamp1_reg<<8;
end
else if(i<=12)begin
icmp_send_fifo_wrdata <=local_timestamp2_reg[31:24];
local_timestamp2_reg <=local_timestamp2_reg<<8;
if(i==11)begin
i <=0;
state <=send_launch;
end
else begin
i <=i+1;
end
end
end
else begin
icmp_send_fifo_wren <=0;
end
end
send_launch:begin
if(i==0)begin
icmp_send_fifo_wren <=0;
icmp_send_req <=1;
icmp_send_dst_ip <=dst_ip_reg;
icmp_send_len <=tx_len+8;
i <=i+1;
end
else if(i==1)begin
if(icmp_send_grant)begin
icmp_send_req <=0;
i <=0;
state <=idle;
end
else begin
i <=i;
state <=send_launch;
end
end
end
default:begin
state <=idle;
end
endcase
end
end
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/08/20 11:19:56
// Design Name:
// Module Name: icmp_recv
//
// Description:
// 接收报文回送请求<EFBFBD>?<EFBFBD><EFBFBD>?
// 每次发<EFBFBD>?<EFBFBD>回送请求后开启计时器收到回送应答后停止计时计算环回时间
//////////////////////////////////////////////////////////////////////////////////
module icmp_top(
input clk,
input rst,
input ms_ck,
input host_req,
output host_grant,
input [31:0] host_dst_ip,
input [31:0] host_type_code,
input [11:0] host_tx_len,
output host_intr,
output [31:0] host_intr_state,
output [63:0] host_time, //tx_time+rx_time
input icmp_recv_fifo_empty,
output icmp_recv_fifo_rden,
input [8:0] icmp_recv_fifo_rddata,
output icmp_send_req,
input icmp_send_grant,
output [31:0] icmp_send_dst_ip,
output [15:0] icmp_send_len,
output icmp_send_fifo_empty,
input icmp_send_fifo_rden,
output [7:0] icmp_send_fifo_rddata
);
/////////////////////////////////////////////////////////////////////////////////////
//wire
/////////////////////////////////////////////////////////////////////////////////////
wire icmp_rx_req;
wire icmp_rx_grant;
wire [31:0] rx_src_ip;
wire [11:0] rx_len;
wire [15:0] rx_type_code;
wire [31:0] rx_id_seq;
wire [31:0] rx_tx_timestamp;
wire [31:0] rx_rx_timestamp;
wire [31:0] rx_data_chksum;
wire info_fifo_af;
wire info_fifo_clr;
wire info_fifo_wren;
wire [7:0] info_fifo_wrdata;
wire info_fifo_empty;
wire info_fifo_rden;
wire [7:0] info_fifo_rddata;
wire info_fifo_rden_1;
wire info_fifo_rden_2;
wire icmp_send_fifo_af;
wire icmp_send_fifo_wren;
wire [7:0] icmp_send_fifo_wrdata;
wire icmp_tx_req;
wire icmp_tx_grant;
wire [31:0] tx_data_chksum;
wire [31:0] tx_dst_ip;
wire [15:0] tx_type_code;
wire [11:0] tx_len;
wire [31:0] tx_id_seq;
wire [31:0] tx_local_timestamp;
wire [31:0] tx_remote_timestamp;
reg [31:0] local_time;
wire info_sel;
/////////////////////////////////////////////////////////////////////////////////////
//combinational logic
/////////////////////////////////////////////////////////////////////////////////////
assign info_fifo_rden = info_sel==0 ? info_fifo_rden_1 : info_fifo_rden_2;
assign host_intr_state = 32'b0;
assign host_time = 64'b0; //tx_time+rx_time
/////////////////////////////////////////////////////////////////////////////////////
//module
/////////////////////////////////////////////////////////////////////////////////////
always@(posedge clk or posedge rst)begin
if(rst)begin
local_time <=0;
end
//else if(ms_ck)begin
else begin
local_time <=local_time+1;
end
//else begin
// local_time <=local_time;
//end
end
//----------------------------------------------------------------\\
icmp_recv U_icmp_recv(
.clk (clk ),
.rst (rst ),
.req (icmp_rx_req ),
.grant (icmp_rx_grant ),
//rx info
.src_ip (rx_src_ip ),
.rx_len (rx_len ),
.rx_data_chksum (rx_data_chksum ),
.type_code (rx_type_code ),
.logo_seq (rx_id_seq ),
.tx_timestamp (rx_tx_timestamp ),
.rx_timestamp (rx_rx_timestamp ),
.info_fifo_af (info_fifo_af ),
.info_fifo_clr (info_fifo_clr ),
.info_fifo_wren (info_fifo_wren ),
.info_fifo_wrdata (info_fifo_wrdata ),
.icmp_recv_fifo_empty (icmp_recv_fifo_empty ),
.icmp_recv_fifo_rden (icmp_recv_fifo_rden ),
.icmp_recv_fifo_rddata (icmp_recv_fifo_rddata )
);
//----------------------------------------------------------------\\
syn_fwft_fifo #(
.width (8),
.depth (2048))
U_icmp_info_fifo(
.clk (clk ),
.rst (rst ),
.clr (info_fifo_clr ),
.wr_en (info_fifo_wren ),
.din (info_fifo_wrdata ),
.full (),
.almost_full (info_fifo_af ),
.rd_en (info_fifo_rden ),
.dout (info_fifo_rddata ),
.empty (info_fifo_empty )
);
//----------------------------------------------------------------\\
icmp_send U_icmp_send(
.clk (clk ),
.rst (rst ),
.req (icmp_tx_req ),
.grant (icmp_tx_grant ),
.data_chksum (tx_data_chksum ),
.dst_ip (tx_dst_ip ),
.type_code (tx_type_code ),
.tx_len (tx_len ),
.id_seq (tx_id_seq ),
.local_timestamp (tx_local_timestamp ),
.remote_timestamp (tx_remote_timestamp ),
.info_fifo_empty (info_fifo_empty ),
.info_fifo_rden (info_fifo_rden_1 ),
.info_fifo_rddata (info_fifo_rddata ),
.icmp_send_req (icmp_send_req ),
.icmp_send_grant (icmp_send_grant ),
.icmp_send_dst_ip (icmp_send_dst_ip ),
.icmp_send_len (icmp_send_len ),
.icmp_send_fifo_af (icmp_send_fifo_af ),
.icmp_send_fifo_wren (icmp_send_fifo_wren ),
.icmp_send_fifo_wrdata (icmp_send_fifo_wrdata )
);
//----------------------------------------------------------------\\
syn_fwft_fifo #(
.width (8),
.depth (2048))
U_icmp_send_fifo(
.clk (clk ),
.rst (rst ),
.clr (1'b0 ),
.wr_en (icmp_send_fifo_wren ),
.din (icmp_send_fifo_wrdata ),
.full (),
.almost_full (icmp_send_fifo_af ),
.rd_en (icmp_send_fifo_rden ),
.dout (icmp_send_fifo_rddata ),
.empty (icmp_send_fifo_empty )
);
//----------------------------------------------------------------\\
icmp_processor U_icmp_processor(
.clk (clk ),
.rst (rst ),
.local_time (local_time ),
.host_req (host_req ),
.host_grant (host_grant ),
.host_dst_ip (host_dst_ip ),
.host_type_code (host_type_code[15:0] ),
.host_tx_len (host_tx_len ),
.host_time (),
.host_intr (host_intr ),
.host_remote_time (),
.host_error (),
//icmp recv issue
.icmp_recv_req (icmp_rx_req ),
.icmp_recv_grant (icmp_rx_grant ),
.rx_src_ip (rx_src_ip ),
.rx_len (rx_len ),
.rx_type_code (rx_type_code ),
.rx_id_seq (rx_id_seq ),
.rx_tx_timestamp (rx_tx_timestamp ),
.rx_rx_timestamp (rx_rx_timestamp ),
.rx_data_chksum (rx_data_chksum ),
.info_fifo_empty (info_fifo_empty ),
.info_fifo_rden (info_fifo_rden_2 ),
.info_fifo_rddata (info_fifo_rddata ),
.icmp_send_req (icmp_tx_req ),
.icmp_send_grant (icmp_tx_grant ),
.tx_data_chksum (tx_data_chksum ),
.tx_dst_ip (tx_dst_ip ),
.tx_type_code (tx_type_code ),
.tx_len (tx_len ),
.tx_id_seq (tx_id_seq ),
.tx_local_timestamp (tx_local_timestamp ),
.tx_remote_timestamp (tx_remote_timestamp ),
.info_sel (info_sel )
);
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2020/04/07 08:02:28
// Design Name:
// Module Name: ip_packet_drop
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ip_packet_drop(
input wire clk,
input wire rst,
input wire recv_fifo_wren,
input wire [8:0] recv_fifo_wrdata,
input wire recv_fifo_af,
output reg recv_fifo_wren_int,
output reg [8:0] recv_fifo_wrdata_int,
output reg [31:0]drop_cnt
);
localparam wr_idle = 2'd0,
wr_ok = 2'd1,
wr_fail = 2'd2;
reg [1:0] over_state;
reg [2:0] cnt;
reg frame_over;
reg drop;
always@(posedge clk or posedge rst)begin
if(rst)begin
cnt <=0;
end
else if(recv_fifo_wren && recv_fifo_wrdata[8])begin
cnt <=cnt==3'd4 ? 0 : cnt+1'b1;
end
end
always@(*)begin
if(recv_fifo_wren && recv_fifo_wrdata[8] && cnt==3'd4)begin
frame_over =1'b1;
end
else begin
frame_over =1'b0;
end
end
//prevent the tcp_recv_fifo from overflow
always@(posedge clk or posedge rst)begin
if(rst)begin
over_state <=0;
recv_fifo_wren_int <=0;
recv_fifo_wrdata_int <=0;
drop <=0;
drop_cnt <=0;
end
else begin
case(over_state)
wr_idle:begin
recv_fifo_wren_int <=0;
if(recv_fifo_wren && ~recv_fifo_af)begin
over_state <=wr_ok;
recv_fifo_wren_int <=recv_fifo_wren;
recv_fifo_wrdata_int <=recv_fifo_wrdata;
end
else if(recv_fifo_wren && recv_fifo_af)begin
drop_cnt <=drop_cnt+1'b1;
drop <=1;
over_state <=wr_fail;
end
end
wr_ok:begin
recv_fifo_wren_int <=recv_fifo_wren;
recv_fifo_wrdata_int <=recv_fifo_wrdata;
if(frame_over)begin
over_state <=wr_idle;
end
end
wr_fail:begin
if(frame_over)begin
drop <=0;
over_state <=wr_idle;
end
end
endcase
end
end
endmodule

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`timescale 1ns / 1ps
`define MTU 1500 //<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̫<EFBFBD><EFBFBD><EFBFBD><EFBFBD>MTU=1500
`define icmp 8'd1
`define igmp 8'd2
`define tcp 8'd6
`define udp 8'd17
`define ip_version 4'd4 //ֻ֧<EFBFBD><EFBFBD>IPV4
`define ip_hlen 4'd5 //<EFBFBD><EFBFBD>֧<EFBFBD><EFBFBD>ip<EFBFBD>ײ<EFBFBD><EFBFBD><EFBFBD>չѡ<EFBFBD><EFBFBD>
//////////////////////////////////////////////////////////////////////////////////
// Company: USTC
// Engineer: Xiaodong Zhong
//
// Create Date: 2019/07/18 10:00:03
// Description: ip<EFBFBD><EFBFBD>֡
// Revision:
//<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ: 9<EFBFBD><EFBFBD><EFBFBD>أ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD>Ϊ1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ0
//<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ<EFBFBD><EFBFBD>9<EFBFBD><EFBFBD><EFBFBD>أ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>4<EFBFBD><EFBFBD><EFBFBD>ֽڵ<EFBFBD>src_ip
//----------------------------------------------------------------------------------
//| VER(4) | HLEN(4) | TOS(8) | Total_len(16) |
//----------------------------------------------------------------------------------
//| ID(16) | Flag(3) | offset(13) |
//----------------------------------------------------------------------------------
//| TTL(8) | Protocal(8) | Checksum(16) |
//----------------------------------------------------------------------------------
//| SRC_IP(32) |
//----------------------------------------------------------------------------------
//| DST_IP(32) |
//----------------------------------------------------------------------------------
//FLAG=3'b010:<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƭ<EFBFBD><EFBFBD>reserve_bit+dont't_fragment+more_fragments
//////////////////////////////////////////////////////////////////////////////////
module ip_recv(
input clk,
input rst,
input [31:0] local_ip,
input ip_recv_fifo_empty,
output ip_recv_fifo_rden,
input [8:0] ip_recv_fifo_rddata,
input udp_recv_fifo_af,
output udp_recv_fifo_wren,
output [8:0] udp_recv_fifo_wrdata,
input tcp_recv_fifo_af,
output tcp_recv_fifo_wren,
output [8:0] tcp_recv_fifo_wrdata,
input icmp_recv_fifo_af,
output icmp_recv_fifo_wren,
output [8:0] icmp_recv_fifo_wrdata,
input igmp_recv_fifo_af,
output igmp_recv_fifo_wren,
output [8:0] igmp_recv_fifo_wrdata
);
localparam udp = 2'b00,
tcp = 2'b01,
icmp = 2'b10,
igmp = 2'b11;
localparam recv_VER_HLEN =4'd0,
recv_TOS =4'd1,
recv_TLEN =4'd2,
recv_ID =4'd3,
recv_FLAG_OFFSET =4'd4,
recv_TTL =4'd5,
recv_PROTOCAL =4'd6,
recv_CHECKSUM =4'd7,
recv_SRC_IP =4'd8,
recv_DST_IP =4'd9,
recv_DATAx =4'd10,
send_src_ip =4'd11,
wait_end =4'd12;
/////////////////////////////////////////////////////
//reg & wire
/////////////////////////////////////////////////////
reg [8:0] recv_data;
reg recv_valid;
reg [1:0] recv_type;
reg ready;
reg [3:0] state;
reg [1:0] i;
reg [15:0] data_cnt;
reg [15:0] total_len;
reg [15:0] id;
reg [15:0] flag;
reg [7:0] ttl;
reg [15:0] checksum_reg;
reg [31:0] src_ip;
reg [31:0] dst_ip;
reg [15:0] check_buf;
reg [31:0] check_sum;
wire [31:0] checka;
wire checksum_right;
wire [11:0] data_len;
reg [8:0] rx_data;
reg rx_en;
reg rx_last;
reg [31:0] ip_rx_cnt;
/////////////////////////////////////////////////////
//combinational logic
/////////////////////////////////////////////////////
//data distribution
assign udp_recv_fifo_wren = (recv_type==udp) ? rx_en : 1'b0;
assign udp_recv_fifo_wrdata = (recv_type==udp) ? rx_data : 9'b0;
assign tcp_recv_fifo_wren = (recv_type==tcp) ? rx_en : 1'b0;
assign tcp_recv_fifo_wrdata = (recv_type==tcp) ? rx_data : 9'b0;
assign icmp_recv_fifo_wren = (recv_type==icmp) ? rx_en : 1'b0;
assign icmp_recv_fifo_wrdata = (recv_type==icmp) ? rx_data : 9'b0;
assign igmp_recv_fifo_wren = (recv_type==igmp) ? rx_en : 1'b0;
assign igmp_recv_fifo_wrdata = (recv_type==igmp) ? rx_data : 9'b0;
//read out a frame
assign ip_recv_fifo_rden = !ip_recv_fifo_empty & ready /*& !ip_recv_fifo_rddata[8]*/;
//latch the read-out data
always@(posedge clk or posedge rst)begin
if(rst)begin
recv_data <=0;
recv_valid <=0;
end
else begin
recv_data <=ip_recv_fifo_rddata;
recv_valid <=ip_recv_fifo_rden;
end
end
//ready gen
always@(posedge clk or posedge rst)begin
if(rst)begin
ready <=0;
end
else if(!ip_recv_fifo_empty && state==recv_VER_HLEN)begin
ready <=1;
end
else if(ready==1'b1 && recv_data[8])begin
ready <=0;
end
else begin
ready <=ready;
end
end
//ip checksum calculator
assign checka = check_sum[31:16]+check_sum[15:0];
assign checksum_right =(~checka[15:0]==16'h0000);
assign data_len = total_len-20;
/////////////////////////////////////////////////////
//deframe a ip frame
/////////////////////////////////////////////////////
//fsm
always@(posedge clk or posedge rst)begin
if(rst)begin
state <=0;
i <=0;
recv_type <=0;
total_len <=0;
check_buf <=0;
rx_en <=0;
rx_data <=0;
rx_last <=0;
data_cnt <=0;
id <=0;
flag <=0;
ttl <=0;
checksum_reg <=0;
src_ip <=0;
dst_ip <=0;
check_sum <=0;
ip_rx_cnt <=0;
end
else begin
case(state)
recv_VER_HLEN:begin
if(recv_valid && recv_data[7:0]==8'h45)begin
state <=recv_TOS;
check_buf <={check_buf[7:0],recv_data[7:0]};
end
else if(recv_valid && recv_data[7:0]!=8'h45)begin
state <=wait_end;
end
else begin
state <=recv_VER_HLEN;
end
end
recv_TOS:begin
if(recv_valid)begin
check_buf <={check_buf[7:0],recv_data[7:0]};
check_sum <=check_sum+{check_buf[7:0],recv_data[7:0]};
state <=recv_TLEN;
end
else begin
state <=recv_TOS;
end
end
recv_TLEN:begin
if(i==0 && recv_valid)begin
total_len <={8'h00,recv_data[7:0]};
i <=1;
end
else if(i==1 && recv_valid)begin
total_len <={total_len[7:0],recv_data[7:0]};
check_sum <=check_sum+{total_len[7:0],recv_data[7:0]};
i <=0;
state <=recv_ID;
end
else begin
i <=i;
state <=recv_TLEN;
end
end
recv_ID:begin
if(i==0 && recv_valid)begin
id <={8'h00,recv_data[7:0]};
i <=1;
end
else if(i==1 && recv_valid)begin
id <={id[7:0],recv_data[7:0]};
check_sum <=check_sum+{id[7:0],recv_data[7:0]};
i <=0;
state <=recv_FLAG_OFFSET;
end
else begin
i <=i;
state <=recv_ID;
end
end
recv_FLAG_OFFSET:begin
if(i==0 && recv_valid)begin
flag <={8'h00,recv_data[7:0]};
i <=1;
end
else if(i==1 && recv_valid)begin
flag <={flag[7:0],recv_data[7:0]};
check_sum <=check_sum+{flag[7:0],recv_data[7:0]};
i <=0;
state <=recv_TTL;
end
else begin
i <=i;
state <=recv_FLAG_OFFSET;
end
end
recv_TTL:begin
//IP <EFBFBD><EFBFBD>Ƭ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>:reserve(15)+DF(14)+MF(13)+offset(12-0)
if(flag[13]==1'b1 || flag[12:0]!=0 || total_len>`MTU)begin
state <=wait_end;
end
else if(recv_valid && recv_data[7:0]!=8'h00)begin
ttl <=recv_data[7:0];
state <=recv_PROTOCAL;
end
else if(recv_valid && recv_data[7:0]==8'h00)begin
state <=wait_end;
end
else begin
state <=recv_TTL;
end
end
recv_PROTOCAL:begin
if(recv_valid)begin
check_sum <=check_sum+{ttl[7:0],recv_data[7:0]};
if(recv_data[7:0]==`udp)begin
state <=recv_CHECKSUM;
recv_type <=udp;
end
else if(recv_data[7:0]==`tcp)begin
state <=recv_CHECKSUM;
recv_type <=tcp;
end
else if(recv_data[7:0]==`icmp)begin
state <=recv_CHECKSUM;
recv_type <=icmp;
end
else if(recv_data[7:0]==`igmp)begin
state <=recv_CHECKSUM;
recv_type <=igmp;
end
else begin
state <=wait_end;
end
end
else begin
state <=recv_PROTOCAL;
end
end
recv_CHECKSUM:begin
if(i==0 && recv_valid)begin
checksum_reg <={8'h00,recv_data[7:0]};
i <=1;
end
else if(i==1 && recv_valid)begin
checksum_reg <={checksum_reg[7:0],recv_data[7:0]};
check_sum <=check_sum+{checksum_reg[7:0],recv_data[7:0]};
i <=0;
state <=recv_SRC_IP;
end
else begin
i <=i;
state <=recv_CHECKSUM;
end
end
recv_SRC_IP:begin
if(i==0 && recv_valid)begin
src_ip <={24'h0,recv_data[7:0]};
i <=i+1;
end
else if(i==1 && recv_valid)begin
src_ip <={16'h0,src_ip[7:0],recv_data[7:0]};
i <=i+1;
check_sum <=check_sum+{16'h0,src_ip[7:0],recv_data[7:0]};
end
else if(i==2 && recv_valid)begin
src_ip <={8'h0,src_ip[15:0],recv_data[7:0]};
i <=i+1;
end
else if(i==3 && recv_valid)begin
src_ip <={src_ip[23:0],recv_data[7:0]};
check_sum <=check_sum+{16'h0,src_ip[7:0],recv_data[7:0]};
i <=0;
state <=recv_DST_IP;
end
else begin
i <=i;
state <=recv_SRC_IP;
end
end
recv_DST_IP:begin
if(i==0 && recv_valid)begin
dst_ip <={24'h0,recv_data[7:0]};
i <=i+1;
end
else if(i==1 && recv_valid)begin
dst_ip <={16'h0,dst_ip[7:0],recv_data[7:0]};
i <=i+1;
check_sum <=check_sum+{16'h0,dst_ip[7:0],recv_data[7:0]};
end
else if(i==2 && recv_valid)begin
dst_ip <={8'h0,dst_ip[15:0],recv_data[7:0]};
i <=i+1;
end
else if(i==3 && recv_valid)begin
dst_ip <={dst_ip[23:0],recv_data[7:0]};
check_sum <=check_sum+{16'h0,dst_ip[7:0],recv_data[7:0]};
i <=0;
if({dst_ip[23:0],recv_data[7:0]}==local_ip)begin
state <=recv_DATAx;
ip_rx_cnt <=ip_rx_cnt+1;
end
else begin
state <=wait_end;
end
end
else begin
i <=i;
state <=recv_SRC_IP;
end
end
recv_DATAx:begin
if(recv_valid)begin
if(checksum_right && data_cnt<=(data_len-1))begin
rx_en <=1;
if(data_cnt==(data_len-1))begin
data_cnt <=0;
rx_last <=1;
rx_data <={1'b1,recv_data[7:0]};
state <=send_src_ip;
end
else begin
data_cnt <=data_cnt+1;
rx_data <={1'b0,recv_data[7:0]};
rx_last <=0;
end
end
else begin
state <=wait_end;
end
end
else begin
rx_en <=0;
rx_data <=rx_data;
end
end
send_src_ip:begin
if(i==0)begin
i <=1;
rx_en <=1;
rx_data <={1'b1,src_ip[31:24]};
rx_last <=1;
end
else if(i==1)begin
i <=2;
rx_en <=1;
rx_data <={1'b1,src_ip[23:16]};
rx_last <=1;
end
else if(i==2)begin
i <=3;
rx_en <=1;
rx_data <={1'b1,src_ip[15:8]};
rx_last <=1;
end
else if(i==3)begin
i <=0;
rx_en <=1;
rx_data <={1'b1,src_ip[7:0]};
rx_last <=1;
state <=wait_end;
end
end
wait_end:begin
check_sum <=0;
rx_en <=0;
rx_last<=0;
if(!recv_valid)begin
state <=recv_VER_HLEN;
end
else begin
state <=wait_end;
end
end
default:begin
state <=recv_VER_HLEN;
end
endcase
end
end
//---------------------------------------------------------\
//ila_100w ila_ip_recv(
// .clk(clk),
// .probe0({
// state,
// ip_recv_fifo_empty,
// ip_recv_fifo_rden,
// ip_recv_fifo_rddata,
// 17'd0
// } )
//);
endmodule

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@ -0,0 +1,495 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: USTC
// Engineer: Xiaodong Zhong
//
// Create Date: 2019/07/18 16:33:25
// Description: ip frame
//----------------------------------------------------------------------------------
//| VER(4) | HLEN(4) | TOS(8) | Total_len(16) |
//----------------------------------------------------------------------------------
//| ID(16) | Flag(3) | offset(13) |
//----------------------------------------------------------------------------------
//| TTL(8) | Protocal(8) | Checksum(16) |
//----------------------------------------------------------------------------------
//| SRC_IP(32) |
//----------------------------------------------------------------------------------
//| DST_IP(32) |
//----------------------------------------------------------------------------------
//FLAG=3'b010:<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƭ<EFBFBD><EFBFBD>reserve_bit+dont't_fragment+more_fragments
//<EFBFBD><EFBFBD><EFBFBD>
//Ŀ<EFBFBD><EFBFBD>ip<EFBFBD><EFBFBD>ַ<EFBFBD><EFBFBD>4byte
//<EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><EFBFBD><EFBFBD>: 2byte
// <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//////////////////////////////////////////////////////////////////////////////////
module ip_send(
input clk,
input rst,
input [31:0] local_ip,
input [31:0] gate_ip,
input [31:0] gate_mask,
output reg ip_rslv_req, //ip resolve request
input ip_rslv_grant,
output reg [31:0] ip_rslv_ip,
input ip_rslvd_req, //ip resolved resp
output reg ip_rslvd_grant,
input [80:0] ip_rslvd_ipmac, //sucess/fail+ip+mac
output want_arp,
input udp_send_req,
output udp_send_grant,
input [31:0] udp_send_dst_ip,
input [15:0] udp_send_len,
output udp_send_fifo_rden,
input [7:0] udp_send_fifo_rddata,
input tcp_send_req,
output tcp_send_grant,
input [31:0] tcp_send_dst_ip,
input [15:0] tcp_send_len,
output tcp_send_fifo_rden,
input [7:0] tcp_send_fifo_rddata,
input icmp_send_req,
output icmp_send_grant,
input [31:0] icmp_send_dst_ip,
input [15:0] icmp_send_len,
output icmp_send_fifo_rden,
input [7:0] icmp_send_fifo_rddata,
input igmp_send_req,
output igmp_send_grant,
input [31:0] igmp_send_dst_ip,
input [15:0] igmp_send_len,
output igmp_send_fifo_rden,
input [7:0] igmp_send_fifo_rddata,
input ip_send_fifo_af,
output reg ip_send_fifo_wren,
output reg [8:0] ip_send_fifo_wrdata //mac+frame
);
///////////////////////////////////////////////////
//parameter
///////////////////////////////////////////////////
localparam idle = 4'd0,
req_arbiter = 4'd1,
judge_local = 4'd2,
start_ip_rslv = 4'd3,
wait_ip_rslv = 4'd4,
make_head = 4'd5,
chksum_cal = 4'd6,
wait_cal = 4'd7,
send_mac_addr = 4'd8,
send_head = 4'd9,
send_data = 4'd10,
next_judge = 4'd11,
ip_send_err = 4'd12;
///////////////////////////////////////////////////
//reg & wire
///////////////////////////////////////////////////
reg [3:0] state;
reg [31:0] dst_ip_reg;
reg [15:0] len_reg;
reg [15:0] ip_len;
reg [1:0] selection;
reg if_local;
reg [47:0] dst_mac;
reg [15:0] tx_cnt;
reg [31:0] ip0_head,ip1_head,ip2_head,ip3_head,ip4_head;
reg [31:0] check_buf;
reg [15:0] i;
reg [1:0] j;
reg ready;
reg grant;
reg [31:0] ip_tx_cnt;
wire [7:0] protocal_type;
wire fifo_rden;
wire [7:0] fifo_rddata;
///////////////////////////////////////////////////
//combinational logic
///////////////////////////////////////////////////
assign protocal_type = selection == 2'b00 ? 8'd17 :
selection == 2'b01 ? 8'd6 :
selection == 2'b10 ? 8'd1 :
selection == 2'b11 ? 8'd2 : 8'd0;
assign udp_send_fifo_rden = selection == 2'b00 ? fifo_rden : 1'b0;
assign tcp_send_fifo_rden = selection == 2'b01 ? fifo_rden : 1'b0;
assign icmp_send_fifo_rden = selection == 2'b10 ? fifo_rden : 1'b0;
assign igmp_send_fifo_rden = selection == 2'b11 ? fifo_rden : 1'b0;
assign fifo_rddata = selection == 2'b00 ? udp_send_fifo_rddata :
selection == 2'b01 ? tcp_send_fifo_rddata :
selection == 2'b10 ? icmp_send_fifo_rddata :
selection == 2'b11 ? igmp_send_fifo_rddata : 8'h00;
assign fifo_rden = ready & ~ip_send_fifo_af;
assign udp_send_grant = selection == 2'b00 ? grant : 1'b0;
assign tcp_send_grant = selection == 2'b01 ? grant : 1'b0;
assign icmp_send_grant = selection == 2'b10 ? grant : 1'b0;
assign igmp_send_grant = selection == 2'b11 ? grant : 1'b0;
assign want_arp = state==wait_ip_rslv;
///////////////////////////////////////////////////
//fsm
///////////////////////////////////////////////////
always@(posedge clk or posedge rst)begin
if(rst)begin
state <=0;
dst_ip_reg <=0;
len_reg <=0;
selection <=0;
tx_cnt <=0;
i <=0;
j <=0;
grant <=0;
ip_rslv_req <=0;
ip_rslv_ip <=0;
ip_rslvd_grant <=0;
ready <=0;
ip_send_fifo_wren <=0;
ip_send_fifo_wrdata <=0;
ip_len <=0;
if_local <=0;
dst_mac <=0;
ip0_head <=0;
ip1_head <=0;
ip2_head <=0;
ip3_head <=0;
ip4_head <=0;
check_buf <=0;
ip_tx_cnt <=0;
end
else begin
case(state)
idle:begin
if(!udp_send_req && !tcp_send_req && !icmp_send_req && !igmp_send_req)begin
state <=idle;
end
else begin
state <=req_arbiter;
end
end
//arbiter strategy
req_arbiter:begin
if(selection==0 && udp_send_req)begin
grant <=1;
dst_ip_reg <=udp_send_dst_ip;
len_reg <=udp_send_len;
state <=judge_local;
end
else if(selection==1 && tcp_send_req)begin
grant <=1;
dst_ip_reg <=tcp_send_dst_ip;
len_reg <=tcp_send_len;
state <=judge_local;
end
else if(selection==2 && icmp_send_req)begin
grant <=1;
dst_ip_reg <=icmp_send_dst_ip;
len_reg <=icmp_send_len;
state <=judge_local;
end
else if(selection==3 && igmp_send_req)begin
grant <=1;
dst_ip_reg <=igmp_send_dst_ip;
len_reg <=igmp_send_len;
state <=judge_local;
end
else begin
state <=next_judge;
end
end
//judge if the ip is in the local area network
judge_local:begin
ip_tx_cnt <=ip_tx_cnt+1;
grant <=0;
ip_len <=len_reg+20;
state <=start_ip_rslv;
if((dst_ip_reg & gate_mask)==(gate_ip & gate_mask))begin
if_local <=1;
end
else begin
if_local <=0;
end
end
//send ip resolve req to arp
start_ip_rslv:begin
ip_rslv_req <=1;
ip_rslv_ip <=if_local ? dst_ip_reg : gate_ip;
if(ip_rslv_grant)begin
ip_rslv_req <=0;
state <=wait_ip_rslv;
end
else begin
state <=start_ip_rslv;
end
end
//wait ip resolve result from arp
wait_ip_rslv:begin
if(ip_rslvd_req)begin
ip_rslvd_grant <=1;
if(ip_rslvd_ipmac[80] && ip_rslvd_ipmac[79:48]==ip_rslv_ip)begin
dst_mac <=ip_rslvd_ipmac[47:0];
state <=make_head;
end
else begin
state <=ip_send_err;
end
end
else begin
state <=wait_ip_rslv;
end
end
make_head:begin
ip_rslvd_grant <=0;
ip0_head <={16'h4500,ip_len[15:0]}; //<EFBFBD><EFBFBD><EFBFBD>4<EFBFBD><EFBFBD>+<EFBFBD>ײ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȣ<EFBFBD>4<EFBFBD><EFBFBD>+TOS(8)+IP<EFBFBD>ܳ<EFBFBD><EFBFBD>ȣ<EFBFBD>16<EFBFBD><EFBFBD>
ip0_head <={16'h4500,ip_len[15:0]}; //<EFBFBD><EFBFBD><EFBFBD>4<EFBFBD><EFBFBD>+<EFBFBD>ײ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȣ<EFBFBD>4<EFBFBD><EFBFBD>+TOS(8)+IP<EFBFBD>ܳ<EFBFBD><EFBFBD>ȣ<EFBFBD>16<EFBFBD><EFBFBD>
ip1_head[31:16] <=tx_cnt; //id
ip1_head[15:14] <=2'b01; //<EFBFBD><EFBFBD>ֹ<EFBFBD><EFBFBD>Ƭ<EFBFBD><EFBFBD>DF<EFBFBD><EFBFBD>don't fragment,DF=1,<EFBFBD><EFBFBD>ʾ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƭ<EFBFBD><EFBFBD>DF=0<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƭ
ip1_head[13] <=0; //MF<EFBFBD><EFBFBD>more fragment,MF=1,<EFBFBD><EFBFBD>ʾ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>з<EFBFBD>Ƭ<EFBFBD><EFBFBD>MF=0<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƭ
ip1_head[12:0] <=0; //Ƭƫ<EFBFBD><EFBFBD>
ip2_head[31:24] <=8'h80; //TTL<EFBFBD><EFBFBD>ÿ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD>·<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1
ip2_head[23:16] <=protocal_type; //<EFBFBD>ϲ<EFBFBD>Э<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD>icmp,igmp,tcp,udp
ip2_head[15:0] <=0; //<EFBFBD>ײ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
ip3_head <=local_ip[31:0]; //<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ip<EFBFBD><EFBFBD>ַ
ip4_head <=dst_ip_reg; //Ŀ<EFBFBD><EFBFBD>IP<EFBFBD><EFBFBD>ַ
tx_cnt <=tx_cnt+1;
state <=chksum_cal;
end
chksum_cal:begin
check_buf <=ip0_head[15:0]+ip0_head[31:16]+ip1_head[15:0]+ip1_head[31:16]+
ip2_head[15:0]+ip2_head[31:16]+ip3_head[15:0]+ip3_head[31:16]+
ip4_head[15:0]+ip4_head[31:16];
state <=wait_cal;
end
wait_cal:begin
if(i==2)begin
check_buf <=check_buf[31:16]+check_buf[15:0];
i <=i+1;
end
else if(i==3)begin
ip2_head[15:0] <=~(check_buf[31:16]+check_buf[15:0]);
i <=0;
state <=send_mac_addr;
end
else begin
i <=i+1;
end
end
send_mac_addr:begin
if(!ip_send_fifo_af)begin
ip_send_fifo_wren <=1;
ip_send_fifo_wrdata <={1'b0,dst_mac[47:40]};
dst_mac <=dst_mac<<8;
if(i==5)begin
i <=0;
state <=send_head;
end
else begin
i <=i+1;
end
end
else begin
ip_send_fifo_wren <=0;
ip_send_fifo_wrdata <=ip_send_fifo_wrdata;
end
end
send_head:begin
if(!ip_send_fifo_af)begin
//no.1
if(i==0)begin
ip_send_fifo_wren <=1;
ip_send_fifo_wrdata <={1'b0,ip0_head[31:24]};
ip0_head<=ip0_head<<8;
if(j==3)begin
j <=0;
i <=i+1;
end
else begin
j <=j+1;
i <=i;
end
end
//no.2
else if(i==1)begin
ip_send_fifo_wren <=1;
ip_send_fifo_wrdata <={1'b0,ip1_head[31:24]};
ip1_head<=ip1_head<<8;
if(j==3)begin
j <=0;
i <=i+1;
end
else begin
j <=j+1;
i <=i;
end
end
//no.3
else if(i==2)begin
ip_send_fifo_wren <=1;
ip_send_fifo_wrdata <={1'b0,ip2_head[31:24]};
ip2_head<=ip2_head<<8;
if(j==3)begin
j <=0;
i <=i+1;
end
else begin
j <=j+1;
i <=i;
end
end
//no.4
else if(i==3)begin
ip_send_fifo_wren <=1;
ip_send_fifo_wrdata <={1'b0,ip3_head[31:24]};
ip3_head<=ip3_head<<8;
if(j==3)begin
j <=0;
i <=i+1;
end
else begin
j <=j+1;
i <=i;
end
end
//no.5
else if(i==4)begin
ip_send_fifo_wren <=1;
ip_send_fifo_wrdata <={1'b0,ip4_head[31:24]};
ip4_head<=ip4_head<<8;
if(j==3)begin
j <=0;
i <=0; //exit
state <=send_data;
ready <=1;
end
else begin
j <=j+1;
i <=i;
end
end
end
else begin
ip_send_fifo_wren <=0;
ip_send_fifo_wrdata <=ip_send_fifo_wrdata;
end
end
send_data:begin
if(fifo_rden)begin
ip_send_fifo_wren <=1;
if(i==len_reg-1)begin
i <=0;
ready <=0;
state <=next_judge;
ip_send_fifo_wrdata <={1'b1,fifo_rddata[7:0]};
end
else begin
i <=i+1;
ip_send_fifo_wrdata <={1'b0,fifo_rddata[7:0]};
end
end
else begin
ip_send_fifo_wren <=0;
ip_send_fifo_wrdata <=ip_send_fifo_wrdata;
end
end
//choose next protocal to send
next_judge:begin
ip_send_fifo_wren <=0;
if(selection==0)begin
if(tcp_send_req)begin
selection <=1;
state <=req_arbiter;
end
else if(icmp_send_req)begin
selection <=2;
state <=req_arbiter;
end
else if(igmp_send_req)begin
selection <=3;
state <=req_arbiter;
end
else begin
selection <=0;
state <=idle;
end
end
else if(selection==1)begin
if(icmp_send_req)begin
selection <=2;
state <=req_arbiter;
end
else if(igmp_send_req)begin
selection <=3;
state <=req_arbiter;
end
else begin
selection <=0;
state <=idle;
end
end
else if(selection==2)begin
if(igmp_send_req)begin
selection <=3;
state <=req_arbiter;
end
else begin
selection <=0;
state <=idle;
end
end
else begin
selection <=0;
end
end
default:begin
state <=idle;
end
endcase
end
end
//---------------------------------------------------------\
//ila_100w ila_ip_send(
// .clk(clk),
// .probe0({
// state, //4
// icmp_send_req,
// icmp_send_grant,
// icmp_send_dst_ip,
// icmp_send_len,
// icmp_send_fifo_rden,
// icmp_send_fifo_rddata
// }
// )
//);
endmodule

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@ -0,0 +1,337 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/08/14 13:41:10
// Design Name:
// Module Name: ip_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ip_top(
input clk,
input rst,
input [31:0] local_ip,
input [31:0] gate_ip,
input [31:0] gate_mask,
//arp interface
output ip_rslv_req,
input ip_rslv_grant,
output [31:0]ip_rslv_ip,
input ip_rslvd_req,
output ip_rslvd_grant,
input [80:0]ip_rslvd_ipmac,
output want_arp,
//mac interface
input ip_recv_fifo_empty,
output ip_recv_fifo_rden,
input [8:0] ip_recv_fifo_rddata,
output ip_send_fifo_empty,
input ip_send_fifo_rden,
output [8:0] ip_send_fifo_rddata,
//udp interface
output udp_recv_fifo_empty,
input udp_recv_fifo_rden,
output [8:0] udp_recv_fifo_rddata,
input udp_send_req,
output udp_send_grant,
input [31:0] udp_send_dst_ip,
input [15:0] udp_send_len,
output udp_send_fifo_rden,
input [7:0] udp_send_fifo_rddata,
//tcp interface
output tcp_recv_fifo_empty,
input tcp_recv_fifo_rden,
output [8:0] tcp_recv_fifo_rddata,
input tcp_send_req,
output tcp_send_grant,
input [31:0] tcp_send_dst_ip,
input [15:0] tcp_send_len,
output tcp_send_fifo_rden,
input [7:0] tcp_send_fifo_rddata,
//icmp interface
output icmp_recv_fifo_empty,
input icmp_recv_fifo_rden,
output [8:0] icmp_recv_fifo_rddata,
input icmp_send_req,
output icmp_send_grant,
input [31:0] icmp_send_dst_ip,
input [15:0] icmp_send_len,
output icmp_send_fifo_rden,
input [7:0] icmp_send_fifo_rddata,
output reg icmp_recv_overflow,
output reg udp_recv_overflow,
output reg tcp_recv_overflow,
output [31:0] tcp_drop_cnt,
output reg [31:0] tcp_recv_cnt_max
);
////////////////////////////////////////////
//wire
////////////////////////////////////////////
wire udp_recv_fifo_wren;
wire [8:0] udp_recv_fifo_wrdata;
wire udp_recv_fifo_full;
wire tcp_recv_fifo_wren;
wire [8:0] tcp_recv_fifo_wrdata;
wire [15:0] tcp_recv_fifo_cnt;
wire tcp_recv_fifo_full;
wire tcp_recv_fifo_af;
wire tcp_recv_fifo_wren_int;
wire [8:0] tcp_recv_fifo_wrdata_int;
wire icmp_recv_fifo_wren;
wire [8:0] icmp_recv_fifo_wrdata;
wire igmp_recv_fifo_wren;
wire [8:0] igmp_recv_fifo_wrdata;
wire ip_send_fifo_af;
wire ip_send_fifo_wren;
wire [8:0] ip_send_fifo_wrdata;
////////////////////////////////////////////
//ip receive
////////////////////////////////////////////
ip_recv U_ip_recv(
.clk (clk ),
.rst (rst ),
.local_ip (local_ip ),
.ip_recv_fifo_empty (ip_recv_fifo_empty ),
.ip_recv_fifo_rden (ip_recv_fifo_rden ),
.ip_recv_fifo_rddata (ip_recv_fifo_rddata ),
.udp_recv_fifo_af (),
.udp_recv_fifo_wren (udp_recv_fifo_wren ),
.udp_recv_fifo_wrdata (udp_recv_fifo_wrdata ),
.tcp_recv_fifo_af (),
.tcp_recv_fifo_wren (tcp_recv_fifo_wren ),
.tcp_recv_fifo_wrdata (tcp_recv_fifo_wrdata ),
.icmp_recv_fifo_af (),
.icmp_recv_fifo_wren (icmp_recv_fifo_wren ),
.icmp_recv_fifo_wrdata (icmp_recv_fifo_wrdata ),
.igmp_recv_fifo_af (),
.igmp_recv_fifo_wren (igmp_recv_fifo_wren ),
.igmp_recv_fifo_wrdata (igmp_recv_fifo_wrdata )
);
//--------------------------------------------------
//udp rx fifo
//--------------------------------------------------
syn_fwft_fifo #(
.width (9),
.depth (32))
U_udp_recv_fifo(
.clk (clk ),
.rst (rst ),
.clr (1'b0 ),
.wr_en (udp_recv_fifo_wren ),
.din (udp_recv_fifo_wrdata ),
.full (udp_recv_fifo_full ),
.almost_full (),
.rd_en (udp_recv_fifo_rden ),
.dout (udp_recv_fifo_rddata ),
.empty (udp_recv_fifo_empty )
);
always@(posedge clk or posedge rst)begin
if(rst)begin
udp_recv_overflow <=1'b0;
end
else if(udp_recv_fifo_wren && udp_recv_fifo_full)begin
udp_recv_overflow <=1'b1;
end
end
//--------------------------------------------------
//tcp rx fifo
//--------------------------------------------------
syn_fwft_fifo #(
.width (9),
.prog_full_thre(64076),
.depth (65536)
)
U_tcp_recv_fifo(
.clk (clk ),
.rst (rst ),
.clr (1'b0 ),
.wr_en (tcp_recv_fifo_wren_int ),
.din (tcp_recv_fifo_wrdata_int ),
.full (tcp_recv_fifo_full ),
.almost_full (),
.prog_full (tcp_recv_fifo_af ),
.rd_en (tcp_recv_fifo_rden ),
.dout (tcp_recv_fifo_rddata ),
.empty (tcp_recv_fifo_empty ),
.cnt (tcp_recv_fifo_cnt )
);
ip_packet_drop U_ip_packet_drop(
.clk (clk ),
.rst (rst ),
.recv_fifo_wren (tcp_recv_fifo_wren ),
.recv_fifo_wrdata (tcp_recv_fifo_wrdata ),
.recv_fifo_af (tcp_recv_fifo_af ),
.recv_fifo_wren_int (tcp_recv_fifo_wren_int ),
.recv_fifo_wrdata_int (tcp_recv_fifo_wrdata_int ),
.drop_cnt (tcp_drop_cnt )
);
always@(posedge clk or posedge rst)begin
if(rst)begin
tcp_recv_overflow <=1'b0;
end
else if(tcp_recv_fifo_wren_int && tcp_recv_fifo_full)begin
tcp_recv_overflow <=1'b1;
end
end
//tcp_recv_cnt_max
always@(posedge clk or posedge rst)begin
if(rst)begin
tcp_recv_cnt_max <=0;
end
else if(tcp_recv_fifo_cnt>tcp_recv_cnt_max)begin
tcp_recv_cnt_max <=tcp_recv_fifo_cnt;
end
else begin
tcp_recv_cnt_max <=tcp_recv_cnt_max;
end
end
//ila_100 ila_ip(//122
// .clk (clk ),
// .probe0 ({
// tcp_recv_fifo_wren,
// tcp_recv_fifo_wrdata,
// tcp_recv_fifo_full,
// tcp_recv_fifo_af,
// tcp_recv_fifo_wren_int,
// tcp_recv_fifo_wrdata_int,
// tcp_recv_overflow,
// tcp_recv_fifo_cnt,
// //over_state,
// 58'd0
// })
//);
//--------------------------------------------------
//icmp rx fifo
//--------------------------------------------------
syn_fwft_fifo #(
.width (9),
.depth (32))
U_icmp_recv_fifo(
.clk (clk ),
.rst (rst ),
.clr (1'b0 ),
.wr_en (icmp_recv_fifo_wren ),
.din (icmp_recv_fifo_wrdata ),
.full (),
.almost_full (),
.rd_en (icmp_recv_fifo_rden ),
.dout (icmp_recv_fifo_rddata ),
.empty (icmp_recv_fifo_empty )
);
always@(posedge clk or posedge rst)begin
if(rst)begin
icmp_recv_overflow <=1'b0;
end
else if(udp_recv_fifo_wren && udp_recv_fifo_full)begin
icmp_recv_overflow <=1'b1;
end
end
////////////////////////////////////////////
//ip send
////////////////////////////////////////////
ip_send U_ip_send(
.clk (clk ),
.rst (rst ),
.local_ip (local_ip ),
.gate_ip (gate_ip ),
.gate_mask (gate_mask ),
.ip_rslv_req (ip_rslv_req ), //ip resolve request
.ip_rslv_grant (ip_rslv_grant ),
.ip_rslv_ip (ip_rslv_ip ),
.ip_rslvd_req (ip_rslvd_req ), //ip resolved resp
.ip_rslvd_grant (ip_rslvd_grant ),
.ip_rslvd_ipmac (ip_rslvd_ipmac ), //sucess/fail+ip+mac
.want_arp (want_arp ),
.udp_send_req (udp_send_req ),
.udp_send_grant (udp_send_grant ),
.udp_send_dst_ip (udp_send_dst_ip ),
.udp_send_len (udp_send_len ),
.udp_send_fifo_rden (udp_send_fifo_rden ),
.udp_send_fifo_rddata (udp_send_fifo_rddata ),
.tcp_send_req (tcp_send_req ),
.tcp_send_grant (tcp_send_grant ),
.tcp_send_dst_ip (tcp_send_dst_ip ),
.tcp_send_len (tcp_send_len ),
.tcp_send_fifo_rden (tcp_send_fifo_rden ),
.tcp_send_fifo_rddata (tcp_send_fifo_rddata ),
.icmp_send_req (icmp_send_req ),
.icmp_send_grant (icmp_send_grant ),
.icmp_send_dst_ip (icmp_send_dst_ip ),
.icmp_send_len (icmp_send_len ),
.icmp_send_fifo_rden (icmp_send_fifo_rden ),
.icmp_send_fifo_rddata (icmp_send_fifo_rddata ),
.igmp_send_req (1'b0 ),
.igmp_send_grant (),
.igmp_send_dst_ip (),
.igmp_send_len (),
.igmp_send_fifo_rden (),
.igmp_send_fifo_rddata (),
.ip_send_fifo_af (ip_send_fifo_af ),
.ip_send_fifo_wren (ip_send_fifo_wren ),
.ip_send_fifo_wrdata (ip_send_fifo_wrdata )//mac+frame
);
//--------------------------------------------------
//icmp rx fifo
//--------------------------------------------------
syn_fwft_fifo #(
.width (9),
.depth (2048))
U_ip_send_fifo(
.clk (clk ),
.rst (rst ),
.clr (1'b0 ),
.wr_en (ip_send_fifo_wren ),
.din (ip_send_fifo_wrdata ),
.full (),
.almost_full (ip_send_fifo_af ),
.rd_en (ip_send_fifo_rden ),
.dout (ip_send_fifo_rddata ),
.empty (ip_send_fifo_empty )
);
endmodule

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`timescale 1ns / 1ps
//`include "../head.v"
`define ISN_seed 32'hAAAA_BBBB
//////////////////////////////////////////////////////////////////////////////////
//功能产生初始序号存储在ISN_fifo中
//designed by Xiaodong Zhong
//2018.11.8
//如果ISN_buffer将要空往里面写入8个数
//////////////////////////////////////////////////////////////////////////////////
module ISN_generator(
input clk,
input rst,
input isn_gen,
output [31:0] isn
);
reg [31:0] r;
reg state;
reg [3:0] i;
parameter load =2'd0,
gen_ISN =2'd1;
assign isn =r;
always@(posedge clk or posedge rst) begin
if(rst) begin
r <=0;
state <=0;
end
else begin
case(state)
load:begin
r <=`ISN_seed;
state <=gen_ISN;
end
gen_ISN:begin
if(isn_gen)begin
r[31:0] <={r[30:2],r[1]^r[31],r[0]^r[31],r[31]};
end
else begin
r <=r;
end
state <=gen_ISN;
end
default:begin
state <=load;
end
endcase
end
end
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/08/14 13:53:46
// Design Name:
// Module Name: mac_recv
// Description:
//
// +-----------------------------------------------------------------+
// | dst_mac(6) | src_mac(6) | type/len(2) | payload(46~1514) |
// +-----------------------------------------------------------------+
//////////////////////////////////////////////////////////////////////////////////
module mac_recv(
input clk,
input rst,
input [47:0] local_mac,
output reg mac_rx_ready, //always ready
input mac_rx_valid,
input [7:0] mac_rx_data,
input mac_rx_last,
output arp_recv_fifo_wren,
output [8:0] arp_recv_fifo_wrdata,//[8]->last_flag
output ip_recv_fifo_wren,
output [8:0] ip_recv_fifo_wrdata //[8]->last_flag
);
/////////////////////////////////////////////////////
//parameter
/////////////////////////////////////////////////////
localparam idle = 3'd0,
recv_dst_mac = 3'd1,
recv_src_mac = 3'd2,
recv_type = 3'd3,
recv_payload = 3'd4,
wait_end = 3'd5;
/////////////////////////////////////////////////////
//reg & wire
/////////////////////////////////////////////////////
reg [2:0] state;
reg fifo_wren;
reg [8:0] fifo_wrdata;
reg selection;
reg [2:0] i;
reg [47:0] dst_mac_reg;
reg [47:0] src_mac_reg;
reg [31:0] mac_rx_ip_cnt;
/////////////////////////////////////////////////////
//combinational logic
/////////////////////////////////////////////////////
assign arp_recv_fifo_wren = selection == 1'b0 ? fifo_wren : 1'b0;
assign arp_recv_fifo_wrdata = selection == 1'b0 ? fifo_wrdata : 9'b0;
assign ip_recv_fifo_wren = selection == 1'b1 ? fifo_wren : 1'b0;
assign ip_recv_fifo_wrdata = selection == 1'b1 ? fifo_wrdata : 9'b0;
//assign mac_rx_ready = 1'b1;
/////////////////////////////////////////////////////
//fsm
/////////////////////////////////////////////////////
always@(posedge clk or posedge rst)begin
if(rst)begin
state <=0;
fifo_wren <=0;
fifo_wrdata <=0;
i <=0;
selection <=0;
dst_mac_reg <=0;
src_mac_reg <=0;
mac_rx_ip_cnt <=0;
mac_rx_ready <=0;
end
else begin
case(state)
idle:begin
fifo_wren <=0;
fifo_wrdata <=0;
mac_rx_ready <=0;
i <=0;
if(mac_rx_valid)begin
mac_rx_ready <=1;
state <=recv_dst_mac;
end
else begin
state <=idle;
end
end
recv_dst_mac:begin
fifo_wren <=0;
fifo_wrdata <=0;
if(mac_rx_valid)begin
dst_mac_reg <={dst_mac_reg[39:0],mac_rx_data[7:0]};
if(i==5)begin
i <=0;
if({dst_mac_reg[39:0],mac_rx_data[7:0]}==local_mac || {dst_mac_reg[39:0],mac_rx_data[7:0]}== 48'hffff_ffff_ffff)begin
state <=recv_src_mac;
end
else begin
state <=wait_end;
end
end
else begin
i <=i+1;
end
end
else begin
state <=recv_dst_mac;
end
end
recv_src_mac:begin
if(mac_rx_valid)begin
src_mac_reg <={src_mac_reg[39:0],mac_rx_data[7:0]};
if(i==5)begin
i <=0;
state <=recv_type;
end
else begin
i <=i+1;
end
end
end
recv_type:begin
if(mac_rx_valid)begin
if(i==0 && mac_rx_data==8'h08)begin
i <=i+1;
end
else if(i==1 && mac_rx_data==8'h06)begin //arp packet
i <=0;
state <=recv_payload;
selection <=0;
end
else if(i==1 && mac_rx_data==8'h00)begin //ip packect
if(dst_mac_reg==local_mac)begin
mac_rx_ip_cnt <=mac_rx_ip_cnt+1;
end
i <=0;
state <=recv_payload;
selection <=1;
end
else begin
i <=0;
state <=wait_end;
end
end
end
recv_payload:begin
if(mac_rx_valid && mac_rx_last)begin
fifo_wren <=1;
fifo_wrdata <={1'b1,mac_rx_data[7:0]};
//state <=recv_dst_mac;
state <=idle;
mac_rx_ready <=0;
end
else if(mac_rx_valid && !mac_rx_last)begin
fifo_wren <=1;
fifo_wrdata <={1'b0,mac_rx_data[7:0]};
end
else begin
fifo_wren <=0;
fifo_wrdata <=fifo_wrdata;
end
end
wait_end:begin
if(mac_rx_last && mac_rx_valid)begin
mac_rx_ready <=0;
//state <=recv_dst_mac;
state <=idle;
end
else begin
state <=wait_end;
end
end
default:begin
state <=recv_dst_mac;
end
endcase
end
end
//-----------------------------------------
//reg [31:0] ifg_cnt;
//reg [31:0] ifg_min;
//reg run;
//always@(posedge clk or posedge rst)begin
// if(rst)begin
// run <=0;
// end
// else if(run==0 && mac_rx_valid && mac_rx_last)begin
// run <=1;
// end
// else if(run==1 && mac_rx_valid && mac_rx_last)begin
// run <=0;
// end
//end
//always@(posedge clk or posedge rst)begin
// if(rst)begin
// ifg_cnt <=0;
// end
// else if(run)begin
// ifg_cnt<=ifg_cnt+1;
// end
// else begin
// ifg_cnt <=0;
// end
//end
//always@(posedge clk or posedge rst)begin
// if(rst)begin
// ifg_min <=32'hffff_ffff;
// end
// else if(run==1 && mac_rx_valid && mac_rx_last)begin
// if(ifg_cnt <ifg_min)begin
// ifg_min <=ifg_cnt;
// end
// else begin
// ifg_min <=ifg_min;
// end
// end
// else begin
// ifg_min <=ifg_min;
// end
//end
//==========================================
//ila_100w ila_mac_recv(
// .clk(clk),
// .probe0({
// mac_rx_valid, //1
// mac_rx_data, //8
// mac_rx_last, //1
// mac_rx_ready, //1
// ip_recv_fifo_wren, //1
// ip_recv_fifo_wrdata, //9
// arp_recv_fifo_wren,
// arp_recv_fifo_wrdata//[8]->last_flag
// })
//);
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/08/14 13:53:22
// Design Name:
// Module Name: mac_send
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mac_send(
input clk,
input rst,
input [47:0] local_mac,
input [7:0] ifg,
input arp_send_fifo_empty,
output arp_send_fifo_rden,
input [8:0] arp_send_fifo_rddata,
input ip_send_fifo_empty,
output ip_send_fifo_rden,
input [8:0] ip_send_fifo_rddata,
input mac_tx_ready,
output mac_tx_valid,
output reg [7:0] mac_tx_data,
output mac_tx_last
);
////////////////////////////////////////////////
//parameter
////////////////////////////////////////////////
localparam idle = 3'd0,
send_dst_mac = 3'd1,
send_src_mac = 3'd2,
send_type = 3'd3,
send_payload = 3'd4,
wait_ifg = 3'd5;
////////////////////////////////////////////////
//reg & wire
////////////////////////////////////////////////
reg [2:0] state;
reg ping_pang;
reg ready;
reg [3:0] sel;
reg [7:0] cnt;
reg mac_tx_valid_r;
wire fifo_rden;
wire [8:0] fifo_rddata;
////////////////////////////////////////////////
//combinational logic
////////////////////////////////////////////////
assign arp_send_fifo_rden = ping_pang == 1'b0 ? fifo_rden : 1'b0;
assign ip_send_fifo_rden = ping_pang == 1'b1 ? fifo_rden : 1'b0;
assign fifo_rddata = ping_pang == 1'b0 ? arp_send_fifo_rddata : ip_send_fifo_rddata;
assign fifo_rden = ready & mac_tx_ready;
//data output mux sel
always@(*)begin
mac_tx_data =0;
case(sel)
1:mac_tx_data = fifo_rddata[7:0];
2:mac_tx_data = local_mac[47:40];
3:mac_tx_data = local_mac[39:32];
4:mac_tx_data = local_mac[31:24];
5:mac_tx_data = local_mac[23:16];
6:mac_tx_data = local_mac[15:8];
7:mac_tx_data = local_mac[7:0];
8:mac_tx_data = 8'h08;
9:mac_tx_data = ping_pang == 1'b0 ? 8'h06 :8'h00;
10:mac_tx_data = fifo_rddata[7:0];
default:begin
mac_tx_data =8'h00;
end
endcase
end
assign mac_tx_last = fifo_rddata[8] & mac_tx_valid;
assign mac_tx_valid = sel!=0;
////////////////////////////////////////////////
//fsm
////////////////////////////////////////////////
always@(posedge clk or posedge rst)begin
if(rst)begin
state <=0;
ping_pang <=0;
ready <=0;
sel <=0;
cnt <=0;
mac_tx_valid_r <=0;
//mac_tx_last <=0;
end
else begin
case(state)
idle:begin //wait request and arbiter
sel <=0;
if(arp_send_fifo_empty && ip_send_fifo_empty)begin
ping_pang <=ping_pang;
end
else if(ping_pang == 1'b0 && arp_send_fifo_empty)begin
ping_pang <=~ping_pang;
end
else if(ping_pang == 1'b1 && ip_send_fifo_empty)begin
ping_pang <=~ping_pang;
end
else if(ping_pang == 1'b0 && !arp_send_fifo_empty)begin
state <=send_dst_mac;
ready <=1;
mac_tx_valid_r <=1;
sel <=1;
//mac_tx_last <=0;
end
else if(ping_pang == 1'b1 && !ip_send_fifo_empty)begin
state <=send_dst_mac;
ready <=1;
mac_tx_valid_r <=1;
sel <=1;
//mac_tx_last <=0;
end
end
send_dst_mac:begin
if(fifo_rden)begin
if(cnt==5)begin
cnt <=0;
sel <=2;
ready <=0;
state <=send_src_mac;
end
else begin
cnt <=cnt+1;
end
end
end
send_src_mac:begin
if(mac_tx_ready)begin
sel <=sel+1;
if(cnt==5)begin
cnt <=0;
state <=send_type;
end
else begin
cnt <=cnt+1;
end
end
end
send_type:begin
if(mac_tx_ready)begin
sel <=sel+1;
if(cnt==1)begin
cnt <=0;
ready <=1;
state <=send_payload;
end
else begin
cnt <=cnt+1;
end
end
end
send_payload:begin
if(fifo_rden && !fifo_rddata[8])begin
sel <=sel;
mac_tx_valid_r <=1;
//mac_tx_last <=0;
end
else if(fifo_rden && fifo_rddata[8])begin
sel <=0;
ready <=0;
state <=wait_ifg;
mac_tx_valid_r <=0;
//mac_tx_last <=1;
end
end
wait_ifg:begin
mac_tx_valid_r <=0;
//mac_tx_last <=0;
if(cnt==(ifg-1))begin
ping_pang <=~ping_pang;
cnt <=0;
state <=idle;
end
else begin
cnt <=cnt+1;
end
end
default:begin
state <=idle;
end
endcase
end
end
//================================================
//reg flag;
//always@(posedge clk or posedge rst)begin
// if(fifo_rden && fifo_rddata[8])begin
// flag <=1;
// end
// else begin
// flag <=0;
// end
//end
//ila_32 ila_arp_mac_send(
// .clk (clk),
// .probe0 (
// {
// arp_send_fifo_empty, //1
// ip_send_fifo_empty, //1
// ping_pang, //1
// state, //3
// mac_tx_ready, //1
// mac_tx_valid, //1
// mac_tx_data, //8
// mac_tx_last, //1
// 15'b0
// }
// )
//);
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/08/14 15:12:00
// Design Name:
// Module Name: mac_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mac_top(
input clk,
input rst,
input [47:0] local_mac,
input [7:0] ifg,
output mac_rx_ready,
input mac_rx_valid,
input [7:0] mac_rx_data,
input mac_rx_last,
input mac_tx_ready,
output mac_tx_valid,
output [7:0] mac_tx_data,
output mac_tx_last,
//arp interafce
input arp_send_fifo_empty,
output arp_send_fifo_rden,
input [8:0] arp_send_fifo_rddata,
output arp_recv_fifo_empty,
input arp_recv_fifo_rden,
output [8:0] arp_recv_fifo_rddata,
//ip interface
input ip_send_fifo_empty,
output ip_send_fifo_rden,
input [8:0] ip_send_fifo_rddata,
output ip_recv_fifo_empty,
input ip_recv_fifo_rden,
output [8:0] ip_recv_fifo_rddata
);
//////////////////////////////////////////////
// wire
/////////////////////////////////////////////
wire arp_recv_fifo_wren;
wire [8:0] arp_recv_fifo_wrdata;
wire ip_recv_fifo_wren;
wire [8:0] ip_recv_fifo_wrdata;
//////////////////////////////////////////////
// mac_send
/////////////////////////////////////////////
mac_recv U_mac_recv(
.clk (clk ),
.rst (rst ),
.local_mac (local_mac ),
.mac_rx_ready (mac_rx_ready ), //always ready
.mac_rx_valid (mac_rx_valid ),
.mac_rx_data (mac_rx_data ),
.mac_rx_last (mac_rx_last ),
.arp_recv_fifo_wren (arp_recv_fifo_wren ),
.arp_recv_fifo_wrdata (arp_recv_fifo_wrdata ), //[8]->last_flag
.ip_recv_fifo_wren (ip_recv_fifo_wren ),
.ip_recv_fifo_wrdata (ip_recv_fifo_wrdata ) //[8]->last_flag
);
//ila_mac ila_mac_arp(
// .clk (clk),
// .probe0 (
// {
// mac_rx_valid, //1
// mac_rx_data, //8
// mac_rx_last, //1
// arp_recv_fifo_wren, //1
// arp_recv_fifo_wrdata, //9
// 2'b0
// }
// )
//);
//--------------------------------------------------
//arp rx fifo
//--------------------------------------------------
syn_fwft_fifo #(
.width (9),
.depth (32))
U_arp_recv_fifo(
.clk (clk ),
.rst (rst ),
.clr (1'b0 ),
.wr_en (arp_recv_fifo_wren ),
.din (arp_recv_fifo_wrdata),
.full (),
.almost_full (),
.rd_en (arp_recv_fifo_rden ),
.dout (arp_recv_fifo_rddata),
.empty (arp_recv_fifo_empty )
);
//--------------------------------------------------
//ip rx fifo
//--------------------------------------------------
syn_fwft_fifo #(
.width (9),
.depth (32))
U_ip_recv_fifo(
.clk (clk ),
.rst (rst ),
.clr (1'b0 ),
.wr_en (ip_recv_fifo_wren ),
.din (ip_recv_fifo_wrdata ),
.full (),
.almost_full (),
.rd_en (ip_recv_fifo_rden ),
.dout (ip_recv_fifo_rddata ),
.empty (ip_recv_fifo_empty )
);
//////////////////////////////////////////////
// mac_send
/////////////////////////////////////////////
mac_send U_mac_send(
.clk (clk ),
.rst (rst ),
.local_mac (local_mac ),
.ifg (ifg ),
.arp_send_fifo_empty (arp_send_fifo_empty ),
.arp_send_fifo_rden (arp_send_fifo_rden ),
.arp_send_fifo_rddata (arp_send_fifo_rddata),
.ip_send_fifo_empty (ip_send_fifo_empty ),
.ip_send_fifo_rden (ip_send_fifo_rden ),
.ip_send_fifo_rddata (ip_send_fifo_rddata ),
.mac_tx_ready (mac_tx_ready ),
.mac_tx_valid (mac_tx_valid ),
.mac_tx_data (mac_tx_data ),
.mac_tx_last (mac_tx_last )
);
//ila_mac ila_mac_send(
// .clk (clk),
// .probe0 (
// {
// mac_tx_valid, //1
// mac_tx_data, //8
// mac_tx_ready, //1
// mac_tx_last, //1
// mac_rx_valid, //1
// mac_rx_data, //8
// mac_rx_ready, //1
// mac_rx_last //1
// }
// )
// );
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/08/22 16:23:44
// Design Name:
// Module Name: pulse_trans
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pulse_trans(
input clk,
input rst,
input p_in,
output p_out
);
// +-------------------+
// | |
//--------+ +-----------------------
// +-------------------+
// | |
//------------+ +--------------------
// +---+
// | |
//--------+ +----------------------------------------
reg p_in_delay;
always@(posedge clk or posedge rst)begin
if(rst)begin
p_in_delay <=1'b0;
end
else begin
p_in_delay <=p_in;
end
end
assign p_out = p_in & ~p_in_delay;
endmodule

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`define win_width 16
`define win_bytes 65536
///////////////////////////////////////////////////
//Karn算法在计算新的RTT时不考虑重传报文段的往返时间
///////////////////////////////////////////////////
module rto_calculator(
input clk,
input rst,
input retreat_ena,
input [31:0] RTO_min,
input paper_send_req,
input [31:0] tx_seqNo,
input [15:0] tx_data_len,
input retrans,
input paper_rcvd_req,
input [31:0] rx_ackNo,
input tcp_connected,
output [31:0] RTO,
output [31:0] RTT
);
//parameter RTO_min =32'd125_000;
//parameter RTO_min =32'd125_000*300; //300ms
(*keep="true"*)reg [31:0] RTT_M; //娴嬮噺RTT
(*keep="true"*)reg [31:0] RTT_S; //骞虫粦RTT
(*keep="true"*)reg [31:0] RTT_D; //RTT鍋忓樊
reg [31:0] measure_seqNo;
reg [15:0] measure_len;
reg flag_init;
reg measure_type; //0:正常1异常
reg [2:0] state;
reg [31:0] TIME_CNT;
reg TIME_ADD;
reg TIME_RST;
reg [31:0] RTO_reg;
wire [31:0] RTO_min_probe;
/*
vio_0 rto_vio(
.clk (clk ),
.probe_in0 (RTO_min_probe ),
.probe_out0 (RTO_min_probe )
);*/
assign RTO = RTO_reg+RTO_min; //RTO>300ms
//assign RTO = RTO_reg+RTO_min_probe;
assign RTT = RTT_S;
//////////////////////////////////////////////////////////
//RTT_S鐨勮<EFBFBD>绠楋細
//RTT_S=RTT_M
//RTT_S=1/8*RTT_S+7/8*RTT_M
//RTT_D鐨勮<EFBFBD>?
//RTT_D=RTT_M/2
//RTT_D=3/4*RTT_D+3/4*|RTT_S-RTT_M|
//RTO璁
//RTO=RTT_S+4*RTT_D
//////////////////////////////////////////////////////////
parameter wait_connected =3'd0,
measure_start =3'd1,
measure_over =3'd2,
measure_cal =3'd3,
rto_update =3'd4;
always@(posedge clk or posedge rst) begin
if(rst) begin
RTT_M <=0;
RTT_S <=0;
RTT_D <=0;
RTO_reg <=0;
TIME_ADD <=1'b0;
TIME_RST <=1'b0;
measure_seqNo <=0;
measure_len <=0;
flag_init <=0;
measure_type <=0;
state <=0;
end
else begin
case(state)
wait_connected:begin
RTO_reg <=32'd750_000_000; //6s
RTT_M <=0;
RTT_S <=0;
RTT_D <=0;
TIME_ADD <=1'b0;
TIME_RST <=1'b0;
measure_seqNo <=0;
flag_init <=0;
if(tcp_connected) begin
state <=measure_start;
end
else begin
state <=wait_connected;
end
end
measure_start:begin
if(tcp_connected) begin
if(paper_send_req && (tx_data_len!=0)) begin
measure_seqNo <=tx_seqNo;
measure_len <=tx_data_len;
TIME_ADD <=1'b1;
TIME_RST <=1'b0;
state <=measure_over;
end
else begin
state <=measure_start;
end
end
else begin
state <=wait_connected;
end
end
measure_over:begin
if(tcp_connected) begin
if(retrans)begin
measure_type <=1'b1;
TIME_ADD <=1'b0;
TIME_RST <=1'b1;
RTT_M <=RTT_M;
state <=measure_cal;
end
//seq seq+len-1 ack
else if(paper_rcvd_req && ((rx_ackNo-measure_seqNo)>=measure_len) && ((rx_ackNo-measure_seqNo)<=`win_bytes/*32'd32768*/)) begin//确认序号在测量起始数据包长度和8个MMS之间
measure_type <=1'b0;
TIME_ADD <=1'b0;
TIME_RST <=1'b1;
RTT_M <=TIME_CNT;
state <=measure_cal;
end
else begin
state <=measure_over;
end
end
else begin
state <=wait_connected;
end
end
measure_cal:begin
state <=rto_update;
flag_init <=1'b1;
if(flag_init==0) begin
RTT_S <=RTT_M;
RTT_D <=RTT_M>>1;
end
else if(measure_type==1'b0)begin //正常
RTT_S <=7*(RTT_S>>3)+(RTT_M>>3);
if(RTT_S>RTT_M) begin
RTT_D <=3*(RTT_D>>2)+((RTT_S-RTT_M)>>2);
end
else begin
RTT_D <=3*(RTT_D>>2)+((RTT_M-RTT_S)>>2);
end
end
else if(measure_type==1'b1)begin //发生了重传
RTT_S <=RTT_S;
RTT_D <=RTT_D;
end
end
rto_update:begin
state <=measure_start;
if(measure_type==1'b0)begin
RTO_reg <=RTT_S+(RTT_D<<2);
end
else if(measure_type==1'b1)begin
RTO_reg <=retreat_ena ? (RTO_reg<<1) : RTO_reg; //RTO指数退避
end
end
default:begin
state <=wait_connected;
end
endcase
end
end
//////////////////////////////////////////////////////////
//椂鍣<EFBFBD>紝鍗曚綅ns
//////////////////////////////////////////////////////////
always@(posedge clk or posedge rst) begin
if(rst) begin
TIME_CNT <=0;
end
else if(TIME_RST) begin
TIME_CNT <=0;
end
else if(TIME_ADD) begin
TIME_CNT <=TIME_CNT+1'b1;
end
else begin
TIME_CNT <=TIME_CNT;
end
end
//ila_rx_win ila_rx_win(
// .clk (clk),
// .probe0 ( {
// measure_seqNo, //32
// measure_len, //16
// state, //3
// paper_rcvd_req, //1
// rx_ackNo, //32
// TIME_ADD, //1
// RTT_M, //32
// measure_type, //1
// RTO_reg, //32 //150
// retrans,
// 39'd0
// }
// )
//);
endmodule

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@ -0,0 +1,735 @@
///////////////////////////////////////////////////////////////
//<EFBFBD><EFBFBD><EFBFBD>ܣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>մ<EFBFBD><EFBFBD>ڹ<EFBFBD><EFBFBD><EFBFBD>
//designed by Xiaodong Zhong
//2018.12.3
//a<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݵ<EFBFBD><EFBFBD><EFBFBD>Ž<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݷ<EFBFBD>Ϊ<EFBFBD><EFBFBD><EFBFBD>˳<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʧ<EFBFBD>򵽴<EFBFBD><EFBFBD><EFBFBD>ڽ<EFBFBD><EFBFBD>մ<EFBFBD><EFBFBD><EFBFBD>֮<EFBFBD>ڣ<EFBFBD>ʧ<EFBFBD>򵽴<EFBFBD><EFBFBD><EFBFBD>ڽ<EFBFBD><EFBFBD>մ<EFBFBD><EFBFBD><EFBFBD>֮<EFBFBD><EFBFBD>
//<EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD><EFBFBD><EFBFBD>ram,<EFBFBD><EFBFBD><EFBFBD>ڶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><EFBFBD>ram<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʧ<EFBFBD><EFBFBD><EFBFBD>¼<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//b<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ<EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD><EFBFBD><EFBFBD>ȡ˳<EFBFBD>򵽴<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//c<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȷ<EFBFBD>Ϻ<EFBFBD>
//d<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȷ<EFBFBD><EFBFBD>
///////////////////////////////////////////////////////////////
module rx_win_manage(
input clk,
input rst,
input [31:0] ack_delay_time,
input [15:0] rx_win_block,
input [15:0] mss,
output [15:0] rwnd_size,
input rwnd_set,
input [15:0] rwnd,
input remote_isn_set,
input [31:0] remote_isn,
output reg rw_send_ack_req,
input rw_send_ack_grant,
output [31:0] ackNo,
input tw_data_send_pulse,
input rw_rcvd_req,
output reg rw_rcvd_grant,
input [15:0] rw_data_len,
input [31:0] rw_seq_num,
output tcp_rx_data_fifo_rden,
input [7:0] tcp_rx_data_fifo_rddata,
output reg tcp_user_rx_fifo_wren,
output reg [7:0] tcp_user_rx_fifo_wrdata,
input tcp_user_rx_fifo_af,
// ddr interface
input user_wr_fifo_af,
output reg user_wr_fifo_wren,
output reg [7:0] user_wr_fifo_wrdata,
input user_wr_fifo_done,
output reg user_rd_req,
input user_rd_grant,
output reg [31:0] user_rd_addr,
output reg [31:0] user_rd_len,
input user_rd_fifo_empty,
output user_rd_fifo_rden,
input [7:0] user_rd_fifo_rddata //mask(3)+data(64)
);
//==============================================================
//three point logic
//==============================================================
//Rf------Rn------Rw
//Rf<EFBFBD><EFBFBD>Rn֮<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD><EFBFBD>û<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ<EFBFBD>ߣ<EFBFBD>Rn<EFBFBD><EFBFBD>Rw֮<EFBFBD><EFBFBD>TCP<EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD>Ĵ<EFBFBD><EFBFBD>ڴ<EFBFBD>С
reg [31:0] Rf; //<EFBFBD>û<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD><EFBFBD>ĵ<EFBFBD>һ<EFBFBD><EFBFBD><EFBFBD>ֽڵĵ<EFBFBD>ַ
reg [31:0] Rn; //TCPд<EFBFBD>ĵ<EFBFBD>һ<EFBFBD><EFBFBD><EFBFBD>ֽڵĵ<EFBFBD>ַ
reg [31:0] Rw; //<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ұ<EFBFBD>
wire [31:0] rx_win_left;
wire [31:0] user_avlb_cnt;
wire ackNo_update;
assign rx_win_left = Rw-Rn;
assign user_avlb_cnt = Rn-Rf;
assign rwnd_size = rx_win_left;
//Rf:Զ<EFBFBD>˳<EFBFBD>ʼ<EFBFBD><EFBFBD><EFBFBD>к<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>û<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD>
always@(posedge clk or posedge rst)begin
if(rst)begin
Rf <=0;
end
else if(remote_isn_set)begin
Rf <=remote_isn+1;
end
else if(user_rd_fifo_rden)begin
Rf <=Rf+1;
end
else begin
Rf <=Rf;
end
end
//Rw
always@(posedge clk or posedge rst)begin
if(rst)begin
Rw <=0;
end
else if(rwnd_set && remote_isn_set)begin
Rw <=remote_isn+1+rwnd;
end
else if(user_rd_fifo_rden)begin
Rw <=Rw+1;
end
else begin
Rw <=Rw;
end
end
//Rn:TCP<EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD><EFBFBD>ֽڵ<EFBFBD>ַ<EFBFBD><EFBFBD>TCPϣ<EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD><EFBFBD>ֽڵ<EFBFBD><EFBFBD><EFBFBD>ţ<EFBFBD>
assign ackNo = Rn;
//==============================================================
//data receive logic
//==============================================================
//parameter
localparam recv_idle = 3'd0,
recv_judge = 3'd1,
recv_abort = 3'd2,
recv_wr_info = 3'd3,
recv_wr_ddr = 3'd4,
recv_record = 3'd5,
recv_wr_done = 3'd6,
recv_check_t = 3'd7;
localparam In_range_accept = 2'b00,
In_range_abort = 2'b01,
In_range_keep = 2'b10,
Out_range = 2'b11;
//reg
reg [2:0] state;
reg [31:0] seqNo_reg;
reg [15:0] len_reg;
reg ready;
reg [1:0] recv_type;
reg if_disorder;
reg [10:0] i;
reg update_Rn_req;
reg update_Rn_grant;
reg table_wren;
reg [31:0] table_sof;
reg [31:0] table_eof;
wire table_busy;
wire table_empty;
wire table_full;
wire [15:0] ddr_start_addr;
wire [15:0] ddr_rd_addr;
reg table_check;
reg table_accept;
wire [31:0] ackNo_o;
//combinational logic
assign tcp_rx_data_fifo_rden = ready & ~user_wr_fifo_af;
assign ddr_start_addr = rx_win_block==16'd1023 ? seqNo_reg[9:0] :
rx_win_block==16'd2047 ? seqNo_reg[10:0] :
rx_win_block==16'd4095 ? seqNo_reg[11:0] :
rx_win_block==16'd8191 ? seqNo_reg[12:0] :
rx_win_block==16'd16383 ? seqNo_reg[13:0] :
rx_win_block==16'd32767 ? seqNo_reg[14:0] :
rx_win_block==16'd65535 ? seqNo_reg[15:0] : seqNo_reg[15:0];
assign ddr_rd_addr = rx_win_block==16'd1023 ? Rf[9:0] :
rx_win_block==16'd2047 ? Rf[10:0] :
rx_win_block==16'd4095 ? Rf[11:0] :
rx_win_block==16'd8191 ? Rf[12:0] :
rx_win_block==16'd16383 ? Rf[13:0] :
rx_win_block==16'd32767 ? Rf[14:0] :
rx_win_block==16'd65535 ? Rf[15:0] : Rf[15:0];
//fsm
always@(posedge clk or posedge rst)begin
if(rst)begin
state <=0;
ready <=0;
i <=0;
rw_rcvd_grant <=0;
user_wr_fifo_wren <=0;
user_wr_fifo_wrdata <=0;
seqNo_reg <=0;
len_reg <=0;
recv_type <=0;
if_disorder <=0;
table_sof <=0;
table_eof <=0;
table_wren <=0;
update_Rn_req <=0;
Rn <=0;
table_check <=0;
table_accept <=0;
end
else begin
case(state)
recv_idle:begin
user_wr_fifo_wren <=1'b0;
table_wren <=1'b0;
if(remote_isn_set)begin
Rn <=remote_isn+1;
end
else if(rw_rcvd_req)begin
rw_rcvd_grant <=1'b1;
seqNo_reg <=rw_seq_num;
len_reg <=rw_data_len;
state <=recv_judge;
end
else begin
state <=recv_idle;
end
end
recv_judge:begin
rw_rcvd_grant <=1'b0;
if(seqNo_reg==ackNo && rx_win_left>=len_reg)begin
if_disorder <=1'b0;
recv_type <=In_range_accept;
ready <=1'b0;
state <=recv_wr_info;
end
else if(seqNo_reg==ackNo && rx_win_left<len_reg)begin
if_disorder <=1'b1;
recv_type <=In_range_abort;
ready <=1'b1;
state <=recv_abort;
end
//Rn---(paper)---Rw
else if(seqNo_reg!=ackNo && (seqNo_reg+len_reg-1-Rn)<=rx_win_left && !table_full)begin
if_disorder <=1'b1;
recv_type <=In_range_keep;
ready <=1'b0;
state <=recv_wr_info;
end
else begin
if_disorder <=1'b1;
recv_type <=Out_range;
ready <=1'b1;
state <=recv_abort;
end
end
recv_abort:begin
if(tcp_rx_data_fifo_rden)begin
if(i==len_reg-1)begin
i <=0;
ready <=0;
state <=recv_idle;
end
else begin
i <=i+1;
end
end
else begin
i <=i;
end
end
recv_wr_info:begin
if(!user_wr_fifo_af)begin
user_wr_fifo_wren <=1'b1;
if(i==0)begin
i <=i+1;
user_wr_fifo_wrdata <=ddr_start_addr[15:8];
end
else if(i==1)begin
i <=i+1;
user_wr_fifo_wrdata <=ddr_start_addr[7:0];
end
else if(i==2)begin
i <=i+1;
user_wr_fifo_wrdata <=len_reg[15:8];
end
else if(i==3)begin
i <=0;
state <=recv_wr_ddr;
ready <=1'b1;
user_wr_fifo_wrdata <=len_reg[7:0];
end
end
else begin
user_wr_fifo_wren <=1'b0;
user_wr_fifo_wrdata <=user_wr_fifo_wrdata;
end
end
recv_wr_ddr:begin
if(tcp_rx_data_fifo_rden)begin
user_wr_fifo_wren <=1'b1;
user_wr_fifo_wrdata <=tcp_rx_data_fifo_rddata;
if(i==(len_reg-1))begin
i <=0;
ready <=0;
state <= (recv_type == In_range_accept) ? recv_wr_done :
(recv_type == In_range_keep ) ? recv_record : recv_idle;;
end
else begin
i <=i+1;
end
end
else begin
user_wr_fifo_wren <=1'b0;
user_wr_fifo_wrdata <=user_wr_fifo_wrdata;
end
end
recv_record:begin
user_wr_fifo_wren <=1'b0;
if(table_busy==0)begin
table_wren <=1;
table_sof <=seqNo_reg;
table_eof <=seqNo_reg+len_reg-1;
state <=recv_idle;
end
else begin
state <=recv_record;
end
end
recv_wr_done:begin //<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Rn
user_wr_fifo_wren <=1'b0;
if(user_wr_fifo_done)begin
Rn <=Rn+len_reg;
if(table_empty)begin
state <=recv_idle;
end
else begin
state <=recv_check_t;
table_check <=1;
end
end
end
recv_check_t:begin
table_check <=0;
if(table_busy)begin
table_accept <=1;
end
else if(table_accept && !table_busy)begin
table_accept <=0;
Rn <=ackNo_o;
state <=recv_idle;
end
end
default:begin
state <=recv_idle;
end
endcase
end
end
//==============================================================
//Rn (ackNo) update logic
//==============================================================
//state==recv_wr_done && recv_type==In_range_accept ==>Rn =Rn+len_reg
//<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʰȡ<EFBFBD><EFBFBD>Ч<EFBFBD>ֽڣ<EFBFBD>ÿ<EFBFBD>յ<EFBFBD><EFBFBD><EFBFBD>In_range_accept<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>disorder_table
localparam update_idle = 2'b00,
update_check = 2'b01,
update_add = 2'b10;
//reg [1:0] update_state;
//fsm
/*
always@(posedge clk or posedge rst)begin
if(rst)begin
Rn <=0;
update_state <=0;
update_Rn_grant <=0;
table_check <=0;
table_accept <=0;
end
else begin
case(update_state)
update_idle:begin
if(remote_isn_set)begin
Rn <=remote_isn+1;
end
else if(ackNo_update)begin
Rn <=ackNo_o;
end
else if(update_Rn_req)begin
update_Rn_grant <=1'b1;
update_state <=update_add;
//Rn <=Rn+len_reg;
//update_state <= table_empty ? update_idle : update_check;
//table_check <= table_empty ? 1'b0 : 1'b1;
end
else begin
update_state <=update_idle;
//Rn <=ackNo_o;
update_Rn_grant <=1'b0;
end
end
update_add:begin
update_Rn_grant <=1'b0;
Rn <=Rn+len_reg;
update_state <= table_empty ? update_idle : update_check;
table_check <= table_empty ? 1'b0 : 1'b1;
end
update_check:begin
table_check <=1'b0;
update_Rn_grant <=1'b0;
//Rn <=ackNo_o;
if(table_busy)begin
table_accept <=1;
update_state <=update_check;
end
else if(table_accept && !table_busy)begin
table_accept <=0;
Rn <=ackNo_o;
update_state <=update_idle;
end
end
default:begin
update_state <=update_idle;
end
endcase
end
end*/
//---------------------- disorder table loic-----------------------------
disorder_table21 U_disorder_table(
.clk (clk ),
.rst (rst ),
.rx_win_block (rx_win_block ),
.add (table_wren ),
.sof (table_sof ),
.eof (table_eof ),
.check (table_check ),
.ackNo_i (ackNo ),
.ackNo_o (ackNo_o ),
.update (ackNo_update ),
.table_busy (table_busy ),
.table_full (table_full ),
.table_empty (table_empty )
);
//==============================================================
//user read logic
//==============================================================
localparam rd_idle = 2'd0,
rd_wait_grant = 2'd1,
rd_wait_done = 2'd2;
reg [1:0] rd_state;
reg rd_ready;
reg [11:0] rd_cnt;
assign user_rd_fifo_rden = rd_ready & ~user_rd_fifo_empty & ~tcp_user_rx_fifo_af;
always@(posedge clk or posedge rst)begin
if(rst)begin
rd_state <=0;
user_rd_req <=0;
user_rd_len <=0;
user_rd_addr <=0;
rd_ready <=0;
rd_cnt <=0;
tcp_user_rx_fifo_wren <=0;
tcp_user_rx_fifo_wrdata <=0;
end
else begin
case(rd_state)
rd_idle:begin
tcp_user_rx_fifo_wren <=1'b0;
if(user_avlb_cnt!=0 /*&&*/ )begin /**************************************///<EFBFBD>û<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD>ܴ<EFBFBD><EFBFBD><EFBFBD>
user_rd_req <=1'b1;
user_rd_addr <=ddr_rd_addr;
rd_state <=rd_wait_grant;
if(user_avlb_cnt>=mss)begin
user_rd_len <=mss;
end
else begin
user_rd_len <=user_avlb_cnt;
end
end
else begin
rd_state <=rd_idle;
end
end
rd_wait_grant:begin
if(user_rd_grant)begin
user_rd_req <=1'b0;
rd_ready <=1'b1;
rd_state <=rd_wait_done;
end
else begin
rd_state <=rd_wait_grant;
end
end
rd_wait_done:begin
if(user_rd_fifo_rden)begin
tcp_user_rx_fifo_wren <=1'b1;
tcp_user_rx_fifo_wrdata <=user_rd_fifo_rddata;
if(rd_cnt==(user_rd_len-1))begin
rd_cnt <=0;
rd_ready <=0;
rd_state <=rd_idle;
end
else begin
rd_cnt <=rd_cnt+1;
end
end
else begin
tcp_user_rx_fifo_wren <=1'b0;
tcp_user_rx_fifo_wrdata <=tcp_user_rx_fifo_wrdata;
end
end
default:begin
rd_state <=rd_idle;
end
endcase
end
end
//==============================================================
//ACK send logic
//==============================================================
//<EFBFBD>ӳ<EFBFBD>ȷ<EFBFBD><EFBFBD>
//<EFBFBD>յ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>İ<EFBFBD>,<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȷ<EFBFBD><EFBFBD>
//<EFBFBD><EFBFBD><EFBFBD><EFBFBD>֮<EFBFBD><EFBFBD><EFBFBD>ܵ<EFBFBD>˳<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȷ<EFBFBD><EFBFBD>
localparam ack_idle = 2'b00,
ack_wait = 2'b01;
reg [1:0] ack_state;
reg [1:0] ack_counter;
reg [31:0] ack_delay_timer;
reg table_busy_delay;
reg after_disorder;
wire order_arrive;
wire disorder_arrive;
wire ack_delay_ok;
wire arrive_two;
wire table_update;
assign order_arrive = seqNo_reg==ackNo & rw_rcvd_req & rw_rcvd_grant;
assign disorder_arrive = seqNo_reg!=ackNo & rw_rcvd_req & rw_rcvd_grant;
assign ack_delay_ok = ack_delay_timer == ack_delay_time && ack_counter!=0;
assign arrive_two = ack_counter>=2 ? 1'b1 : 1'b0;
assign table_update = table_busy_delay & ~table_busy;
//-------------------------------------------------------------
//after disorder, expected seq arrive
always@(posedge clk or posedge rst)begin
if(rst)begin
after_disorder <=0;
end
else if(if_disorder==1'b1 && order_arrive)begin
after_disorder <=1;
end
else begin
after_disorder <=0;
end
end
//-------------------------------------------------------------
//disorder table update
always@(posedge clk or posedge rst)begin
if(rst)begin
table_busy_delay <=0;
end
else if(table_busy)begin
table_busy_delay <=table_busy;
end
else begin
table_busy_delay <=0;
end
end
//-------------------------------------------------------------
//ack delay timer
always@(posedge clk or posedge rst)begin
if(rst)begin
ack_delay_timer <=0;
end
else if(ack_counter>=1 && ack_delay_timer <ack_delay_time)begin
ack_delay_timer <=ack_delay_timer+1;
end
else if(ack_counter==0)begin
ack_delay_timer <=0;
end
end
//-------------------------------------------------------------
//ack delay
always@(posedge clk or posedge rst)begin
if(rst)begin
ack_counter <=0;
end
else if(order_arrive)begin
ack_counter <=ack_counter+1;
end
else if(rw_send_ack_req && rw_send_ack_grant || tw_data_send_pulse)begin
ack_counter <=0;
end
end
//-------------------------------------------------------------
//send ack request
always@(posedge clk or posedge rst)begin
if(rst)begin
rw_send_ack_req <=0;
ack_state <=ack_idle;
end
else begin
case(ack_state)
ack_idle:begin
if(disorder_arrive || ack_delay_ok || arrive_two || after_disorder || table_update)begin
ack_state <=ack_wait;
rw_send_ack_req <=1;
end
else begin
ack_state <=ack_idle;
end
end
ack_wait:begin
if(rw_send_ack_grant)begin
rw_send_ack_req <=0;
ack_state <=ack_idle;
end
else begin
ack_state <=ack_wait;
end
end
default:begin
ack_state <=ack_idle;
end
endcase
end
end
//////////////////////////////////////////////////////////////////
//<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
/////////////////////////////////////////////////////////////////
/*
reg [1:0] cnt;
reg [31:0] ping_data;
reg ping_valid;
reg ping_error;
reg [31:0] last_data;
always@(posedge clk or posedge rst)begin
if(rst)begin
cnt <=0;
ping_data <=0;
ping_valid <=0;
end
else if(cnt==0 && tcp_user_rx_fifo_wren)begin
ping_data <={ping_data[23:0],tcp_user_rx_fifo_wrdata};
cnt <=cnt+1;
ping_valid <=0;
end
else if(cnt==1 && tcp_user_rx_fifo_wren)begin
ping_data <={ping_data[23:0],tcp_user_rx_fifo_wrdata};
cnt <=cnt+1;
ping_valid <=0;
end
else if(cnt==2 && tcp_user_rx_fifo_wren)begin
ping_data <={ping_data[23:0],tcp_user_rx_fifo_wrdata};
cnt <=cnt+1;
ping_valid <=0;
end
else if(cnt==3 && tcp_user_rx_fifo_wren)begin
ping_data <={ping_data[23:0],tcp_user_rx_fifo_wrdata};
cnt <=cnt+1;
ping_valid <=1;
end
else begin
ping_valid <=0;
end
end
always@(posedge clk or posedge rst)begin
if(rst)begin
last_data <=0;
end
else if(ping_valid)begin
last_data <=ping_data;
end
else begin
last_data <=last_data;
end
end
always@(posedge clk or posedge rst)begin
if(rst)begin
ping_error <=0;
end
else if(ping_valid && ping_data!=32'h0000_0000 && ping_data!=(last_data+1))begin
ping_error <=1;
end
else begin
ping_error <=0;
end
end*/
//-------------------------------------------------------
//ila_200 ila_rx_win(
// .clk (clk ),
// .probe0 ({
// Rf,
// Rn,
// Rw, //96
// tcp_user_rx_fifo_wren,
// tcp_user_rx_fifo_wrdata,
// tcp_user_rx_fifo_af, //10
// state, //3
// rw_rcvd_req,
// rw_rcvd_grant,
// rw_data_len,
// rw_seq_num, //50
// rd_state, //2
// cnt,
// ping_data,
// ping_valid,
// ping_error,
// last_data, //70
// recv_type,
// 32'd0,
// user_rd_req,
// user_rd_grant,
// user_rd_addr[15:0],
// user_rd_len[10:0], //27
// user_rd_fifo_empty,
// user_rd_fifo_rden,
// user_rd_fifo_rddata //10
// })
//);
endmodule

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`define WIDTH 16
//////////////////////////////////////////////////
//ENgineer: Xiaodong Zhong
//Date: 2019.10.18
//Description: sram control top
//
//+----------------------------+
//////////////////////////////////////////////////
module sram_ctrl_top(
input clk,
input rst,
input [15:0] win_block,
//user write interface
input user_wr_fifo_empty,
output user_wr_fifo_rden,
input [7:0] user_wr_fifo_rddata,
output user_wr_done,
//user read interface
input user_rd_req,
output user_rd_grant,
input [31:0] user_rd_addr,
input [31:0] user_rd_len,
output user_rd_fifo_empty,
input user_rd_fifo_rden,
output [7:0] user_rd_fifo_rddata, //mask(3)+data(64)
//sram rd & wr interface
output sram_wren,
output [`WIDTH-1:0] sram_wraddr,
output [7:0] sram_wrdata,
output sram_rden,
output [`WIDTH-1:0] sram_rdaddr,
input [7:0] sram_rddata
);
/////////////////////////////////////////////////////////
//sram write
/////////////////////////////////////////////////////////
sram_write U_sram_write(
.clk (clk ),
.rst (rst ),
.win_block (win_block ),
.user_wr_fifo_empty (user_wr_fifo_empty ),
.user_wr_fifo_rden (user_wr_fifo_rden ),
.user_wr_fifo_rddata (user_wr_fifo_rddata ),
.user_wr_done (user_wr_done ),
.sram_wren (sram_wren ),
.sram_wraddr (sram_wraddr ),
.sram_wrdata (sram_wrdata )
);
/////////////////////////////////////////////////////////
//sram read
/////////////////////////////////////////////////////////
sram_read U_sram_read(
.clk (clk ),
.rst (rst ),
.win_block (win_block ),
.user_rd_req (user_rd_req ),
.user_rd_grant (user_rd_grant ),
.user_rd_addr (user_rd_addr ),
.user_rd_len (user_rd_len ),
.user_rd_fifo_empty (user_rd_fifo_empty ),
.user_rd_fifo_rden (user_rd_fifo_rden ),
.user_rd_fifo_rddata (user_rd_fifo_rddata), //mask(3)+data(64)
.sram_rden (sram_rden ),
.sram_rdaddr (sram_rdaddr ),
.sram_rddata (sram_rddata )
);
endmodule

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`define WIDTH 16
//////////////////////////////////////////////////
//ENgineer: Xiaodong Zhong
//Date: 2019.10.18
//Description: sram read
//
//////////////////////////////////////////////////
module sram_read(
input clk,
input rst,
input [15:0] win_block,
//user read interface
input user_rd_req,
output reg user_rd_grant,
input [31:0] user_rd_addr,
input [31:0] user_rd_len,
output user_rd_fifo_empty,
input user_rd_fifo_rden,
output [7:0] user_rd_fifo_rddata, //mask(3)+data(64)
output sram_rden,
output reg [`WIDTH-1:0] sram_rdaddr,
input [7:0] sram_rddata
);
///////////////////////////////////////////////////////////
//parameter
///////////////////////////////////////////////////////////
localparam idle = 2'd0,
read = 2'd1,
over = 2'd2;
///////////////////////////////////////////////////////////
//reg
///////////////////////////////////////////////////////////
reg [1:0] state;
reg [15:0] addr;
reg [15:0] len;
reg [15:0] i;
reg user_rd_fifo_wren;
///////////////////////////////////////////////////////////
//wire
///////////////////////////////////////////////////////////
wire user_rd_fifo_full;
wire user_rd_fifo_af;
wire [7:0] user_rd_fifo_wrdata;
///////////////////////////////////////////////////////////
//combinational logic
///////////////////////////////////////////////////////////
assign sram_rden = state == read && ~user_rd_fifo_af;
assign user_rd_fifo_wrdata = sram_rddata;
///////////////////////////////////////////////////////////
//fsm
///////////////////////////////////////////////////////////
always@(posedge clk or posedge rst)begin
if(rst)begin
state <=0;
user_rd_grant <=0;
sram_rdaddr <=0;
addr <=0;
len <=0;
i <=0;
end
else begin
case(state)
idle:begin
if(user_rd_req)begin
user_rd_grant <=1'b1;
addr <=user_rd_addr[15:0];
len <=user_rd_len[15:0];
sram_rdaddr <=user_rd_addr[15:0];
state <=read;
end
else begin
state <=idle;
end
end
read:begin
user_rd_grant <=1'b0;
if(sram_rden)begin
//sram_rdaddr <=sram_rdaddr == 16'h7FFF ? 16'h0000 : sram_rdaddr+1'b1;
sram_rdaddr <=sram_rdaddr == win_block ? 16'h0000 : sram_rdaddr+1'b1;
if(i==len-1)begin
i <=0;
state <=idle;
end
else begin
i <=i+1;
end
end
else begin
i <=i;
end
end
endcase
end
end
//
//fifo write delay
always@(posedge clk or posedge rst)begin
if(rst)begin
user_rd_fifo_wren <=1'b0;
end
else if(sram_rden)begin
user_rd_fifo_wren <=1'b1;
end
else begin
user_rd_fifo_wren <=1'b0;
end
end
///////////////////////////////////////////////////////////
//fifo
///////////////////////////////////////////////////////////
syn_fwft_fifo #(
.width (8),
.depth (64))
U_ddr_rd_fifo(
.clk (clk ),
.rst (rst ),
.clr (1'b0 ),
.wr_en (user_rd_fifo_wren ),
.din (user_rd_fifo_wrdata ),
.full (user_rd_fifo_full ),
.almost_full (user_rd_fifo_af ),
.rd_en (user_rd_fifo_rden ),
.dout (user_rd_fifo_rddata ),
.empty (user_rd_fifo_empty )
);
endmodule

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`define WIDTH 16
//////////////////////////////////////////////////
//ENgineer: Xiaodong Zhong
//Date: 2019.10.18
//Description: sram write
//
//+----------------------------+
//| addr(2) | len(2) | data*N |
//+----------------------------+
//////////////////////////////////////////////////
module sram_write(
input clk,
input rst,
input [15:0] win_block,
//user write interface
input user_wr_fifo_empty,
output user_wr_fifo_rden,
input [7:0] user_wr_fifo_rddata,
output reg user_wr_done,
output reg sram_wren,
output reg [`WIDTH-1:0] sram_wraddr,
output reg [7:0] sram_wrdata
);
///////////////////////////////////////////////////////////
//parameter
///////////////////////////////////////////////////////////
localparam idle = 2'd0,
get_addr_len = 2'd1,
write = 2'd2,
over = 2'd3;
///////////////////////////////////////////////////////////
//reg
///////////////////////////////////////////////////////////
reg [1:0] state;
reg ready;
reg [15:0] addr;
reg [15:0] len;
reg [15:0] i;
///////////////////////////////////////////////////////////
//wire
///////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////
//combinational logic
///////////////////////////////////////////////////////////
assign user_wr_fifo_rden = ~user_wr_fifo_empty & ready;
///////////////////////////////////////////////////////////
//fsm
///////////////////////////////////////////////////////////
always@(posedge clk or posedge rst)begin
if(rst)begin
state <=0;
ready <=0;
addr <=0;
len <=0;
i <=0;
user_wr_done <=0;
sram_wren <=0;
sram_wraddr <=0;
sram_wrdata <=0;
end
else begin
case(state)
idle:begin
user_wr_done <=1'b0;
if(!user_wr_fifo_empty)begin
ready <=1;
state <=get_addr_len;
end
else begin
ready <=0;
state <=idle;
end
end
get_addr_len:begin
if(user_wr_fifo_rden)begin
if(i==0)begin
addr <={addr[7:0],user_wr_fifo_rddata};
i <=i+1;
end
else if(i==1)begin
addr <={addr[7:0],user_wr_fifo_rddata};
i <=i+1;
end
else if(i==2)begin
len <={len[7:0],user_wr_fifo_rddata};
i <=i+1;
end
else if(i==3)begin
len <={len[7:0],user_wr_fifo_rddata};
i <=0;
state <=write;
end
end
else begin
i <=i;
addr <=addr;
len <=len;
end
end
write:begin
if(user_wr_fifo_rden)begin
sram_wren <=1;
sram_wraddr <=addr;
sram_wrdata <=user_wr_fifo_rddata;
//addr <=(addr==16'h7FFF )? 16'h0000 : (addr+1);
addr <=(addr==win_block )? 16'h0000 : (addr+1);
if(i==len-1)begin
ready <=0;
i <=0;
state <=over;
end
else begin
i <=i+1;
end
end
else begin
sram_wren <=0;
addr <=addr;
end
end
over:begin
sram_wren <=0;
user_wr_done <=1;
state <=idle;
end
endcase
end
end
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/08/20 11:33:24
// Design Name:
// Module Name: tcp_recv
// Description:
// (1)<EFBFBD><EFBFBD>֡<EFBFBD><EFBFBD>У<EFBFBD><EFBFBD>͹<EFBFBD><EFBFBD><EFBFBD>
// (2)<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>8<EFBFBD><EFBFBD>
// //tcp:20-60byte
// +----------------------------------------------------------------------------+
// | src_port(16) | dst_port (16) |
// +----------------------------------------------------------------------------+
// | seq_no(32) |
// +----------------------------------------------------------------------------+
// | ack_no(32) |
// +----------------------------------------------------------------------------+
// | hlen(4) | R(6) |URG|ACK|PSH|RST|SYN|FIN| win_size(16) |
// +----------------------------------------------------------------------------+
// | checksum(16) | urg_point(16) |
// +----------------------------------------------------------------------------+
//tcpα<EFBFBD>ײ<EFBFBD>
// +----------------------------------------------------------------------------+
// | src_ip(32) |
// +----------------------------------------------------------------------------+
// | dst_ip(32) |
// +----------------------------------------------------------------------------+
// | 8'h00 | 8'h06 | tcp_total_len(16) |
// +----------------------------------------------------------------------------+
//////////////////////////////////////////////////////////////////////////////////
module tcp_recv(
input clk,
input rst,
input [31:0] local_ip,
input [7:0] connected,
output [1:0] recv_sel,
input [7:0] port_en,
input [31:0] port0,
input [31:0] port1,
input [31:0] port2,
input [31:0] port3,
input [31:0] port4,
input [31:0] port5,
input [31:0] port6,
input [31:0] port7,
input tcp_recv_fifo_empty,
output tcp_recv_fifo_rden,
input [8:0] tcp_recv_fifo_rddata,
input tcp_recv_data_fifo_af,
input [10:0] tcp_recv_data_fifo_cnt,
output reg tcp_recv_data_fifo_clr,
output reg tcp_recv_data_fifo_wren,
output reg [7:0] tcp_recv_data_fifo_wrdata,
output reg paper_rcvd_req,
input paper_rcvd_grant,
output reg [31:0] src_ip,
output reg [31:0] src_dst_port,
output reg [31:0] seq_no,
output reg [31:0] ack_no,
output reg [5:0] ctrl_flag,
output reg [15:0] win_size,
output reg [15:0] recv_data_len,
//tcp option
output reg [15:0] mss, //maximum segment size
output reg [7:0] wss, //window scale size
output reg [63:0] timestamp,
output reg sack_permitted,
output reg [2:0] sack_block_num, //1-4
output reg [63:0] sack_block0,
output reg [63:0] sack_block1,
output reg [63:0] sack_block2,
output reg [63:0] sack_block3
);
/////////////////////////////////////////////////////
//parameter
/////////////////////////////////////////////////////
localparam idle = 4'd0,
recv_src_port = 4'd1,
recv_dst_port = 4'd2,
recv_seq_no = 4'd3,
recv_ack_no = 4'd4,
recv_hlen_flag = 4'd5,
recv_win_size = 4'd6,
recv_chk_urg_p = 4'd7,
recv_option = 4'd8,
recv_data = 4'd9,
recv_src_ip = 4'd10,
check_chksum = 4'd11,
clear_fifo = 4'd12,
send_req = 4'd13,
wait_end = 4'd14;
localparam EOP = 8'd0,
NOP = 8'd1,
MSSx = 8'd2,
WSF = 8'd3,
ASACK = 8'd4,
SACK = 8'd5,
TSTMP = 8'd8;
/////////////////////////////////////////////////////
//reg & wire
/////////////////////////////////////////////////////
reg [3:0] state;
reg ready;
reg [2:0] cnt;
reg [3:0] hlen;
reg [7:0] op_part_cnt;
reg [7:0] op_type;
reg [7:0] op_len;
reg [7:0] op_len_cnt;
reg [10:0] data_cnt;
wire [15:0] total_len;
wire [7:0] port_match;
wire [6:0] op_part_len;
/////////////////////////////////////////////////////
//combinational logic
/////////////////////////////////////////////////////
assign tcp_recv_fifo_rden = (state!=recv_data) ? (~tcp_recv_fifo_empty & ready)
: (~tcp_recv_fifo_empty & ready & ~tcp_recv_data_fifo_af);
assign port_match[0] = (connected[0] ? port0==src_dst_port : port0[15:0] == src_dst_port[15:0]) && port_en[0];
assign port_match[1] = (connected[1] ? port1==src_dst_port : port1[15:0] == src_dst_port[15:0]) && port_en[1];
assign port_match[2] = (connected[2] ? port2==src_dst_port : port2[15:0] == src_dst_port[15:0]) && port_en[2];
assign port_match[3] = (connected[3] ? port3==src_dst_port : port3[15:0] == src_dst_port[15:0]) && port_en[3];
assign port_match[4] = (connected[4] ? port4==src_dst_port : port4[15:0] == src_dst_port[15:0]) && port_en[4];
assign port_match[5] = (connected[5] ? port5==src_dst_port : port5[15:0] == src_dst_port[15:0]) && port_en[5];
assign port_match[6] = (connected[6] ? port6==src_dst_port : port6[15:0] == src_dst_port[15:0]) && port_en[6];
assign port_match[7] = (connected[7] ? port7==src_dst_port : port7[15:0] == src_dst_port[15:0]) && port_en[7];
assign op_part_len = (hlen-5)<<2; //(hlen-5)*4
assign total_len = data_cnt+hlen*4;
assign recv_sel ={port_match[1],port_match[0]};
//---------------------------------------------------------------------------------
//<EFBFBD><EFBFBD><EFBFBD><EFBFBD>У<EFBFBD><EFBFBD><EFBFBD>
localparam add_data = 2'd0,
add_fake_head = 2'd1,
add_out = 2'd2;
reg [1:0] add_state;
reg k;
reg [31:0] chk_buf;
reg [7:0] data_buf;
reg [1:0] add_cnt;
reg check_ok;
reg [31:0] chk_buf_a;
always@( * )begin
chk_buf_a = chk_buf[31:16]+chk_buf[15:0];
check_ok = ~(chk_buf_a[31:16]+chk_buf_a[15:0])==16'h00 ? 1'b1 : 1'b0;
end
always@(posedge clk or posedge rst)begin
if(rst)begin
add_state <=0;
k <=0;
chk_buf <=0;
data_buf <=0;
add_cnt <=0;
end
else begin
case(add_state)
add_data:begin
if(tcp_recv_fifo_rden)begin
if(tcp_recv_fifo_rddata[8] && k==1)begin //even bytes
chk_buf <=chk_buf+{data_buf[7:0],tcp_recv_fifo_rddata[7:0]};
k <=0;
add_state <=add_fake_head;
end
else if(tcp_recv_fifo_rddata[8] && k==0)begin //odd bytes
chk_buf <=chk_buf+{tcp_recv_fifo_rddata[7:0],8'h00};
add_state <=add_fake_head;
end
else if(k==0)begin
data_buf <=tcp_recv_fifo_rddata[7:0];
k <=k+1;
end
else if(k==1)begin
chk_buf <=chk_buf+{data_buf[7:0],tcp_recv_fifo_rddata[7:0]};
k <=0;
end
end
end
add_fake_head:begin
if(tcp_recv_fifo_rden)begin
if(add_cnt==0)begin
chk_buf <=chk_buf+16'h0006+total_len;
add_cnt <=add_cnt+1;
end
else if(add_cnt==1)begin
chk_buf <=chk_buf+local_ip[15:0]+local_ip[31:16];
add_cnt <=add_cnt+1;
end
else if(add_cnt==2)begin
chk_buf <=chk_buf+src_ip[15:0];
add_cnt <=add_cnt+1;
end
else if(add_cnt==3)begin
chk_buf <=chk_buf+{src_ip[7:0],tcp_recv_fifo_rddata[7:0]};
add_cnt <=0;
add_state <=add_out;
end
end
else begin
add_state <=add_fake_head;
end
end
add_out:begin
chk_buf <=0;
add_state <=add_data;
end
default:begin
add_state <=add_data;
end
endcase
end
end
//---------------------------------------------------------------------------------
//tcp<EFBFBD><EFBFBD>ʽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
always@(posedge clk or posedge rst)begin
if(rst)begin
state <=0;
ready <=0;
tcp_recv_data_fifo_clr <=0;
tcp_recv_data_fifo_wren <=0;
tcp_recv_data_fifo_wrdata <=0;
src_ip <=0;
src_dst_port <=0;
seq_no <=0;
ack_no <=0;
ctrl_flag <=0;
win_size <=0;
recv_data_len <=0;
cnt <=0;
hlen <=0;
op_part_cnt <=0;
data_cnt <=0;
//total_len <=0;
paper_rcvd_req <=0;
end
else begin
case(state)
idle:begin
data_cnt <=0;
if(!tcp_recv_fifo_empty)begin
ready <=1;
state <=recv_src_port;
end
else begin
state <=idle;
end
end
recv_src_port:begin
if(tcp_recv_fifo_rden)begin
src_dst_port <={src_dst_port[23:0],tcp_recv_fifo_rddata[7:0]};
if(cnt==1)begin
cnt <=0;
state <=recv_dst_port;
end
else begin
cnt <=cnt+1;
end
end
else begin
state <=recv_src_port;
end
end
recv_dst_port:begin
if(tcp_recv_fifo_rden)begin
src_dst_port <={src_dst_port[23:0],tcp_recv_fifo_rddata[7:0]};
if(cnt==1)begin
cnt <=0;
state <=recv_seq_no;
end
else begin
cnt <=cnt+1;
end
end
else begin
state <=recv_dst_port;
end
end
recv_seq_no:begin
if(tcp_recv_fifo_rden)begin
seq_no <={seq_no[23:0],tcp_recv_fifo_rddata[7:0]};
if(port_match==8'h00)begin
state <=wait_end;
end
else begin
if(cnt==3)begin
cnt <=0;
state <=recv_ack_no;
end
else begin
cnt <=cnt+1;
end
end
end
else begin
state <=recv_seq_no;
end
end
recv_ack_no:begin
if(tcp_recv_fifo_rden)begin
ack_no <={ack_no[23:0],tcp_recv_fifo_rddata[7:0]};
if(cnt==3)begin
cnt <=0;
state <=recv_hlen_flag;
end
else begin
cnt <=cnt+1;
end
end
else begin
state <=recv_ack_no;
end
end
recv_hlen_flag:begin
if(tcp_recv_fifo_rden)begin
if(cnt==0)begin
hlen <=tcp_recv_fifo_rddata[7:4];
cnt <=cnt+1;
end
else if(cnt==1)begin
ctrl_flag <=tcp_recv_fifo_rddata[5:0];
cnt <=0;
state <=recv_win_size;
end
end
else begin
state <=recv_hlen_flag;
end
end
recv_win_size:begin
if(tcp_recv_fifo_rden)begin
win_size <={win_size[7:0],tcp_recv_fifo_rddata[7:0]};
if(cnt==1)begin
cnt <=0;
state <=recv_chk_urg_p;
end
else begin
cnt <=cnt+1;
end
end
else begin
state <=recv_win_size;
end
end
recv_chk_urg_p:begin
if(tcp_recv_fifo_rden)begin
if(cnt==3 && tcp_recv_fifo_rddata[8])begin
cnt <=0;
//state <=send_req;
state <=recv_src_ip;
end
else if(cnt==3 && ~tcp_recv_fifo_rddata[8])begin
cnt <=0;
if(op_part_len!=0)begin
state <=recv_option;
end
else begin
state <=recv_data;
end
end
else begin
cnt <=cnt+1;
end
end
end
recv_option:begin
if(tcp_recv_fifo_rden) begin
//<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
if(op_part_cnt==(op_part_len-1) && tcp_recv_fifo_rddata[8]) begin
state <=recv_src_ip;
op_part_cnt <=0;
end
else if(op_part_cnt==(op_part_len-1) && !tcp_recv_fifo_rddata[8]) begin
state <=recv_data;
op_part_cnt <=0;
end
else begin
op_part_cnt <=op_part_cnt+1;
end
end
end
recv_data:begin
if(tcp_recv_fifo_rden)begin
data_cnt <=data_cnt+1;
tcp_recv_data_fifo_wren <=1;
tcp_recv_data_fifo_wrdata <=tcp_recv_fifo_rddata[7:0];
if(tcp_recv_fifo_rddata[8])begin
//total_len <=data_cnt+1+hlen*4;
state <=recv_src_ip;
end
else begin
state <=recv_data;
end
end
else begin
tcp_recv_data_fifo_wren <=0;
tcp_recv_data_fifo_wrdata <=tcp_recv_data_fifo_wrdata;
state <=recv_data;
end
end
recv_src_ip:begin
tcp_recv_data_fifo_wren <=0;
if(tcp_recv_fifo_rden)begin
src_ip <={src_ip[23:0],tcp_recv_fifo_rddata[7:0]};
if(cnt==3)begin
cnt <=0;
ready <=0;
state <=check_chksum;
end
else begin
cnt <=cnt+1;
end
end
else begin
state <=recv_src_ip;
end
end
check_chksum:begin
recv_data_len <= data_cnt;
if(add_state==add_out && check_ok)begin
state <=send_req;
end
else if(add_state==add_out && !check_ok)begin
state <=clear_fifo;
end
else begin
state <=check_chksum;
end
end
clear_fifo:begin
if(cnt==0)begin
//<EFBFBD><EFBFBD>ֹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
if(tcp_recv_data_fifo_cnt==recv_data_len)begin
tcp_recv_data_fifo_clr <=1;
cnt <=cnt+1;
end
else begin
tcp_recv_data_fifo_clr <=0;
cnt <=cnt;
end
end
else if(cnt==3)begin
cnt <=0;
state <=idle;
tcp_recv_data_fifo_clr <=0;
end
else begin
cnt <=cnt+1;
end
end
send_req:begin
paper_rcvd_req <=1;
recv_data_len <=data_cnt;
if(paper_rcvd_grant)begin
state <=idle;
paper_rcvd_req <=0;
end
else begin
state <=send_req;
end
end
//wait last
wait_end:begin
if(tcp_recv_fifo_rddata[8] && tcp_recv_fifo_rden)begin
if(cnt==4)begin
ready <=0;
state <=idle;
cnt <=0;
end
else begin
ready <=1;
cnt <=cnt+1;
end
end
else begin
ready <=1;
state <=wait_end;
end
end
default:begin
state <=idle;
end
endcase
end
end
//---------------------------------------------------------------------------
//<EFBFBD><EFBFBD><EFBFBD><EFBFBD>tcpѡ<EFBFBD><EFBFBD>
localparam analyze_type = 2'd0,
analyze_len = 2'd1,
analyze_op = 2'd2;
reg [1:0] analyze_state;
always@(posedge clk or posedge rst)begin
if(rst)begin
analyze_state <=0;
mss <=0; //maximum segment size
wss <=0; //window scale size
timestamp <=0;
sack_permitted <=0;
sack_block_num <=0;
sack_block0 <=0;
sack_block1 <=0;
sack_block2 <=0;
sack_block3 <=0;
op_type <=0;
op_len <=0;
op_len_cnt <=0;
end
else if(state==recv_option && tcp_recv_fifo_rden)begin
case(analyze_state) //0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD>1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȣ<EFBFBD>2<EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD>
analyze_type:begin
if(tcp_recv_fifo_rddata[7:0]==8'd0) begin //EOP
analyze_state <=analyze_type;
op_type <=EOP;
end
else if(tcp_recv_fifo_rddata[7:0]==8'd1) begin //NOP
analyze_state <=analyze_type;
op_type <=NOP;
end
else if(tcp_recv_fifo_rddata[7:0]==8'd2) begin //MSS
analyze_state <=analyze_len;
op_type <=MSSx;
end
else if(tcp_recv_fifo_rddata[7:0]==8'd3) begin //WSF
analyze_state <=analyze_len;
op_type <=WSF;
end
else if(tcp_recv_fifo_rddata[7:0]==8'd4) begin //ASACK;
analyze_state <=analyze_len;
op_type <=ASACK;
sack_permitted <=1;
end
else if(tcp_recv_fifo_rddata[7:0]==8'd5) begin //SACK
analyze_state <=analyze_len;
op_type <=SACK;
end
else if(tcp_recv_fifo_rddata[7:0]==8'd8) begin //STMP
analyze_state <=analyze_len;
op_type <=TSTMP;
end
else begin
op_type <=op_type;
analyze_state <=analyze_state;
end
end
analyze_len:begin //<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
if((op_type==MSSx) || (op_type==WSF) || (op_type==TSTMP) || (op_type==SACK))begin
op_len <=tcp_recv_fifo_rddata[7:0]-2;
analyze_state <=analyze_op;
sack_block_num <=op_type==SACK ? ((tcp_recv_fifo_rddata[7:0]-2)>>3) : 0;
end
else if(op_type==ASACK) begin
op_len <=tcp_recv_fifo_rddata[7:0];
analyze_state <=analyze_type;
end
end
analyze_op:begin //<EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD>
if(op_type==MSSx) begin
mss <={mss[7:0],tcp_recv_fifo_rddata[7:0]};
if(op_len_cnt==0) begin
op_len_cnt <=op_len_cnt+1;
end
else begin
op_len_cnt <=0;
analyze_state <=analyze_type;
end
end
else if(op_type==WSF) begin
wss <=tcp_recv_fifo_rddata[7:0];
analyze_state <=analyze_type;
end
else if(op_type==TSTMP) begin
timestamp <={timestamp[55:0],tcp_recv_fifo_rddata[7:0]};
if(op_len_cnt==7) begin
op_len_cnt <=0;
analyze_state <=analyze_type;
end
else begin
op_len_cnt <=op_len_cnt+1;
end
end
else if(op_type==SACK) begin
//null
if(op_len_cnt==(op_len-1)) begin
op_len_cnt <=0;
analyze_state <=analyze_type;
end
else begin
op_len_cnt <=op_len_cnt+1;
end
if(op_len_cnt <=7)begin
sack_block0 <={sack_block0[23:0],tcp_recv_fifo_rddata[7:0]};
end
else if(op_len_cnt<=15)begin
sack_block1 <={sack_block1[23:0],tcp_recv_fifo_rddata[7:0]};
end
else if(op_len_cnt<=23)begin
sack_block2 <={sack_block2[23:0],tcp_recv_fifo_rddata[7:0]};
end
else if(op_len_cnt <=31)begin
sack_block3 <={sack_block3[23:0],tcp_recv_fifo_rddata[7:0]};
end
end
end
default:begin
analyze_state <=analyze_type;
end
endcase
end
else if(state!=recv_option)begin
analyze_state <=analyze_type;
op_len_cnt <=0;
end
end
//---------------------------------------------------------------------
//ila_32 ila_tcp_recv( //122
// .clk (clk ),
// .probe0 ({
// state, //4
// analyze_state, //2
// tcp_recv_fifo_empty, //1
// tcp_recv_fifo_rden, //1
// tcp_recv_fifo_rddata, //9
// paper_rcvd_req, //1
// paper_rcvd_grant, //1
// 13'd0
// })
//);
endmodule

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@ -0,0 +1,388 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/08/20 15:53:05
// Design Name:
// Module Name: tcp_send
// Description:
//
// //tcp:20-60byte
// +----------------------------------------------------------------------------+
// | src_port(16) | dst_port (16) |
// +----------------------------------------------------------------------------+
// | seq_no(32) |
// +----------------------------------------------------------------------------+
// | ack_no(32) |
// +----------------------------------------------------------------------------+
// | hlen(4) | R(6) |URG|ACK|PSH|RST|SYN|FIN| win_size(16) |
// +----------------------------------------------------------------------------+
// | checksum(16) | urg_point(16) |
// +----------------------------------------------------------------------------+
//tcpα<EFBFBD>ײ<EFBFBD>
// +----------------------------------------------------------------------------+
// | src_ip(32) |
// +----------------------------------------------------------------------------+
// | dst_ip(32) |
// +----------------------------------------------------------------------------+
// | 8'h00 | 8'h06 | tcp_total_len(16) |
// +----------------------------------------------------------------------------+
//////////////////////////////////////////////////////////////////////////////////
module tcp_send(
input clk,
input rst,
input [31:0] local_ip,
output tcp_send_data_fifo_rden,
input [7:0] tcp_send_data_fifo_rddata,
input paper_send_req,
output reg paper_send_grant,
output paper_pro_over,
input [11:0] send_data_len,
input [31:0] send_data_chk,
input [31:0] dst_ip,
input [31:0] src_dst_port,
input [31:0] seq_no,
input [31:0] ack_no,
input [5:0] ctrl_flag,
input [15:0] win_size,
//tcp option
input [3:0] op_ena,
input [31:0] op1, //maximum segment size
input [31:0] op2, //window scale size
input [31:0] op3,
input [31:0] op4,
input [31:0] op5,
input [31:0] op6,
input [31:0] op7,
input [31:0] op8,
input [31:0] op9,
input [31:0] op10,
output reg tcp_send_req,
input tcp_send_grant,
output reg [31:0] tcp_send_dst_ip,
output reg [15:0] tcp_send_len,
input tcp_send_fifo_af,
output reg tcp_send_fifo_wren,
output reg [7:0] tcp_send_fifo_wrdata
);
//////////////////////////////////////////////
//parameter
//////////////////////////////////////////////
localparam idle = 3'd0,
make_head = 3'd1,
latch_chksum = 3'd2,
wait_send_over = 3'd3,
send_req = 3'd4;
localparam idle_b = 2'd0,
send_head = 2'd1,
send_data = 2'd2,
send_over = 2'd3;
//////////////////////////////////////////////
//reg & wire
//////////////////////////////////////////////
reg [2:0] state_a;
reg [1:0] state_b;
reg ready;
//reg [31:0] tcp_head [0:18];
reg [31:0] tcp_head [0:17]; //modified 2020.09.21
reg [3:0] cnt;
reg [31:0] chksum;
reg [31:0] chk_buf_a;
reg [31:0] chk_buf_b;
reg [3:0] op_ena_reg;
reg [11:0] send_data_len_reg;
reg [31:0] send_data_chk_reg;
reg [7:0] hlen_byte;
//reg [1:0] i;
reg [11:0] data_cnt;
wire [15:0] tcp_total_len;
wire [3:0] hlen;
wire paper_send_start;
wire paper_send_over;
//////////////////////////////////////////////
//combinational logic
//////////////////////////////////////////////
assign tcp_send_data_fifo_rden = ready & !tcp_send_fifo_af;
assign tcp_total_len = send_data_len+20+op_ena*4;
assign hlen = 5+op_ena;
always@( * )begin
chk_buf_a = chksum[31:16]+chksum[15:0];
chk_buf_b = ~(chk_buf_a[31:16]+chk_buf_a[15:0]);
end
assign paper_send_over = state_b == send_over;
assign paper_send_start = state_a == make_head && cnt==0;
assign paper_pro_over = paper_send_over;
//////////////////////////////////////////////
//fsm
//////////////////////////////////////////////
//initial begin
// tcp_head[0] =0;
// tcp_head[1] =0;
// tcp_head[2] =0;
// tcp_head[3] =0;
// tcp_head[4] =0;
// tcp_head[5] =0;
// tcp_head[6] =0;
// tcp_head[7] =0;
// tcp_head[8] =0;
// tcp_head[9] =0;
// tcp_head[10] =0;
// tcp_head[11] =0;
// tcp_head[12] =0;
// tcp_head[13] =0;
// tcp_head[14] =0;
// tcp_head[15] =0;
// tcp_head[16] =0;
// tcp_head[17] =0;
// tcp_head[18] =0;
//end
//-------------------------------------------------------------------------------
//make tcp head & control
always@(posedge clk or posedge rst)begin
if(rst)begin
state_a <=0;
paper_send_grant <=0;
cnt <=0;
chksum <=0;
tcp_send_req <=0;
tcp_send_dst_ip <=0;
tcp_send_len <=0;
op_ena_reg <=0;
send_data_len_reg <=0;
send_data_chk_reg <=0;
hlen_byte <=0;
tcp_head[0] <=0;
tcp_head[1] <=0;
tcp_head[2] <=0;
tcp_head[3] <=0;
tcp_head[4] <=0;
tcp_head[5] <=0;
tcp_head[6] <=0;
tcp_head[7] <=0;
tcp_head[8] <=0;
tcp_head[9] <=0;
tcp_head[10] <=0;
tcp_head[11] <=0;
tcp_head[12] <=0;
tcp_head[13] <=0;
tcp_head[14] <=0;
tcp_head[15] <=0;
tcp_head[16] <=0;
tcp_head[17] <=0;
//tcp_head[18] <=0;
end
else begin
case(state_a)
idle:begin
if(paper_send_req)begin
state_a <=make_head;
chksum <=0;
paper_send_grant <=1;
op_ena_reg <=op_ena;
send_data_len_reg <=send_data_len;
send_data_chk_reg <=send_data_chk;
hlen_byte <=20+op_ena*4;
//tcp fake head
tcp_head[0] <=local_ip;
tcp_head[1] <=dst_ip;
tcp_head[2] <={16'h0006,tcp_total_len};
//tcp head
tcp_head[3] <=src_dst_port;
tcp_head[4] <=seq_no;
tcp_head[5] <=ack_no;
tcp_head[6] <={hlen[3:0],6'h0,ctrl_flag,win_size[15:0]};
tcp_head[7] <={16'h0000,16'h0000};
//tcp_head[8] <=send_data_chk;
tcp_head[8] <=op1;
tcp_head[9] <=op2;
tcp_head[10] <=op3;
tcp_head[11] <=op4;
tcp_head[12] <=op5;
tcp_head[13] <=op6;
tcp_head[14] <=op7;
tcp_head[15] <=op8;
tcp_head[16] <=op9;
tcp_head[17] <=op10;
end
else begin
state_a <=idle;
end
end
make_head:begin
paper_send_grant <=0;
if(cnt==(hlen+2))begin
if(send_data_len_reg!=0)begin
chksum <=chksum+tcp_head[cnt][31:16]+tcp_head[cnt][15:0]+send_data_chk_reg;
end
else begin
chksum <=chksum+tcp_head[cnt][31:16]+tcp_head[cnt][15:0];
end
cnt <=0;
state_a <=latch_chksum;
end
else begin
chksum <=chksum+tcp_head[cnt][31:16]+tcp_head[cnt][15:0];
cnt <=cnt+1;
state_a <=make_head;
end
end
latch_chksum:begin
tcp_head[7] <={chk_buf_b[15:0],16'h0000};
state_a <=wait_send_over;
end
wait_send_over:begin
if(paper_send_over)begin
paper_send_grant <=0;
state_a <=send_req;
end
else begin
state_a <=wait_send_over;
end
end
send_req:begin
tcp_send_req <=1;
tcp_send_dst_ip <=tcp_head[1];
tcp_send_len <=tcp_head[2];
if(tcp_send_grant)begin
tcp_send_req <=0;
state_a <=idle;
end
else begin
state_a <=send_req;
end
end
default:begin
state_a <=0;
end
endcase
end
end
//-------------------------------------------------------------------------------
//send_data
wire [4:0] head_addr;
assign head_addr = data_cnt[6:2]+3;
always@(posedge clk or posedge rst)begin
if(rst)begin
ready <=0;
state_b <=idle_b;
tcp_send_fifo_wren <=0;
tcp_send_fifo_wrdata <=0;
data_cnt <=0;
end
else begin
case(state_b)
idle_b:begin
if(paper_send_start)begin
state_b <=send_head;
end
else begin
state_b <=idle_b;
end
end
send_head:begin
if(!tcp_send_fifo_af)begin
tcp_send_fifo_wren <=1;
tcp_send_fifo_wrdata <=data_cnt[1:0]==2'b00 ? tcp_head[head_addr][31:24] :
data_cnt[1:0]==2'b01 ? tcp_head[head_addr][23:16] :
data_cnt[1:0]==2'b10 ? tcp_head[head_addr][15:8] :
data_cnt[1:0]==2'b11 ? tcp_head[head_addr][7:0] : 8'h00;
if(data_cnt==(hlen_byte-1))begin
data_cnt <=0;
if(send_data_len_reg!=0)begin
ready <=1;
state_b <=send_data;
end
else begin
state_b <=send_over;
end
end
else begin
data_cnt <=data_cnt+1;
end
end
else begin
tcp_send_fifo_wren <=0;
tcp_send_fifo_wrdata <=tcp_send_fifo_wrdata;
end
end
send_data:begin
if(tcp_send_data_fifo_rden)begin
tcp_send_fifo_wren <=1;
tcp_send_fifo_wrdata <=tcp_send_data_fifo_rddata;
if(data_cnt==(send_data_len_reg-1))begin
data_cnt <=0;
ready <=0;
state_b <=send_over;
end
else begin
data_cnt <=data_cnt+1;
end
end
else begin
tcp_send_fifo_wren <=0;
tcp_send_fifo_wrdata <=tcp_send_fifo_wrdata;
end
end
send_over:begin
tcp_send_fifo_wren <=0;
state_b <=idle_b;
end
default:begin
state_b <=idle_b;
end
endcase
end
end
//----------------------------------------------------------
//ila_200 ila_tcp_send(
// .clk (clk ),
// .probe0 ({
// paper_send_req, //1
// paper_send_grant, //1
// send_data_len, //12
// send_data_chk,
// input [31:0] dst_ip,
// input [31:0] src_dst_port,
// input [31:0] seq_no,
// input [31:0] ack_no,
// input [5:0] ctrl_flag,
// input [15:0] win_size,
// //tcp option
// input [3:0] op_ena,
// })
//);
endmodule

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

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@ -0,0 +1,63 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/09/20 10:15:18
// Design Name:
// Module Name: timer
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module timer(
input clk,
input rst,
input ena,
output reg ck
);
parameter one_ms =32'd125_000;
reg [31:0] cnt;
//
//counter 0-124999
always@(posedge clk or posedge rst)begin
if( rst)begin
cnt <=0;
end
else if(ena)begin
if(cnt==(one_ms-1))begin
cnt <=0;
end
else begin
cnt <=cnt+1;
end
end
else begin
cnt <=cnt;
end
end
//one_ms heart generator
always@(posedge clk or posedge rst)begin
if(rst)begin
ck <=1'b0;
end
else if(ena && cnt==10)begin
ck <=1'b1;
end
else begin
ck <=1'b0;
end
end
endmodule

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@ -0,0 +1,97 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/08/28 10:12:20
// Design Name:
// Module Name: tmp_decode
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tmp_decode(
input [47:0] din,
output reg [5:0] tmp_code
);
always@( * )begin
case(1'b0)
din[0]: tmp_code =0;
din[1]: tmp_code =1;
din[2]: tmp_code =2;
din[3]: tmp_code =3;
din[4]: tmp_code =4;
din[5]: tmp_code =5;
din[6]: tmp_code =6;
din[7]: tmp_code =7;
din[8]: tmp_code =8;
din[9]: tmp_code =9;
din[10]: tmp_code =10;
din[11]: tmp_code =11;
din[12]: tmp_code =12;
din[13]: tmp_code =13;
din[14]: tmp_code =14;
din[15]: tmp_code =15;
din[16]: tmp_code =16;
din[17]: tmp_code =17;
din[18]: tmp_code =18;
din[19]: tmp_code =19;
din[20]: tmp_code =20;
din[21]: tmp_code =21;
din[22]: tmp_code =22;
din[23]: tmp_code =23;
din[24]: tmp_code =24;
din[25]: tmp_code =25;
din[26]: tmp_code =26;
din[27]: tmp_code =27;
din[28]: tmp_code =28;
din[29]: tmp_code =29;
din[30]: tmp_code =30;
din[31]: tmp_code =31;
din[32]: tmp_code =32;
din[33]: tmp_code =33;
din[34]: tmp_code =34;
din[35]: tmp_code =35;
din[36]: tmp_code =36;
din[37]: tmp_code =37;
din[38]: tmp_code =38;
din[39]: tmp_code =39;
din[40]: tmp_code =40;
din[41]: tmp_code =41;
din[42]: tmp_code =42;
din[43]: tmp_code =43;
din[44]: tmp_code =44;
din[45]: tmp_code =45;
din[46]: tmp_code =46;
din[47]: tmp_code =47;
default:begin
tmp_code=6'b11_1111;
end
endcase
end
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/08/14 16:32:34
// Design Name:
// Module Name: toe_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
// +---------------------------------------------------------------+
// | app |
// +---------------------------------------------------------------+
// | tcp | udp |
// +---------------------------------------------------------------+
// | ip | arp |
// +---------------------------------------------------------------+
// | mac |
// +---------------------------------------------------------------+
//////////////////////////////////////////////////////////////////////////////////
module toe_top_s (
input clk,
input rst,
//host interface:apb bus
input reg_clk,
input reg_rst,
input [31:0] reg_addr,
input reg_wren,
input [31:0] reg_wrdata,
input reg_rden,
output[31:0] reg_rddata,
//interrupt
output intr,
output ex_in,
//gmac interface
//output [1:0] mac_speed,
//output update_speed,
output [3:0] s0_tcp_state,
output mac_rx_ready,
input mac_rx_valid,
input [7:0] mac_rx_data,
input mac_rx_last,
input mac_tx_ready,
output mac_tx_valid,
output [7:0] mac_tx_data,
output mac_tx_last,
//udp app interface
input udp_app_recv_fifo_rdclk,
output udp_app_recv_fifo_empty,
output [11:0]udp_app_recv_fifo_rdcnt,
input udp_app_recv_fifo_rden,
output [7:0] udp_app_recv_fifo_rddata,
output udp_app_send_fifo_rdclk,
input udp_app_send_fifo_empty,
input [11:0] udp_app_send_fifo_rdcnt,
output udp_app_send_fifo_rden,
input [7:0] udp_app_send_fifo_rddata,
//tcp app interface
output s0_user_tx_fifo_rdclk, // <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
input [11:0] s0_user_tx_fifo_rdcnt,
output s0_user_tx_fifo_rden,
input [7:0] s0_user_tx_fifo_rddata,
input s0_user_rx_fifo_rdclk, // <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
output s0_user_rx_fifo_empty,
input s0_user_rx_fifo_rden,
output [7:0] s0_user_rx_fifo_rddata
// output s1_user_tx_fifo_rdclk,
// input [11:0] s1_user_tx_fifo_rdcnt,
// output s1_user_tx_fifo_rden,
// input [7:0] s1_user_tx_fifo_rddata,
// input s1_user_rx_fifo_rdclk,
// output s1_user_rx_fifo_empty,
// input s1_user_rx_fifo_rden,
// output [7:0] s1_user_rx_fifo_rddata
);
//
//arp - mac interafce
wire arp_send_fifo_empty;
wire arp_send_fifo_rden;
wire [8:0] arp_send_fifo_rddata;
wire arp_recv_fifo_empty;
wire arp_recv_fifo_rden;
wire [8:0] arp_recv_fifo_rddata;
//
//ip - mac interface
wire ip_send_fifo_empty;
wire ip_send_fifo_rden;
wire [8:0] ip_send_fifo_rddata;
wire ip_recv_fifo_empty;
wire ip_recv_fifo_rden;
wire [8:0] ip_recv_fifo_rddata;
//
//ip->arp ip resolve interface
wire ip_rslv_req;
wire ip_rslv_grant;
wire [31:0] ip_rslv_ip;
wire ip_rslvd_req;
wire ip_rslvd_grant;
wire [80:0] ip_rslvd_ipmac;
//udp interface
wire udp_recv_fifo_empty;
wire udp_recv_fifo_rden;
wire [8:0] udp_recv_fifo_rddata;
wire udp_send_req;
wire udp_send_grant;
wire [31:0] udp_send_dst_ip;
wire [15:0] udp_send_len;
wire udp_send_fifo_rden;
wire [7:0] udp_send_fifo_rddata;
//tcp interface
wire tcp_recv_fifo_empty;
wire tcp_recv_fifo_rden;
wire [8:0] tcp_recv_fifo_rddata;
wire tcp_send_req;
wire tcp_send_grant;
wire [31:0] tcp_send_dst_ip;
wire [15:0] tcp_send_len;
wire tcp_send_fifo_rden;
wire [7:0] tcp_send_fifo_rddata;
//icmp interface
wire icmp_recv_fifo_empty;
wire icmp_recv_fifo_rden;
wire [8:0] icmp_recv_fifo_rddata;
wire icmp_send_req;
wire icmp_send_grant;
wire [31:0] icmp_send_dst_ip;
wire [15:0] icmp_send_len;
wire icmp_send_fifo_rden;
wire [7:0] icmp_send_fifo_rddata;
//
//configuration
wire [47:0] local_mac;
wire [31:0] local_ip;
wire [31:0] gate_ip;
wire [31:0] gate_mask;
wire [7:0] ifg;
wire [3:0] retry_time;
wire [31:0] live_time;
wire [80:0] static_table0;
wire [80:0] static_table1;
wire [80:0] static_table2;
wire [80:0] static_table3;
wire arp_error;
wire [31:0] udp_dst_ip;
wire [15:0] udp_local_port;
wire [15:0] udp_dst_port;
wire [15:0] udp_send_thre;
wire udp_send_mode;
wire [15:0] tx_win_block;
wire [15:0] rx_win_block;
wire [31:0] orr_thre;
wire [31:0] tw_thre;
wire [15:0] mss;
wire [31:0] ack_delay_time;
wire Nagle_disable;
wire [3:0] retrans_thre;
wire [31:0] Nagle_delay_time;
wire [31:0] RTO_min;
wire retreat_ena;
//tcp socket0
wire [31:0] s0_dst_ip;
wire [15:0] s0_port;
wire [15:0] s0_dst_port;
wire s0_s_c;
wire s0_active_open_req;
wire s0_active_open_grant;
wire s0_passive_open_req;
wire s0_passive_open_grant;
wire s0_link_close_req;
wire s0_link_close_grant;
//wire [3:0] s0_tcp_state;
wire [31:0] s0_tx_ddr_base;
wire [31:0] s0_rx_ddr_base;
wire [31:0] s0_RTT;
//tcp socket1
wire [31:0] s1_dst_ip;
wire [15:0] s1_port;
wire [15:0] s1_dst_port;
wire s1_s_c;
wire s1_active_open_req;
wire s1_active_open_grant=0;
wire s1_passive_open_req;
wire s1_passive_open_grant=0;
wire s1_link_close_req;
wire s1_link_close_grant=0;
wire [3:0] s1_tcp_state=0;
wire [31:0] s1_tx_ddr_base;
wire [31:0] s1_rx_ddr_base;
wire [31:0] s1_RTT=0;
//icmp
wire icmp_req;
wire icmp_grant;
wire [31:0] icmp_dst_ip;
wire [31:0] icmp_len_type_code;
wire [63:0] icmp_time;
wire icmp_intr;
wire [31:0] icmp_intr_state;
wire ms_ck;
wire want_arp;
wire icmp_recv_overflow;
wire udp_recv_overflow;
wire tcp_recv_overflow;
wire s0_retrans_int;
wire s1_retrans_int=0;
wire s0_link_successful;
wire s0_link_fail;
wire s0_remote_link_close;
wire s0_link_close_fail;
wire s1_link_successful=0;
wire s1_link_fail=0;
wire s1_remote_link_close=0;
wire s1_link_close_fail=0;
wire tcp_ip_bind;
wire [31:0] tcp_drop_cnt;
wire [31:0] tcp_recv_cnt_max;
///////////////////////////////////////////////////////
//mac pkg
///////////////////////////////////////////////////////
mac_top U_mac_top(
.clk (clk ),
.rst (rst ),
.local_mac (local_mac ),
.ifg (ifg ),
.mac_rx_ready (mac_rx_ready ),
.mac_rx_valid (mac_rx_valid ),
.mac_rx_data (mac_rx_data ),
.mac_rx_last (mac_rx_last ),
.mac_tx_ready (mac_tx_ready ),
.mac_tx_valid (mac_tx_valid ),
.mac_tx_data (mac_tx_data ),
.mac_tx_last (mac_tx_last ),
.arp_send_fifo_empty (arp_send_fifo_empty ),
.arp_send_fifo_rden (arp_send_fifo_rden ),
.arp_send_fifo_rddata (arp_send_fifo_rddata ),
.arp_recv_fifo_empty (arp_recv_fifo_empty ),
.arp_recv_fifo_rden (arp_recv_fifo_rden ),
.arp_recv_fifo_rddata (arp_recv_fifo_rddata ),
.ip_send_fifo_empty (ip_send_fifo_empty ),
.ip_send_fifo_rden (ip_send_fifo_rden ),
.ip_send_fifo_rddata (ip_send_fifo_rddata ),
.ip_recv_fifo_empty (ip_recv_fifo_empty ),
.ip_recv_fifo_rden (ip_recv_fifo_rden ),
.ip_recv_fifo_rddata (ip_recv_fifo_rddata )
);
///////////////////////////////////////////////////////
//arp pkg
///////////////////////////////////////////////////////
arp_top U_arp_top(
.clk (clk ),
.rst (rst ),
.local_mac (local_mac ),
.local_ip (local_ip ),
.retry_time (retry_time ),
.live_time (live_time ),
.static_table0 (static_table0 ),
.static_table1 (static_table1 ),
.static_table2 (static_table2 ),
.static_table3 (static_table3 ),
.arp_error (arp_error ),
.ip_rslv_req (ip_rslv_req ),
.ip_rslv_grant (ip_rslv_grant ),
.ip_rslv_ip (ip_rslv_ip ),
.ip_rslvd_req (ip_rslvd_req ),
.ip_rslvd_grant (ip_rslvd_grant ),
.ip_rslvd_ipmac (ip_rslvd_ipmac ),
.want_arp (want_arp ),
.arp_recv_fifo_empty (arp_recv_fifo_empty ),
.arp_recv_fifo_rden (arp_recv_fifo_rden ),
.arp_recv_fifo_rddata (arp_recv_fifo_rddata ),
.arp_send_fifo_empty (arp_send_fifo_empty ),
.arp_send_fifo_rden (arp_send_fifo_rden ),
.arp_send_fifo_rddata (arp_send_fifo_rddata )
);
///////////////////////////////////////////////////////
// ip pkg
///////////////////////////////////////////////////////
ip_top U_ip_top(
.clk (clk ),
.rst (rst ),
.local_ip (local_ip ),
.gate_ip (gate_ip ),
.gate_mask (gate_mask ),
//arp interface
.ip_rslv_req (ip_rslv_req ),
.ip_rslv_grant (ip_rslv_grant ),
.ip_rslv_ip (ip_rslv_ip ),
.ip_rslvd_req (ip_rslvd_req ),
.ip_rslvd_grant (ip_rslvd_grant ),
.ip_rslvd_ipmac (ip_rslvd_ipmac ),
.want_arp (want_arp ),
//mac interface
.ip_recv_fifo_empty (ip_recv_fifo_empty ),
.ip_recv_fifo_rden (ip_recv_fifo_rden ),
.ip_recv_fifo_rddata (ip_recv_fifo_rddata ),
.ip_send_fifo_empty (ip_send_fifo_empty ),
.ip_send_fifo_rden (ip_send_fifo_rden ),
.ip_send_fifo_rddata (ip_send_fifo_rddata ),
//udp interface
.udp_recv_fifo_empty (udp_recv_fifo_empty ),
.udp_recv_fifo_rden (udp_recv_fifo_rden ),
.udp_recv_fifo_rddata (udp_recv_fifo_rddata ),
.udp_send_req (udp_send_req ),
.udp_send_grant (udp_send_grant ),
.udp_send_dst_ip (udp_send_dst_ip ),
.udp_send_len (udp_send_len ),
.udp_send_fifo_rden (udp_send_fifo_rden ),
.udp_send_fifo_rddata (udp_send_fifo_rddata ),
//tcp interface
.tcp_recv_fifo_empty (tcp_recv_fifo_empty ),
.tcp_recv_fifo_rden (tcp_recv_fifo_rden ),
.tcp_recv_fifo_rddata (tcp_recv_fifo_rddata ),
.tcp_send_req (tcp_send_req ),
.tcp_send_grant (tcp_send_grant ),
.tcp_send_dst_ip (tcp_send_dst_ip ),
.tcp_send_len (tcp_send_len ),
.tcp_send_fifo_rden (tcp_send_fifo_rden ),
.tcp_send_fifo_rddata (tcp_send_fifo_rddata ),
//icmp interface
.icmp_recv_fifo_empty (icmp_recv_fifo_empty ),
.icmp_recv_fifo_rden (icmp_recv_fifo_rden ),
.icmp_recv_fifo_rddata (icmp_recv_fifo_rddata),
.icmp_send_req (icmp_send_req ),
.icmp_send_grant (icmp_send_grant ),
.icmp_send_dst_ip (icmp_send_dst_ip ),
.icmp_send_len (icmp_send_len ),
.icmp_send_fifo_rden (icmp_send_fifo_rden ),
.icmp_send_fifo_rddata (icmp_send_fifo_rddata),
.icmp_recv_overflow (icmp_recv_overflow ),
.udp_recv_overflow (udp_recv_overflow ),
.tcp_recv_overflow (tcp_recv_overflow ),
.tcp_drop_cnt (tcp_drop_cnt ),
.tcp_recv_cnt_max (tcp_recv_cnt_max )
);
///////////////////////////////////////////////////////
//icmp pkg
///////////////////////////////////////////////////////
icmp_top U_icmp_top(
.clk (clk ),
.rst (rst ),
.ms_ck (ms_ck ),
.host_req (icmp_req ),
.host_grant (icmp_grant ),
.host_dst_ip (icmp_dst_ip ),
.host_type_code ({16'b0,icmp_len_type_code[15:0]} ),
.host_tx_len (icmp_len_type_code[27:16] ),
.host_intr (icmp_intr ),
.host_intr_state (icmp_intr_state ),
.host_time (icmp_time ), //tx_time+rx_time
.icmp_recv_fifo_empty (icmp_recv_fifo_empty ),
.icmp_recv_fifo_rden (icmp_recv_fifo_rden ),
.icmp_recv_fifo_rddata (icmp_recv_fifo_rddata),
.icmp_send_req (icmp_send_req ),
.icmp_send_grant (icmp_send_grant ),
.icmp_send_dst_ip (icmp_send_dst_ip ),
.icmp_send_len (icmp_send_len ),
.icmp_send_fifo_empty (icmp_send_fifo_empty ),
.icmp_send_fifo_rden (icmp_send_fifo_rden ),
.icmp_send_fifo_rddata (icmp_send_fifo_rddata)
);
///////////////////////////////////////////////////////
// udp pkg
///////////////////////////////////////////////////////
udp_top U_udp_top(
.clk (clk ),
.rst (rst ),
.dst_ip (udp_dst_ip ),
.local_port (udp_local_port ),
.dst_port (udp_dst_port ),
.send_mode (udp_send_mode ),
.send_thre (udp_send_thre ),
//udp interface
.udp_recv_fifo_empty (udp_recv_fifo_empty ),
.udp_recv_fifo_rden (udp_recv_fifo_rden ),
.udp_recv_fifo_rddata (udp_recv_fifo_rddata ),
.udp_send_req (udp_send_req ),
.udp_send_grant (udp_send_grant ),
.udp_send_len (udp_send_len ),
.udp_send_dst_ip (udp_send_dst_ip ),
.udp_send_fifo_empty (udp_send_fifo_empty ),
.udp_send_fifo_rden (udp_send_fifo_rden ),
.udp_send_fifo_rddata (udp_send_fifo_rddata ),
//app interface
.app_recv_fifo_rdclk (udp_app_recv_fifo_rdclk ),
.app_recv_fifo_empty (udp_app_recv_fifo_empty ),
.app_recv_fifo_rdcnt (udp_app_recv_fifo_rdcnt ),
.app_recv_fifo_rden (udp_app_recv_fifo_rden ),
.app_recv_fifo_rddata (udp_app_recv_fifo_rddata),
.app_send_fifo_rdclk (udp_app_send_fifo_rdclk ),
.app_send_fifo_empty (udp_app_send_fifo_empty ),
.app_send_fifo_rdcnt (udp_app_send_fifo_rdcnt ),
.app_send_fifo_rden (udp_app_send_fifo_rden ),
.app_send_fifo_rddata (udp_app_send_fifo_rddata)
);
///////////////////////////////////////////////////////
//tcp pkg
///////////////////////////////////////////////////////
tcp_top_s U_tcp_top(
.clk (clk ),
.rst (rst ),
.local_ip (local_ip ),
.socket0_dst_ip (s0_dst_ip ),
// .socket1_dst_ip (s1_dst_ip ),
.socket0_port (s0_port ),
.socket1_port (s1_port ),
.socket2_port (16'd0),
.socket3_port (16'd0),
.socket4_port (16'd0),
.socket5_port (16'd0),
.socket6_port (16'd0),
.socket7_port (16'd0),
.tx_win_block (tx_win_block ),
.rx_win_block (rx_win_block ),
.orr_thre (orr_thre ),
.tw_thre (tw_thre ),
.mss (mss ),
.ack_delay_time (ack_delay_time ),
.Nagle_disable (Nagle_disable ),
.retrans_thre (retrans_thre ),
.Nagle_delay_time (Nagle_delay_time ),
.RTO_min (RTO_min ),
.retreat_ena (retreat_ena ),
.tcp_ip_bind (tcp_ip_bind ),
.socket0_dst_port (s0_dst_port ),
.socket0_s_c (s0_s_c ),
.s0_tcp_state (s0_tcp_state ),
.s0_RTT (s0_RTT ),
.s0_tx_ddr_base (s0_tx_ddr_base ),
.s0_rx_ddr_base (s0_rx_ddr_base ),
.socket0_retrans_int (s0_retrans_int ),
.s0_active_open_req (s0_active_open_req ),
.s0_active_open_grant (s0_active_open_grant ),
.s0_passive_open_req (s0_passive_open_req ),
.s0_passive_open_grant (s0_passive_open_grant ),
.s0_link_close_req (s0_link_close_req ),
.s0_link_close_grant (s0_link_close_grant ),
// .socket1_dst_port (s1_dst_port ),
// .socket1_s_c (s1_s_c ),
// .s1_tcp_state (s1_tcp_state ),
// .s1_RTT (s1_RTT ),
// .s1_tx_ddr_base (s1_tx_ddr_base ),
// .s1_rx_ddr_base (s1_rx_ddr_base ),
// .socket1_retrans_int (s1_retrans_int ),
// .s1_active_open_req (s1_active_open_req ),
// .s1_active_open_grant (s1_active_open_grant ),
// .s1_passive_open_req (s1_passive_open_req ),
// .s1_passive_open_grant (s1_passive_open_grant ),
// .s1_link_close_req (s1_link_close_req ),
// .s1_link_close_grant (s1_link_close_grant ),
.s0_user_tx_fifo_rdcnt (s0_user_tx_fifo_rdcnt ),
.s0_user_tx_fifo_rden (s0_user_tx_fifo_rden ),
.s0_user_tx_fifo_rddata (s0_user_tx_fifo_rddata ),
.s0_user_rx_fifo_rdclk (s0_user_rx_fifo_rdclk ),
.s0_user_rx_fifo_empty (s0_user_rx_fifo_empty ),
.s0_user_rx_fifo_rden (s0_user_rx_fifo_rden ),
.s0_user_rx_fifo_rddata (s0_user_rx_fifo_rddata ),
// .s1_user_tx_fifo_rdcnt (s1_user_tx_fifo_rdcnt ),
// .s1_user_tx_fifo_rden (s1_user_tx_fifo_rden ),
// .s1_user_tx_fifo_rddata (s1_user_tx_fifo_rddata ),
// .s1_user_rx_fifo_rdclk (s1_user_rx_fifo_rdclk ),
// .s1_user_rx_fifo_empty (s1_user_rx_fifo_empty ),
// .s1_user_rx_fifo_rden (s1_user_rx_fifo_rden ),
// .s1_user_rx_fifo_rddata (s1_user_rx_fifo_rddata ),
.tcp_recv_fifo_empty (tcp_recv_fifo_empty ),
.tcp_recv_fifo_rden (tcp_recv_fifo_rden ),
.tcp_recv_fifo_rddata (tcp_recv_fifo_rddata ),
.tcp_send_req (tcp_send_req ),
.tcp_send_grant (tcp_send_grant ),
.tcp_send_dst_ip (tcp_send_dst_ip ),
.tcp_send_len (tcp_send_len ),
.tcp_send_fifo_empty (tcp_send_fifo_empty ),
.tcp_send_fifo_rden (tcp_send_fifo_rden ),
.tcp_send_fifo_rddata (tcp_send_fifo_rddata ),
.s0_link_successful (s0_link_successful ),
.s0_link_fail (s0_link_fail ),
.s0_remote_link_close (s0_remote_link_close ),
.s0_link_close_fail (s0_link_close_fail )
// .s1_link_successful (s1_link_successful ),
// .s1_link_fail (s1_link_fail ),
// .s1_remote_link_close (s1_remote_link_close ),
// .s1_link_close_fail (s1_link_close_fail )
);
///////////////////////////////////////////////////////
//ms clock
///////////////////////////////////////////////////////
timer U_timer(
.clk (clk ),
.rst (rst ),
.ena (1'b1 ),
.ck (ms_ck )
);
///////////////////////////////////////////////////////
//regfile
///////////////////////////////////////////////////////
toe_regfile U_toe_regfile (
.clk (clk ),
.rst (rst ),
.reg_clk (reg_clk ),
.reg_rst (reg_rst ),
.reg_addr (reg_addr ),
.reg_wren (reg_wren ),
.reg_wrdata (reg_wrdata ),
.reg_rden (reg_rden ),
.reg_rddata (reg_rddata ),
.intr (intr),
.local_mac_sync (local_mac ),
.local_ip_sync (local_ip ),
.udp_dst_ip_sync (udp_dst_ip ),
.ifg_sync (ifg ),
.local_port_sync (udp_local_port ),
.remote_port_sync (udp_dst_port ),
.retry_time_sync (retry_time ),
.live_time_sync (live_time ),
.st0_sync (static_table0 ),
.st1_sync (static_table1 ),
.st2_sync (static_table2 ),
.st3_sync (static_table3 ),
.udp_thre_sync (udp_send_thre ),
.udp_send_mode_sync (udp_send_mode ),
.gate_ip_sync (gate_ip ),
.gate_mask_sync (gate_mask ),
.tx_win_block_sync (tx_win_block ),
.rx_win_block_sync (rx_win_block ),
.orr_thre_sync (orr_thre ),
.tw_thre_sync (tw_thre ),
.mss_sync (mss ),
.ack_delay_time_sync (ack_delay_time ),
.Nagle_disable_sync (Nagle_disable ),
.retrans_thre_sync (retrans_thre ),
.Nagle_delay_time_sync (Nagle_delay_time ),
.RTO_min_sync (RTO_min ),
.retreat_ena_sync (retreat_ena ),
//tcp socket0
.s0_dst_ip_sync (s0_dst_ip ),
.s0_port_sync (s0_port ),
.s0_dst_port_sync (s0_dst_port ),
.s0_s_c_sync (s0_s_c ),
.s0_active_open_req (s0_active_open_req ),
.s0_active_open_grant (s0_active_open_grant ),
.s0_passive_open_req (s0_passive_open_req ),
.s0_passive_open_grant (s0_passive_open_grant ),
.s0_link_close_req (s0_link_close_req ),
.s0_link_close_grant (s0_link_close_grant ),
.s0_tcp_state (s0_tcp_state ),
.s0_tx_ddr_base_sync (s0_tx_ddr_base ),
.s0_rx_ddr_base_sync (s0_rx_ddr_base ),
.s0_RTT (s0_RTT ),
//tcp socket0
.s1_dst_ip_sync (s1_dst_ip ),
.s1_port_sync (s1_port ),
.s1_dst_port_sync (s1_dst_port ),
.s1_s_c_sync (s1_s_c ),
.s1_active_open_req (s1_active_open_req ),
.s1_active_open_grant (s1_active_open_grant ),
.s1_passive_open_req (s1_passive_open_req ),
.s1_passive_open_grant (s1_passive_open_grant ),
.s1_link_close_req (s1_link_close_req ),
.s1_link_close_grant (s1_link_close_grant ),
.s1_tcp_state (s1_tcp_state ),
.s1_tx_ddr_base_sync (s1_tx_ddr_base ),
.s1_rx_ddr_base_sync (s1_rx_ddr_base ),
.s1_RTT (s1_RTT ),
//icmp
.icmp_req (icmp_req ),
.icmp_grant (icmp_grant ),
.icmp_dst_ip_sync (icmp_dst_ip ),
.icmp_len_type_code_sync (icmp_len_type_code ),
.icmp_time (icmp_time ),
.icmp_intr_state (icmp_intr_state ),
//error
.icmp_recv_overflow (icmp_recv_overflow ),
.udp_recv_overflow (udp_recv_overflow ),
.tcp_recv_overflow (tcp_recv_overflow ),
.arp_error (arp_error ),
.s0_retrans_int (s0_retrans_int ),
.s1_retrans_int (s1_retrans_int ),
.s0_link_successful (s0_link_successful ),
.s0_link_fail (s0_link_fail ),
.s0_remote_link_close (s0_remote_link_close ),
.s0_link_close_fail (s0_link_close_fail ),
.s1_link_successful (s1_link_successful ),
.s1_link_fail (s1_link_fail ),
.s1_remote_link_close (s1_remote_link_close ),
.s1_link_close_fail (s1_link_close_fail ),
.tcp_ip_bind_sync (tcp_ip_bind ),
.ex_in (ex_in ),
.tcp_drop_cnt (tcp_drop_cnt ),
.tcp_recv_cnt_max (tcp_recv_cnt_max )
);
//============================================================
assign s0_user_tx_fifo_rdclk =clk;
//assign s1_user_tx_fifo_rdclk =clk;
//assign intr = tcp_recv_overflow | arp_error | s0_retrans_int | s1_retrans_int;
//(*dont_touch = "true"*)reg [0 : 0] ila_tcp_recv_fifo_empty;
//(*dont_touch = "true"*)reg [0 : 0] ila_tcp_recv_fifo_rden;
//(*dont_touch = "true"*)reg [8 : 0] ila_tcp_recv_fifo_rddata;
//always @(posedge clk ) begin
// ila_tcp_recv_fifo_empty <= tcp_recv_fifo_empty;
// ila_tcp_recv_fifo_rden <= tcp_recv_fifo_rden ;
// ila_tcp_recv_fifo_rddata <= tcp_recv_fifo_rddata;
//end
// ila_toe_top ila_toe_top_s(
// .clk(s0_user_tx_fifo_rdclk),
// .probe0({s0_user_tx_fifo_rdcnt, s0_user_tx_fifo_rden, s0_user_tx_fifo_rddata, s0_user_rx_fifo_empty, s0_user_rx_fifo_rden, s0_user_rx_fifo_rddata}), // 32
// .probe1({mac_rx_ready, mac_rx_valid, mac_rx_data, mac_rx_last, arp_recv_fifo_empty, arp_recv_fifo_rden, arp_recv_fifo_rddata, ip_recv_fifo_empty, ip_recv_fifo_rden, ip_recv_fifo_rddata}), // 33
// .probe2({tcp_recv_fifo_empty,tcp_recv_fifo_rden, tcp_recv_fifo_rddata}) // 11
// );
//ila_toe_top ila_toe_top_s(
// .clk(s0_user_rx_fifo_rdclk),
// .probe0({s0_user_tx_fifo_rdcnt, s0_user_tx_fifo_rden, s0_user_tx_fifo_rddata, s0_user_rx_fifo_empty, s0_user_rx_fifo_rden, s0_user_rx_fifo_rddata}) // 32
//);
endmodule

View File

@ -0,0 +1,848 @@
`define win_width 16
`define win_bytes 65536
///////////////////////////////////////////////////////////////
//功能发送窗口的管理
//designed by Xiaodong Zhong
//2018.12.3
///////////////////////////////////////////////////////////////
module tx_win_manage(
input clk,
input rst,
input [15:0] tx_win_block,
//config
input connected,
input nagle_disable,
input [31:0] rto_thre,
input [31:0] rtt,
input [15:0] mss,
input [3:0] retrans_thre,
input [31:0] Nagle_delay_time,
output reg over_time_occur,
output reg over_dup_occur,
output retrans_int, //重传5次失败
input [11:0] tcp_user_fifo_rdcnt, //2048
output tcp_user_fifo_rden,
input [7:0] tcp_user_fifo_rddata,
//tcp send interface
input tcp_data_send_fifo_af,
output reg tcp_data_send_fifo_wren,
output reg [7:0] tcp_data_send_fifo_wrdata,
output reg tw_send_req, //发送调用请求
input tw_send_grant,
output reg [31:0] tw_seq_num, //序号
output reg [15:0] tw_send_len,
output reg [31:0] tw_send_chksum,
input [31:0] isn,
input isn_set,
input [31:0] ackNo, //确认号
input [31:0] seqNo,
input ackNo_set,
input [15:0] rwnd, //接收窗口设置
input rwnd_set,
// ddr interface
input user_wr_fifo_af,
output reg user_wr_fifo_wren,
output reg [7:0] user_wr_fifo_wrdata,
input user_wr_fifo_done,
output reg user_rd_req,
input user_rd_grant,
output reg [31:0] user_rd_addr,
output reg [31:0] user_rd_len,
input user_rd_fifo_empty,
output user_rd_fifo_rden,
input [7:0] user_rd_fifo_rddata
//output re_err
);
//========================================================================
//参数
//========================================================================
localparam wr_idle = 3'd0,
wr_send = 3'd1,
wr_info = 3'd2,
wr_fetch = 3'd3,
wr_resend = 3'd4,
wr_send_req = 3'd5;
localparam user_send = 2'b00,
overtime_send = 2'b01,
overdup_send = 2'b10,
zero_det_send = 2'b11;
localparam three_redundance_ack = 8'd3;
localparam one_ms =32'd125_000;
//========================================================================
//reg & wire
//========================================================================
reg [2:0] wr_state;
reg user_rd_ready;
reg ddr_rd_ready;
reg [11:0] cnt0,cnt1,cnt2,cnt3,cnt4,cnt5,cnt6,cnt7;
reg [1:0] send_type;
reg [10:0] i;
reg [31:0] ackNo_before;
reg [31:0] seqNo_before;
reg [31:0] Sf,Sn,Sw;
wire tx_win_empty;
wire tx_win_full;
wire [31:0] tx_win_use_cnt; //发送窗口使用的字节数
wire [31:0] tx_win_left_cnt; //发送窗口剩余可以填充的字节数
wire [31:0] tx_win_size; //发送窗口的大小
reg [31:0] RTO_CNT;
reg RTO_RST;
reg RTO_ADD;
wire RTO_HOLD;
reg [7:0] DUP_CNT;
reg DUP_RST;
reg DUP_ADD;
wire DUP_HOLD;
wire write_stop;
wire [1:0] length_sel;
wire small_permitted;
wire [15:0] ddr_start_addr;
wire [15:0] ddr_start_addr_re;
wire [15:0] ddr_start_addr_pe;
wire [31:0] persist_seq;
wire PES_HOLD;
wire USER_HOLD;
//========================================================================
//combinational logic
//========================================================================
//
//---------------- user write stop if logic------------------------------
always@(posedge clk or posedge rst)begin
if(rst)begin
cnt0 <=0;
cnt1 <=0;
cnt2 <=0;
cnt3 <=0;
cnt4 <=0;
cnt5 <=0;
cnt6 <=0;
cnt7 <=0;
end
else begin
cnt0 <=tcp_user_fifo_rdcnt;
cnt1 <=cnt0;
cnt2 <=cnt1;
cnt3 <=cnt2;
cnt4 <=cnt3;
cnt5 <=cnt4;
cnt6 <=cnt5;
cnt7 <=cnt6;
end
end
assign write_stop = cnt0==tcp_user_fifo_rdcnt & cnt0==cnt1 &
cnt0==cnt2 & cnt0==cnt3 &
cnt0==cnt4 & cnt0==cnt5 &
cnt0==cnt6 & cnt0==cnt7 &
cnt0!=0;
//写停止+字节数过阈值+发送窗口未满+数据缓冲区没满
assign USER_HOLD = (write_stop | (tcp_user_fifo_rdcnt>=mss)) & (tx_win_left_cnt!=0) & (~tcp_data_send_fifo_af) & connected;
//
//---------------- RTO counter if logic------------------------------
always@(posedge clk or posedge rst) begin
if(rst) begin
RTO_CNT <=32'd0;
end
else if(RTO_RST) begin
RTO_CNT <=32'd0;
end
else if(RTO_ADD) begin
RTO_CNT <=RTO_CNT+1'b1;
end
else if(RTO_HOLD)begin
RTO_CNT <=RTO_CNT;
end
else begin
RTO_CNT <=RTO_CNT;
end
end
assign RTO_HOLD = RTO_CNT>=rto_thre;
//
//---------------- DUP counter if logic------------------------------
wire dup_exist; //需要快重传的包是否已经存在待确认缓冲区 //sf---ackNo---Sn
wire dup_live_ok; //需要快重传的包是否已经存在大于一定时间
assign dup_exist = (ackNo-Sf)<=(Sn-Sf) & (tx_win_use_cnt!=0);
assign dup_live_ok = (rtt<one_ms) ? (RTO_CNT>=one_ms) : (RTO_CNT>=rtt);
always@(posedge clk or posedge rst) begin
if(rst) begin
DUP_CNT <=0;
end
else if(DUP_RST) begin
DUP_CNT <=0;
end
else if(DUP_ADD) begin
if(DUP_CNT>=three_redundance_ack)begin //收到三个连续冗余ACK
DUP_CNT <=DUP_CNT;
end
else if(ackNo_set)begin
if(ackNo_set && ackNo==ackNo_before && seqNo==seqNo_before && dup_exist)begin
DUP_CNT <=DUP_CNT+1'b1;
end
else begin
DUP_CNT <=0;
end
end
end
else begin
DUP_CNT <=DUP_CNT;
end
end
assign DUP_HOLD = DUP_CNT>=three_redundance_ack ? 1'b1 : 1'b0;
//
//记录上一次的确认号
always@(posedge clk or posedge rst)begin
if(rst)begin
ackNo_before <=0;
end
else if(ackNo_set)begin
ackNo_before <=ackNo;
end
else begin
ackNo_before <=ackNo_before;
end
end
//记录上一次的序号
always@(posedge clk or posedge rst)begin
if(rst)begin
seqNo_before <=0;
end
else if(ackNo_set)begin
seqNo_before <=seqNo;
end
else begin
seqNo_before <=seqNo_before;
end
end
//
//---------------- tx win point logic------------------------------
// Sf------Sn------Sw
assign tx_win_size = Sw-Sf; //发送窗口的大小右壁减去左壁
assign tx_win_empty =(Sf==Sw) ? 1'b1 : 1'b0;
assign tx_win_full =(Sn==Sw) ? 1'b1 : 1'b0; //下一个写入的位置是窗口右壁
assign tx_win_use_cnt = Sn-Sf;
assign tx_win_left_cnt = Sw-Sn;
//Sf
always@(posedge clk or posedge rst)begin
if(rst)begin
Sf <=32'h0000_0000;
end
else if(isn_set)begin
Sf <=isn+1;
end
else if(ackNo_set && ((ackNo-Sf)<=(Sn-Sf)) && (ackNo!=ackNo_before)) begin //确认号合理,在需要确认的区间之内,且是第一次到达
Sf <=ackNo;
end
else begin
Sf <=Sf;
end
end
reg acked_unseen_segment;
always@(posedge clk or posedge rst)begin
if(rst)begin
acked_unseen_segment <=0;
end
else if(ackNo_set && ((ackNo-Sf)>(Sn-Sf)))begin
acked_unseen_segment <=1;
end
end
//Sn
always@(posedge clk or posedge rst)begin
if(rst)begin
Sn <=32'h0000_0000;
end
else if(isn_set)begin
Sn <=isn+1;
end
else if(wr_state==wr_send && user_wr_fifo_wren)begin
Sn <=Sn+1;
end
else begin
Sn <=Sn;
end
end
//Sw
always@(posedge clk or posedge rst)begin
if(rst)begin
Sw <=32'h0000_0000;
end
else if(isn_set & rwnd_set)begin
Sw <= (rwnd>=tx_win_size) ? isn+1+rwnd-tx_win_size : Sw;
end
else if(isn_set)begin
Sw <=isn+1;
end
else if(rwnd_set)begin
Sw <= (rwnd>=tx_win_size) ? Sf+rwnd : Sw;
end
end
//
//---------------- ddr start addr logic------------------------------
assign ddr_start_addr = tx_win_block==16'd1023 ? Sn[9:0] :
tx_win_block==16'd2047 ? Sn[10:0] :
tx_win_block==16'd4095 ? Sn[11:0] :
tx_win_block==16'd8191 ? Sn[12:0] :
tx_win_block==16'd16383 ? Sn[13:0] :
tx_win_block==16'd32767 ? Sn[14:0] :
tx_win_block==16'd65535 ? Sn[15:0] : Sn[15:0];
assign ddr_start_addr_re = tx_win_block==16'd1023 ? Sf[9:0] :
tx_win_block==16'd2047 ? Sf[10:0] :
tx_win_block==16'd4095 ? Sf[11:0] :
tx_win_block==16'd8191 ? Sf[12:0] :
tx_win_block==16'd16383 ? Sf[13:0] :
tx_win_block==16'd32767 ? Sf[14:0] :
tx_win_block==16'd65535 ? Sf[15:0] : Sf[15:0];
assign persist_seq = Sf==0 ? 32'hffff_ffff : Sf-1;
assign ddr_start_addr_pe = tx_win_block==16'd1023 ? persist_seq[9:0] :
tx_win_block==16'd2047 ? persist_seq[10:0] :
tx_win_block==16'd4095 ? persist_seq[11:0] :
tx_win_block==16'd8191 ? persist_seq[12:0] :
tx_win_block==16'd16383 ? persist_seq[13:0] :
tx_win_block==16'd32767 ? persist_seq[14:0] :
tx_win_block==16'd65535 ? persist_seq[15:0] : persist_seq[15:0];
//========================================================================
//send fsm
//========================================================================
assign tcp_user_fifo_rden = user_rd_ready & tcp_user_fifo_rdcnt!=0 & ~tcp_data_send_fifo_af & ~user_wr_fifo_af;
assign user_rd_fifo_rden = ddr_rd_ready & ~user_rd_fifo_empty & ~tcp_data_send_fifo_af;
//tcp_user_fifo_rdcnt:00; tx_win_left_cnt:01; mss:10
assign length_sel = (mss>=tx_win_left_cnt) & (tx_win_left_cnt>=tcp_user_fifo_rdcnt) ? 2'b00 :
(mss>=tcp_user_fifo_rdcnt) & (tcp_user_fifo_rdcnt>=tx_win_left_cnt) ? 2'b01 :
(tx_win_left_cnt >=mss) & (mss >=tcp_user_fifo_rdcnt) ? 2'b00 :
(tx_win_left_cnt>=tcp_user_fifo_rdcnt) &(tcp_user_fifo_rdcnt>=mss) ? 2'b10 :
(tcp_user_fifo_rdcnt >= mss) & (mss>=tx_win_left_cnt) ? 2'b01 :
(tcp_user_fifo_rdcnt >=tx_win_left_cnt) & (tx_win_left_cnt>=mss) ? 2'b10 : 2'b11;
always@(posedge clk or posedge rst)begin
if(rst)begin
wr_state <=0;
send_type <=0;
user_rd_ready <=0;
ddr_rd_ready <=0;
tcp_data_send_fifo_wren <=0;
tcp_data_send_fifo_wrdata <=0;
tw_send_req <=0;
tw_send_len <=0;
tw_seq_num <=0;
user_wr_fifo_wren <=0;
user_wr_fifo_wrdata <=0;
user_rd_req <=0;
user_rd_len <=0;
user_rd_addr <=0;
i <=0;
DUP_RST <=0;
DUP_ADD <=0;
end
else begin
case(wr_state)
//判断传输的类型
wr_idle:begin
tw_seq_num <=Sn;
if(RTO_HOLD & tx_win_use_cnt!=0)begin //超时重传
send_type <=overtime_send;
tw_send_len <=(tx_win_use_cnt>=mss) ? mss : tx_win_use_cnt;
tw_seq_num <=Sf;
user_rd_req <=1'b1;
user_rd_addr <=ddr_start_addr_re;//Sf;
user_rd_len <=(tx_win_use_cnt>=mss) ? mss : tx_win_use_cnt;
wr_state <=wr_fetch;
end
else if(DUP_HOLD)begin //快重传
DUP_RST <=1;
DUP_ADD <=0;
if(tx_win_use_cnt!=0)begin
send_type <=overdup_send;
tw_send_len <=(tx_win_use_cnt>=mss) ? mss : tx_win_use_cnt;
tw_seq_num <=Sf;
user_rd_req <=1'b1;
user_rd_addr <=ddr_start_addr_re;//Sf;
user_rd_len <=(tx_win_use_cnt>=mss) ? mss : tx_win_use_cnt;
wr_state <=wr_fetch;
end
else begin
wr_state <=wr_idle;
end
end
else if (PES_HOLD)begin //零窗口探测
send_type <=zero_det_send;
tw_send_len <=16'd1;
tw_seq_num <=persist_seq;//Sf==0 ? 32'hffff_ffff : Sf-1;
user_rd_req <=1'b1;
user_rd_addr <=ddr_start_addr_pe;//Sf==0 ? 32'hffff_ffff : Sf-1;
user_rd_len <=16'd1;
wr_state <=wr_fetch;
end
else if(USER_HOLD)begin //正常发送数据
send_type <=user_send;
tw_seq_num <=Sn;
if(length_sel==2'b10)begin
tw_send_len <=mss;
wr_state <=wr_info;
end
else if(length_sel==2'b01)begin
tw_send_len <=tx_win_left_cnt;
wr_state <=small_permitted ? wr_info : wr_idle;
end
else if(length_sel==2'b00)begin
tw_send_len <=tcp_user_fifo_rdcnt;
wr_state <=small_permitted ? wr_info : wr_idle;
end
end
else begin
DUP_RST <=0;
DUP_ADD <=1;
end
end
wr_fetch:begin
if(user_rd_grant)begin
user_rd_req <=1'b0;
ddr_rd_ready <=1'b1;
wr_state <=wr_resend;
end
else begin
wr_state <=wr_fetch;
end
end
wr_info:begin //addr_len
if(!user_wr_fifo_af)begin
user_wr_fifo_wren <=1'b1;
if(i==0)begin
i <=i+1;
user_wr_fifo_wrdata <=ddr_start_addr[15:8];
end
else if(i==1)begin
i <=i+1;
user_wr_fifo_wrdata <=ddr_start_addr[7:0];
end
else if(i==2)begin
i <=i+1;
user_wr_fifo_wrdata <=tw_send_len[15:8];
end
else if(i==3)begin
i <=0;
wr_state <=wr_send;
user_rd_ready <=1'b1;
user_wr_fifo_wrdata <=tw_send_len[7:0];
end
end
else begin
user_wr_fifo_wren <=1'b0;
user_wr_fifo_wrdata <=user_wr_fifo_wrdata;
end
end
wr_send:begin
if(tcp_user_fifo_rden)begin
tcp_data_send_fifo_wren <=1'b1;
tcp_data_send_fifo_wrdata <=tcp_user_fifo_rddata;
user_wr_fifo_wren <=1'b1;
user_wr_fifo_wrdata <=tcp_user_fifo_rddata;
if(i==(tw_send_len-1))begin
user_rd_ready <=1'b0;
i <=0;
wr_state <=wr_send_req;
end
else begin
i <=i+1;
end
end
else begin
tcp_data_send_fifo_wren <=1'b0;
user_wr_fifo_wren <=1'b0;
end
end
wr_resend:begin
if(user_rd_fifo_rden)begin
tcp_data_send_fifo_wren <=1'b1;
tcp_data_send_fifo_wrdata <=user_rd_fifo_rddata;
if(i==(tw_send_len-1))begin
ddr_rd_ready <=1'b0;
i <=0;
wr_state <=wr_send_req;
end
else begin
i <=i+1;
end
end
else begin
tcp_data_send_fifo_wren <=1'b0;
tcp_data_send_fifo_wrdata <=tcp_data_send_fifo_wrdata;
end
end
wr_send_req:begin
tcp_data_send_fifo_wren <=1'b0;
user_wr_fifo_wren <=1'b0;
if(send_type==user_send && user_wr_fifo_done && !tw_send_req)begin
tw_send_req <=1'b1;
end
else if(send_type!=user_send && !tw_send_req)begin
tw_send_req <=1'b1;
end
else if(tw_send_req && tw_send_grant==1'b1)begin
tw_send_req <=1'b0;
wr_state <=wr_idle;
end
else begin
wr_state <=wr_send_req;
end
end
default:begin
wr_state <=wr_idle;
end
endcase
end
end
//
//---------------- data checksum calculate logic------------------------------
reg [7:0] data_buf;
wire chk_data_vld;
wire [7:0] chk_data;
assign chk_data_vld = wr_state == wr_send ? tcp_user_fifo_rden : user_rd_fifo_rden;
assign chk_data = wr_state == wr_send ? tcp_user_fifo_rddata : user_rd_fifo_rddata;
always@(posedge clk or posedge rst)begin
if(rst)begin
data_buf <=0;
tw_send_chksum <=0;
end
else if(wr_state==wr_idle)begin //clear
data_buf <=0;
tw_send_chksum <=0;
end
else if(wr_state== wr_resend || wr_state==wr_send)begin
if(chk_data_vld)begin
if(i==(tw_send_len-1) && i[0]==1'b0)begin
tw_send_chksum <=tw_send_chksum+{chk_data,8'h00};
end
else if(i[0]==1'b0)begin
data_buf <=chk_data;
end
else if(i[0]==1'b1)begin
tw_send_chksum <=tw_send_chksum+{data_buf,chk_data};
end
end
else begin
tw_send_chksum <=tw_send_chksum;
data_buf <=data_buf;
end
end
end
//
//---------------- RTO counter control logic------------------------------
localparam waiting =2'd0,
reboot =2'd1;
reg RTO_state;
always@(posedge clk or posedge rst)begin
if(rst)begin
RTO_ADD <=1'b0;
RTO_RST <=1'b0;
RTO_state <=0;
end
else begin
case(RTO_state)
waiting:begin
//Sf---(ackNo)----Sn
if(((ackNo-Sf)<=(Sn-Sf)) && (ackNo!=Sf) && ackNo_set)begin //到达无差错的ACK,且确认的是队列中最前面的报文段重启计数器
RTO_ADD <=1'b0;
RTO_RST <=1'b1;
RTO_state <=reboot;
end
else if(wr_state ==wr_send_req && send_type==overtime_send && tw_send_req)begin //发生了超时重传
RTO_ADD <=1'b0;
RTO_RST <=1'b1;
RTO_state <=reboot;
end
else if(wr_state ==wr_send_req && send_type==overdup_send && tw_send_req)begin //发生了快重传
RTO_ADD <=1'b0;
RTO_RST <=1'b1;
RTO_state <=reboot;
end
else if(wr_state ==wr_send_req && send_type==user_send && tw_send_req) begin //正常传输
if(RTO_ADD==0)begin
RTO_ADD <=1'b1;
RTO_RST <=1'b0;
end
else begin //缓冲区内已经有报文
RTO_ADD <=RTO_ADD;
RTO_RST <=RTO_RST;
end
end
end
reboot:begin
RTO_state <=waiting;
if(tx_win_use_cnt!=0)begin //队列中还有数据启动计数器
RTO_ADD <=1'b1;
RTO_RST <=1'b0;
end
else begin
RTO_ADD <=1'b0;
RTO_RST <=1'b1;
end
end
default:begin
RTO_state <=waiting;
end
endcase
end
end
//
//---------------- overtime or overdup dedicate logic------------------------------
always@(posedge clk or posedge rst)begin
if(rst)begin
over_time_occur <=0;
over_dup_occur <=0;
end
else if(wr_state==wr_send_req && send_type==overtime_send && tw_send_grant)begin //超时重传
over_time_occur <=1;
over_dup_occur <=0;
end
else if(wr_state==wr_send_req && send_type==overdup_send && tw_send_grant)begin //快重传
over_time_occur <=0;
over_dup_occur <=1;
end
else begin
over_time_occur <=0;
over_dup_occur <=0;
end
end
//
//---------------- same packet retrans counter logic------------------------------
reg [3:0] retrans_cnt;
reg [31:0] retrans_seq_num;
//锁存上一次重传的帧序号
always@(posedge clk or posedge rst)begin
if(rst)begin
retrans_seq_num <=0;
end
else if(over_time_occur || over_dup_occur)begin
retrans_seq_num <=tw_seq_num;
end
else begin
retrans_seq_num <=retrans_seq_num;
end
end
//计数
always@(posedge clk or posedge rst)begin
if(rst)begin
retrans_cnt <=0;
end
else if(over_time_occur || over_dup_occur)begin
if(retrans_seq_num==tw_seq_num)begin
retrans_cnt <=retrans_cnt+1'b1;
end
else begin
retrans_cnt <=0;
end
end
else begin
retrans_cnt <=retrans_cnt;
end
end
//中断产生
assign retrans_int = (retrans_cnt>=retrans_thre ) ? 1'b1 :1'b0;
//
//---------------- Nagle logic------------------------------
//该算法要求TCP连接上只能有一个未被确认的小分组在该分组的确认到达之前不能发送其他的小分组
parameter monitor_small =1'd0,
wait_small_ack =1'd1;
reg Nagle_state;
reg [31:0] Nagle_delay_cnt;
reg Nagle_small_en;
reg [31:0] small_seq;
reg [15:0] small_len;
assign small_permitted = nagle_disable ? 1'b1 : Nagle_small_en;
always@(posedge clk or posedge rst)begin
if(rst)begin
Nagle_small_en <=1'b1;
Nagle_state <=0;
small_seq <=0;
small_len <=0;
Nagle_delay_cnt <=0;
end
else begin
case(Nagle_state)
monitor_small:begin
if(wr_state==wr_send_req && send_type==user_send && tw_send_grant && tw_send_len<mss)begin //发现发送第一个小包
Nagle_small_en <=1'b0; //不允许发送小包
small_seq <=tw_seq_num;
small_len <=tw_send_len;
Nagle_state <=wait_small_ack;
end
else begin
Nagle_small_en <=Nagle_small_en;
small_seq <=small_seq;
small_len <=small_len;
Nagle_state <=monitor_small;
end
end
wait_small_ack:begin
if(ackNo_set && ((ackNo-small_seq)>=small_len) && ((ackNo-small_seq)<=tx_win_block))begin //收到对该小包的确认
Nagle_small_en <=1'b1;
Nagle_state <=monitor_small;
Nagle_delay_cnt <=0;
end
else if(Nagle_delay_cnt==Nagle_delay_time)begin //200ms延迟超时
Nagle_small_en <=1'b1;
Nagle_state <=monitor_small;
Nagle_delay_cnt <=0;
end
else begin
Nagle_small_en <=1'b0;
Nagle_state <=wait_small_ack;
Nagle_delay_cnt <=Nagle_delay_cnt+1'b1;
end
end
default:begin
Nagle_state <=monitor_small;
end
endcase
end
end
//
//---------------- Persistence logic------------------------------
//当发送TCP接收到一个零窗口通告后就启动一个持续计数器
//收到零窗口通告使能持续计数器收到非零窗口通告关闭持续计数器
localparam persist_thre = 100*one_ms;
reg persist_ena;
reg [31:0] persist_cnt;
assign PES_HOLD = persist_cnt==persist_thre;
always@(posedge clk or posedge rst)begin
if(rst)begin
persist_ena <=1'b0;
end
else if(rwnd_set && rwnd==0)begin
persist_ena <=1'b1;
end
else if(rwnd_set && rwnd!=0)begin
persist_ena <=1'b0;
end
end
//持续计数器
always@(posedge clk or posedge rst)begin
if(rst)begin
persist_cnt <=32'h0000_0000;
end
else if(persist_ena)begin
if(wr_state==wr_fetch && send_type==zero_det_send)begin
persist_cnt <=32'h0000_0000;
end
else if(persist_cnt==persist_thre)begin
persist_cnt <=persist_cnt;
end
else begin
persist_cnt <=persist_cnt+1;
end
end
else begin
persist_cnt <=32'h0000_0000;
end
end
//-------------------------------------------------------
/*
wire err_a;
wire err_b;
wire err_p;
linear8_check linear8_check(
.clk (clk),
.rst (rst),
.din_a (user_wr_fifo_wrdata),
.din_vld_a (user_wr_fifo_wren),
.req (user_rd_req),
.grant (user_rd_grant),
.len_b (user_rd_len[15:0]),
.din_b (user_rd_fifo_rddata),
.din_vld_b (user_rd_fifo_rden),
.err_a (err_a),
.err_b (err_b)
);
ping_data_check ping_data_check(
.clk (clk),
.rst (rst),
.req (user_rd_req),
.grant (user_rd_grant),
.din_vld (user_rd_fifo_rden),
.din (user_rd_fifo_rddata),
.err (err_p)
);
assign re_err = err_p;*/
//-------------------------------------------------------
//ila_200 ila_tx_win(
// .clk (clk ),
// .probe0 ({
// wr_state, //3
// send_type, //2
// tw_seq_num, //32
// Sf, //32
// Sn, //32
// Sw, //32
// user_rd_req, //1
// user_rd_grant, //1
// user_rd_addr[15:0],//16
// user_rd_len[15:0], //16
// user_rd_fifo_empty, //1
// user_rd_fifo_rden, //1
// user_rd_fifo_rddata, //8
// user_wr_fifo_wren, //1
// user_wr_fifo_wrdata, //8
// err_a,//1
// err_b,//1
// err_p,
// rwnd_set, //1
// rwnd, //16
// i,//11
// 84'd0
// })
//);
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/08/15 12:23:15
// Design Name:
// Module Name: udp_recv
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
//+--------------------------------------------------------------+
//| src_port(16) | dst_port(16£© |
//+--------------------------------------------------------------+
//| udp_len | udp_checksum(16'h0000) |
//+--------------------------------------------------------------+
//////////////////////////////////////////////////////////////////////////////////
module udp_recv(
input clk,
input rst,
input [15:0] local_port,
input [15:0] dst_port,
input udp_recv_fifo_empty,
output udp_recv_fifo_rden,
input [8:0] udp_recv_fifo_rddata,
input app_recv_fifo_af,
//output reg app_recv_fifo_wren,
output app_recv_fifo_wren_l,
output reg [8:0] app_recv_fifo_wrdata
);
// liu's update
reg app_recv_fifo_wren;
assign app_recv_fifo_wren_l = app_recv_fifo_wren && (~udp_recv_fifo_empty);
//////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////
//parameter
///////////////////////////////////////////////////////////
localparam idle = 3'd0,
recv_src_port = 3'd1,
recv_dst_port = 3'd2,
recv_len = 3'd3,
recv_chksum = 3'd4,
recv_payload = 3'd5,
wait_end = 3'd6;
///////////////////////////////////////////////////////////
//reg & wire
///////////////////////////////////////////////////////////
reg [2:0] state;
reg ready;
reg [15:0] i;
reg [15:0] src_port_reg;
reg [15:0] dst_port_reg;
reg [15:0] udp_len_reg;
reg [15:0] data_len;
reg [31:0] udp_rx_cnt;
///////////////////////////////////////////////////////////
//combinational logic
///////////////////////////////////////////////////////////
assign udp_recv_fifo_rden = ready & ~udp_recv_fifo_empty;
///////////////////////////////////////////////////////////
//fsm
///////////////////////////////////////////////////////////
always@(posedge clk or posedge rst)begin
if(rst)begin
state <=0;
ready <=0;
app_recv_fifo_wren <=0;
app_recv_fifo_wrdata <=0;
i <=0;
src_port_reg <=0;
dst_port_reg <=0;
udp_len_reg <=0;
data_len <=0;
udp_rx_cnt <=0;
end
else begin
case(state)
idle:begin
app_recv_fifo_wren <=0;
if(!udp_recv_fifo_empty)begin
state <=recv_src_port;
ready <=1;
end
else begin
state <=idle;
end
end
recv_src_port:begin
if(udp_recv_fifo_rden)begin
src_port_reg <={src_port_reg[7:0],udp_recv_fifo_rddata[7:0]};
if(i==1)begin
i <=0;
state <=recv_dst_port;
end
else begin
i <=i+1;
end
end
else begin
state <=recv_src_port;
end
end
recv_dst_port:begin
if(udp_recv_fifo_rden)begin
if(i==0 && udp_recv_fifo_rddata[7:0]==local_port[15:8] && src_port_reg==dst_port)begin
i <=i+1;
end
else if(i==1 && udp_recv_fifo_rddata[7:0]==local_port[7:0])begin
i <=0;
state <=recv_len;
end
else begin
i <=0;
state <=wait_end;
end
end
else begin
state <=recv_dst_port;
end
end
recv_len:begin
if(udp_recv_fifo_rden)begin
udp_len_reg <={udp_len_reg[7:0],udp_recv_fifo_rddata[7:0]};
if(i==1)begin
i <=0;
state <=recv_chksum;
end
else begin
i <=i+1;
end
end
else begin
state <=recv_len;
end
end
recv_chksum:begin
if(udp_recv_fifo_rden)begin
if(i==1)begin
udp_rx_cnt <=udp_rx_cnt+1;
i <=0;
state <=recv_payload;
end
else begin
data_len <=udp_len_reg-8;
i <=i+1;
end
end
else begin
state <=recv_chksum;
end
end
recv_payload:begin
if(udp_recv_fifo_rden)begin
app_recv_fifo_wren <=1;
if(i==(data_len-1) && udp_recv_fifo_rddata[8])begin
ready <=0;
i <=0;
state <=idle;
app_recv_fifo_wrdata <={1'b1,udp_recv_fifo_rddata[7:0]};
end
else if(i==(data_len-1) && !udp_recv_fifo_rddata[8])begin
i <=0;
state <=wait_end;
app_recv_fifo_wrdata <={1'b1,udp_recv_fifo_rddata[7:0]};
end
else begin
i <=i+1;
app_recv_fifo_wrdata <={1'b0,udp_recv_fifo_rddata[7:0]};
end
end
else begin
state <=recv_payload;
end
end
wait_end:begin
app_recv_fifo_wren <=0;
if(udp_recv_fifo_rddata[8])begin
ready <=0;
state <=idle;
end
else begin
state <=wait_end;
end
end
default:begin
state <=idle;
end
endcase
end
end
//---------------------------------------------------------\
//ila_32 ila_udp_recv(
// .clk(clk),
// .probe0(
// udp_rx_cnt
// )
//);
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/08/15 12:23:15
// Design Name:
// Module Name: udp_send
// Description:
//
//+--------------------------------------------------------------+
//| src_port(16) | dst_port(16£© |
//+--------------------------------------------------------------+
//| udp_len | udp_checksum(16'h0000) |
//+--------------------------------------------------------------+
//////////////////////////////////////////////////////////////////////////////////
module udp_send(
input clk,
input rst,
input [31:0] dst_ip,
input [15:0] local_port,
input [15:0] dst_port,
input send_mode, //0:thre+stop;1:thre
input [15:0] send_thre,
output reg udp_send_req,
input udp_send_grant,
output reg [15:0] udp_send_len,
output reg [31:0] udp_send_dst_ip,
input udp_send_fifo_af,
output reg udp_send_fifo_wren,
output reg [7:0] udp_send_fifo_wrdata,
output app_send_fifo_rdclk,
input app_send_fifo_empty,
input [11:0] app_send_fifo_rdcnt,
output app_send_fifo_rden,
input [7:0] app_send_fifo_rddata
);
///////////////////////////////////////////////
//localparam
///////////////////////////////////////////////
localparam idle = 3'd0,
send_src_port = 3'd1,
send_dst_port = 3'd2,
send_len = 3'd3,
send_chksum = 3'd4,
send_payload = 3'd5,
send_req = 3'd6;
///////////////////////////////////////////////
//reg & wire
///////////////////////////////////////////////
reg [2:0] state;
reg [11:0] cnt1,cnt2,cnt3,cnt4,cnt5,cnt6,cnt7,cnt8; //8*8=64ns
reg send_start;
reg ready;
reg [15:0] data_len_reg;
reg [15:0] udp_len_reg;
reg [15:0] i;
reg [31:0] udp_tx_cnt;
wire over_thre;
wire wr_stop;
///////////////////////////////////////////////
//combinational logic
///////////////////////////////////////////////
assign app_send_fifo_rdclk = clk;
assign over_thre = (app_send_fifo_rdcnt>send_thre) ? 1'b1 : 1'b0;
assign wr_stop = cnt1==app_send_fifo_rdcnt & cnt1==cnt2 & cnt1==cnt3 & cnt1==cnt4 &
cnt1==cnt5 & cnt1==cnt6 & cnt1==cnt6 & cnt1==cnt7 & cnt1==cnt8 & (cnt1!=0);
assign app_send_fifo_rden = ~app_send_fifo_empty & ready & ~udp_send_fifo_af;
///////////////////////////////////////////////
//fsm
///////////////////////////////////////////////
//
//send start logic
always@(posedge clk or posedge rst)begin
if(rst)begin
send_start <=0;
end
else if(send_mode==1'b0)begin //over_thre+wr_stop
if(state==idle && (over_thre || wr_stop))begin
send_start <=1;
end
else if(state==send_src_port)begin
send_start <=0;
end
else begin
send_start <=send_start;
end
end
else if(send_mode==1'b1)begin //over_thre
if(state==idle && over_thre)begin
send_start <=1;
end
else if(state==send_src_port)begin
send_start <=0;
end
else begin
send_start <=send_start;
end
end
end
//
//cnt delay
always@(posedge clk or posedge rst)begin
if(rst)begin
cnt1 <=0;
cnt2 <=0;
cnt3 <=0;
cnt4 <=0;
cnt5 <=0;
cnt6 <=0;
cnt7 <=0;
cnt8 <=0;
end
else begin
cnt1 <=app_send_fifo_rdcnt;
cnt2 <=cnt1;
cnt3 <=cnt2;
cnt4 <=cnt3;
cnt5 <=cnt4;
cnt6 <=cnt5;
cnt7 <=cnt6;
cnt8 <=cnt7;
end
end
//
//generate a udp frame
always@(posedge clk or posedge rst)begin
if(rst)begin
state <=0;
ready <=0;
udp_send_req <=0;
udp_send_fifo_wren <=0;
udp_send_fifo_wrdata <=0;
udp_send_len <=0;
udp_send_dst_ip <=0;
data_len_reg <=0;
udp_len_reg <=0;
i <=0;
udp_tx_cnt <=0;
end
else begin
case(state)
idle:begin
udp_send_fifo_wren <=0;
if(send_start)begin
state <=send_src_port;
udp_tx_cnt <=udp_tx_cnt+1;
if(app_send_fifo_rdcnt<send_thre)begin
data_len_reg <=app_send_fifo_rdcnt;
udp_len_reg <=app_send_fifo_rdcnt+8;
end
else begin
data_len_reg <=send_thre;
udp_len_reg <=send_thre+8;
end
end
else begin
state <=idle;
end
end
send_src_port:begin
if(!udp_send_fifo_af)begin
if(i==0)begin
udp_send_fifo_wren <=1;
udp_send_fifo_wrdata <=local_port[15:8];
i <=i+1;
end
else if(i==1)begin
udp_send_fifo_wren <=1;
udp_send_fifo_wrdata <=local_port[7:0];
i <=0;
state <=send_dst_port;
end
end
else begin
udp_send_fifo_wren <=0;
end
end
send_dst_port:begin
if(!udp_send_fifo_af)begin
if(i==0)begin
udp_send_fifo_wren <=1;
udp_send_fifo_wrdata <=dst_port[15:8];
i <=i+1;
end
else if(i==1)begin
udp_send_fifo_wren <=1;
udp_send_fifo_wrdata <=dst_port[7:0];
i <=0;
state <=send_len;
end
end
else begin
udp_send_fifo_wren <=0;
end
end
send_len:begin
if(!udp_send_fifo_af)begin
if(i==0)begin
udp_send_fifo_wren <=1;
udp_send_fifo_wrdata <=udp_len_reg[15:8];
i <=i+1;
end
else if(i==1)begin
udp_send_fifo_wren <=1;
udp_send_fifo_wrdata <=udp_len_reg[7:0];
i <=0;
state <=send_chksum;
end
end
else begin
udp_send_fifo_wren <=0;
end
end
send_chksum:begin
if(!udp_send_fifo_af)begin
if(i==0)begin
udp_send_fifo_wren <=1;
udp_send_fifo_wrdata <=8'h00;
i <=i+1;
end
else if(i==1)begin
udp_send_fifo_wren <=1;
udp_send_fifo_wrdata <=8'h00;
ready <=1;
i <=0;
state <=send_payload;
end
end
else begin
udp_send_fifo_wren <=0;
end
end
send_payload:begin
if(app_send_fifo_rden)begin
if(i==(data_len_reg-1))begin
i <=0;
ready <=0;
state <=send_req;
udp_send_fifo_wren <=1;
udp_send_fifo_wrdata <=app_send_fifo_rddata[7:0];
end
else begin
i <=i+1;
udp_send_fifo_wren <=1;
udp_send_fifo_wrdata <=app_send_fifo_rddata[7:0];
end
end
else begin
udp_send_fifo_wren <=0;
end
end
send_req:begin
udp_send_fifo_wren <=0;
udp_send_req <=1;
udp_send_len <=udp_len_reg;
udp_send_dst_ip <=dst_ip;
if(udp_send_grant)begin
udp_send_req <=0;
state <=idle;
end
else begin
state <=send_req;
end
end
default:begin
state <=idle;
end
endcase
end
end
//---------------------------------------------------------\
//ila_32 ila_udp_send(
// .clk(clk),
// .probe0(
// udp_tx_cnt
// )
//);
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/08/15 12:23:15
// Design Name:
// Module Name: udp_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module udp_top(
input clk,
input rst,
input [31:0] dst_ip,
input [15:0] local_port,
input [15:0] dst_port,
input send_mode,
input [15:0] send_thre,
//udp interface
input udp_recv_fifo_empty,
output udp_recv_fifo_rden,
input [8:0] udp_recv_fifo_rddata,
output udp_send_req,
input udp_send_grant,
output [15:0]udp_send_len,
output [31:0]udp_send_dst_ip,
output udp_send_fifo_empty,
input udp_send_fifo_rden,
output [7:0] udp_send_fifo_rddata,
//app interface
input app_recv_fifo_rdclk,
output app_recv_fifo_empty,
output [11:0]app_recv_fifo_rdcnt,
input app_recv_fifo_rden,
output [7:0] app_recv_fifo_rddata,
output app_send_fifo_rdclk,
input app_send_fifo_empty,
input [11:0] app_send_fifo_rdcnt,
output app_send_fifo_rden,
input [7:0] app_send_fifo_rddata
);
wire udp_send_fifo_af;
wire udp_send_fifo_wren;
wire [7:0] udp_send_fifo_wrdata;
wire app_recv_fifo_af;
wire app_recv_fifo_wren;
wire [8:0] app_recv_fifo_wrdata;
//////////////////////////////////////////////
// udp receive
//////////////////////////////////////////////
udp_recv U_udp_recv(
.clk (clk ),
.rst (rst ),
.local_port (local_port ),
.dst_port (dst_port ),
.udp_recv_fifo_empty (udp_recv_fifo_empty ),
.udp_recv_fifo_rden (udp_recv_fifo_rden ),
.udp_recv_fifo_rddata (udp_recv_fifo_rddata ),
.app_recv_fifo_af (app_recv_fifo_af ),
// .app_recv_fifo_wren (app_recv_fifo_wren ),
.app_recv_fifo_wren_l (app_recv_fifo_wren ),
.app_recv_fifo_wrdata (app_recv_fifo_wrdata )
);
//--------------------------------------------
//udp send fifo
//--------------------------------------------
asyn_fwft_fifo #(
.dw (8), //****//
.depth (2048))
U_app_recv_fifo(
.wr_clk (clk ),
.rd_clk (app_recv_fifo_rdclk ),
.rst (rst ),
.clr (1'b0 ),
.we (app_recv_fifo_wren ),
.din_ (app_recv_fifo_wrdata[7:0]),
.wr_full (),
.wr_af (app_recv_fifo_af ),
.rd_in (app_recv_fifo_rden ),
.dout_ (app_recv_fifo_rddata),
.rd_cnt_ (app_recv_fifo_rdcnt ),
.rd_empty (app_recv_fifo_empty )
);
//////////////////////////////////////////////
//udp send
//////////////////////////////////////////////
udp_send U_udp_send(
.clk (clk ),
.rst (rst ),
.dst_ip (dst_ip ),
.local_port (local_port ),
.dst_port (dst_port ),
.send_mode (send_mode ), //0:thre+stop;1:thre
.send_thre (send_thre ),
.udp_send_req (udp_send_req ),
.udp_send_grant (udp_send_grant ),
.udp_send_len (udp_send_len ),
.udp_send_dst_ip (udp_send_dst_ip ),
.udp_send_fifo_af (udp_send_fifo_af ),
.udp_send_fifo_wren (udp_send_fifo_wren ),
.udp_send_fifo_wrdata (udp_send_fifo_wrdata),
.app_send_fifo_rdclk (app_send_fifo_rdclk ),
.app_send_fifo_empty (app_send_fifo_empty ),
.app_send_fifo_rdcnt (app_send_fifo_rdcnt ),
.app_send_fifo_rden (app_send_fifo_rden ),
.app_send_fifo_rddata (app_send_fifo_rddata )
);
//--------------------------------------------
//udp send fifo
//--------------------------------------------
syn_fwft_fifo #(
.width (8),
.depth (2048))
U_udp_send_fifo(
.clk (clk ),
.rst (rst ),
.clr (1'b0 ),
.wr_en (udp_send_fifo_wren ),
.din (udp_send_fifo_wrdata),
.full (),
.almost_full (udp_send_fifo_af ),
.rd_en (udp_send_fifo_rden ),
.dout (udp_send_fifo_rddata),
.empty (udp_send_fifo_empty )
);
endmodule

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/*--------------------------------------------------------------------------------------------------
File name : dc_fifo.v
--------------------------------------------------------------------------------------------------*/
module asyn_fwft_fifo
(
rd_clk,
wr_clk,
rst,
clr,
din_,
we,
dout_,
rd_in,
wr_full,
rd_full,
rd_empty,
wr_af,
wr_ae,
rd_af,
rd_ae,
wr_cnt_,
rd_cnt_
);
function integer clog2(input integer bit_depth);
begin
for(clog2=0;bit_depth>0;clog2=clog2+1)
bit_depth =bit_depth>>1;
end
endfunction
parameter dw=16;
parameter depth =256;
localparam aw=clog2(depth-1);
localparam mb=dw*(32'h0000_0001<<aw);
input rd_clk;
input wr_clk;
input rst;
//FIFO clear signal
input clr;
//FIFO input data
input [dw-1:0] din_;
//FIFO write enable
input we;
//FIFO read enable
input rd_in;
//FIFO read data
output [dw-1:0] dout_;
//FIFO write full signal
output wr_full;
//FIFO read empty signal
output rd_empty;
output rd_ae;
output rd_af;
output wr_ae;
output wr_af;
output rd_full;
//read FIFO residual data indication
output [aw:0] rd_cnt_;
//write FIFO data indication
output [aw:0] wr_cnt_;
////////////////////////////////////////////////////////////////////
// Local Wires
////////////////////////////////////////////////////////////////////
reg [aw:0] wr_cnt_;
reg [aw:0] rd_cnt_;
reg [aw:0] wp_bin_, wp_gray_;
reg [aw:0] rp_bin_, rp_gray_;
reg [aw:0] wp_s_, rp_s_;
reg [aw:0] wp_d1_, rp_d1_;
reg [dw-1:0] dout_;
wire [dw-1:0] dpram_out_;
wire [aw:0] wp_bin_next_, wp_gray_next_;
wire [aw:0] rp_bin_next_, rp_gray_next_;
wire [aw:0] wp_bin_x_, rp_bin_x_;
reg rd_rst;
reg wr_rst;
reg rd_rst_r;
reg wr_rst_r;
reg rd_clr;
reg wr_clr;
reg rd_clr_r;
reg wr_clr_r;
wire re;
reg ram_empty;
reg wr_full;
reg wr_empty;
reg rd_empty;
reg rd_full;
reg [aw-1:0] wr_cnt_tmp_;
////////////////////////////////////////////////////////////////////
// Registered Level Indicators
////////////////////////////////////////////////////////////////////
reg [1:0] wr_level_;
reg [1:0] rd_level_;
reg rd_ae,rd_af;
reg wr_ae,wr_af;
wire rd_ae_tmp,rd_af_tmp;
wire wr_ae_tmp,wr_af_tmp;
wire rd_ram;
wire ram_rden;
////////////////////////////////////////////////////////////////////
// Reset Logic
////////////////////////////////////////////////////////////////////
always @(posedge rd_clk or posedge rst)
if(rst)
rd_rst <= 1'b0;
else if(rd_rst_r)
rd_rst <= 1'b1;// Release Reset
always @(posedge rd_clk or posedge rst)
if(rst)
rd_rst_r <= 1'b0;
else
rd_rst_r <= 1'b1;
always @(posedge wr_clk or posedge rst)
if(rst)
wr_rst <= 1'b0;
else if(wr_rst_r)
wr_rst <= 1'b1;// Release Reset
always @(posedge wr_clk or posedge rst)
if(rst)
wr_rst_r <= 1'b0;
else
wr_rst_r <= 1'b1;
always @(posedge rd_clk or posedge clr)
if(clr)
rd_clr <= 1'b1;
else if(!rd_clr_r)
rd_clr <= 1'b0;// Release Clear
always @(posedge rd_clk or posedge clr)
if(clr)
rd_clr_r <= 1'b1;
else
rd_clr_r <= 1'b0;
always @(posedge wr_clk or posedge clr)
if(clr)
wr_clr <= 1'b1;
else if(!wr_clr_r)
wr_clr <= 1'b0;// Release Clear
always @(posedge wr_clk or posedge clr)
if(clr)
wr_clr_r <= 1'b1;
else
wr_clr_r <= 1'b0;
////////////////////////////////////////////////////////////////////
// Memory Block
////////////////////////////////////////////////////////////////////
spram #(
.width (dw ),
.depth (depth )
)spram(
.clka (wr_clk ),
.ena (we ),
.dina (din_ ),
.addra (wp_bin_[aw-1:0] ),
.clkb (rd_clk ),
//.enb (1'b1 ),
.enb (ram_rden ),
.doutb (dpram_out_ ),
.addrb (rp_bin_next_[aw-1:0] )
);
assign ram_rden = wp_s_ != rp_gray_next_;
////////////////////////////////////////////////////////////////////
// Read/Write Pointers Logic
////////////////////////////////////////////////////////////////////
always @(posedge wr_clk)
if(!wr_rst)
wp_bin_[aw:0] <= {aw+1{1'b0}};
else if(wr_clr)
wp_bin_[aw:0] <= {aw+1{1'b0}};
else
wp_bin_[aw:0] <= wp_bin_next_[aw:0];
assign wp_bin_next_[aw:0] = wp_bin_[aw:0] + {{aw{1'b0}},((!wr_full)&we)};
always @(posedge wr_clk)
if(!wr_rst)
wp_gray_[aw:0] <= {aw+1{1'b0}};
else if(wr_clr)
wp_gray_[aw:0] <= {aw+1{1'b0}};
else
wp_gray_[aw:0] <= wp_gray_next_[aw:0];
assign wp_gray_next_[aw:0] = wp_bin_next_[aw:0] ^ {1'b0, wp_bin_next_[aw:1]};
always @(posedge rd_clk)
if(!rd_rst)
rp_bin_[aw:0] <= {aw+1{1'b0}};
else if(rd_clr)
rp_bin_[aw:0] <= {aw+1{1'b0}};
else
rp_bin_[aw:0] <= rp_bin_next_[aw:0];
assign rp_bin_next_[aw:0] = rp_bin_[aw:0] + {{aw{1'b0}},(re&(!ram_empty))};
always @(posedge rd_clk)
if(!rd_rst)
rp_gray_ <= {aw+1{1'b0}};
else if(rd_clr)
rp_gray_ <= {aw+1{1'b0}};
else
rp_gray_ <= rp_gray_next_;
assign rp_gray_next_ = rp_bin_next_ ^ {1'b0, rp_bin_next_[aw:1]};
////////////////////////////////////////////////////////////////////
// Synchronization Logic
////////////////////////////////////////////////////////////////////
// write pointer
always @(posedge rd_clk) wp_d1_ <= wp_gray_;
always @(posedge rd_clk) wp_s_ <= wp_d1_;
// read pointer
always @(posedge wr_clk) rp_d1_ <= rp_gray_;
always @(posedge wr_clk) rp_s_ <= rp_d1_;
////////////////////////////////////////////////////////////////////
// Registered Full & Empty Flags
////////////////////////////////////////////////////////////////////
assign wp_bin_x_ = wp_s_ ^ {1'b0, wp_bin_x_[aw:1]}; // convert gray to binary
assign rp_bin_x_ = rp_s_ ^ {1'b0, rp_bin_x_[aw:1]}; // convert gray to binary
always @(posedge rd_clk)
ram_empty <= (wp_s_ == rp_gray_) | (re & (wp_s_ == rp_gray_next_));
always @ (posedge rd_clk)
if(!rd_rst)
rd_empty <= 1'b1;
else if(rd_clr)
rd_empty <= 1'b1;
else if(rd_in&ram_empty)
rd_empty <= 1'b1;
else if(re)
rd_empty <= 1'b0;
assign rd_ram = (ram_empty)?1'b0:((rd_empty)? 1'b1:rd_in );
assign re = rd_ram;
always @(posedge wr_clk)
wr_full <= ((wp_bin_[aw-1:0] == rp_bin_x_[aw-1:0]) & (wp_bin_[aw] != rp_bin_x_[aw])) |
(we & (wp_bin_next_[aw-1:0] == rp_bin_x_[aw-1:0]) & (wp_bin_next_[aw] != rp_bin_x_[aw]));
always @(posedge wr_clk)
wr_empty <= (wp_bin_[aw:0] == rp_bin_x_[aw:0]);
always @(posedge wr_clk) wr_cnt_tmp_ <= wp_bin_next_[aw-1:0] + ~rp_bin_x_[aw-1:0];
always @(posedge wr_clk)
if(!wr_rst)
wr_cnt_[aw:0] <= {aw+1{1'b0}};
else if(wr_clr)
wr_cnt_[aw:0] <= {aw+1{1'b0}};
else if(wr_empty)
wr_cnt_[aw:0] <= {aw+1{1'b0}};
else
wr_cnt_[aw:0] <= wr_cnt_tmp_ + {{aw-2{1'b0}},1'b1};
always @(posedge wr_clk) wr_level_ <= {wr_cnt_[aw-1] | wr_full , wr_cnt_[aw-2] | wr_full };
always @(posedge rd_clk)
if(!rd_rst)
rd_cnt_ <= {aw+1{1'b0}};
else if(rd_clr)
rd_cnt_ <= {aw+1{1'b0}};
else if(rd_empty)
rd_cnt_ <= {aw+1{1'b0}};
else
rd_cnt_ <= wp_bin_x_[aw:0] + ~rp_bin_next_[aw:0] + {{aw-1{1'b0}},!(rd_in&ram_empty),rd_in&ram_empty};
always @(posedge rd_clk) rd_full <= (wp_bin_x_[aw-1:0] == rp_bin_[aw-1:0])&(wp_bin_x_[aw]!= rp_bin_[aw]) ;
always @(posedge rd_clk) rd_level_ <= rd_full ? 2'h0 : {!rd_cnt_[aw-1]&(!rd_cnt_[aw]) | rd_empty, !rd_cnt_[aw-2]&(!rd_cnt_[aw]) | rd_empty};
always @(posedge rd_clk)
if(!rd_rst)
dout_ <= {dw{1'b0}};
else if(rd_clr)
dout_ <= {dw{1'b0}};
else if(re)
dout_ <= dpram_out_;
assign rd_af_tmp = (rd_level_ == 2'b0)?1'b1:1'b0;
assign rd_ae_tmp = (rd_level_ == 2'b11)?1'b1:1'b0;
always @(posedge rd_clk) rd_af <= rd_af_tmp;
always @(posedge rd_clk) rd_ae <= rd_ae_tmp;
assign wr_af_tmp = (wr_level_ == 2'b11)?1'b1:1'b0;
assign wr_ae_tmp = (wr_level_ == 2'b0)?1'b1:1'b0;
always @(posedge wr_clk) wr_af <= wr_af_tmp;
always @(posedge wr_clk) wr_ae <= wr_ae_tmp;
endmodule

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////////////////////////////////////////////////
//Engineer: Xiaodong Zhong
//Date: 2019.5.21
//Description: ?????ram
////////////////////////////////////////////////
module syn_fwft_fifo #(
parameter width =16,
parameter depth =1024,
parameter prog_full_thre =512,
parameter prog_empty_thre =16,
parameter DEBUG = 0
)(
input clk,
input rst,
input clr,
input wr_en,
input [width-1:0] din,
output full,
output almost_full,
output prog_full,
input rd_en,
output [width-1:0] dout,
output empty,
output almost_empty,
output prog_empty,
output [clog2(depth-1)-1:0] cnt
);
////////////////////////////////////////////////
//log2 function
////////////////////////////////////////////////
function integer clog2(input integer depth);
begin
for(clog2=0;depth>0;clog2=clog2+1)
depth =depth>>1;
end
endfunction
localparam aw = clog2(depth-1);
////////////////////////////////////////////////
//reg & wire
////////////////////////////////////////////////
reg [aw-1:0] wr_p;
reg [aw-1:0] rd_p;
wire [aw-1:0] rd_p_next;
reg [aw:0] i;
reg wr_en_dly;
wire [width-1:0] ram_dout;
wire ram_rden;
////////////////////////////////////////////////
//combinational logic
////////////////////////////////////////////////
//assign cnt = (wr_p >= rd_p) ? wr_p - rd_p : depth-rd_p+wr_p;
assign full = (i>=(depth-1)) ? 1'b1 : 1'b0;
assign almost_full = (i >=(depth-4)) ? 1'b1 : 1'b0;
assign prog_full = (i >= (prog_full_thre-1)) ? 1'b1 :1'b0;
assign empty = (i==1'b0) ? 1'b1 : 1'b0;
assign almost_empty = (i<=1'b1) ? 1'b1 : 1'b0;
assign prog_empty = (i<=prog_empty_thre) ? 1'b1 :1'b0;
assign cnt = i[clog2(depth-1)-1:0];
assign rd_p_next = rd_p + {{(aw-2){1'b0}}, (rd_en & !empty)};
////////////////////////////////////////////////
//timing
////////////////////////////////////////////////
reg wr_clr_r;
reg wr_clr;
//----------------------------------------------
always @(posedge clk or posedge clr)
if(clr)
wr_clr <= 1'b1;
else if(!wr_clr_r)
wr_clr <= 1'b0;// Release Clear
always @(posedge clk or posedge clr)
if(clr)
wr_clr_r <= 1'b1;
else
wr_clr_r <= 1'b0;
//----------------------------------------------
always@(posedge clk or posedge rst)begin
if(rst )begin
wr_en_dly <=1'b0;
end
else begin
wr_en_dly <=wr_en;
end
end
always@(posedge clk or posedge rst)begin
if(rst )begin
wr_p <=0;
end
else if(wr_clr)begin
wr_p <=0;
end
else if(wr_en)begin
if(wr_p == depth-1)begin
wr_p <=0;
end
else begin
wr_p <=wr_p+1;
end
end
else begin
wr_p <=wr_p;
end
end
//----------------------------------------------
always@(posedge clk or posedge rst)begin
if(rst )begin
rd_p <=0;
end
else if(wr_clr)begin
rd_p <=0;
end
else if(rd_en)begin
if(rd_p == depth-1)begin
rd_p <=0;
end
else begin
rd_p <=rd_p+1;
end
end
else begin
rd_p <=rd_p;
end
end
//----------------------------------------------
always@(posedge clk or posedge rst)begin
if(rst)begin
i <=0;
end
else if(wr_clr)begin
i <=0;
end
else begin
case({wr_en_dly,rd_en})
2'b00:begin
i <=i;
end
2'b01:begin
if(i!=0)begin
i <=i-1'b1;
end
else begin
i <=i;
end
end
2'b10:begin
if(i!=depth)begin
i <=i+1'b1;
end
else begin
i <=i;
end
end
2'b11:begin
i <=i;
end
default:begin
i <=i;
end
endcase
end
end
////////////////////////////////////////////////
//SRAM
////////////////////////////////////////////////
spram #(
.width (width ),
.depth (depth )
)spram(
.clka (clk ),
.ena (wr_en ),
.dina (din ),
.addra (wr_p ),
.clkb (clk ),
//.enb (1'b1 ),
.enb (ram_rden ),
.doutb (ram_dout ),
.addrb (rd_p_next )
);
assign ram_rden = wr_p != rd_p_next;
assign dout = empty ? 0 : ram_dout;
//generate
// if (DEBUG == 1) begin: debug_gen
// ila_fwft_fifo ila_fwft_fifo_u(
// .clk(clk),
// .probe0({wr_en, din, wr_p, ram_rden, ram_dout, rd_p_next, rd_en, empty, dout}) // 120
// );
// end
//endgenerate
endmodule

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//------------------------------------------------------------------------------
// File : tri_mode_ethernet_mac_0_axi_lite_sm.v
// Author : Xilinx Inc.
// -----------------------------------------------------------------------------
// (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// -----------------------------------------------------------------------------
// Description: This module is reponsible for bringing up both the MAC and the
// attached PHY (if any) to enable basic packet transfer in both directions.
// It is intended to be directly usable on a xilinx demo platform to demonstrate
// simple bring up and data transfer. The mac speed is set via inputs (which
// can be connected to dip switches) and the PHY is configured to ONLY advertise the
// specified speed. To maximise compatibility on boards only IEEE registers are used
// and the PHY address can be set via a parameter.
//
//------------------------------------------------------------------------------
`timescale 1 ps/1 ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module tri_mode_ethernet_mac_0_axi_lite_sm (
input s_axi_aclk,
input s_axi_resetn,
input [1:0] mac_speed,
input update_speed,
input serial_command,
output serial_response,
output reg [11:0] s_axi_awaddr = 0,
output reg s_axi_awvalid = 0,
input s_axi_awready,
output reg [31:0] s_axi_wdata = 0,
output reg s_axi_wvalid = 0,
input s_axi_wready,
input [1:0] s_axi_bresp,
input s_axi_bvalid,
output reg s_axi_bready = 0,
output reg [11:0] s_axi_araddr = 0,
output reg s_axi_arvalid = 0,
input s_axi_arready,
input [31:0] s_axi_rdata,
input [1:0] s_axi_rresp,
input s_axi_rvalid,
output reg s_axi_rready = 0
);
// main state machine
localparam STARTUP = 0,
UPDATE_SPEED = 1,
RESET_MAC_TX = 16,
RESET_MAC_RX = 17,
CNFG_MDIO = 18,
CNFG_FLOW = 19,
CNFG_FILTER = 22,
CNFG_LO_ADDR = 20,
CNFG_HI_ADDR = 21,
CHECK_SPEED = 25;
// AXI State Machine
localparam IDLE = 0,
READ = 1,
WRITE = 2,
DONE = 3;
// Flow control configuration register address (0x40C)
localparam CONFIG_FLOW_CTRL_ADD = 17'h40C;
// Receiver configuration register address (0x404)
localparam RECEIVER_ADD = 17'h404;
// Transmitter configuration register address (0x408)
localparam TRANSMITTER_ADD = 17'h408;
// Speed configuration register address (0x410)
localparam SPEED_CONFIG_ADD = 17'h410;
// Unicast Word 0 configuration register address (0x700)
localparam CONFIG_UNI0_CTRL_ADD = 17'h700;
// Unicast Word 1 configuration register address (0x704)
localparam CONFIG_UNI1_CTRL_ADD = 17'h704;
// Address Filter configuration register address (0x708)
localparam CONFIG_ADDR_CTRL_ADD = 17'h708;
//-------------------------------------------------
// Wire/reg declarations
reg [4:0] axi_status; // used to keep track of axi transactions
reg [31:0] axi_rd_data;
reg [31:0] axi_wr_data;
reg [4:0] axi_state; // main state machine to configure example design
reg [1:0] axi_access_sm; // axi state machine - handles the 5 channels
reg start_access; // used to kick the axi acees state machine
reg writenread;
reg [16:0] addr;
reg [1:0] speed;
wire update_speed_sync;
reg update_speed_reg;
reg [20:0] count_shift = {21{1'b1}};
reg [36:0] serial_command_shift;
reg load_data;
reg capture_data;
reg write_access;
reg read_access;
wire s_axi_reset;
assign s_axi_reset = !s_axi_resetn;
tri_mode_ethernet_mac_0_sync_block update_speed_sync_inst (
.clk (s_axi_aclk),
.data_in (update_speed),
.data_out (update_speed_sync)
);
always @(posedge s_axi_aclk)
begin
if (s_axi_reset) begin
update_speed_reg <= 0;
end
else begin
update_speed_reg <= update_speed_sync;
end
end
//----------------------------------------------------------------------------
// Management process. This process sets up the configuration by
// turning off flow control, then checks gathered statistics at the
// end of transmission
//----------------------------------------------------------------------------
always @(posedge s_axi_aclk)
begin
if (s_axi_reset) begin
axi_state <= STARTUP;
start_access <= 0;
writenread <= 0;
addr <= 0;
axi_wr_data <= 0;
speed <= mac_speed;
end
// main state machine is kicking off multi cycle accesses in each state so has to
// stall while they take place
else if (axi_access_sm == IDLE && !start_access) begin
case (axi_state)
STARTUP : begin
// this state will be ran after reset to wait for count_shift
if (count_shift[20] == 1'b0) begin
speed <= mac_speed;
axi_state <= UPDATE_SPEED;
end
end
// program the MAC to the required speed
UPDATE_SPEED : begin
$display("** Note: Programming MAC speed");
start_access <= 1;
writenread <= 1;
addr <= SPEED_CONFIG_ADD;
// bits 31:30 are used
axi_wr_data <= {speed, 30'h0};
axi_state <= RESET_MAC_RX;
end
// this state will drive the reset to the example design (apart from this block)
// this will be separately captured and synched into the various clock domains
RESET_MAC_RX : begin
$display("** Note: Reseting MAC RX");
start_access <= 1;
writenread <= 1;
addr <= RECEIVER_ADD;
axi_wr_data <= 32'h90000000;
axi_state <= RESET_MAC_TX;
end
// this state will drive the reset to the example design (apart from this block)
// this will be separately captured and synched into the various clock domains
RESET_MAC_TX : begin
$display("** Note: Reseting MAC TX");
start_access <= 1;
writenread <= 1;
addr <= TRANSMITTER_ADD;
axi_wr_data <= 32'h90000000;
axi_state <= CNFG_FLOW;
end
CNFG_FLOW : begin
$display("** Note: Disabling Flow control....");
start_access <= 1;
writenread <= 1;
addr <= CONFIG_FLOW_CTRL_ADD;
axi_wr_data <= 32'h0;
axi_state <= CNFG_LO_ADDR;
end
CNFG_LO_ADDR : begin
$display("** Note: Configuring unicast address(low word)....");
start_access <= 1;
writenread <= 1;
addr <= CONFIG_UNI0_CTRL_ADD;
axi_wr_data <= 32'h040302DA;
axi_state <= CNFG_HI_ADDR;
end
CNFG_HI_ADDR : begin
$display("** Note: Configuring unicast address(high word)....");
start_access <= 1;
writenread <= 1;
addr <= CONFIG_UNI1_CTRL_ADD;
axi_wr_data <= 32'h0605;
axi_state <= CNFG_FILTER;
end
CNFG_FILTER : begin
$display("** Note: Setting core to promiscuous mode....");
start_access <= 1;
writenread <= 1;
addr <= CONFIG_ADDR_CTRL_ADD;
axi_wr_data <= 32'h80000000;
axi_state <= CHECK_SPEED;
end
CHECK_SPEED : begin
if (update_speed_reg) begin
axi_state <= UPDATE_SPEED;
speed <= mac_speed;
end
else begin
if (capture_data)
axi_wr_data <= serial_command_shift[33:2];
if (write_access || read_access) begin
addr <= {5'b0, serial_command_shift[13:2]};
start_access <= 1;
writenread <= write_access;
end
end
end
default : begin
axi_state <= STARTUP;
end
endcase
end
else begin
start_access <= 0;
end
end
//-------------------------------------------------------------------------------------------
// processes to generate the axi transactions - only simple reads and write can be generated
always @(posedge s_axi_aclk)
begin
if (s_axi_reset) begin
axi_access_sm <= IDLE;
end
else begin
case (axi_access_sm)
IDLE : begin
if (start_access) begin
if (writenread) begin
axi_access_sm <= WRITE;
end
else begin
axi_access_sm <= READ;
end
end
end
WRITE : begin
// wait in this state until axi_status signals the write is complete
if (axi_status[4:2] == 3'b111)
axi_access_sm <= DONE;
end
READ : begin
// wait in this state until axi_status signals the read is complete
if (axi_status[1:0] == 2'b11)
axi_access_sm <= DONE;
end
DONE : begin
axi_access_sm <= IDLE;
end
endcase
end
end
// need a process per axi interface (i.e 5)
// in each case the interface is driven accordingly and once acknowledged a sticky
// status bit is set and the process waits until the access_sm moves on
// READ ADDR
always @(posedge s_axi_aclk)
begin
if (axi_access_sm == READ) begin
if (!axi_status[0]) begin
s_axi_araddr <= addr;
s_axi_arvalid <= 1'b1;
if (s_axi_arready == 1'b1 && s_axi_arvalid) begin
axi_status[0] <= 1;
s_axi_araddr <= 0;
s_axi_arvalid <= 0;
end
end
end
else begin
axi_status[0] <= 0;
s_axi_araddr <= 0;
s_axi_arvalid <= 0;
end
end
// READ DATA/RESP
always @(posedge s_axi_aclk)
begin
if (axi_access_sm == READ) begin
if (!axi_status[1]) begin
s_axi_rready <= 1'b1;
if (s_axi_rvalid == 1'b1 && s_axi_rready) begin
axi_status[1] <= 1;
s_axi_rready <= 0;
axi_rd_data <= s_axi_rdata;
end
end
end
else begin
s_axi_rready <= 0;
axi_status[1] <= 0;
if (axi_access_sm == IDLE & start_access) begin
axi_rd_data <= 0;
end
end
end
// WRITE ADDR
always @(posedge s_axi_aclk)
begin
if (axi_access_sm == WRITE) begin
if (!axi_status[2]) begin
s_axi_awaddr <= addr;
s_axi_awvalid <= 1'b1;
if (s_axi_awready == 1'b1 && s_axi_awvalid) begin
axi_status[2] <= 1;
s_axi_awaddr <= 0;
s_axi_awvalid <= 0;
end
end
end
else begin
s_axi_awaddr <= 0;
s_axi_awvalid <= 0;
axi_status[2] <= 0;
end
end
// WRITE DATA
always @(posedge s_axi_aclk)
begin
if (axi_access_sm == WRITE) begin
if (!axi_status[3]) begin
s_axi_wdata <= axi_wr_data;
s_axi_wvalid <= 1'b1;
if (s_axi_wready == 1'b1 && s_axi_wvalid) begin
axi_status[3] <= 1;
s_axi_wvalid <= 0;
end
end
end
else begin
s_axi_wdata <= 0;
s_axi_wvalid <= 0;
axi_status[3] <= 0;
end
end
// WRITE RESP
always @(posedge s_axi_aclk)
begin
if (axi_access_sm == WRITE) begin
if (!axi_status[4]) begin
s_axi_bready <= 1'b1;
if (s_axi_bvalid == 1'b1 && s_axi_bready) begin
axi_status[4] <= 1;
s_axi_bready <= 0;
end
end
end
else begin
s_axi_bready <= 0;
axi_status[4] <= 0;
end
end
//-------------------------------------------------------------------------------------------------------
// to avoid logic being stripped a serial input is included which enables an address/data and control to be setup for
// a user config access..
always @(posedge s_axi_aclk)
begin
if (load_data)
serial_command_shift <= {serial_command_shift[35:33], axi_rd_data, serial_command_shift[0], serial_command};
else
serial_command_shift <= {serial_command_shift[35:0], serial_command};
end
// only deassert serial_response once we reach the state in which we can use the serial_command
assign serial_response = (axi_state == CHECK_SPEED) ? serial_command_shift[35] : 1'b1;
// the serial command is expected to have a start and stop bit - to avoid a counter -
// and a two bit code field in the uppper two bits.
// these decode as follows:
// 00 - read address
// 01 - write address
// 10 - write data
// 11 - read data - slightly more involved - when detected the read data is registered into the shift and passed out
// 11 is used for read data as if the input is tied high the output will simply reflect whatever was
// captured but will not result in any activity
// it is expected that the write data is setup BEFORE the write address
always @(posedge s_axi_aclk)
begin
load_data <= 0;
capture_data <= 0;
write_access <= 0;
read_access <= 0;
if (!serial_command_shift[36] & serial_command_shift[35] & serial_command_shift[0])
if (serial_command_shift[34] & serial_command_shift[33]) // READ DATA
load_data <= 1;
else if (serial_command_shift[34] & !serial_command_shift[33]) // WRITE DATA
capture_data <= 1;
else if (!serial_command_shift[34] & serial_command_shift[33]) // WRITE ADDRESS
write_access <= 1;
else // READ ADDRESS
read_access <= 1;
end
// don't reset this - it will always be updated before it is used..
// it does need an init value (all ones)
always @(posedge s_axi_aclk)
begin
count_shift <= {count_shift[19:0], s_axi_reset};
end
endmodule

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