46 lines
772 B
Verilog
46 lines
772 B
Verilog
module exp6_changed(
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input clk,pbl,enable,
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output [7-1:0] led_high,led_low
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);
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wire clk_3Hz;
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wire[7:0] cnt;
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reg clk_3Hz_ff0;
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wire positive_edge_clk3Hz;
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freq_div #(
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.n(3)
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) u_freq_div(
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.clk(clk),
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.rst_n(pbl),
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.freqdiv_out(clk_3Hz)
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);
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always @ (posedge clk or negedge pbl)
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begin
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if (!pbl)
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clk_3Hz_ff0 <= 0;
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else
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clk_3Hz_ff0 <= clk_3Hz;
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end
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assign positive_edge_clk3Hz = clk_3Hz==1 && clk_3Hz_ff0==0;
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counter u_counter(
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.clk(clk),
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.enable(enable && positive_edge_clk3Hz),
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.rst_n(pbl),
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.count(cnt)
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);
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seg7_led u_seg7_led_high(
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.data_in(cnt[7:4]),
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.led_out(led_high)
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);
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seg7_led u_seg7_led_low(
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.data_in(cnt[3:0]),
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.led_out(led_low)
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);
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endmodule |