473 lines
17 KiB
Verilog
473 lines
17 KiB
Verilog
module status_to_udp (
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input clk,
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input reset,
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input status_report_en,
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input TOE_reg_out_valid,
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input [65:0] TOE_reg_dout,
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// 通信板(CMU)状态信息接口
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output reg CMU_Status_Info_ready,
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input CMU_Status_Info_valid,
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input CMU_Status_Info_last,
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input [31:0] CMU_Status_Info_data,
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// 调控板(XYZ)状态信息接口
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output reg XYZ_Status_Info_ready,
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input XYZ_Status_Info_valid,
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input XYZ_Status_Info_last,
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input [31:0] XYZ_Status_Info_data,
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// 读出板(DAQ)状态信息接口
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output reg DAQ_Status_Info_ready,
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input DAQ_Status_Info_valid,
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input DAQ_Status_Info_last,
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input [31:0] DAQ_Status_Info_data,
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// UDP发送FIFO接口
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input udp_app_send_fifo_rden,
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output [7:0] udp_app_send_fifo_rddata,
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output [11:0] udp_app_send_fifo_rdcnt,
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output udp_app_send_fifo_empty
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);
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// =========================== 参数定义 ===========================
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reg [3:0] A_state; // 需要4位，因为增加了WAIT_CMU_VALID等状态
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localparam IDLE = 4'd0;
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localparam WAIT_READ = 4'd1;
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localparam RECV_TOE = 4'd2;
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localparam WAIT_CMU_VALID = 4'd3; // 新增：等待CMU valid
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localparam RECV_CMU = 4'd4;
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localparam WAIT_XYZ_VALID = 4'd5; // 新增：等待XYZ valid
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localparam RECV_XYZ = 4'd6;
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localparam WAIT_DAQ_VALID = 4'd7; // 新增：等待DAQ valid
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localparam RECV_DAQ = 4'd8;
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reg [2:0] S_state;
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localparam SEND_IDLE = 3'd0;
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localparam SEND_TOE_HEAD_LENGTH = 3'd1;
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localparam SEND_TOE_DATA_1 = 3'd2;
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localparam SEND_TOE_DATA_LENGTH = 3'd3;
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localparam SEND_TOE_DATA_2 = 3'd4;
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localparam SEND_CRC = 3'd5;
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localparam SEND_INFO_HEAD_LENGTH = 3'd6;
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localparam SEND_INFO_DATA = 3'd7;
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// =========================== 寄存器定义 ===========================
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reg [31:0] data_buffer;
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reg [1:0] byte_counter;
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reg buffer_valid;
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// FIFO相关信号
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reg fifo_wr_en;
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reg [31:0] fifo_wr_data;
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wire fifo_full;
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wire TOE_rec_fifo_empty;
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reg TOE_rec_fifo_rden;
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wire [65:0] TOE_rec_fifo_dout;
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reg [63:0] TOE_ready_Data;
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reg TOE_ready_Data_valid;
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reg [63:0] TOE_payload;
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reg [31:0] CMU_Status_data;
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reg send_busy;
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reg send_finish;
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reg [31:0] crc32_calc;
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reg info_recv_flag;
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reg [15:0] Info_data_bytes_num;
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reg [15:0] Info_data_bytes_num_reg;
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// 超时计数器
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reg [7:0] wait_timeout_cnt;
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// 轮询计数器
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reg [1:0] poll_counter;
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reg [31:0] info_cache_fifo_din;
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reg info_cache_fifo_wren;
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reg info_cache_fifo_rden;
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wire [31:0] info_cache_fifo_dout;
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wire info_cache_fifo_full;
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wire info_cache_fifo_empty;
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// =========================== FIFO实例化 ===========================
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//512 depth 32to8
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fifo_generator_32to8 fifo_32to8 (
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.clk(clk), // input wire clk
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.rst(reset), // input wire rst
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.wr_en(fifo_wr_en), // input wire wr_en
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.din(fifo_wr_data), // input wire [31 : 0] din
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.full(fifo_full), // output wire full
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.rd_en(udp_app_send_fifo_rden), // input wire rd_en
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.dout(udp_app_send_fifo_rddata), // output wire [7 : 0] dout
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.empty(udp_app_send_fifo_empty), // output wire empty
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.rd_data_count(udp_app_send_fifo_rdcnt), // output wire [11 : 0] rd_data_count
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.wr_rst_busy(), // output wire wr_rst_busy
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.rd_rst_busy() // output wire rd_rst_busy
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);
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//256 depth 66 to 66
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fifo_generator_66to66 TOE_rec_fifo (
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.clk(clk), // input wire clk
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.srst(reset), // input wire srst
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.din(TOE_reg_dout), // input wire [65 : 0] din
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.wr_en(TOE_reg_out_valid), // input wire wr_en
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.rd_en(TOE_rec_fifo_rden), // input wire rd_en
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.dout(TOE_rec_fifo_dout), // output wire [65 : 0] dout
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.full(), // output wire full
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.empty(TOE_rec_fifo_empty) // output wire empty
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);
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//32 to 32
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fifo_generator_32to32 info_cache_fifo (
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.clk(clk), // input wire clk
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.srst(reset), // input wire srst
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.din(info_cache_fifo_din), // input wire [31 : 0] din
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.wr_en(info_cache_fifo_wren), // input wire wr_en
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.rd_en(info_cache_fifo_rden), // input wire rd_en
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.dout(info_cache_fifo_dout), // output wire [31 : 0] dout
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.full(info_cache_fifo_full), // output wire full
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.empty(info_cache_fifo_empty) // output wire empty
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);
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// ILA实例化（调试用）
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ila_00 ila_udp_data (
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.clk(clk), // input wire clk
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.probe0({
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reset,
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fifo_wr_en,
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fifo_wr_data,
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TOE_reg_dout,
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TOE_reg_out_valid,
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TOE_rec_fifo_rden,
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TOE_rec_fifo_dout,
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TOE_rec_fifo_empty,
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info_cache_fifo_din,
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info_cache_fifo_wren,
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info_cache_fifo_rden,
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info_cache_fifo_dout,
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info_cache_fifo_empty,
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TOE_ready_Data,
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TOE_ready_Data_valid,
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info_recv_flag,
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send_busy,
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A_state,
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S_state,
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crc32_calc,
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TOE_payload,
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Info_data_bytes_num,
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Info_data_bytes_num_reg,
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wait_timeout_cnt,
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poll_counter
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})
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);
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// =========================== 仲裁存储状态机 ===========================
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always @(posedge clk) begin
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if (reset) begin
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A_state <= IDLE;
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TOE_ready_Data <= 64'b0;
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TOE_ready_Data_valid <= 1'b0;
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TOE_rec_fifo_rden <= 1'b0;
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info_cache_fifo_din <= 32'b0;
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info_cache_fifo_wren <= 1'b0;
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info_recv_flag <= 1'b0;
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Info_data_bytes_num <= 16'b0;
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send_busy <= 1'b0;
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CMU_Status_Info_ready <= 1'b0;
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XYZ_Status_Info_ready <= 1'b0;
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DAQ_Status_Info_ready <= 1'b0;
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wait_timeout_cnt <= 8'b0;
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poll_counter <= 2'b00;
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end else begin
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case (A_state)
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IDLE: begin //0
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TOE_ready_Data <= 64'b0;
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TOE_ready_Data_valid <= 1'b0;
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info_cache_fifo_wren <= 1'b0;
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info_cache_fifo_din <= 32'b0;
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info_recv_flag <= 1'b0;
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CMU_Status_Info_ready <= 1'b0;
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XYZ_Status_Info_ready <= 1'b0;
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DAQ_Status_Info_ready <= 1'b0;
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Info_data_bytes_num <= 16'b0;
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wait_timeout_cnt <= 8'b0;
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if (send_finish) begin
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send_busy <= 1'b0;
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end
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// 优先级仲裁：TOE > 状态信息板卡
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if ((!TOE_rec_fifo_empty) && (!send_busy)) begin
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A_state <= WAIT_READ;
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TOE_rec_fifo_rden <= 1'b1;
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end else if (status_report_en && (!send_busy)) begin
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// 轮询不同的板卡：按照CMU->XYZ->DAQ的顺序
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case (poll_counter)
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2'b00: begin // CMU
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A_state <= WAIT_CMU_VALID;
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CMU_Status_Info_ready <= 1'b1;
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end
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2'b01: begin // XYZ
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A_state <= WAIT_XYZ_VALID;
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XYZ_Status_Info_ready <= 1'b1;
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end
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2'b10: begin // DAQ
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A_state <= WAIT_DAQ_VALID;
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DAQ_Status_Info_ready <= 1'b1;
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end
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default: begin
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A_state <= IDLE;
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poll_counter <= 2'b00;
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end
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endcase
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end else begin
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A_state <= IDLE;
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end
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end
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WAIT_READ: begin //1
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A_state <= RECV_TOE;
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TOE_rec_fifo_rden <= 1'b0;
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end
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RECV_TOE: begin //2
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TOE_ready_Data[63] <= 1'b1; // 读标志位
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TOE_ready_Data[56:52] <= 5'h02; // 新增
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TOE_ready_Data[49:48] <= TOE_rec_fifo_dout[65:64]; // CID
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TOE_ready_Data[47:32] <= TOE_rec_fifo_dout[47:32]; // 地址
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TOE_ready_Data[31:0] <= TOE_rec_fifo_dout[31:0]; // 数据
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TOE_ready_Data_valid <= 1'b1;
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send_busy <= 1'b1; // 拿到数立马进行发送状态
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A_state <= IDLE;
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poll_counter <= 2'b00; // 重置轮询计数器
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end
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WAIT_CMU_VALID: begin //3
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wait_timeout_cnt <= wait_timeout_cnt + 1;
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if (CMU_Status_Info_valid) begin
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wait_timeout_cnt <= 8'b0;
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A_state <= RECV_CMU;
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info_cache_fifo_wren <= 1'b1;
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info_cache_fifo_din <= CMU_Status_Info_data;
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Info_data_bytes_num <= Info_data_bytes_num + 4;
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end else if (wait_timeout_cnt > 8'd10) begin // 超时10个周期
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wait_timeout_cnt <= 8'b0;
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CMU_Status_Info_ready <= 1'b0;
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poll_counter <= poll_counter + 1; // 尝试下一个板卡
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A_state <= IDLE;
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end
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end
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RECV_CMU: begin //4
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// 保持ready为高，直到last信号到来
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CMU_Status_Info_ready <= 1'b1;
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if(CMU_Status_Info_valid) info_cache_fifo_wren <= 1'b1;
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else info_cache_fifo_wren <= 1'b0;
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info_cache_fifo_din <= CMU_Status_Info_data;
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if (CMU_Status_Info_valid) begin /////valid可能为高低高低交替，所以计数也要加判断逻辑，以免多计数。
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Info_data_bytes_num <= Info_data_bytes_num + 4;
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end
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if (CMU_Status_Info_last) begin
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A_state <= IDLE;
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CMU_Status_Info_ready <= 1'b0;
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// info_cache_fifo_wren <= 1'b0;
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send_busy <= 1'b1; // 拿到数立马进行发送状态
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info_recv_flag <= 1'b1;
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poll_counter <= 2'b00; // 重置轮询计数器
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end
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end
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WAIT_XYZ_VALID: begin //5
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wait_timeout_cnt <= wait_timeout_cnt + 1;
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if (XYZ_Status_Info_valid) begin
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wait_timeout_cnt <= 8'b0;
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A_state <= RECV_XYZ;
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info_cache_fifo_wren <= 1'b1;
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info_cache_fifo_din <= XYZ_Status_Info_data;
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Info_data_bytes_num <= Info_data_bytes_num + 4;
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end else if (wait_timeout_cnt > 8'd10) begin // 超时10个周期
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wait_timeout_cnt <= 8'b0;
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XYZ_Status_Info_ready <= 1'b0;
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poll_counter <= poll_counter + 1; // 尝试下一个板卡
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A_state <= IDLE;
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end
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end
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RECV_XYZ: begin //6
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XYZ_Status_Info_ready <= 1'b1;
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if(XYZ_Status_Info_valid) info_cache_fifo_wren <= 1'b1;
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else info_cache_fifo_wren <= 1'b0;
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info_cache_fifo_din <= XYZ_Status_Info_data;
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if (XYZ_Status_Info_valid) begin /////valid可能为高低高低交替，所以计数也要加判断逻辑，以免多计数。
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Info_data_bytes_num <= Info_data_bytes_num + 4;
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end
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if (XYZ_Status_Info_last) begin
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A_state <= IDLE;
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XYZ_Status_Info_ready <= 1'b0;
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// info_cache_fifo_wren <= 1'b0;
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send_busy <= 1'b1;
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info_recv_flag <= 1'b1;
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poll_counter <= 2'b00; // 重置轮询计数器
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end
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end
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WAIT_DAQ_VALID: begin //7
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wait_timeout_cnt <= wait_timeout_cnt + 1;
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if (DAQ_Status_Info_valid) begin
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wait_timeout_cnt <= 8'b0;
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A_state <= RECV_DAQ;
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info_cache_fifo_wren <= 1'b1;
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info_cache_fifo_din <= DAQ_Status_Info_data;
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Info_data_bytes_num <= Info_data_bytes_num + 4;
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end else if (wait_timeout_cnt > 8'd10) begin // 超时10个周期
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wait_timeout_cnt <= 8'b0;
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DAQ_Status_Info_ready <= 1'b0;
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poll_counter <= 2'b00; // 轮询回到CMU
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A_state <= IDLE;
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end
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end
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RECV_DAQ: begin //8
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DAQ_Status_Info_ready <= 1'b1;
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if(DAQ_Status_Info_valid) info_cache_fifo_wren <= 1'b1;
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else info_cache_fifo_wren <= 1'b0;
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info_cache_fifo_din <= DAQ_Status_Info_data;
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if (DAQ_Status_Info_valid) begin /////valid可能为高低高低交替，所以计数也要加判断逻辑，以免多计数。
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Info_data_bytes_num <= Info_data_bytes_num + 4;
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end
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if (DAQ_Status_Info_last) begin
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A_state <= IDLE;
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DAQ_Status_Info_ready <= 1'b0;
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// info_cache_fifo_wren <= 1'b0;
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send_busy <= 1'b1;
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info_recv_flag <= 1'b1;
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poll_counter <= 2'b00; // 重置轮询计数器
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end
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end
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default: A_state <= IDLE;
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endcase
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end
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end
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// =========================== 发送状态机 ===========================
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always @(posedge clk or posedge reset) begin
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if(reset) begin
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S_state <= SEND_IDLE;
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fifo_wr_en <= 1'b0;
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fifo_wr_data <= 32'b0;
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crc32_calc <= 32'hFFFFFFFF;
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info_cache_fifo_rden <= 1'b0;
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TOE_payload <= 64'b0;
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send_finish <= 1'b0;
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Info_data_bytes_num_reg <= 1'b0;
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end else begin
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case(S_state)
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SEND_IDLE: begin //0
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fifo_wr_en <= 1'b0;
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fifo_wr_data <= 32'b0;
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crc32_calc <= 32'hFFFFFFFF;
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send_finish <= 1'b0;
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Info_data_bytes_num_reg <= 1'b0;
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info_cache_fifo_rden <= 1'b0;
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if(TOE_ready_Data_valid) begin
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TOE_payload <= TOE_ready_Data;
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S_state <= SEND_TOE_HEAD_LENGTH;
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end else if(info_recv_flag) begin
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S_state <= SEND_INFO_HEAD_LENGTH;
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info_cache_fifo_rden <= 1'b1;
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Info_data_bytes_num_reg <= Info_data_bytes_num;
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end
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end
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SEND_TOE_HEAD_LENGTH: begin //1
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fifo_wr_en <= 1'b1;
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fifo_wr_data <= 32'h4547000c;
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S_state <= SEND_TOE_DATA_1;
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end
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SEND_TOE_DATA_1: begin //2
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fifo_wr_en <= 1'b1;
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fifo_wr_data <= TOE_payload[63:32];
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crc32_calc <= calc_crc32(TOE_payload[63:32], crc32_calc);
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S_state <= SEND_TOE_DATA_LENGTH;
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end
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SEND_TOE_DATA_LENGTH: begin //3
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fifo_wr_en <= 1'b1;
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fifo_wr_data <= 32'd4; // 固定四字节长度
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crc32_calc <= calc_crc32(32'd4, crc32_calc);
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S_state <= SEND_TOE_DATA_2;
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end
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SEND_TOE_DATA_2: begin //4
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fifo_wr_en <= 1'b1;
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fifo_wr_data <= TOE_payload[31:0];
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crc32_calc <= calc_crc32(TOE_payload[31:0], crc32_calc);
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S_state <= SEND_CRC;
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end
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SEND_CRC: begin //5
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fifo_wr_en <= 1'b1;
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fifo_wr_data <= crc32_calc;
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S_state <= SEND_IDLE;
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send_finish <= 1'b1;
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info_cache_fifo_rden <= 1'b0;
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end
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SEND_INFO_HEAD_LENGTH: begin //6
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fifo_wr_en <= 1'b1;
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fifo_wr_data[31:16] <= 16'h494e; // "IN"
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fifo_wr_data[15:0] <= Info_data_bytes_num_reg;
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crc32_calc <= 32'hFFFFFFFF; //be ready to caculate crc
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S_state <= SEND_INFO_DATA;
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end
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SEND_INFO_DATA: begin //7
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fifo_wr_en <= 1'b1;
|
||
fifo_wr_data <= info_cache_fifo_dout;
|
||
crc32_calc <= calc_crc32(info_cache_fifo_dout, crc32_calc);
|
||
|
||
if(info_cache_fifo_empty) begin
|
||
info_cache_fifo_rden <= 1'b0;
|
||
S_state <= SEND_CRC;
|
||
end else begin
|
||
info_cache_fifo_rden <= 1'b1;
|
||
end
|
||
end
|
||
|
||
default: S_state <= SEND_IDLE;
|
||
endcase
|
||
end
|
||
end
|
||
|
||
// =========================== CRC32计算函数 ===========================
|
||
function [31:0] calc_crc32;
|
||
input [31:0] data;
|
||
input [31:0] crc;
|
||
reg [31:0] new_crc;
|
||
integer i;
|
||
localparam [31:0] POLY = 32'h04C11DB7;
|
||
begin
|
||
new_crc = crc ^ data;
|
||
for (i = 0; i < 32; i = i + 1) begin
|
||
if (new_crc[31]) begin
|
||
new_crc = (new_crc << 1) ^ POLY;
|
||
end else begin
|
||
new_crc = new_crc << 1;
|
||
end
|
||
end
|
||
calc_crc32 = new_crc;
|
||
end
|
||
endfunction
|
||
|
||
endmodule |