27 lines
650 B
Verilog
27 lines
650 B
Verilog
module seg7_led(
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input [4-1:0] data_in,
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output reg [7-1:0] led_out
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);
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always @(*) begin
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case(data_in)
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4'h0:led_out = 7'b1000000;
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4'h1:led_out = 7'b1111001;
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4'h2:led_out = 7'b0100100;
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4'h3:led_out = 7'b0110000;
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4'h4:led_out = 7'b0011001;
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4'h5:led_out = 7'b0010010;
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4'h6:led_out = 7'b0000010;
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4'h7:led_out = 7'b1111000;
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4'h8:led_out = 7'b0000000;
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4'h9:led_out = 7'b0010000;
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4'ha:led_out = 7'b0001000;
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4'hb:led_out = 7'b0000011;
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4'hc:led_out = 7'b1000110;
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4'hd:led_out = 7'b0100001;
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4'he:led_out = 7'b0000110;
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4'hf:led_out = 7'b0001110;
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default:led_out = 7'b1111111;
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endcase
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end
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endmodule
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