358 lines
11 KiB
Verilog
358 lines
11 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2025/10/31 16:59:43
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// Design Name:
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// Module Name: UDP_data_process
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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module UDP_data_process (
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input clk,
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input reset,
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input eth_linked,
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output reg pulse_second,
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// input data_fifo_rden,
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// UDP接收FIFO接口
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output reg udp_app_recv_fifo_rden,
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input [7:0] udp_app_recv_fifo_rddata,
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input [11:0] udp_app_recv_fifo_rdcnt,
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input udp_app_recv_fifo_empty,
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// UDP发送FIFO接口
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input udp_app_send_fifo_rden,
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output [7:0] udp_app_send_fifo_rddata,
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output [11:0] udp_app_send_fifo_rdcnt,
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output udp_app_send_fifo_empty,
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// TOE寄存器接口
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output reg TOE_reg_wren,
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output reg TOE_reg_rden,
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output reg [65:0] TOE_reg_din,
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input TOE_reg_out_valid,
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input [65:0] TOE_reg_dout,
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// 通信板(CMU)状态信息接口
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output CMU_Status_Info_ready,
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input CMU_Status_Info_valid,
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input CMU_Status_Info_last,
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input [31:0] CMU_Status_Info_data,
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// 调控板(XYZ)状态信息接口
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output XYZ_Status_Info_ready,
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input XYZ_Status_Info_valid,
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input XYZ_Status_Info_last,
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input [31:0] XYZ_Status_Info_data,
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// 读出板(DAQ)状态信息接口
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output DAQ_Status_Info_ready,
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input DAQ_Status_Info_valid,
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input DAQ_Status_Info_last,
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input [31:0] DAQ_Status_Info_data
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);
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// wire udp_app_recv_fifo_rden_r;
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wire udp_app_recv_fifo_ready;
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wire udp_recv_data_tvalid;
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wire [31:0]udp_recv_data;
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// 协议头
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parameter [15:0] HDR_DATA = 16'h4d44;
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parameter [15:0] HDR_CTRL = 16'h4547;
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parameter [15:0] HDR_TOE = 16'h494e;
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// 4个状态：空闲、读Header、读Length、读Payload&Check
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reg [1:0] parse_state;
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localparam P_IDLE = 2'd0;
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localparam P_DATA = 2'd1;
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reg [2:0] deal_state;
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reg deal_busy;
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localparam D_IDLE = 3'd0;
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localparam D_HEAD = 3'd1;
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localparam D_TOE_1 = 3'd2;
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localparam D_TOE_2 = 3'd3;
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localparam D_EXE = 3'd4;
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localparam D_CTRL =3'd5;
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reg [3:0]TOE_SFP_ID;
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reg TOE_RW_FLAG;
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reg [31:0] TOE_ADDR;
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reg [31:0] TOE_DATA;
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reg [15:0] header_reg;
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reg [15:0] length_reg;
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reg [31:0] data_reg;
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reg [31:0] crc32_calc;
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reg [31:0] crc32_recv;
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reg [15:0] payload_remain;
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reg recv_udp_frame_last;
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reg crc_match; // CRC校验匹配标记
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wire crc_error;
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wire [31:0]udp_recv_data_reorder;
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reg cnt;
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wire data_fifo_rst ;
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reg data_fifo_wren;
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reg [31:0] data_fifo_din;
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reg data_fifo_rden;
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wire [31:0] data_fifo_dout;
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wire data_fifo_empty;
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wire data_fifo_full;
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reg state_report_en;
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reg [27:0] second_timer = 'b0;
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// ---------------------------
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// 读取FIFO逻辑
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// ---------------------------
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always@(posedge clk)
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if(reset)
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udp_app_recv_fifo_rden <= 1'b0;
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else if((~udp_app_recv_fifo_empty) && udp_app_recv_fifo_ready && (~deal_busy))
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udp_app_recv_fifo_rden <= 1'b1;
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else if(udp_app_recv_fifo_rdcnt == 12'b0)
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udp_app_recv_fifo_rden <= 1'b0;
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else
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udp_app_recv_fifo_rden <= 1'b0;
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//assign udp_app_recv_fifo_rden_r = udp_app_recv_fifo_rden && (~udp_app_recv_fifo_empty); // udp recv data does not delay, so the en needn't delay
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axis_dwidth_converter_0 axis_dwidth_converter_udprx(
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.aclk (clk), // input
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.aresetn (~reset), // input
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.s_axis_tvalid(udp_app_recv_fifo_rden), // input
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.s_axis_tready(udp_app_recv_fifo_ready), // output
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.s_axis_tdata (udp_app_recv_fifo_rddata), // input [7:0]
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.m_axis_tvalid(udp_recv_data_tvalid), // output
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.m_axis_tready(1'b1), // input
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.m_axis_tdata (udp_recv_data) // output [63:0]
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);
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assign udp_recv_data_reorder = {udp_recv_data[7:0], udp_recv_data[15:8], udp_recv_data[23:16], udp_recv_data[31:24]};
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assign crc_error = crc_match ^ recv_udp_frame_last;
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always @(posedge clk or posedge reset) begin
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if(reset)begin
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cnt <=0;
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parse_state <= 0;
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crc32_recv<=0;
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crc_match =1'b0;
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payload_remain<=0;
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recv_udp_frame_last <=0;
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crc32_calc <= 32'hFFFFFFFF;
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end
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else begin
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case (parse_state)
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P_IDLE : begin
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crc32_calc <= 32'hFFFFFFFF;
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recv_udp_frame_last <=1'b0;
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crc_match =1'b0;
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if (udp_recv_data_tvalid) begin
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payload_remain <= udp_recv_data_reorder[15:0];
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data_fifo_din <=udp_recv_data_reorder;//存数据,跳到PDATA的时候就存成功了。
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data_fifo_wren <=1'b1;
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parse_state <= P_DATA;
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end
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end
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P_DATA : begin
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data_fifo_wren <=1'b0;
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if (udp_recv_data_tvalid) begin
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if(payload_remain == 0) begin //判断余量为0的时候的tvalid，crc_rev数据就到了。
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parse_state <= P_IDLE;
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crc32_recv <= udp_recv_data_reorder;
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recv_udp_frame_last <=1'b1; //收到完整一帧
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data_fifo_rden <= 1'b1;
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if(crc32_calc == udp_recv_data_reorder)
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crc_match =1'b1;
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else
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crc_match =1'b0;
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end
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else begin
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data_reg <= udp_recv_data_reorder;
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data_fifo_din <=udp_recv_data_reorder; //存数据,判断payload_remain == 0 ，payload就完整存进去了。
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data_fifo_wren <=1'b1;
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crc32_calc <= calc_crc32(udp_recv_data_reorder,crc32_calc);
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payload_remain <= payload_remain -4;
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end
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end
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end
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endcase
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end
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end
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fifo_generator_0 data_cache_fifo (
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.clk (clk), // 时钟
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.srst (data_fifo_rst), // 同步复位
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.din (data_fifo_din), // 写入数据
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.wr_en (data_fifo_wren), // 写使能
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.rd_en (data_fifo_rden), // 读使能
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.dout (data_fifo_dout), // 读出数据
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.full (data_fifo_full), // 满标志
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.empty (data_fifo_empty) // 空标志
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);
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//处理状态机
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always @(posedge clk or posedge reset) begin
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if(reset)begin
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data_fifo_rden <= 0;
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deal_state <=0;
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deal_busy <=0;
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TOE_SFP_ID <=0;
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TOE_RW_FLAG <=0;
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TOE_ADDR <= 0;
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TOE_DATA <= 0;
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header_reg <=0;
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TOE_reg_wren <= 0;
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TOE_reg_rden <= 0;
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TOE_reg_din <= 0;
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state_report_en <= 0;
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end
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else begin
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case(deal_state)
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D_IDLE : begin
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TOE_reg_wren <= 0;
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TOE_reg_rden <= 0;
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TOE_reg_din <= 0;
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if(recv_udp_frame_last)begin //last拉高的同时 ，也把data_fifo_rden拉高了
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deal_busy <= 1'b1;
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data_fifo_rden <= 1; // 这个拉高其实没用。如果这时候拉高，下个时钟数据处来，下下个时钟才能触发。所以这个时钟数据就要出来。
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deal_state <= D_HEAD;
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end
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end
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D_HEAD :begin //判断是头的类型，执行对应操作
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header_reg <= data_fifo_dout[31:16]; // Header高字节 data_fifo_dout出来的操作，和被赋值的操作是同时进行的，默认赋值前一个数。
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if( data_fifo_dout[31:16]== HDR_TOE )begin
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deal_state<= D_TOE_1;
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data_fifo_rden <= 1;
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end
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else if(data_fifo_dout[31:16] == HDR_CTRL)begin
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deal_state <= D_CTRL;
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data_fifo_rden <= 0; //如果现在拉低了，
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end
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else
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deal_state <= D_IDLE;
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end
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D_TOE_1 :begin
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TOE_reg_wren <= 0;
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TOE_reg_rden <= 0;
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TOE_reg_din <= 0; //TOE控制清除。
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TOE_SFP_ID <= data_fifo_dout[23:20]; //TOE是64比特的数据，此时获得的是高32bit
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TOE_RW_FLAG <= data_fifo_dout[16] ;
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TOE_ADDR <= data_fifo_dout[15:0] ; //虽然是32比特的寄存器，但地址就是16位。
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deal_state <= D_TOE_2;
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data_fifo_rden <= 1;
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end
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D_TOE_2 : begin
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TOE_DATA <= data_fifo_dout;
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deal_state <= D_EXE;
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data_fifo_rden <= 0;
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end
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D_EXE : begin
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if(header_reg == HDR_TOE)begin
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//开始TOE命令处理
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if(TOE_RW_FLAG) TOE_reg_rden <= 1'b1;
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else TOE_reg_wren <= 1'b1;
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TOE_reg_din <= {TOE_SFP_ID[1:0],TOE_ADDR,TOE_DATA};
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//处理结束
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if(data_fifo_empty) begin deal_state <=D_IDLE; deal_busy = 1'b0; end
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else begin deal_state <= D_TOE_1; data_fifo_rden <= 1; end
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end
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end
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D_CTRL : begin
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if(data_fifo_dout ==32'h1000_0001)begin
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state_report_en <= 1;
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end
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else if (data_fifo_dout ==32'h1000_0000)begin
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state_report_en <= 0;
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end
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else begin
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state_report_en <= 0;
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end
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deal_busy = 1'b0;
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deal_state <= D_IDLE;
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end
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endcase
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end
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end
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//CRC32计算函数（生成多项式G(x) = x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1）初始值0xffffffff。
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function [31:0] calc_crc32;
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input [31:0] data;
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input [31:0] crc;
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reg [31:0] new_crc;
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integer i;
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localparam [31:0] POLY = 32'h04C11DB7;
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begin
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new_crc = crc ^ data;
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for (i = 0; i < 32; i = i + 1) begin
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if (new_crc[31]) begin
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new_crc = (new_crc << 1) ^ POLY;
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end else begin
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new_crc = new_crc << 1;
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end
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end
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calc_crc32 = new_crc;
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end
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endfunction
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// 1 second timer
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always@(posedge clk)
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if(reset)
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second_timer <= 'b0;
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else if((second_timer < 28'd125 - 1) && state_report_en) //状态上报开启，秒计数器才开始工作 实际为：28'd125000000
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second_timer <= second_timer + 1'b1;
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else
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second_timer <= 28'd0;
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always@(posedge clk)
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if(reset)
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pulse_second <= 1'b0;
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else if( (second_timer >28'd125 - 1 -16))begin
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pulse_second <= 1'b1;
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end
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else
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pulse_second <= 1'b0;
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endmodule
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