module exp6_changed(
    input clk,pbl,enable,
    output [7-1:0] led_high,led_low
);

wire clk_3Hz;
wire[7:0] cnt;
reg clk_3Hz_ff0;
wire positive_edge_clk3Hz;

freq_div #(
    .n(3)
) u_freq_div(
    .clk(clk),
    .rst_n(pbl),
    .freqdiv_out(clk_3Hz)
);

always @ (posedge clk or negedge pbl)
begin
    if (!pbl)
        clk_3Hz_ff0 <= 0;
    else
        clk_3Hz_ff0 <= clk_3Hz;
end

assign positive_edge_clk3Hz = clk_3Hz==1 && clk_3Hz_ff0==0;

counter u_counter(
    .clk(clk),
    .enable(enable && positive_edge_clk3Hz),
    .rst_n(pbl),
    .count(cnt)
);

seg7_led u_seg7_led_high(
    .data_in(cnt[7:4]),
    .led_out(led_high)
);

seg7_led u_seg7_led_low(
    .data_in(cnt[3:0]),
    .led_out(led_low)
);

endmodule