module counter
(
    input clk, enable, rst_n,
    output reg [8-1:0] count
);

always @ (posedge clk or negedge rst_n)
begin
    if (!rst_n)
        count <= 0;
    else if (enable == 1'b1)
<<<<<<< HEAD
        count <= count + 1;
end//
=======
        count <= count + 1;//00sss
end
>>>>>>> 3dc244fbc9669daee2436d70f0933dbd577fece0
endmodule