module freq_div
#(
    parameter n
)
(
    input clk,rst_n,
    output freqdiv_out
);

reg [n-1:0] count;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        count <= 0;
    else
        count <= count + 1;
end

assign freqdiv_out = count[n-1];

endmodule